Driver circuit and display device

Abstract

To reduce the circuit scale of a driver circuit.SOLUTION: The driver circuit includes a plurality of stages of unit circuits and drives a plurality of signal lines, and an n-th stage of unit circuit includes a setting terminal that outputs a setting signal to another stage of unit circuit and a plurality of drive terminals including a first drive terminal that outputs a first drive signal to one of the plurality of signal lines and a second drive terminal that outputs a second drive signal to another one of the plurality of signal lines. The setting signal is active in the first period, and the first period includes at least a part of the active period of the first drive signal and at least a part of the active period of the second drive signal.SELECTED DRAWING: Figure 2

Description

[Technical Field]

[0001] The present disclosure relates to driver circuits. [Background technology]

[0002] Patent Document 1 discloses a driver circuit used in a display device that performs partial display. [Prior art documents] [Patent documents]

[0003] [Patent Document 1] Japanese Patent Publication No. 2011-209714 Summary of the Invention [Problem to be solved by the invention]

[0004] Conventional driver circuits have a problem in that the circuit size is large. [Means for solving the problem]

[0005] A driver circuit according to one embodiment of the present disclosure is a driver circuit that includes multiple stages of unit circuits and drives multiple signal lines, wherein the nth stage unit circuit has a setting terminal that outputs a setting signal to the unit circuits of the other stages, and multiple drive terminals including a first drive terminal that outputs a first drive signal to one of the multiple signal lines, and a second drive terminal that outputs a second drive signal to another one of the multiple signal lines, wherein the setting signal is active during a first period, and the first period includes at least a portion of the active period of the first drive signal and at least a portion of the active period of the second drive signal. [Effects of the Invention]

[0006] The circuit size of the driver circuit can be reduced. [Brief explanation of the drawings]

[0007] [Figure 1]FIG. 2 is a schematic diagram showing the configuration of a driver circuit according to the present embodiment. [Figure 2] 4 is a timing chart showing the operation of the driver circuit according to the present embodiment. [Figure 3] FIG. 2 is a circuit diagram showing the configuration of a unit circuit of a driver circuit according to the present embodiment. [Figure 4] FIG. 2 is a circuit diagram showing the configuration of a unit circuit of a driver circuit according to the present embodiment. [Figure 5] FIG. 2 is a circuit diagram showing the configuration of a unit circuit of a driver circuit according to the present embodiment. [Figure 6] 1 is a block diagram showing a configuration of a display device according to an embodiment of the present invention. [Figure 7] FIG. 2 is a schematic diagram showing the configuration of a driver circuit according to the present embodiment. [Figure 8] 4 is a timing chart showing the operation of the driver circuit according to the present embodiment. [Figure 9] FIG. 2 is a schematic diagram showing the configuration of a driver circuit according to the present embodiment. [Figure 10] 4 is a timing chart showing the operation of the driver circuit according to the present embodiment. [Figure 11] FIG. 2 is a schematic diagram showing the configuration of a driver circuit according to the present embodiment. [Figure 12] 4 is a timing chart showing the operation of the driver circuit according to the present embodiment. [Figure 13] FIG. 2 is a schematic diagram showing the configuration of a driver circuit according to the present embodiment. [Figure 14] FIG. 2 is a circuit diagram showing the configuration of a unit circuit of a driver circuit according to the present embodiment. [Figure 15] 4 is a timing chart showing the operation of the driver circuit according to the present embodiment. DETAILED DESCRIPTION OF THE INVENTION

[0008] FIG. 1 is a schematic diagram showing the configuration of a driver circuit according to this embodiment. FIG. 2 is a timing chart showing the operation of the driver circuit according to this embodiment. FIGS. 3 to 5 are circuit diagrams showing the configuration of a unit circuit of the driver circuit according to this embodiment. As shown in FIGS. 1 to 5, the driver circuit 20 is a driver circuit including multiple stages of unit circuits (Jn, Jn-1, Jn+1, etc.) and driving multiple signal lines (Ga to Gf, etc.). The n-th stage unit circuit Jn includes a setting terminal Un that outputs a setting signal Qn to the unit circuits of other stages (Jn+1, etc.), a first driving terminal Xn that outputs a first driving signal Va to a signal line Ga that is one of the multiple signal lines, and a second driving terminal Yn that outputs a second driving signal Vb to a signal line Gb that is another of the multiple signal lines. n is a natural number. The setting signal Qn may have a function of setting the unit circuit in the subsequent stage. The setting signal Qn may have a function of resetting the unit circuit in the previous stage.

[0009] In the driver circuit 20, the setting signal Qn is active during a first period L1, and the first period L1 includes at least a portion of the active period La of the first drive signal Va and at least a portion of the active period Lb of the second drive signal Vb. The first period L1 may include the entire active period La of the first drive signal Va and the entire active period Lb of the second drive signal Vb. The first period L1 may include the entire active period La of the first drive signal Va and a portion of the active period Lb of the second drive signal Vb.

[0010] In the driver circuit 20, the two signal lines Ga and Gb can be driven by the first and second drive signals Va and Vb generated by the n-th stage unit circuit Jn, thereby reducing the circuit scale of the driver circuit 20.

[0011] Each of the signals Ga to Gf ​​may be a scanning line, and each of the first and second drive signals Va and Vb may be a scan signal. The signal line Ga may be a (2n-1)-stage scanning line formed on the display unit 40, and the signal line Gb may be a (2n)-stage scanning line formed on the display unit 40.

[0012] The nth-stage unit circuit Jn has a setting transistor Tq, one of whose two conduction terminals (source / drain) receives a clock signal K1 and the other is connected to a setting terminal Un. During a period LZ in which the gate terminal (control node NZ) of the setting transistor Tq remains active (high), at least a portion of the active period La of the first drive signal Va and at least a portion of the active period Lb of the second drive signal Vb may overlap. The entire active period La of the first drive signal Va and the entire active period Lb of the second drive signal Vb may overlap during the period LZ (i.e., the entire period La and the entire period Lb may be included in the period LZ). The potential of the control node NZ is Vz.

[0013] In the driver circuit 20, the setting signal Qn may be active during the second period L2, and the first and second drive signals Va and Vb may be inactive during the second period L2. That is, full scanning, which scans all of the signal lines (including Ga to Gf), and partial scanning, which scans only some of the signal lines (including Ge and Gf), may be performed. The setting signal Qn functions as a set signal, and another stage (Jn+1) may be set during the first period L1 and the second period L2. This allows the refresh rate (rewriting frequency) to be changed for each region of the display unit 40 (including signal lines Ga to Gf) to be driven, thereby reducing power consumption.

[0014] 1 to 5, the area including the signal lines (scanning lines) Ga to Gd has a low refresh rate, and the area including the signal lines (scanning lines) Ge and Gf has a high refresh rate. A still image may be displayed in the low refresh rate area, and a moving image may be displayed in the high refresh rate area.

[0015] 2, in the driver circuit 20, the first and second drive signals Va and Vb may be sequentially activated (rising from low to high) during a first period L1. Part (e.g., the latter half) of the active period of the first drive signal Va may overlap with part (e.g., the first half) of the active period of the second drive signal Vb. During the first period L1, each of the first and second drive signals Va and Vb may return to an inactive state (from active high).

[0016] 3, the n-th stage unit circuit Jn may have a first input terminal I1 to which a first pulse signal P1 is input, a second input terminal I2 to which a second pulse signal P2 is input, a clock terminal IK to which a clock signal K1 is input, a setting transistor Tq, and first and second transistors T1 and T2. The first drive terminal Xn may be connected to the first input terminal I1 via the first transistor T1, the second drive terminal Yn may be connected to the second input terminal I2 via the second transistor T2, and the setting terminal Un that outputs Qn may be connected to the clock terminal IK via the setting transistor Tq.

[0017] As shown in Figure 4, the unit circuit Jn+1 of the (n+1)th stage may have a setting terminal Un+1 that outputs a setting signal Qn+1 to a unit circuit of another stage (Jn+2, etc.), a first drive terminal Xn+1 that outputs a first drive signal Vc to a signal line Gc that is one of the multiple signal lines, and a second drive terminal Yn+1 that outputs a second drive signal Vd to a signal line Gd that is another of the multiple signal lines.

[0018] The (n+1)-th stage unit circuit Jn+1 may have a first input terminal I1 to which the third pulse signal P3 is input, a second input terminal I2 to which the fourth pulse signal P4 is input, a clock terminal IK to which the clock signal K2 is input, a setting transistor Tq, and first and second transistors T1 and T2. The first drive terminal Xn+1 may be connected to the first input terminal I1 via the first transistor T1, the second drive terminal Yn+1 may be connected to the second input terminal I2 via the second transistor T2, and the setting terminal Un+1 that outputs Qn+1 may be connected to the clock terminal IK via the setting transistor Tq.

[0019] As shown in Figure 5, the unit circuit Jn+2 of the (n+2)th stage may have a setting terminal Un+2 that outputs a setting signal Qn+2 to a unit circuit of another stage (Jn+3, etc.), a first drive terminal Xn+1 that outputs a first drive signal Ve to a signal line Ge that is one of the multiple signal lines, and a second drive terminal Yn+2 that outputs a second drive signal Vf to a signal line Gf that is another of the multiple signal lines.

[0020] The (n+2)-th stage unit circuit Jn+2 may have a first input terminal I1 to which the fifth pulse signal P5 is input, a second input terminal I2 to which the sixth pulse signal P6 is input, a clock terminal IK to which the clock signal K3 is input, a setting transistor Tq, and first and second transistors T1 and T2. The first drive terminal Xn+2 may be connected to the first input terminal I1 via the first transistor T1, the second drive terminal Yn+2 may be connected to the second input terminal I2 via the second transistor T2, and the setting terminal Un+2 that outputs Qn+2 may be connected to the clock terminal IK via the setting transistor Tq.

[0021] As shown in FIG. 2, during the first period L1, the first and second pulse signals P1 and P2 may be sequentially activated while the clock signal K1 remains active. In FIG. 2, the first and second pulse signals P1 and P2 have the same pulse width but different phases, and the pulse width of the clock signal K1 is a natural number multiple (e.g., twice) of the pulse widths of the first and second pulse signals P1 and P2, but this is not a limitation. Furthermore, the activation (rising) timing of the clock signal K1 and the activation (rising) timing of the first pulse signal P1 are synchronized, but this is not a limitation.

[0022] The phase shift between the first and second pulse signals may correspond to one horizontal scanning period. The periods of the clock signal K1 and the first and second pulse signals P1 and P2 may be equal. In FIG. 2, as an example, the clock signal K1 has a period of 6H and is active 4H, and the first and second pulse signals P1 and P2 have a period of 6H and are active 2H. 1H is one horizontal scanning period.

[0023] As shown in FIG. 2, the setting signal Qn may be active during the second period L2, and the pulses of the first and second pulse signals P1 and P2 may be thinned out during the second period L2.

[0024] A group of clock signals (K1 to KK3) with two or more phases including clock signal K1 and a group of pulse signals (P1 to P6) with three or more phases including first and second pulse signals P1 and P2 may be input to driver circuit 20. The number of phases of the group of clock signals (three phases, K1 to K3, in FIG. 2) may be less than the number of phases of the group of pulse signals (six phases, P1 to P6, in FIG. 2).

[0025] As shown in FIGS. 1 to 3, the n-th stage unit circuit Jn has a control node NZ connected to the gate terminal of the setting transistor Tq and a bootstrap capacitance (transformer capacitance) Cq, and the control node NZ may be connected to the setting terminal Un via the bootstrap capacitance Cq. When the control node NZ becomes active during the set period LS (the period during which Qn-1 is active), the setting transistor Tq turns on and the bootstrap capacitance Cq is charged, and the control node NZ may be boosted by the rising edge of the clock signal K1. This increases the driving capability of the setting transistor Tq and stabilizes the setting signal Qn. That is, the pulse of the clock signal K1 is stably output from the setting terminal Un.

[0026] The control node NZ may be connected to the gate terminals of the first and second transistors T1 and T2. In this case, the control node NZ is boosted by the bootstrap capacitance Cq, thereby increasing the drive capabilities of the first and second transistors T1 and T2 and stabilizing the first and second drive signals Va and Vb. That is, the pulses of the first pulse signal P1 are stably output from the first drive terminal Xn, and the pulses of the second pulse signal P2 are stably output from the second drive terminal Yn.

[0027] As shown in Figures 1 to 3, the driver circuit 20 has a first power supply line D1 (e.g., a high-potential side power supply line) and a second power supply line (e.g., a low-potential side power supply line), and the n-th stage unit circuit Jn has a third transistor T3 to which a set signal Qn-1 from the previous stage is input, and a fourth transistor T4 to which a reset signal Qn+2 from the subsequent stage is input, and the control node NZ may be connected to the first power supply line D1 via the third transistor T3 and to the second power supply line D2 via the fourth transistor T4.

[0028] The n-th stage unit circuit Jn may have an inversion node NR whose state is inverted with respect to the control node NZ, and a plurality of pull-down transistors T11 to T14 whose gate terminals are connected to the inversion node NR.

[0029] The setting terminal Un and the control node NZ may be connected to the second power supply line D2 (low potential side power supply line) via different pull-down transistors. That is, the setting terminal Un may be connected to the second power supply line D2 via the pull-down transistor T13, and the control node NZ may be connected to the second power supply line D2 via the pull-down transistor T14.

[0030] In this way, during the period LZ when the control node NZ is active (high), the pull-down transistors T13 and T14 are turned off, while the control node NZ becomes inactive (low) (the inversion node NR becomes active high), turning the setting transistor Tq off and the pull-down transistors T13 and T14 on. As a result, the potentials of the setting terminal Un and the control node NZ are maintained at low level regardless of the level of the clock signal K1, and the setting signal Qn is maintained inactive (low).

[0031] The first drive terminal Xn and the second drive terminal Yn may be connected to the second power supply line D2 via different pull-down transistors, i.e., the first drive terminal Xn may be connected to the second power supply line D2 via the pull-down transistor T11, and the second drive terminal Yn may be connected to the second power supply line D2 via the pull-down transistor T12.

[0032] In this manner, during the period LZ when the control node NZ is active (high), the pull-down transistors T11 and T12 are turned off, while the control node NZ becomes inactive (low) (the inversion node NR becomes active high), turning off the first and second transistors T1 and T2 and turning on the pull-down transistors T11 and T12. As a result, the potentials of the first and second drive terminals Xn and Yn are maintained at low level regardless of the levels of the first and second pulse signals P1 and P2, and the first and second drive signals Va and Vb are maintained inactive (low).

[0033] In the n-th stage unit circuit Jn, the inverting node NR may be connected to a first power supply line D1 (high-potential side power supply line) via a diode-connected transistor T9 (power supply transistor) and to a second power supply line D2 (low-potential side power supply line) via a transistor T10 (inverting transistor), and the gate terminal of the transistor T10 may be connected to a control node NZ. The transistors T9 to T14 may form an inverting circuit.

[0034] 3 to 5, the setting transistor Tq, the transistors T1 to T4, and the transistors T9 to T14 may be n-channel transistors, but are not limited to this. These transistors may be p-channel transistors, or may be a combination of n-channel and p-channel transistors.

[0035] As shown in FIG. 1, the driver circuit 20 may include a signal generating circuit 30 that generates clock signals K1 to K6 and first to third pulse signals P1 to P3, and a group of input lines 25 that transmit the clock signals K1 to K6 and the first to third pulse signals P1 to P3.

[0036] Fig. 6 is a block diagram showing the configuration of a display device according to this embodiment. As shown in Fig. 6, a display device 50 according to this embodiment may include a display unit 40, a data driver 2, a scan driver 3, and a controller 4. The display unit 40 may be capable of setting a refresh rate for each region. The driver circuit 20 may include a scan driver 3 (shift register circuit), a controller 4, and an input line group 25. The controller 4 may include a signal generating circuit 30 and a processor 35. The controller 4 may be a timing controller.

[0037] In the display device 50, the display unit 40 may have a plurality of liquid crystal capacitors (including pixel electrodes, counter electrodes, and a liquid crystal layer), and the driver circuit 20 may be a scan driver that drives the scan lines of the display unit 40. The display device 50 may also include a data driver 35 that drives the data lines of the display unit 40.

[0038] In the display device 50, the display unit 40 may have a plurality of light-emitting elements (for example, organic light-emitting diodes, quantum dot light-emitting diodes), and the driver circuit 20 may be a scan driver or a light-emission control driver.

[0039] Fig. 7 is a schematic diagram showing the configuration of a driver circuit according to this embodiment. Fig. 8 is a timing chart showing the operation of the driver circuit according to this embodiment. In Figs. 1 and 2, the region including signal lines (scanning lines) Ga to Gd has a low refresh rate, and the region including signal lines (scanning lines) Ge and Gf has a high refresh rate. However, as shown in Figs. 7 and 8, by thinning out the pulses of pulse signals P1, P2, P5, and P6, the region including signal lines (scanning lines) Ga to Gd may have a high refresh rate, and the region including signal lines (scanning lines) Ge and Gf may have a low refresh rate.

[0040] As described above, in the display device 50 including the driver circuit 20, by thinning out pulses (setting the pulse pattern) for the first to sixth pulse signals P1 to P6 from a reference pulse pattern when the reference refresh rate (for example, 60 Hz) is set for all regions, it is possible to arbitrarily set the refresh rate (rewriting frequency) for each of the multiple regions of the display unit 40. The pulse pattern setting may be performed by cooperation between the signal generating circuit 30 and the controller 45.

[0041] FIG. 9 is a schematic diagram showing the configuration of a driver circuit according to this embodiment. FIG. 10 is a timing chart showing the operation of the driver circuit according to this embodiment. As shown in FIG. 9, the n-th stage unit circuit Jn may have a first node N1 that is activated during the set period LS in addition to a control node NZ. In this case, the control node NZ may be connected to the gate terminal of the set transistor Tq, and the first node N1 may be connected to the gate terminals of the first and second transistors T1 and T2. The potential of the control node NZ is Vz, and the potential of the first node N1 is V1.

[0042] The n-th stage unit circuit Jn shown in FIG. 9 may have first and second capacitances C1 and C2, and the gate terminal of the first transistor T1 may be connected to the first drive terminal Xn via the first capacitance C1, and the gate terminal of the second transistor T2 may be connected to the second drive terminal Yn via the second capacitance C2.

[0043] The n-th stage unit circuit Jn may have third and fifth transistors T3 and T5 to which a set signal is input from the previous stage, and fourth and sixth transistors T4 and T6 to which a reset signal is input from the subsequent stage.

[0044] The control node NZ may be connected to a first power supply line D1 (high potential side power supply line) via a third transistor T3, and may be connected to a second power supply line (low potential side power supply line) via a fourth transistor T4. The first node N1 may be connected to the first power supply line D1 via a fifth transistor T5, and may be connected to a second power supply line D2 via a sixth transistor T6.

[0045] The n-th stage unit circuit Jn may have an inversion node NR whose state is inverted with respect to the control node NZ, and a plurality of pull-down transistors T11 to T15 whose gate terminals are connected to the inversion node NR.

[0046] The setting terminal Un, the control node NZ, and the first node N1 may be connected to the second power supply line D2 via different pull-down transistors. That is, the setting terminal Un may be connected to the second power supply line D2 via the pull-down transistor T13, the control node NZ may be connected to the second power supply line D2 via the pull-down transistor T14, and the first node N1 may be connected to the second power supply line D2 via the pull-down transistor T15.

[0047] The first drive terminal Xn and the second drive terminal Yn may be connected to the second power supply line D2 via different pull-down transistors, i.e., the first drive terminal Xn may be connected to the second power supply line D2 via the pull-down transistor T11, and the second drive terminal Yn may be connected to the second power supply line D2 via the pull-down transistor T12.

[0048] 9 and 10, during the set period LS (the period during which Qn-1 is active), the first node N1 becomes active, turning on the first and second transistors T1 and T2 and charging the first and second capacitors C1 and C2, and the first node N1 may be boosted by the rising edges of the first and second pulse signals P1 and P2. This increases the drive capabilities of the first and second transistors T1 and T2 and stabilizes the first and second drive signals Va and Vb. That is, the pulse of the first pulse signal P1 is stably output from the first drive terminal Xn, and the pulse of the second pulse signal P2 is stably output from the second drive terminal Yn.

[0049] In addition to the control node NZ, a first node N1 that is activated during the set period LS is provided, and the gate terminals of the first and second transistors T1 and T2 are connected to the first node N1. This reduces the load on the control node NZ and suppresses the influence of the first and second pulse signals P1 and P2 on the control node NZ, thereby further stabilizing the set signal Qn.

[0050] FIG. 11 is a schematic diagram showing the configuration of a driver circuit according to this embodiment. FIG. 12 is a timing chart showing the operation of the driver circuit according to this embodiment. As shown in FIG. 11, the n-th stage unit circuit Jn may have a first node N1 that is activated during the set period LS in addition to a control node NZ. In this case, the control node NZ may be connected to the gate terminal of the set transistor Tq, and the first node N1 may be connected to the gate terminals of the first and second transistors T1 and T2. The potential of the control node NZ is Vz, and the potential of the first node N1 is V1.

[0051] The n-th stage unit circuit Jn shown in FIG. 11 may have a control capacitance Ck and a control transistor Tk, and the first node N1 may be connected to the clock terminal IK via the control capacitance Ck and the control transistor Tk.

[0052] The n-th stage unit circuit Jn may have third and fifth transistors T3 and T5 to which a set signal is input from the previous stage, and fourth and sixth transistors T4 and T6 to which a reset signal is input from the subsequent stage.

[0053] The control node NZ may be connected to a first power supply line D1 (high potential side power supply line) via a third transistor T3, and may be connected to a second power supply line (low potential side power supply line) via a fourth transistor T4. The first node N1 may be connected to the first power supply line D1 via a fifth transistor T5, and may be connected to a second power supply line D2 via a sixth transistor T6.

[0054] The n-th stage unit circuit Jn may have an inversion node NR whose state is inverted with respect to the control node NZ, and a plurality of pull-down transistors T11 to T15 whose gate terminals are connected to the inversion node NR.

[0055] The setting terminal Un, the control node NZ, and the first node N1 may be connected to the second power supply line D2 via different pull-down transistors. That is, the setting terminal Un may be connected to the second power supply line D2 via the pull-down transistor T13, the control node NZ may be connected to the second power supply line D2 via the pull-down transistor T14, and the first node N1 may be connected to the second power supply line D2 via the pull-down transistor T15.

[0056] The first drive terminal Xn and the second drive terminal Yn may be connected to the second power supply line D2 via different pull-down transistors, i.e., the first drive terminal Xn may be connected to the second power supply line D2 via the pull-down transistor T11, and the second drive terminal Yn may be connected to the second power supply line D2 via the pull-down transistor T12.

[0057] 11 and 12, the control node NZ becomes active during the set period LS, turning on the setting transistor Tq and charging the bootstrap capacitance Cq, and the rising edge of the clock signal K1 may boost the control node NZ. This increases the driving capability of the setting transistor Tq and stabilizes the setting signal Qn. In other words, the pulse of the clock signal K1 is stably output from the setting terminal Un.

[0058] During the set period LS, the first node N1 becomes active, turning on the control transistor Tk and the first and second transistors T1 and T2, charging the control capacitance Ck, and the rising edge of the clock signal K1 may boost the first node N1. That is, the control capacitance Ck boosts (bootstraps) the gate potentials of the first and second transistors T1 and T2. This increases the drive capabilities of the first and second transistors T1 and T2, stabilizing the first and second drive signals Va and Vb. That is, the pulse of the first pulse signal P1 is stably output from the first drive terminal Xn, and the pulse of the second pulse signal P2 is stably output from the second drive terminal Yn.

[0059] 11, in addition to the control node NZ, a first node N1 that is activated during the set period LS is provided, and the control capacitor Ck and the gate terminals of the first and second transistors T1 and T2 are connected to the first node N1. This reduces the load on the control node NZ and suppresses the influence of the first and second pulse signals P1 and P2 on the control node NZ. This further stabilizes the set signal Qn.

[0060] FIG. 13 is a schematic diagram showing the configuration of a driver circuit according to this embodiment. FIG. 14 is a circuit diagram showing the configuration of a unit circuit of the driver circuit according to this embodiment. FIG. 15 is a timing chart showing the operation of the driver circuit according to this embodiment. As shown in FIGS. 13 and 14, the n-th stage unit circuit Jn may have a second node N2 that is activated during the set period LS in addition to a control node NZ and a first node N1. The first node N1 may be connected to the gate terminal of the first transistor T1, and the second node N2 may be connected to the gate terminal of the second transistor T2. Let Vz be the potential of the control node NZ, V1 be the potential of the first node N1, and V2 be the potential of the second node N2.

[0061] The n-th stage unit circuit Jn shown in Figures 13 and 14 may include a register circuit Hn including a control node NZ and a setting terminal Un, and an output circuit On including first and second nodes N1 and N2 and first and second drive terminals Xn and Yn.

[0062] The register circuit Hn may have a setting terminal Un that outputs a setting signal Qn to a unit circuit of another stage (such as Jn+1), a clock terminal IK to which a clock signal K1 is input, a setting transistor Tq, and a bootstrap capacitance (transformer capacitance) Cq. The setting terminal Un may be connected to the clock terminal IK via the setting transistor Tq. The control node NZ may be connected to the setting terminal Un via the bootstrap capacitance Cq.

[0063] The register circuit Hn may have a third transistor T3 to which a set signal (Qn-1) from the previous stage is input, and a fourth transistor T4 to which a reset signal (Qn+1) from the next stage is input. The control node NZ may be connected to a first power supply line D1 (high potential side power supply line, VDD line) via the third transistor T3, and may be connected to a second power supply line D2 (low potential side power supply line, VSS line) via the fourth transistor T4.

[0064] The register circuit Hn may have a discharge transistor Tu to which a reset signal (Qn+1) is input from the subsequent stage. The setting terminal Un may be connected to the second power supply line D2 via the discharge transistor Tu.

[0065] The register circuit Hn may include a third node N3 whose state is inverted with respect to the control node NZ, and multiple pull-down transistors T13-T14 whose gate terminals are connected to the third node N3. The setting terminal Un and the control node NZ are connected to the second power supply line D2 via different pull-down transistors. That is, the setting terminal Un may be connected to the second power supply line D2 via the pull-down transistor T13, and the control node NZ may be connected to the second power supply line D2 via the pull-down transistor T14.

[0066] In the register circuit Hn, the third node N3 may be connected to a first power supply line D1 (high potential side power supply line) via a diode-connected transistor T9 (power supply transistor) and to a second power supply line D2 (low potential side power supply line) via a transistor T10 (inversion transistor), and the gate terminal of the transistor T10 may be connected to a control node NZ.

[0067] The output circuit On may have a first input terminal I1 to which a first pulse signal P1 is input, a second input terminal I2 to which a second pulse signal P2 is input, first and second transistors T1 and T2, a first drive terminal Xn to output a first drive signal Va to a signal line Ga of the display unit 40, and a second drive terminal Yn to output a second drive signal Vb to a signal line Gb of the display unit 40. The first drive terminal Xn may be connected to the first input terminal I1 via the first transistor T1, and the second drive terminal Yn may be connected to the second input terminal I2 via the second transistor T2.

[0068] In the register circuit Hn, when the control node NZ becomes active during the set period LS, the setting transistor Tq turns on and the bootstrap capacitance Cq is charged, and the rising edge of the clock signal K1 boosts the control node NZ. This increases the driving capability of the setting transistor Tq and stabilizes the setting signal Qn. In other words, the pulse of the clock signal K1 is stably output from the setting terminal Un.

[0069] The output circuit On may have first and second capacitances C1 and C2, and the gate terminal of the first transistor T1 may be connected to the first drive terminal Xn via the first capacitance C1, and the gate terminal of the second transistor T2 may be connected to the second drive terminal Yn via the second capacitance C2.

[0070] The output circuit On may have fifth and seventh transistors T5 and T7 to which a set signal (Qn-1) from the previous stage is input, and sixth and eighth transistors T6 and T8 to which a reset signal (Q+2) from the next stage is input. The first node N1 may be connected to the first power supply line D1 via the fifth transistor T5 and to the second power supply line D2 via the sixth transistor T6. The second node N2 may be connected to the first power supply line D1 via the seventh transistor T7 and to the second power supply line D2 via the eighth transistor T8.

[0071] The output circuit On may have a fourth node N4 whose state is inverted relative to the first and second nodes N1 and N2, and a plurality of pull-down transistors T11, T12, T15, and T16 whose gate terminals are connected to the fourth node N4.

[0072] The first and second nodes N1 and N2 may be connected to the second power supply line D2 via different pull-down transistors, i.e., the first node N1 may be connected to the second power supply line D2 via the pull-down transistor T15, and the second node N2 may be connected to the second power supply line D2 via the pull-down transistor T16.

[0073] The first and second drive terminals Xn and Yn may be connected to the second power supply line D2 via different pull-down transistors, i.e., the first drive terminal Xn may be connected to the second power supply line D2 via the pull-down transistor T11, and the second drive terminal Yn may be connected to the second power supply line D2 via the pull-down transistor T12.

[0074] In the output circuit On, the fourth node N4 may be connected to the first power supply line D1 (high potential side power supply line) via a diode-connected transistor T17 (power supply transistor) and to the second power supply line D2 (low potential side power supply line) via a transistor T18 (inverting transistor). The gate terminal of the transistor T18 may be connected to the first node N1 or the second node N2.

[0075] In the output circuit On, the first node N1 may become active during the set period LS, thereby turning the first transistor ON and charging the first capacitor C1, and the first node N1 may be boosted by the rising edge of the first pulse signal P1. Also, the second node N2 may become active during the set period LS, thereby turning the second transistor ON and charging the second capacitor C2, and the second node N2 may be boosted by the rising edge of the second pulse signal P2.

[0076] This increases the drive capabilities of the first and second transistors T1 and T2, stabilizing the first and second drive signals Va and Vb, so that the pulses of the first pulse signal P1 are stably output from the first drive terminal Xn, and the pulses of the second pulse signal P2 are stably output from the second drive terminal Yn.

[0077] In the driver circuit 20 shown in Figures 13 to 15, the setting signal Qn is active during the first period L1, and the first period L1 overlaps with at least a portion of the active period La of the first drive signal Va and at least a portion of the active period Lb of the second drive signal Vb.

[0078] In the driver circuit 20, the two signal lines Ga and Gb can be driven by the first and second drive signals Va and Vb generated by the output circuit On, which reduces the circuit scale of the driver circuit 20.

[0079] Each of the signals Ga to Gf ​​may be a scanning line, and each of the first and second drive signals Va and Vb may be a scan signal. The signal line Ga may be a (2n-1)-stage scanning line formed on the display unit 40, and the signal line Gb may be a (2n)-stage scanning line formed on the display unit 40.

[0080] In the n-th stage unit circuit Jn, the period LZ during which the gate terminal (control node NZ) of the setting transistor Tq remains active (High) may include the active period of the first drive signal Va and the active period of the second drive signal Vb.

[0081] In the driver circuit 20, the setting signal Qn may be active during the second period L2, and the first and second drive signals Va and Vb may be inactive during the second period L2. That is, full scanning may be performed to scan all of the multiple signal lines (including Ga to Gf), and partial scanning may be performed to scan only some of the multiple signal lines (including Ge and Gf). In this way, the refresh rate (rewriting frequency) can be changed for each region of the display unit 40 (including the signal lines Ga to Gf) to be driven.

[0082] As shown in FIG. 15, in the driver circuit 20, the first and second drive signals Va and Vb may be sequentially activated (rising from low to high) during a first period L1. A portion (e.g., the latter half) of the active period of the first drive signal Va may overlap with a portion (e.g., the first half) of the active period of the second drive signal Vb. The first drive signal Va may return to an inactive state (low) during the first period T1, and the second drive signal Vb may return to an inactive state (low) after the first period T1 ends. During the first period L1, the first and second pulse signals P1 and P2 may be sequentially activated while the clock signal K1 remains active.

[0083] 15, the first and second pulse signals P1 and P2 have the same pulse width but different phases, and the pulse width of the clock signal K1 is a natural number multiple (e.g., 1) of the pulse width of the first and second pulse signals P1 and P2, but is not limited to this. Also, the activation (rising) timing of the clock signal K1 and the activation (rising) timing of the first pulse signal P1 are synchronized, but are not limited to this.

[0084] In Figure 15, the phase difference between the first and second pulse signals P1 and P2 may be one horizontal scanning period (1H). As an example, the clock signal K1 is set to an active state of 2H with a period of 4H, and the first and second pulse signals P1 and P2 are set to an active state of 2H with a period of 6H. 1H may be one horizontal scanning period.

[0085] As shown in FIG. 15, the setting signal Qn may be active during the second period L2, and the pulses of the first and second pulse signals P1 and P2 may be thinned out during the second period L2.

[0086] A group of clock signals (K1-K2) with two or more phases including clock signal K1 and a group of pulse signals (P1-P6) with three or more phases including first and second pulse signals P1-P2 may be input to driver circuit 20. The number of phases of the group of clock signals (two phases, K1-K2 in FIG. 15) may be less than the number of phases of the group of pulse signals (six phases, P1-P6 in FIG. 15).

[0087] 13 and 14, the n-th stage unit circuit Jn includes a register circuit Hn including a control node NZ, an output circuit On including first and second nodes N1 and N2, and the gate terminal of the first transistor T1 is connected to the first node N1, and the gate terminal of the second transistor T2 is connected to the second node N2. This reduces the load on the control node NZ and suppresses the influence of the first and second pulse signals P1 and P2 on the control node NZ. This further stabilizes the setting signal Qn.

[0088] Furthermore, by providing the first and second nodes N1 and N2 in the output circuit On, it is possible to substantially eliminate the influence of the second pulse signal P2 on the first node N1 and the influence of the first pulse signal P1 on the second node N2, thereby further stabilizing the first and second drive signals Va and Vb.

[0089] The above-described embodiments are intended to be illustrative and explanatory, and not limiting, and many variations will be apparent to those skilled in the art based on these examples and descriptions.

[0090] The gist of this embodiment will be described below. In the following, "the above" includes the technical content disclosed in at least one of FIGS.

[0091] 〔summary〕 A driver circuit including a plurality of unit circuits and configured to drive a plurality of signal lines, the n-th stage unit circuit includes a setting terminal that outputs a setting signal to the other stage unit circuits, a first drive terminal that outputs a first drive signal to one of the plurality of signal lines, and a second drive terminal that outputs a second drive signal to another one of the plurality of signal lines; the setting signal is active during a first time period; The driver circuit, wherein the first period includes at least a portion of an active period of the first drive signal and at least a portion of an active period of the second drive signal.

[0092] the n-th stage unit circuit has a setting transistor having two conduction terminals to one of which a clock signal is input and the other of which is connected to the setting terminal; The driver circuit described above, wherein at least a part of an active period of the first drive signal and at least a part of an active period of the second drive signal overlap (are included) during a period in which the gate terminal of the setting transistor remains active.

[0093] the setting signal is active during a second time period; The driver circuit as described above, wherein during the second period, the first drive signal and the second drive signal are each inactive.

[0094] The setting signal has a function of a set signal, The driver circuit as described above, wherein the other stage is set during the first period and the second period.

[0095] The driver circuit as described above, wherein the first and second drive signals are sequentially activated within the first period.

[0096] The driver circuit described above, wherein a portion of an active period of the first drive signal overlaps with a portion of an active period of the second drive signal.

[0097] The driver circuit as described above, wherein during the first period, each of the first and second drive signals returns to an inactive state.

[0098] the first drive signal returns to inactive during the first period; The driver circuit as described above, wherein the second drive signal returns to inactive after the first period ends.

[0099] the n-th stage unit circuit has a first input terminal to which a first pulse signal is input, a second input terminal to which a second pulse signal is input, a clock terminal to which a clock signal is input, a setting transistor, and first and second transistors; the first drive terminal is connected to the first input terminal via the first transistor; the second drive terminal is connected to the second input terminal via the second transistor; The driver circuit described above, wherein the setting terminal is connected to the clock terminal via the setting transistor.

[0100] The driver circuit as described above, wherein in the first period, the clock signal maintains an active state, and the first and second pulse signals are sequentially activated.

[0101] the first and second pulse signals have the same pulse width but different phases; The driver circuit as described above, wherein the pulse width of the clock signal is a natural number multiple of the pulse widths of the first and second pulse signals.

[0102] The driver circuit as described above, wherein the activation timing of the clock signal and the activation timing of the first pulse signal are synchronized.

[0103] The driver circuit as described above, wherein the phase difference between the first and second pulse signals corresponds to one horizontal scanning period.

[0104] the setting signal is active during a second time period; The driver circuit described above, wherein the pulses in the second period of each of the first and second pulse signals are thinned out.

[0105] The driver circuit described above receives as input a group of clock signals of two or more phases including the clock signal, and a group of pulse signals of three or more phases including the first and second pulse signals.

[0106] The driver circuit as described above, wherein the number of phases of the clock signal group is smaller than the number of phases of the pulse signal group.

[0107] each of the plurality of signal lines is a scanning line; The driver circuit as described above, wherein each of the first drive signal and the second drive signal is a scan signal.

[0108] The driver circuit as described above, wherein the plurality of signal lines are formed in a display section in which a refresh rate can be set for each area.

[0109] The driver circuit described above performs full scanning, which scans all of the plurality of signal lines, and partial scanning, which scans some of the plurality of signal lines.

[0110] the n-th stage unit circuit has a control node connected to a gate terminal of the setting transistor and a bootstrap capacitance; The driver circuit as described above, wherein the control node is connected to the setting terminal via the bootstrap capacitance.

[0111] The driver circuit described above, wherein the control node becomes active during a set period, thereby turning on the setting transistor and charging the bootstrap capacitance, and the control node is boosted by the rising edge of the clock signal.

[0112] The driver circuit as described above, wherein the control node is connected to the gate terminals of the first and second transistors, respectively.

[0113] a first power line and a second power line; the n-th stage unit circuit has a third transistor to which a set signal from a previous stage is input, and a fourth transistor to which a reset signal from a subsequent stage is input, The driver circuit described above, wherein the control node is connected to the first power supply line via the third transistor and is connected to the second power supply line via the fourth transistor.

[0114] The driver circuit as described above, wherein the nth stage unit circuit has a first node that is activated during a set period in addition to the control node.

[0115] the n-th stage unit circuit has a control capacitance and a control transistor, The driver circuit described above, wherein the first node is connected to the clock terminal via the control capacitance and the control transistor.

[0116] The driver circuit as described above, wherein the first node is connected to the gate terminals of the first and second transistors.

[0117] the n-th stage unit circuit has first and second capacitors; a gate terminal of the first transistor is connected to the first drive terminal via the first capacitance; The driver circuit as described above, wherein the gate terminal of the second transistor is connected to the second drive terminal via the second capacitance.

[0118] a first power line and a second power line; the n-th stage unit circuit has third and fifth transistors to which a set signal is input from a previous stage side, and fourth and sixth transistors to which a reset signal is input from a subsequent stage side, the control node is connected to the first power supply line via the third transistor and to the second power supply line via the fourth transistor; The driver circuit described above, wherein the first node is connected to the first power supply line via the fifth transistor and is connected to the second power supply line via the sixth transistor.

[0119] the first power supply line is a high-potential side power supply line, and the second power supply line is a low-potential side power supply line, the n-th stage unit circuit has an inversion node whose state is inverted with respect to the control node, and a plurality of pull-down transistors whose gate terminals are connected to the inversion node; The driver circuit as described above, wherein the setting terminal and the control node are connected to the second power supply line via different pull-down transistors.

[0120] The driver circuit as described above, wherein the first drive terminal and the second drive terminal are connected to the second power supply line via different pull-down transistors.

[0121] the n-th stage unit circuit has a second node that is activated in the set period in addition to the control node and the first node; the first node is connected to a gate terminal of the first transistor; The driver circuit as described above, wherein the second node is connected to a gate terminal of the second transistor.

[0122] a first power line and a second power line; the n-th stage unit circuit includes a register circuit including the control node and a setting terminal, and an output circuit including the first and second nodes and first and second drive terminals; the register circuit has a third transistor to which a set signal is input from a previous stage side and a fourth transistor to which a reset signal is input from a subsequent stage side, The driver circuit described above, wherein the control node is connected to the first power supply line via the third transistor and is connected to the second power supply line via the fourth transistor.

[0123] the register circuit has a discharge transistor to which a reset signal is input from a subsequent stage, The driver circuit described above, wherein the setting terminal is connected to the second power supply line via the discharge transistor.

[0124] the first power supply line is a high-potential side power supply line, and the second power supply line is a low-potential side power supply line, the register circuit has a third node whose state is inverted relative to the control node, and a plurality of pull-down transistors whose gate terminals are connected to the third node; The driver circuit as described above, wherein the setting terminal and the control node are connected to the second power supply line via different pull-down transistors.

[0125] the output circuit has fifth and seventh transistors to which a set signal is input from a preceding stage side, and sixth and eighth transistors to which a reset signal is input from a subsequent stage side, the first node is connected to the first power supply line via the fifth transistor and to the second power supply line via the sixth transistor; The driver circuit described above, wherein the second node is connected to the first power supply line via the seventh transistor and is connected to the second power supply line via the eighth transistor.

[0126] the output circuit has a fourth node whose state is inverted relative to the first node and the second node, and a plurality of pull-down transistors whose gate terminals are connected to the fourth node; The driver circuit as described above, wherein the first drive terminal and the second drive terminal are connected to the second power supply line via different pull-down transistors.

[0127] The driver circuit described above includes a signal generating circuit that generates the clock signal and the first and second pulse signals, and a group of input lines that transmit the clock signal and the first and second pulse signals.

[0128] A display device comprising the driver circuit described above.

[0129] The display device described above includes a display unit capable of setting a refresh rate for each area. [Explanation of symbols]

[0130] 20 Driver circuit 40 Display section Un setting terminal Xn 1st drive terminal Yn Second drive terminal Jn nth stage unit circuit Qn setting signal Va 1st drive signal Vb Second drive signal L1 1st period L2 2nd period

Claims

1. A driver circuit including a plurality of unit circuits and configured to drive a plurality of signal lines, the n-th stage unit circuit has a setting terminal that outputs a setting signal to the unit circuits of other stages, and a plurality of driving terminals including a first driving terminal that outputs a first driving signal to one of the plurality of signal lines and a second driving terminal that outputs a second driving signal to another one of the plurality of signal lines; the setting signal is active during a first time period; The driver circuit, wherein the first period includes at least a portion of an active period of the first drive signal and at least a portion of an active period of the second drive signal.

2. the n-th stage unit circuit has a setting transistor having two conduction terminals to one of which a clock signal is input and the other of which is connected to the setting terminal; 2. The driver circuit of claim 1, wherein at least a portion of an active period of the first drive signal and at least a portion of an active period of the second drive signal overlap during a period in which the gate terminal of the setting transistor remains active.

3. the setting signal is active during a second time period; The driver circuit of claim 1 , wherein during the second period, the first drive signal and the second drive signal are each inactive.

4. The setting signal has a function of a set signal, 4. The driver circuit according to claim 3, wherein other stages are set during the first period and the second period.

5. The driver circuit of claim 1 , wherein the first and second drive signals are sequentially activated within the first period.

6. The driver circuit of claim 5 , wherein a portion of an active period of the first drive signal overlaps with a portion of an active period of the second drive signal.

7. The driver circuit of claim 5 , wherein during the first period, the first and second drive signals each return to an inactive state.

8. the first drive signal returns to inactive during the first period; 6. The driver circuit of claim 5, wherein the second drive signal returns to inactive after the first period ends.

9. the n-th stage unit circuit has a first input terminal to which a first pulse signal is input, a second input terminal to which a second pulse signal is input, a clock terminal to which a clock signal is input, a setting transistor, a first transistor, and a second transistor; the first drive terminal is connected to the first input terminal via the first transistor; the second drive terminal is connected to the second input terminal via the second transistor; 2. The driver circuit according to claim 1, wherein the setting terminal is connected to the clock terminal via the setting transistor.

10. 10. The driver circuit according to claim 9, wherein, in the first period, the first and second pulse signals are sequentially activated while the clock signal remains active.

11. the first and second pulse signals have the same pulse width but different phases; 10. The driver circuit of claim 9, wherein the pulse width of the clock signal is a natural number multiple of the pulse widths of the first and second pulse signals.

12. 12. The driver circuit of claim 11, wherein the activation timing of the clock signal and the activation timing of the first pulse signal are synchronized.

13. 12. The driver circuit according to claim 11, wherein the phase shift between the first and second pulse signals corresponds to one horizontal scanning period.

14. the setting signal is active during a second time period; 10. The driver circuit according to claim 9, wherein the pulses in the second period of each of the first and second pulse signals are thinned out.

15. 10. The driver circuit according to claim 9, wherein a group of clock signals having two or more phases including the clock signal and a group of pulse signals having three or more phases including the first and second pulse signals are input.

16. 16. The driver circuit of claim 15, wherein the number of phases of the group of clock signals is less than the number of phases of the group of pulse signals.

17. each of the plurality of signal lines is a scanning line; 2. The driver circuit of claim 1, wherein each of the first and second drive signals is a scan signal.

18. 18. The driver circuit according to claim 17, wherein the plurality of signal lines are formed in a display section in which a refresh rate can be set for each area.

19. 19. The driver circuit according to claim 18, wherein full scanning is performed to scan all of the plurality of signal lines, and partial scanning is performed to scan some of the plurality of signal lines.

20. the n-th stage unit circuit has a control node connected to a gate terminal of the setting transistor and a bootstrap capacitance; 10. The driver circuit of claim 9, wherein the control node is connected to the setting terminal via the bootstrap capacitance.

21. 21. The driver circuit according to claim 20, wherein the control node becomes active during a set period, thereby turning on the setting transistor and charging the bootstrap capacitance, and the control node is boosted by the rising edge of the clock signal.

22. 21. The driver circuit of claim 20, wherein the control node is connected to a gate terminal of each of the first and second transistors.

23. a first power supply line and a second power supply line; the n-th stage unit circuit has a third transistor to which a set signal from a previous stage is input, and a fourth transistor to which a reset signal from a subsequent stage is input, 21. The driver circuit according to claim 20, wherein the control node is connected to the first power supply line via the third transistor and to the second power supply line via the fourth transistor.

24. 21. The driver circuit according to claim 20, wherein the nth stage unit circuit has a first node that is activated in a set period in addition to the control node.

25. the n-th stage unit circuit has a control capacitance and a control transistor, 25. The driver circuit of claim 24, wherein the first node is connected to the clock terminal via the control capacitance and the control transistor.

26. 25. The driver circuit of claim 24, wherein the first node is connected to a gate terminal of each of the first and second transistors.

27. the n-th stage unit circuit has first and second capacitors; a gate terminal of the first transistor is connected to the first drive terminal via the first capacitance; 27. The driver circuit of claim 26, wherein the gate terminal of the second transistor is connected to the second drive terminal through the second capacitance.

28. a first power supply line and a second power supply line; the n-th stage unit circuit has third and fifth transistors to which a set signal is input from a preceding stage side, and fourth and sixth transistors to which a reset signal is input from a subsequent stage side, the control node is connected to the first power supply line via the third transistor and to the second power supply line via the fourth transistor; 25. The driver circuit according to claim 24, wherein the first node is connected to the first power supply line via the fifth transistor and to the second power supply line via the sixth transistor.

29. the first power supply line is a high-potential side power supply line, and the second power supply line is a low-potential side power supply line, the n-th stage unit circuit has an inversion node whose state is inverted with respect to the control node, and a plurality of pull-down transistors whose gate terminals are connected to the inversion node; 24. The driver circuit of claim 23, wherein the setting terminal and the control node are connected to the second power supply line through different pull-down transistors.

30. 30. The driver circuit of claim 29, wherein the first drive terminal and the second drive terminal are connected to the second power supply line through different pull-down transistors.

31. the n-th stage unit circuit has a second node that is activated in the set period in addition to the control node and the first node; the first node is connected to a gate terminal of the first transistor; 25. The driver circuit of claim 24, wherein the second node is connected to a gate terminal of the second transistor.

32. a first power supply line and a second power supply line; the n-th stage unit circuit includes a register circuit including the control node and a setting terminal, and an output circuit including the first and second nodes and first and second drive terminals; the register circuit has a third transistor to which a set signal is input from a previous stage side, and a fourth transistor to which a reset signal is input from a subsequent stage side, 32. The driver circuit of claim 31, wherein the control node is connected to the first power supply line via the third transistor and to the second power supply line via the fourth transistor.

33. the register circuit has a discharge transistor to which a reset signal is input from a subsequent stage, 33. The driver circuit according to claim 32, wherein the setting terminal is connected to the second power supply line via the discharge transistor.

34. the first power supply line is a high-potential side power supply line, and the second power supply line is a low-potential side power supply line, the register circuit has a third node whose state is inverted relative to the control node, and a plurality of pull-down transistors whose gate terminals are connected to the third node; 33. The driver circuit of claim 32, wherein the setting terminal and the control node are connected to the second power supply line through different pull-down transistors.

35. the output circuit has fifth and seventh transistors to which a set signal is input from a preceding stage side, and sixth and eighth transistors to which a reset signal is input from a subsequent stage side, the first node is connected to the first power supply line via the fifth transistor and to the second power supply line via the sixth transistor; 33. The driver circuit according to claim 32, wherein the second node is connected to the first power supply line via the seventh transistor and to the second power supply line via the eighth transistor.

36. the output circuit has a fourth node whose state is inverted relative to the first node and the second node, and a plurality of pull-down transistors whose gate terminals are connected to the fourth node; 35. The driver circuit of claim 34, wherein the first drive terminal and the second drive terminal are connected to the second power supply line through different pull-down transistors.

37. 10. The driver circuit according to claim 9, comprising: a signal generating circuit that generates the clock signal and the first and second pulse signals; and a group of input lines that transmit the clock signal and the first and second pulse signals.

38. A display device comprising a driver circuit according to any one of claims 1 to 37.

39. 39. The display device according to claim 38, comprising a display section in which the refresh rate can be set for each region.

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