Driver circuit and display device

Abstract

To facilitate control for partial output of a scanning signal or the like.SOLUTION: The driver circuit is a driver circuit that includes a plurality of stages of unit circuits and drives a plurality of signal lines, in which an nth-stage unit circuit includes an input terminal to which a clock signal is input, a drive terminal that outputs a drive signal to one of the plurality of signal lines, a first node, a first transistor whose gate terminal is connected to the first node, a set transistor whose gate terminal receives a set signal from another stage, and a control terminal, the input terminal being connected to the drive terminal via the first transistor, the control terminal is connected to the first node via the set transistor, and a first enable signal that defines whether output of the drive signal is enabled or disabled is input to the control terminal.SELECTED DRAWING: Figure 3A

Description

[Technical Field]

[0001] The present disclosure relates to driver circuits. [Background technology]

[0002] Patent Document 1 discloses a partial output method in which a driver circuit of a display device outputs a partial scanning signal. [Prior art documents] [Patent documents]

[0003] [Patent Document 1] Japanese Patent Publication No. 2011-209714 Summary of the Invention [Problem to be solved by the invention]

[0004] The conventional method requires setting the waveform of the clock signal, and has the problem that it is not easy to control partial output. [Means for solving the problem]

[0005] A driver circuit according to one embodiment of the present disclosure is a driver circuit comprising a plurality of unit circuits in multiple stages, which drives a plurality of signal lines, wherein the nth stage unit circuit comprises an input terminal to which a clock signal is input, a drive terminal to which a drive signal is output to one of the plurality of signal lines, a first node, a first transistor having a gate terminal connected to the first node, a set transistor having a gate terminal to which a set signal from another stage is input, and a control terminal, wherein the input terminal is connected to the drive terminal via the first transistor, the control terminal is connected to the first node via the set transistor, and a first enable signal that determines whether the output of the drive signal is enabled or disabled is input to the control terminal. [Effects of the Invention]

[0006] This driver circuit facilitates control for partial output. [Brief explanation of the drawings]

[0007] [Figure 1] FIG. 2 is a schematic diagram showing the configuration of a driver circuit according to the present embodiment. [Figure 2] 4 is a timing chart showing the operation of the driver circuit according to the present embodiment. [Figure 3A] FIG. 2 is a circuit diagram showing the configuration of a unit circuit of a driver circuit according to the present embodiment. [Figure 3B] FIG. 2 is a circuit diagram showing the configuration of a unit circuit of a driver circuit according to the present embodiment. [Figure 4] FIG. 2 is a schematic diagram showing the configuration of a driver circuit according to the present embodiment. [Figure 5] 4 is a timing chart showing the operation of the driver circuit according to the present embodiment. [Figure 6] 1 is a block diagram showing a configuration of a display device according to an embodiment of the present invention. [Figure 7] FIG. 2 is a schematic diagram showing the configuration of a driver circuit according to the present embodiment. [Figure 8] 4 is a timing chart showing the operation of the driver circuit according to the present embodiment. [Figure 9] 4 is a timing chart showing the operation of the driver circuit according to the present embodiment. [Figure 10] FIG. 2 is a schematic diagram showing the configuration of a driver circuit according to the present embodiment. [Figure 11] 4 is a timing chart showing the operation of the driver circuit according to the present embodiment. [Figure 12] FIG. 11 is a circuit diagram showing a configuration example of a part (two adjacent unit circuits) of FIG. [Figure 13] FIG. 2 is a schematic diagram showing the configuration of a driver circuit according to the present embodiment. [Figure 14A] FIG. 2 is a circuit diagram showing a configuration example of a unit circuit. [Figure 14B] FIG. 2 is a circuit diagram showing a configuration example of a unit circuit. [Figure 15] 4 is a timing chart showing the operation of the driver circuit according to the present embodiment. DETAILED DESCRIPTION OF THE INVENTION

[0008] FIG. 1 is a schematic diagram showing the configuration of a driver circuit according to this embodiment. FIG. 2 is a timing chart showing the operation of the driver circuit according to this embodiment. FIGS. 3A and 3B are circuit diagrams showing the configuration of a unit circuit of the driver circuit according to this embodiment. As shown in FIGS. 1 to 3A and 3B, the driver circuit 20 is a driver circuit that includes multiple stages of unit circuits (Jn, Jn-1, Jn+1, etc.) and drives multiple signal lines (Ga to Gc, etc.). The n-th stage unit circuit Jn includes an input terminal IT to which a clock signal K1 is input, a drive terminal Xn to which a drive signal Va is output to one of the multiple signal lines, a first node N1, a first transistor T1 whose gate terminal is connected to the first node N1, a set transistor TS to which a set signal (e.g., Qn-2) from another stage is input, and a control terminal CT.

[0009] The input terminal IT is connected to the drive terminal Xn via the first transistor T1. The control terminal CT is connected to the first node N1 via the set transistor TS. A first enable signal E1 that determines whether the output of the drive signal Xn is enabled or disabled is input to the control terminal CT.

[0010] In this way, by defining whether the output of the drive signal Xn is valid or invalid by the first enable signal E1 input to the set transistor TS, control for partial output becomes easy.

[0011] Hereinafter, n is a natural number, and the voltage at the first node N1 of the unit circuit Jn is Vn, the voltage at the first node N1 of the unit circuit Jn+1 is Vn+1, etc. When i is a natural number, the notation "n+i" or "ni" can mean the unit circuit at the (n+i)th stage or the unit circuit at the (ni)th stage.

[0012] As shown in Figures 3A and 3B, the nth stage unit circuit Jn may include a clock terminal IK to which a clock signal K1 is input, a setting terminal Un to output a setting signal Qn to a unit circuit of another stage, a setting node NQ, a setting transistor Tq whose gate terminal is connected to the setting node NQ, and a second transistor T2 whose gate terminal receives a set signal (e.g., Qn-2).

[0013] The clock terminal IK may be connected to the setting terminal Un via the setting transistor Tq. The setting node NQ may be connected to one of two conduction terminals (source terminal and drain terminal) of the second transistor T2, and the gate terminal of the second transistor T2 may be connected to the other of these two conduction terminals. The second transistor T2 may be diode-connected.

[0014] 3A and other figures, the second transistor T2 is diode-connected, but this is not limiting. One of the conduction terminals of the second transistor T2 may be connected to the setting node NQ, and the other (the drain terminal in the case of an N-channel T2) may be connected to the high-potential power supply line.

[0015] The n-th stage unit circuit Jn may include a first capacitance C1 and a setting capacitance Cq. The first node N1 may be connected to the drive terminal Xn via the first capacitance C1. The setting node NQ may be connected to the setting terminal Un via the setting capacitance Cq.

[0016] The n-th stage unit circuit Jn may include an output circuit On including an input terminal IT, a drive terminal Xn, a first node N1 and a control terminal CT, and a register circuit Ln including a clock terminal IK, a setting terminal Un and a setting node NQ.

[0017] Each of the n-1th stage unit circuit Jn-1, the nth stage unit circuit Jn, and the n+1th stage unit circuit Jn+1 may include an output circuit On including an input terminal IT, a drive terminal Xn, a first node N1, and a control terminal CT, and a register circuit Ln including a clock terminal IK, a setting terminal Un, and a setting node NQ.

[0018] 2, in the n-th stage unit circuit Jn, the drive signal Va may be activated (the pulse of Va may rise) during the active period of the first enable signal E1. When the first enable signal E1 is active (High), the first node N1 becomes active (High) during the set period (the period when Qn-2 is active), turning on the first transistor T1, and therefore the clock signal K1 is output to the drive terminal Xn. Note that during the set period (the period when Qn-2 is active), the setting node NQ becomes active (High), turning on the setting transistor Tq, and therefore the clock signal K1 is also output to the setting terminal Un.

[0019] As shown in Figure 2, if the first enable signal E1 becomes inactive while the setting signal Qn output from the unit circuit Jn is active (if E1 falls from high to low while Qn is high), the first transistor T1 of the unit circuit Jn remains on and a pulse is output to the drive signal Va of the unit circuit Jn, but the first transistor T1 of the unit circuits Jn+1 and Jn+2 does not turn on, so no pulse is output to the drive signals Vb and Vc of the unit circuits Jn+1 and Jn+2. In other words, the output of the drive pulse stops.

[0020] As shown in FIG. 2, in the n-th stage unit circuit Jn, the drive signal Xn is not activated during the inactive period of the first enable signal E1. When the first enable signal E1 is inactive (low), the first node N1 is inactive (low) during the set period (the period when Qn-2 is active), and the first transistor T1 is turned off, so the clock signal K1 is not output to the drive terminal Xn. Note that even if the first enable signal E1 is inactive, a pulse of the clock signal K1 is output to the set terminal Un during the set period. In other words, the driver circuit 20 continues the shift operation (output of the Q signal) even when the first enable signal E1 becomes inactive (low).

[0021] In the example shown in FIGS. 1 and 2, the area including the signal line (scanning line) Ga has a high refresh rate, and the area including the signal lines (scanning lines) Gb and Gc has a low refresh rate, with the signal line Ga located at the edge of the high refresh rate area. For example, the drive signal Va supplied to the signal line Ga may be active 60 times per second (refresh rate: 60 Hz), while the drive signals Vb and Vc supplied to the signal lines Gb and Gc may each be active approximately 1 to 10 times per second (refresh rate: 1 to 10 Hz). It is also possible to display moving images in the high refresh rate area and still images in the low refresh rate area. The high refresh rate area may be 240 Hz, and the low refresh rate area may be 60 Hz.

[0022] During the active period of the first enable signal E1, the first node N1 becomes active by the set signal (Qn-2), turning the first transistor T1 ON and charging the first capacitor C1, and the first node N1 may be boosted by the rising edge of the clock signal K1. As a result, the driving capability of the first transistor T1 increases, the potential Vn of the first node N1 remains active High (the first transistor T1 is ON) until the reset period, and pulses of the clock signal K1 are accurately output to the driving terminal Xn.

[0023] The set signal (Qn-2) causes the setting node NQ to go active (High), turning on the setting transistor Tq and charging the setting capacitor Cq, and the rising edge of the clock signal K1 may boost the setting node NQ. This increases the driving capability of the setting transistor Tq and keeps the potential of the setting node NQ active High (the setting transistor Tq is ON) until the reset period, allowing the pulse of the clock signal K1 to be output to the setting terminal Un with high precision.

[0024] The driver circuit 20 includes a first power supply line D1 (e.g., a high-potential power supply line, VDD line) and a second power supply line D2 (e.g., a low-potential power supply line, VSS line), and the n-th stage unit circuit Jn has a reset transistor TR to which a reset signal (e.g., Qn+3) from the subsequent stage is input, and the first node N1 may be connected to the second power supply line D2 via the reset transistor TR. During the reset period, the potential of the first node N1 becomes inactive Low and the first transistor T1 is turned OFF, so that the clock signal K1 is not output to the drive terminal Xn.

[0025] The n-th stage unit circuit Jn has a third transistor T3 to which a reset signal (e.g., Qn+3) is input from the subsequent stage, and the setting node NQ may be connected to the second power supply line D2 via the third transistor T3. During the reset period, the potential of the setting node NQ becomes inactive low, and the setting transistor Tq is turned off, so that the clock signal K1 is not output to the setting terminal Un.

[0026] The n-th stage unit circuit Jn may have an inversion node NR whose state is inverted with respect to the first node N1, and multiple pull-down transistors T11 and T12 whose gate terminals are connected to the inversion node NR. The drive terminal Xn and the first node N1 may be connected to the second power supply line D2 via different pull-down transistors T11 and T12. That is, the drive terminal Xn may be connected to the second power supply line D2 via the pull-down transistor T11, and the first node N1 may be connected to the second power supply line D2 via the pull-down transistor T12.

[0027] In this way, the pull-down transistors T11 and T12 are turned off while the first node N1 is active (high), and when the first node N1 becomes inactive (low) (the inversion node NR becomes active high), the first transistor T1 is turned off and the pull-down transistors T11 and T12 are turned on. As a result, the potential of the drive terminal Xn is maintained at a low level regardless of the level of the clock signal K1, and the drive signal Va is maintained inactive (low).

[0028] The n-th stage unit circuit Jn may have an inverting node Nr whose state is inverted with respect to the setting node NQ, and multiple pull-down transistors T13 and T14 whose gate terminals are connected to the inverting node Nr. The setting terminal Un and the setting node NQ may be connected to the second power supply line D2 via different pull-down transistors T13 and T14. That is, the setting terminal Un may be connected to the second power supply line D2 via the pull-down transistor T13, and the setting node NQ may be connected to the second power supply line D2 via the pull-down transistor T14.

[0029] In this way, while the setting node NQ is active (high), the pull-down transistors T13 and T14 are turned off, and when the setting node NQ becomes inactive (low) (the inverting node Nr becomes active high), the setting transistor Tq is turned off and the pull-down transistors T13 and T14 are turned on. As a result, the potential of the setting terminal Un is maintained at a low level regardless of the level of the clock signal K1, and the setting signal Qn is maintained inactive (low).

[0030] In the n-th stage unit circuit Jn, the inverting node NR may be connected to a first power supply line D1 (high-potential side power supply line) via a diode-connected transistor T17 (power supply transistor) and to a second power supply line D2 (low-potential side power supply line) via a transistor T18 (inverting transistor), and the gate terminal of the transistor T18 may be connected to the first node N1. The transistors T11, T12, T17, and T18 may form an inverting circuit.

[0031] In the n-th stage unit circuit Jn, the inverting node Nr may be connected to the first power supply line D1 (high-potential side power supply line) via a diode-connected transistor T19 (power supply transistor) and to the second power supply line D2 (low-potential side power supply line) via a transistor T20 (inverting transistor), and the gate terminal of the transistor T20 may be connected to the setting node NQ. The transistors T13, T14, T19, and T20 may form an inverting circuit.

[0032] As shown in FIG. 1, the driver circuit 20 may include a signal generating circuit 30 that generates clock signals K1 to K6 and a first enable signal E1, and a group of input lines 25 that transmit the clock signals K1 to K6 and the first enable signal E1.

[0033] 3A and 3B, the first to third transistors T1 to T3, the setting transistor Tq, the set transistor TS, the reset transistor TR, the pull-down transistors T11, T12 to T14, and the transistors T17 to T20 may be, but are not limited to, n-channel transistors. These transistors may also be p-channel transistors, or may be a mixture of n-channel and p-channel transistors.

[0034] Fig. 4 is a schematic diagram showing the configuration of a driver circuit according to this embodiment. Fig. 5 is a timing chart showing the operation of the driver circuit according to this embodiment. In the examples of Figs. 4 and 5, the region including the signal line (scanning line) Ga has a low refresh rate, and the region including the signal lines (scanning lines) Gb and Gc has a high refresh rate. For example, the drive signal Va supplied to the signal line Ga may be activated approximately once to ten times per second, while the drive signals Vb and Vc supplied to the signal lines Gb and Gc may each be activated 60 times per second.

[0035] Fig. 6 is a block diagram showing the configuration of a display device according to this embodiment. As shown in Fig. 6, a display device 50 according to this embodiment may include a display unit 40, a data driver 2, a scan driver 3, and a controller 4. The display unit 40 may be capable of setting a refresh rate for each region. The driver circuit 20 may include a scan driver 3 (shift register circuit), a controller 4, and an input line group 25. The controller 4 may include a signal generating circuit 30 and a processor 35. The controller 4 may be a timing controller.

[0036] In the display device 50, the display unit 40 may have a plurality of liquid crystal capacitors (including pixel electrodes, counter electrodes, and a liquid crystal layer). In the display device 50, the display unit 40 may have a plurality of light-emitting elements (e.g., organic light-emitting diodes, quantum dot light-emitting diodes), and the driver circuit 20 may include at least one of a scan driver and a light-emission control driver.

[0037] Fig. 7 is a schematic diagram showing the configuration of a driver circuit according to this embodiment. Figs. 8 and 9 are timing charts showing the operation of the driver circuit according to this embodiment. As shown in Figs. 7 to 9, a first enable signal E1 may be input to the unit circuit Jn in the nth stage, and a second enable signal E2 may be input to the unit circuit Jn+1 in the (n+1)th stage.

[0038] The activation timing of the first enable signal E1 and the second enable signal E2 may be shifted by a predetermined time. The deactivation timing of the first enable signal E1 and the second enable signal E2 may be shifted by a predetermined time. The predetermined time (shifted time) may be shorter than the time corresponding to the pulse width of the clock signals K1 and K2, or may be a time corresponding to half the pulse width of the clock signals K1 and K2. The predetermined time may be a time corresponding to the phase difference between the clock signal CK1 input to the n-th stage unit circuit Jn and the clock signal CK2 input to the (n+1)-th stage unit circuit Jn+1 (e.g., 1H = 1 horizontal scanning period).

[0039] This ensures the waveform of the drive signal Vb for unit circuit Jn+1 is stable even if a signal delay occurs. For example, if clock signals K1 to K6 are active for 2H with a 6H period, the discharge delay margin of the first node N1 of unit circuit Jn+1 (the period from the fall of the first enable signal E1 to the rise of Qn+1) is 0.5H in Figure 2, but in Figure 8, the discharge delay margin (the period from the fall of the second enable signal E2 to the rise of Qn+1) is expanded to 1.5H. In the example of Figure 8, the area including signal line (scanning line) Ga has a high refresh rate, and the area including signal lines (scanning lines) Gb and Gc has a low refresh rate (Figure 7), with signal line Ga located at the edge of the high refresh rate area.

[0040] Also, in Figure 5, the charge delay margin of the first node N1 of the unit circuit Jn+1 (the period from the rise of the first enable signal E1 to the rise of Qn+1) is 0.5 H, but in Figure 9, the charge delay margin (the period from the rise of the second enable signal E2 to the rise of Qn+1) is expanded to 1.5 H. Figure 9 shows the case where the region including the signal line (scan line) Ga has a low refresh rate and the region including the signal lines (scan lines) Gb and Gc has a high refresh rate, and the signal line Ga is located at the edge of the low refresh rate region.

[0041] FIG. 10 is a schematic diagram showing the configuration of a driver circuit according to this embodiment. FIG. 11 is a timing chart showing the operation of the driver circuit according to this embodiment. FIG. 12 is a circuit diagram showing a configuration example of a part (two adjacent unit circuits) of FIG. 10. As shown in FIGS. 10 to 12, the (n-1)th-stage unit circuit Jn-1 and the (n+1)th-stage unit circuit Jn+1 have an output circuit including an input terminal IT, a drive terminal Xn, a first node N1, and a control terminal CT, but may not have a register circuit. That is, the nth-stage unit circuit Jn has an output circuit On and a register circuit Ln, but the previous-stage Jn-1 and subsequent-stage Jn+1 of the nth-stage unit circuit Jn have only an output circuit and do not have a register circuit.

[0042] The unit circuit Jn-1 shown in Figures 10 to 12 includes an input terminal IT to which a clock signal K6 is input, a drive terminal Xn-1, a set terminal Sn-1 (gate terminal of the set transistor TS) to which a set signal Qn-2 is input, a reset terminal Rn-1 to which a reset signal Qn+4 is input, and a control terminal CT to which a first enable signal E1 is input.

[0043] The unit circuit Jn shown in Figures 10 to 12 includes an input terminal IT to which a clock signal K1 is input, a drive terminal Xn, a set terminal Sn (gate terminal of the set transistor TS) to which a set signal Qn-2 is input, a reset terminal Rn-1 to which a reset signal Qn+4 is input, a control terminal CT to which a first enable signal E1 is input, a clock terminal IK to which the clock signal K1 is input, an output terminal Un, a set terminal sn (gate terminal of the second transistor T2) to which the set signal Qn-2 is input, and a reset terminal rn (gate terminal of the third transistor T3) to which a reset signal Qn+4 is input.

[0044] Here, n is 3 or more, and the first-stage unit circuit may include an output circuit and a register circuit. In this case, as shown in Figure 11, the shift operation of the driver circuit 20 continues with only the setting signals (Qn, Qn+2, etc.) output from the odd-numbered stages (Jn, Jn+2, etc.), and during the period when the first enable signal E1 is active, drive signals (Va, Vb, Vc) are output from each unit circuit (for example, Jn, Jn+1, Jn2).

[0045] As shown in Figure 11, if the first enable signal E1 becomes inactive while the setting signal Qn output from the unit circuit Jn is active (if E1 falls from high to low while Qn is high), the first transistor T1 of the unit circuit Jn remains on and a pulse is output to the drive signal Va of the unit circuit Jn. However, since the first transistor T1 of the unit circuits Jn+1 and Jn+2 does not turn on, no pulse is output to the drive signals Vb and Vc of the unit circuits Jn+1 and Jn+2. In other words, the output of drive pulses stops. This allows the area including the signal lines (scanning lines) Gb and Gc in the display unit 40 to be a low-refresh area.

[0046] 11, clock signals K1 and K6 of different phases are input to the n-th stage unit circuit Jn and the n-1-th stage unit circuit Jn-1, but the shift operation of the driver circuit 20 continues with only the Q signals output from the odd-numbered stage unit circuits (Jn and Jn+2, etc.), so that the clock signal K6 input to the n-1-th stage unit circuit Jn-1 (e.g., the clock signal input to the even-numbered stage) may be kept inactive during the inactive period (low period) of the first enable signal E1. This allows power consumption to be reduced.

[0047] The unit circuit Jn-1 in the (n-1)th stage and the unit circuit Jn in the nth stage in Fig. 10 can be collectively formed into an integrated circuit FC, which can be configured as shown in Fig. 12. In the unit circuit Jn-1 and the unit circuit Jn, a common set signal Qn-2 is input to the set terminals Sn·sn·Sn-1, and therefore in the integrated circuit FC in Fig. 12, these set terminals (Sn·sn·Sn-1) can be made into a common set terminal ST.

[0048] In the unit circuits Jn-1 and Jn, a common reset signal Qn+4 is input to the reset terminals Rn·rn·Rn-1, so in the integrated circuit FC of Figure 12, these reset terminals (Rn·rn·Rn-1) can be used as a common reset terminal RT.

[0049] In the unit circuit Jn-1 and the unit circuit Jn, a common first enable signal E1 is input to the control terminal CT, and therefore, in the integrated circuit FC of FIG. 12, these control terminals CT can be made common.

[0050] In the unit circuit Jn, a common clock signal K1 is input to the input terminal IT and the control terminal IK, so that in the integrated circuit FC of FIG. 12, these can be made common to a common input terminal IF.

[0051] The integrated circuit FC may include a first node N1, a setting node NQ, first to third transistors T1 to T3, a setting transistor Tq, and a first capacitor C1, as well as a second capacitor C2, fourth to sixth transistors T4 to T6, and eleventh to eighteenth transistors T11 to T18.

[0052] 12, an input terminal IF to which a clock signal K1 is input is connected to a drive terminal Xn via a first transistor T1 and to a setting terminal Un via a setting transistor Tq. A gate terminal of the first transistor T1 is connected to a first node N1, which is connected to the drive terminal Xn via a first capacitor C1. An input terminal IT to which a clock signal K6 is input is connected to a drive terminal Xn-1 via a fourth transistor T4. A gate terminal of the fourth transistor T4 is connected to a second node N2, which is connected to the drive terminal Xn-1 via a second capacitor C2.

[0053] A control terminal CT to which a first enable signal E1 is input is connected to a first node N1 via a set transistor TS, and is also connected to a second node N2 via a transistor T5. A set signal Qn-2 is input to gate terminals (set terminal ST) of the set transistor TS and transistor T5. The set terminal ST is connected to a setting node NQ via a transistor T2. One conduction terminal (e.g., a drain terminal) of the transistor T2 is connected to the set terminal ST, but this is not limitative and it may be connected to the first power line D1.

[0054] A reset signal Qn+4 is input to the gate terminals (reset terminal RT) of the reset transistor TR and the transistors T3 and T6. The first node N1 is connected to the second power supply line D2 via the reset transistor TR, the second node N2 is connected to the second power supply line D2 via the transistor T6, and the setting node NQ is connected to the second power supply line D2 via the transistor T3.

[0055] The driving terminal Xn is connected to the second power supply line D2 via a pull-down transistor T11, and the first node N1 is connected to the second power supply line D2 via a pull-down transistor T12. The setting terminal Un is connected to the second power supply line D2 via a pull-down transistor T13, and the setting node NQ is connected to the second power supply line D2 via a pull-down transistor T14. The driving terminal Xn-1 is connected to the second power supply line D2 via a pull-down transistor T15, and the second node N2 is connected to the second power supply line D2 via a pull-down transistor T16.

[0056] The integrated circuit FC may include an inverting node NR whose state is inverted with respect to the first node N1, and the inverting node NR may be connected to the gate terminals of the pull-down transistors T11 to T16. The inverting node NR may be connected to a first power supply line D1 (high potential side power supply line) via a diode-connected transistor T17 (power supply transistor) and to a second power supply line D2 (low potential side power supply line) via a transistor T18 (inverting transistor), and the gate terminal of the transistor T18 may be connected to a setting node NQ.

[0057] FIG. 13 is a schematic diagram showing the configuration of a driver circuit according to this embodiment. FIGS. 14A and 14B are circuit diagrams showing an example configuration of a unit circuit. FIG. 15 is a timing chart showing the operation of the driver circuit according to this embodiment. A driver circuit 20 can be configured using the integrated circuit FC shown in FIG. 12 as an n-th stage unit circuit. As shown in FIGS. 13, 14A, 14B, and 15, the driver circuit 20 is a driver circuit that includes multiple stages of unit circuits (Fn, Fn-1, Fn+1, etc.) and drives multiple signal lines (Ga to Gc, etc.). The n-th stage unit circuit Fn includes an input terminal IF to which a clock signal K1 is input, a drive terminal Xn that outputs a drive signal Va to one of the multiple signal lines, a first node N1, a first transistor T1 whose gate terminal is connected to the first node N1, a set transistor TS whose gate terminal receives a set signal (e.g., Qn-2) from another stage, and a control terminal CT.

[0058] The input terminal IF is connected to the drive terminal Xn via a first transistor T1. The control terminal CT is connected to a first node N1 via a set transistor TS. A first enable signal E1 that determines whether the output of the drive signal Xn is enabled or disabled is input to the control terminal CT. Here, n is a natural number, and the voltage of the first node N1 of the unit circuit Fn is Vn, the voltage of the first node N1 of the unit circuit Fn+1 is Vn+1, etc.

[0059] The unit circuit Fn may include a first node N1, a setting node NQ, first to third transistors T1 to T3, a setting transistor Tq, and a first capacitor C1, as well as a second capacitor C2, fourth to sixth transistors T4 to T6, and eleventh to eighteenth transistors T11 to T18.

[0060] In the unit circuit Fn, an input terminal IF to which a clock signal K1 is input is connected to a drive terminal Xn via a first transistor T1 and to a setting terminal Un via a setting transistor Tq. A gate terminal of the first transistor T1 is connected to a first node N1, which is connected to the drive terminal Xn via a first capacitor C1. An input terminal IT to which a clock signal K6 is input is connected to a drive terminal Xn-1 via a fourth transistor T4. A gate terminal of the fourth transistor T4 is connected to a second node N2, which is connected to the drive terminal Xn-1 via a second capacitor C2.

[0061] A control terminal CT to which a first enable signal E1 is input is connected to a first node N1 via a set transistor TS and to a second node N2 via a transistor T5. A set signal Qn-1 is input to the gate terminals (set terminal Sn) of the set transistor TS and the transistor T5. The set terminal Sn is connected to a setting node NQ via a transistor T2.

[0062] A reset signal Qn+2 is input to the gate terminals (reset terminals Rn) of the reset transistor TR and the transistors T3 and T6. The first node N1 is connected to the second power supply line D2 via the reset transistor TR, the second node N2 is connected to the second power supply line D2 via the transistor T6, and the setting node NQ is connected to the second power supply line D2 via the transistor T3.

[0063] The driving terminal Xn is connected to the second power supply line D2 via a pull-down transistor T11, and the first node N1 is connected to the second power supply line D2 via a pull-down transistor T12. The setting terminal Un is connected to the second power supply line D2 via a pull-down transistor T13, and the setting node NQ is connected to the second power supply line D2 via a pull-down transistor T14. The driving terminal Xn-1 is connected to the second power supply line D2 via a pull-down transistor T15, and the second node N2 is connected to the second power supply line D2 via a pull-down transistor T16.

[0064] The n-th stage unit circuit Fn may include an inversion node NR whose state is inverted with respect to the first node N1, and the inversion node NR may be connected to the gate terminals of the pull-down transistors T11 to T16. The inversion node NR may be connected to the first power supply line D1 (high potential side power supply line) via a diode-connected transistor T17 (power supply transistor) and to the second power supply line D2 (low potential side power supply line) via a transistor T18 (inversion transistor), and the gate terminal of the transistor T18 may be connected to the setting node NQ.

[0065] As shown in Figure 15, when the first enable signal E1 becomes inactive while the setting signal Qn output from the unit circuit Fn is active (when E1 falls from high to low during the high period of Qn), the first and fourth transistors T1 and T4 of the unit circuit Fn remain ON, and pulses are output to the drive signals Va and Vb of the unit circuit Fn. However, the first and fourth transistors T1 and T4 of the unit circuit Fn+1 do not turn ON (remain OFF), so no pulses are output to the drive signals Vc and Vd of the unit circuit Fn+1. In other words, the output of drive pulses stops. This allows the area including the signal lines (scanning lines) Gc and Gd in the display unit 40 to be a low-refresh area.

[0066] 15, clock signals K1 to K6 are input to the driver circuit 20, and for example, clock signals K1 and K6 of different phases are input to the n-th stage unit circuit Fn, but since the shift operation of the driver circuit 20 is maintained by clock signals K1, K3, and K5, during the inactive period (low period) of the first enable signal E1, clock signals K2 and K4 in addition to clock signal K6 input to unit circuit Fn may be maintained inactive low. This can reduce power consumption.

[0067] The above-described embodiments are intended to be illustrative and explanatory, and are not intended to be limiting. Based on these examples and explanations, it will be apparent to those skilled in the art that many modifications are possible. The gist of the present embodiment will be described below. In the following, "above" includes the technical content disclosed in at least one of FIGS. 1 to 15.

[0068] 〔summary〕 A driver circuit including a plurality of unit circuits and configured to drive a plurality of signal lines, the n-th stage unit circuit includes an input terminal to which a clock signal is input, a drive terminal to which a drive signal is output to one of the plurality of signal lines, a first node, a first transistor having a gate terminal connected to the first node, a set transistor having a gate terminal to which a set signal from another stage is input, and a control terminal; the input terminal is connected to the drive terminal via the first transistor; the control terminal is connected to the first node via the set transistor; a driver circuit, wherein a first enable signal that specifies whether output of the drive signal is enabled or disabled is input to the control terminal;

[0069] the n-th stage unit circuit comprises a clock terminal to which the clock signal is input, a setting terminal to which a setting signal is output to a unit circuit of another stage, a setting node, a setting transistor having a gate terminal connected to the setting node, and a second transistor having a gate terminal to which the set signal is input; the clock terminal is connected to the setting terminal via the setting transistor; The driver circuit as described above, wherein the set node is connected to one of the two conduction terminals of the second transistor.

[0070] The driver circuit as described above, wherein the second transistor has a gate terminal connected to the other of the two conduction terminals.

[0071] the n-th stage unit circuit includes a first capacitor and a setting capacitor; the first node is connected to the drive terminal via the first capacitance; The driver circuit as described above, wherein the setting node is connected to the setting terminal via the setting capacitance.

[0072] The driver circuit described above, wherein the nth stage unit circuit comprises an output circuit including the input terminal, the drive terminal, the first node, and the control terminal, and a register circuit including the clock terminal, the setting terminal, and the setting node.

[0073] The driver circuit as described above, wherein the drive signal is activated during an active period of a first enable signal.

[0074] The driver circuit as described above, wherein the drive signal is not activated during an inactive period of the first enable signal.

[0075] The above-mentioned driver circuit, wherein during an active period of a first enable signal, the first node is made active by the set signal, thereby turning on the first transistor and charging the first capacitance, and the first node is boosted by the rising edge of the clock signal.

[0076] The driver circuit described above, wherein the setting node becomes active in response to the set signal, thereby turning on the setting transistor and charging the setting capacitor, and the setting node is boosted by the rising edge of the clock signal.

[0077] a first power line and a second power line; the n-th stage unit circuit has a reset transistor to which a reset signal is input from a subsequent stage side; The driver circuit described above, wherein the first node is connected to the second power supply line via the reset transistor.

[0078] the n-th stage unit circuit has a third transistor to which a reset signal is input from a subsequent stage side; The driver circuit described above, wherein the setting node is connected to the second power supply line via the third transistor.

[0079] the first power supply line is a high-potential side power supply line, and the second power supply line is a low-potential side power supply line, the n-th stage unit circuit has an inversion node whose state is inverted with respect to the first node, and a plurality of pull-down transistors whose gate terminals are connected to the inversion node; The driver circuit as described above, wherein the drive terminal and the first node are connected to the second power supply line via different pull-down transistors.

[0080] the first enable signal is input to the n-th stage unit circuit; A second enable signal is input to the (n+1)th stage unit circuit, The driver circuit as described above, wherein the first enable signal and the second enable signal are activated at different times by a predetermined time.

[0081] the first enable signal is input to the n-th stage unit circuit; A second enable signal is input to the (n+1)th stage unit circuit, The driver circuit as described above, wherein the first enable signal and the second enable signal are deactivated at timings that are offset by a predetermined time.

[0082] The driver circuit described above, wherein the predetermined time is shorter than a time corresponding to a pulse width of the clock signal.

[0083] The driver circuit described above, wherein the predetermined time is a time corresponding to a phase difference between a clock signal input to the n-th stage unit circuit and a clock signal input to the (n+1)-th stage unit circuit.

[0084] The above-mentioned driver circuit, wherein each of the nth stage unit circuit and the (n-1)th stage unit circuit comprises an output circuit including the input terminal, the drive terminal, the first node and the control terminal, and a register circuit including the clock terminal, the setting terminal and the setting node.

[0085] The driver circuit described above, wherein the (n-1)th stage unit circuit comprises an output circuit including the input terminal, the drive terminal, the first node, and the control terminal, and does not comprise a register circuit.

[0086] Clock signals with different phases are input to the n-th stage unit circuit and the (n-1)-th stage unit circuit, The driver circuit described above, wherein the clock signal input to the (n-1)th stage unit circuit is maintained inactive during an inactive period of the first enable signal.

[0087] each of the plurality of signal lines is a scanning line; The driver circuit as described above, wherein the first drive signal is a scan signal.

[0088] The driver circuit as described above, wherein the plurality of signal lines are formed in a display section in which a refresh rate can be set for each area.

[0089] The driver circuit described above performs full scanning, which scans all of the plurality of signal lines, and partial scanning, which scans some of the plurality of signal lines.

[0090] A display device comprising the driver circuit described above.

[0091] The display device described above includes a display unit capable of setting a refresh rate for each area. [Explanation of symbols]

[0092] 20 Driver circuit 40 Display section N1 First node NQ configuration node IT input terminal Un setting terminal Xn drive terminal Jn Fn nth stage unit circuit Qn setting signal Va~Vd drive signal T1~T3 1st to 3rd transistors TS Set Transistor Tq setting transistor K1~K6 clock signals E1 First enable signal E2 Second enable signal

Claims

1. A driver circuit including a plurality of unit circuits and configured to drive a plurality of signal lines, the n-th stage unit circuit includes an input terminal to which a clock signal is input, a drive terminal to output a drive signal to one of the plurality of signal lines, a first node, a first transistor having a gate terminal connected to the first node, a set transistor having a gate terminal to which a set signal from another stage is input, and a control terminal; the input terminal is connected to the drive terminal via the first transistor; the control terminal is connected to the first node via the set transistor; a driver circuit, wherein a first enable signal that defines whether output of the drive signal is enabled or disabled is input to the control terminal;

2. the n-th stage unit circuit comprises a clock terminal to which the clock signal is input, a setting terminal to which a setting signal is output to a unit circuit of another stage, a setting node, a setting transistor having a gate terminal connected to the setting node, and a second transistor having a gate terminal to which the set signal is input; the clock terminal is connected to the setting terminal via the setting transistor; 2. The driver circuit of claim 1, wherein the set node is connected to one of two conduction terminals of the second transistor.

3. 3. The driver circuit according to claim 2, wherein the second transistor has a gate terminal connected to the other of the two conduction terminals.

4. the n-th stage unit circuit includes a first capacitor and a setting capacitor; the first node is connected to the drive terminal via the first capacitance; 3. The driver circuit according to claim 2, wherein the setting node is connected to the setting terminal via the setting capacitance.

5. 3. The driver circuit according to claim 2, wherein the nth stage unit circuit comprises an output circuit including the input terminal, the drive terminal, the first node, and the control terminal, and a register circuit including the clock terminal, the setting terminal, and the setting node.

6. The driver circuit of claim 1 , wherein the drive signal is activated during an active period of a first enable signal.

7. The driver circuit of claim 6 , wherein the drive signal is not activated during an inactive period of the first enable signal.

8. 5. The driver circuit according to claim 4, wherein during an active period of a first enable signal, the first node is made active by the set signal, thereby turning on the first transistor and charging the first capacitance, and the first node is boosted by a rising edge of the clock signal.

9. 5. The driver circuit according to claim 4, wherein the setting node is made active by the set signal, thereby turning on the setting transistor and charging the setting capacitor, and the setting node is boosted by the rising edge of the clock signal.

10. a first power supply line and a second power supply line; the n-th stage unit circuit has a reset transistor to which a reset signal is input from a subsequent stage side; 3. The driver circuit according to claim 2, wherein the first node is connected to the second power supply line via the reset transistor.

11. the n-th stage unit circuit has a third transistor to which a reset signal is input from a subsequent stage side; The driver circuit according to claim 10 , wherein the setting node is connected to the second power supply line via the third transistor.

12. the first power supply line is a high-potential side power supply line, and the second power supply line is a low-potential side power supply line, the n-th stage unit circuit has an inversion node whose state is inverted with respect to the first node, and a plurality of pull-down transistors whose gate terminals are connected to the inversion node; 11. The driver circuit of claim 10, wherein the drive terminal and the first node are connected to the second power supply line through different pull-down transistors.

13. the first enable signal is input to the n-th stage unit circuit; A second enable signal is input to the (n+1)th stage unit circuit, 2. The driver circuit according to claim 1, wherein the first enable signal and the second enable signal are activated at timings that are offset by a predetermined time.

14. the first enable signal is input to the n-th stage unit circuit; A second enable signal is input to the (n+1)th stage unit circuit, 2. The driver circuit according to claim 1, wherein the first enable signal and the second enable signal are deactivated at timings that are offset by a predetermined time.

15. 15. The driver circuit according to claim 13, wherein the predetermined time is shorter than a time corresponding to a pulse width of the clock signal.

16. 15. The driver circuit according to claim 13, wherein the predetermined time is a time corresponding to a phase difference between a clock signal input to the nth stage unit circuit and a clock signal input to the (n+1)th stage unit circuit.

17. 6. The driver circuit of claim 5, wherein each of the n-th stage unit circuit and the (n-1)-th stage unit circuit comprises an output circuit including the input terminal, the drive terminal, the first node, and the control terminal, and a register circuit including the clock terminal, the setting terminal, and the setting node.

18. 6. The driver circuit according to claim 5, wherein the (n-1)th stage unit circuit comprises an output circuit including the input terminal, the drive terminal, the first node, and the control terminal, and does not comprise the register circuit.

19. clock signals of different phases are input to the n-th stage unit circuit and the (n-1)-th stage unit circuit; 19. The driver circuit according to claim 18, wherein the clock signal input to the (n-1)th stage unit circuit is maintained inactive during an inactive period of the first enable signal.

20. each of the plurality of signal lines is a scanning line; 2. The driver circuit of claim 1, wherein the drive signal is a scan signal.

21. 21. The driver circuit according to claim 20, wherein the plurality of signal lines are formed in a display section in which a refresh rate can be set for each area.

22. 21. The driver circuit according to claim 20, wherein full scanning is performed to scan all of the plurality of signal lines, and partial scanning is performed to scan some of the plurality of signal lines.

23. A display device comprising the driver circuit according to claim 1.

24. The display device according to claim 23, comprising a display section in which a refresh rate can be set for each area.

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