Systolic array, information processing device, and arithmetic processing method

Abstract

To prevent deterioration in operation performance in a matrix product operation of a small matrix.SOLUTION: A systolic array 10 having a plurality of processing elements 1 includes a first systolic array 10 divided from the systolic array 10, a second systolic array 10 divided from the systolic array 10 and in a subsequent stage of the first systolic array 10, and a control unit 100, and the plurality of processing elements 1 include a selector 15,16 that selects and outputs an output signal. The control unit 100 switches the output signal from the selector 15,16 between the processing element 1 in the final stage of the first systolic array 10 and the processing elements 1 in the stages other than the final stage of the first systolic array 10 and the processing elements 1 of the second systolic array 10 among the plurality of processing elements 1.SELECTED DRAWING: Figure 3

Description

[Technical Field]

[0001] The present invention relates to a systolic array, an information processing device, and an arithmetic processing method. [Background technology]

[0002] In the training and inference of deep neural networks (DNNs), including large language models (LLMs), the main operation is matrix multiplication.

[0003] Two-dimensional Systolic Array (SA) is an accelerator for accelerating matrix multiplication. There are three types of two-dimensional SA for matrix multiplication: output stationary, input stationary, and weight stationary. [Prior art documents] [Patent documents]

[0004] [Patent Document 1] Special Publication No. 2022-540548 [Patent Document 2] U.S. Patent No. 11,003,619 Summary of the Invention [Problem to be solved by the invention]

[0005] However, if the multiplier matrix input to the SA is smaller than the size of the SA, the number of Processor Elements (PEs) used within the SA may decrease, resulting in a decrease in computational performance. The computational performance is expressed by the following equation:

[0006] (FLOP / s) = 2 × (number of PEs used in SA) × (clock frequency) Furthermore, unused PEs perform multiplication and accumulation operations with 0, which wastes power.

[0007] One aspect of the present invention aims to prevent a decrease in the performance of matrix multiplication of small matrices. [Means for solving the problem]

[0008] In one aspect, a systolic array having a plurality of processing elements includes a first systolic array separated from the systolic array, a second systolic array separated from the systolic array and located downstream of the first systolic array, and a control unit, wherein the plurality of processing elements include a selector that selects and outputs an output signal, and the control unit switches the output signal from the selector between a processing element in the final stage of the first systolic array, a processing element other than the final stage of the first systolic array, and a processing element of the second systolic array, among the plurality of processing elements. [Effects of the Invention]

[0009] In one aspect, it is possible to prevent a decrease in calculation performance in matrix multiplication of small matrices. [Brief explanation of the drawings]

[0010] [Figure 1] FIG. 10 is a diagram illustrating a matrix multiply-accumulate operation process in a related example. [Figure 2] 10A and 10B are diagrams illustrating an example of division of SA when a small multiplication matrix is ​​calculated in a related example. [Figure 3] 10A and 10B are diagrams illustrating a matrix multiply-and-accumulate operation process when an SA is vertically divided into two parts in an embodiment. [Figure 4] 4 is a flowchart illustrating processing by a control unit shown in FIG. 3. [Figure 5] 4 is a diagram illustrating the flow of data in the PEs other than the boundary row in the SA in the matrix multiply-accumulate operation process shown in FIG. 3. FIG. [Figure 6] 4 is a diagram illustrating the flow of data in a PE on a boundary row within an SA in the matrix multiply-accumulate operation process shown in FIG. 3. FIG. [Figure 7]10A and 10B are diagrams illustrating a matrix multiply-and-accumulate operation process when an SA is divided into two horizontally in an embodiment. [Figure 8] 8 is a diagram illustrating the flow of data in the PE of the boundary column in the SA in the matrix multiply-accumulate operation process shown in FIG. 7. FIG. [Figure 9] 10A and 10B are diagrams illustrating a matrix multiply-and-accumulate operation process when an SA is vertically divided into three parts in an embodiment. [Figure 10] 10A and 10B are diagrams illustrating a matrix multiply-and-accumulate operation process when an SA is divided into three horizontal sections in an embodiment. [Figure 11] FIG. 1 is a block diagram illustrating an example of a hardware configuration of an information processing device according to an embodiment. [Figure 12] 10A and 10B are diagrams comparing a matrix multiply-accumulate operation process in a related example with a matrix multiply-accumulate operation process in an embodiment; DETAILED DESCRIPTION OF THE INVENTION

[0011] [A] Related Examples FIG. 1 is a diagram for explaining a matrix multiply-accumulate operation process in a related example.

[0012] In the example shown in FIG. 1, as indicated by reference symbol A1, a matrix C having M rows and N columns is added to the product of a matrix A having M rows and K columns and a matrix B having K rows and N columns, thereby calculating a matrix C' having M rows and N columns.

[0013] As shown by the symbol A2, the SA60 has a matrix A t (A t represents the transposed matrix of A.) is input, matrices B and C are input column-wise, and matrix C' is output column-wise.

[0014] The PE 6 indicated by the symbol A3 includes a register (reg) 61, a multiplier 62, an adder 63, and three flip-flops (FFs) 64.

[0015] The elements of multiplier matrix B are stored in register 61 of each PE6 using signal line b, and matrix A is stored from the left using signal line a. tThe values ​​of a', b', and s' are input sequentially. In each PE6, a multiplier 62 calculates the product, and an adder 63 uses the matrix C from the signal line s to pass the partial sum to the PE6 in the lower stage. Three FFs 64 are provided immediately before the output signal lines a', b', and s' to adjust the output timing of the output signals. Then, the values ​​of matrix C' are output sequentially from the output s' of the lowest PE6.

[0016] Here, if the multiplier matrix input to the SA 60 is smaller than the size of the SA 60, the number of PEs 6 used within the SA 60 will decrease, which may result in a decrease in calculation performance. Also, unused PEs 6 will perform multiplication and accumulation with 0, which will waste power.

[0017] Therefore, it is expected that the number of PE6s in use can be increased and the calculation performance can be improved by dividing the SA60 into two smaller SA60s (in other words, SA#1 and SA#2).

[0018] FIG. 2 is a diagram illustrating an example of division of the SA 60 when a small multiplication matrix is ​​calculated in a related example.

[0019] In the example shown in FIG. 2, two matrix operations that are half the size of SA60 are performed, as shown in the following equation. A1·B1+C1=C1′ A2·B2+C2=C2′

[0020] This increases computational performance by 25% to 50% compared to performing a single matrix operation half the size of the SA60.

[0021] However, the method shown in FIG. 2 can only be applied to matrices that are small in both the row and column directions.

[0022] [B] Embodiment Hereinafter, embodiments will be described with reference to the drawings. However, the embodiments shown below are merely examples, and are not intended to exclude various modifications or application of techniques not explicitly stated in the embodiments. In other words, the present embodiments can be implemented with various modifications within the scope of the spirit thereof. Furthermore, each figure does not intend to include only the components shown in the figure, but may include other components, etc.

[0023] FIG. 3 is a diagram illustrating the matrix multiply-and-accumulate operation process when the SA 10 is vertically divided into two parts in this embodiment.

[0024] In the example shown in Figure 3, as indicated by symbol B1, SA10 (systolic array) is divided into SA#1 (in other words, the first systolic array) with 4 rows and 8 columns and SA#2 (in other words, the second systolic array) with 4 rows and 8 columns.

[0025] Of the PE1s included in SA#1, the PE1s in the first to third rows are designated as group #1, and the PE1 in the fourth row, which is the boundary row with SA#2, is designated as group #2. On the other hand, in SA#2, all PE1s in the first to fourth rows are designated as group #1.

[0026] PE1 indicated by symbol B2 includes a register (reg) 11, a multiplier 12, an adder 13, four FFs 14, and selectors 15 and 16. Note that elements indicated by dashed lines in PE1 indicate elements added to elements in PE6, which is a related example shown in FIG.

[0027] Register 11 stores the elements of matrix B from signal line b. Multiplier 12 multiplies the elements of matrix A from signal line a by the elements of matrix B stored in register 11. Adder 13 adds the multiplication result of multiplier 12 to matrix C from signal line s.

[0028] Selector 15 selects either the input from signal line d for inputting matrix C to SA#2 or the addition result of adder 13 and outputs it to signal line d' in response to the sel signal input from control unit 100. Selector 16 selects either the input from signal line d or the addition result of adder 13 in response to the sel signal and outputs it to signal line s'.

[0029] In other words, the control unit 100 switches the output signals from the selectors 15 and 16 between the PE1 at the final stage of SA#1, the PE1 at the other stage than the final stage of SA#1, and the PE1 at SA#2.

[0030] The sel signal is input as "0" to PE1 in group #1 indicated by symbol B1, and as "1" to PE1 in group #2.

[0031] That is, in PE1 of group #1, sel=0 is input to selectors 15 and 16, so selector 15 outputs the input from signal line d, and selector 16 outputs the addition result of adder 13. Also, in PE1 of group #2, sel=1 is input to selectors 15 and 16, so selector 15 outputs the addition result from adder 13, and selector 16 outputs the input from signal line d.

[0032] The four FFs 14 are provided immediately before the output signal lines a', b', d', and s' and adjust the output timing of the output signals.

[0033] In the topmost PE1, matrix C for SA#1 is input from s, and matrix C for SA#2 is input from signal line d. Meanwhile, in the bottommost PE1, the output of SA#1 comes out from signal line d', and the output of SA#2 comes out from signal line s'.

[0034] PE1 indicated by symbol B2 has signal lines s to s' that receive the input of constant matrix C1 and output the calculation result C1', and signal lines d to d' that receive the input of constant matrix C2 and output the calculation result C2'.

[0035] The processing of the control unit 100 shown in FIG. 3 will be described with reference to the flowchart (steps S1 to S3) shown in FIG.

[0036] The control unit 100 determines whether PE1 is designated as group #1 (step S1).

[0037] If PE1 is designated as group #1 (see the Yes route in step S1), the control unit 100 inputs sel=0 to the selectors 15 and 16 (step S2), and the process then ends.

[0038] On the other hand, if PE1 is not designated to group #1, that is, if PE1 is designated to group #2 (see the No route in step S1), the control unit 100 inputs sel=1 to the selectors 15 and 16 (step S3), and the process then ends.

[0039] Fig. 5 is a diagram illustrating the flow of data in PE1 other than the boundary row in SA10 in the matrix multiply-accumulate operation shown in Fig. 3. In reference symbol C1 in Fig. 5, the boundary row in SA10 is indicated by a bold frame.

[0040] In the example shown in FIG. 5, two matrix operations of half the size of SA10 are performed in the row direction, as shown in the following equation. C1′=A1·B1+C1 C2′=A2·B2+C2

[0041] As shown by the symbol C1, SA10 has a matrix A1 t is input, and matrix A2 is input to SA#2. t is input, matrix C1 is input to SA#1 in the column direction, and matrix C2 is input to SA#2. Then, matrix C1' is output from SA#1 in the column direction, and matrix C2' is output from SA#2 in the column direction. Matrix B is input in advance using signal line b and held in register 11.

[0042] As shown by reference symbol C2, since sel=0 is input to the selectors 15 and 16, the selector 15 outputs the input from the signal line d, and the selector 16 outputs the addition result of the adder 13.

[0043] Note that s' ← a*b and d' ← d.

[0044] Fig. 6 is a diagram for explaining the data flow in the PE1 of the boundary row of the SA 10 in the matrix multiply-accumulate operation process shown in Fig. 3. Note that the symbol C1 in Fig. 6 is the same as the symbol C1 in Fig. 5.

[0045] As shown by reference symbol C3, sel=1 is input to the selectors 15 and 16, so the selector 15 outputs the addition result of the adder 13, and the selector 16 outputs the input from the signal line d.

[0046] Note that s' ← d and d' ← s + a*b.

[0047] FIG. 7 is a diagram illustrating the matrix multiply-accumulate operation process when the SA 10 is horizontally divided into two parts in this embodiment.

[0048] In the example shown in FIG. 7, as indicated by the reference symbol D1, SA10 is divided into SA#1 having 8 rows and 4 columns and SA#2 having 8 rows and 4 columns.

[0049] Of the PE1a included in SA#1, the PE1a in the first to third columns are designated as group #1, and the PE1a in the fourth column, which is the boundary column with SA#2, is designated as group #2. On the other hand, in SA#2, the PE1a in all columns, from the first to fourth columns, are designated as group #1.

[0050] PE1a indicated by symbol D2 includes a register (reg) 11, a multiplier 12, an adder 13, four FFs 14, and a selector 17. Note that elements indicated by dashed lines in PE1a indicate elements added to elements in PE6 as a related example shown in FIG.

[0051] Register 11 stores the elements of matrix B from signal line b. Multiplier 12 multiplies the elements of matrix A from signal line a by the elements of matrix B stored in register 11. Adder 13 adds the multiplication result of multiplier 12 to matrix C from signal line s.

[0052] The selector 17 selects the input from the signal line a or the input from the signal line e for inputting the matrix A to SA#2 in response to the sel signal input from the control unit 100, and outputs it to the signal line a'.

[0053] In other words, the control unit 100 switches the output signal from the selector 17 between the PE1a at the final stage of SA#1, the PE1a at the other stages of SA#1, and the PE1a at SA#2.

[0054] The sel signal is input as "0" to the PE1a in group #1 indicated by reference symbol D1, and as "1" to the PE1a in group #2.

[0055] That is, in PE1a of group #1, sel=0 is input to selector 17, so that the input from signal line a is output from selector 17. Also, in PE1a of group #2, sel=1 is input to selector 17, so that the input from signal line e is output from selector 17.

[0056] In the reference symbol D2, the input from the signal line b is outputted as is from the signal line b', and the input from the signal line e is outputted as is from the signal line e'.

[0057] The four FFs 14 are provided immediately before the output signal lines a', b', e', and s' and adjust the output timing of the output signals.

[0058] In PE1a in the leftmost column, matrix A is input to SA#1 via signal line a, and matrix A is input to SA#2 via signal line e.

[0059] The PE1a indicated by the reference symbol D2 has a signal line a for inputting the multiplicand matrix A1 and a signal line e for inputting the multiplicand matrix A2.

[0060] Fig. 8 is a diagram for explaining the data flow in PE1a of the boundary column in SA10 in the matrix multiply-accumulate operation process shown in Fig. 7. At reference numeral E1 in Fig. 8, the boundary column in SA10 is indicated by a thick frame.

[0061] In the example shown in FIG. 8, two matrix operations of half the size of SA10 are performed in the column direction as shown in the following equation. C1′=A1·B1+C1 C2′=A2·B2+C2

[0062] As shown by the symbol E1, SA10 has a matrix A1 t is input, and matrix A2 is input to SA#2. t is input, matrix C1 is input to SA#1 in the column direction, and matrix C2 is input to SA#2. Then, matrix C1' is output from SA#1 in the column direction, and matrix C2' is output from SA#2 in the column direction. Matrix B is input in advance using signal line b and held in register 11.

[0063] As indicated by the symbol E2, in the PE1a in the boundary column, sel=1 is input to the selector 17, and the selector 17 outputs the input from the signal line e.

[0064] FIG. 9 is a diagram illustrating the matrix multiply-accumulate operation process when the SA 10 is vertically divided into three parts in this embodiment.

[0065] In reference symbol F1 in FIG. 9, the boundary lines within SA10 are indicated by a bold frame and a double frame.

[0066] In the example shown in FIG. 9, three matrix operations are performed as shown in the following equations. C1′=A1·B1+C1 C2′=A2·B2+C2 C3′=A3·B3+C3

[0067] As shown by the symbol F1, SA10 has a matrix A1 t is input, and matrix A2 is input to SA#2. t is input, and matrix A3 is input to SA#3. t is input, and matrix C1 is input to SA#1 in the column direction, matrix C2 is input to SA#2, and matrix C3 is input to SA#3. Then, matrix C1' is output from the column direction of SA#1, C2' is output from the column direction of SA#2, and C3' is output from the column direction of SA#3. Matrix B is input in advance using signal line b and held in register 11.

[0068] As shown by the symbol F1, in each PE1b, the matrix A1 t ,A2 t ,A3 t is input from terminal a, matrix C3 is input from terminal d2, matrix C2 is input from terminal d3, and matrix C1 is input from terminal s. Matrix C1' is output from terminal d2', matrix C2' is output from terminal d3', and matrix C3' is output from terminal s'.

[0069] Of the PE1b included in SA#1, the PE1b in the first and second rows are designated as group #1, and the PE1b in the third row, which is the boundary row with SA#2, is designated as group #2. Also, of the PE1b included in SA#2, the PE1b in the first and second rows are designated as group #1, and the PE1b in the third row, which is the boundary row with SA#3, is designated as group #3. Meanwhile, in SA#3, all PE1b in the first and second rows are designated as group #1.

[0070] PE1b indicated by symbol F2 includes a register (reg) 11, a multiplier 12, an adder 13, five FFs 14, and selectors 18 to 20. The elements indicated by the two-dot chain line in PE1b indicate elements added to the elements in PE1 when SA10 shown in FIG. 3 is vertically divided into two.

[0071] Register 11 stores elements of matrix B from signal line b. Multiplier 12 multiplies elements of matrix A from signal line a by the elements of matrix B stored in register 11. Adder 13 adds the multiplication result of multiplier 12 to the partial sum from signal line s.

[0072] Selector 18 selects either the input from signal line d2 or the addition result of adder 13 in response to the sel signal and outputs it to signal line d2'. Selector 19 selects either the input from signal line d3 or the addition result of adder 13 in response to the sel signal and outputs it to signal line d3'. Selector 20 selects either the input from signal line d2, the input from signal line d3 or the addition result of adder 13 in response to the sel signal and outputs it to signal line s'.

[0073] The sel signal is input as "0" to PE1b of group #1 indicated by symbol F1, as "1" to PE1b of group #2, and as "2" to PE1b of group #3.

[0074] That is, in PE1b of group #1, sel=0 is input to selectors 18 to 20, so selector 18 outputs the input from signal line d2, selector 19 outputs the input from signal line d3, and selector 20 outputs the addition result of adder 13. Also, in PE1b of group #2, sel=1 is input to selectors 18 to 20, so selector 19 outputs the input from signal line d3, selector 20 outputs the input from signal line d2, and selector 18 outputs the addition result of adder 13. Furthermore, in PE1b of group #3, sel=2 is input to selectors 18 to 20, so selector 18 outputs the input from signal line d2, selector 19 outputs the addition result of adder 13, and selector 20 outputs the input from signal line d3.

[0075] The five FFs 14 are provided immediately before the output signal lines a', b', d2', d3', and s', and adjust the output timing of the output signals. Symbol F3 shows the output value from each signal line according to the sel signal. When sel=0, value d2 is output from signal line d2', value d3 is output from signal line d3', and value s+a*b is output from signal line s'. When sel=1, value s+a*b is output from signal line d2', value d3 is output from signal line d3', and value d2 is output from signal line s'. When sel=2, value d2 is output from signal line d2', value s+a*b is output from signal line d3', and value d3 is output from signal line s'.

[0076] FIG. 10 is a diagram illustrating the matrix multiply-accumulate operation process when the SA 10 is divided into three parts horizontally in this embodiment.

[0077] In reference numeral G1 in FIG. 10, the boundary columns within SA10 are indicated by a bold frame and a double frame.

[0078] In the example shown in FIG. 10, three matrix operations are performed as shown in the following equations. C1′=A1·B1+C1 C2′=A2·B2+C2 C3′=A3·B3+C3

[0079] As shown by the symbol G1, SA10 has a matrix A1 t is input, and matrix A2 is input to SA#2. t is input, and matrix A3 is input to SA#3. t is input, and matrix C1 is input to SA#1 in the column direction, matrix C2 is input to SA#2, and matrix C3 is input to SA#3. Then, matrix C1' is output from the column direction of SA#1, C2' is output from the column direction of SA#2, and C3' is output from the column direction of SA#3. Matrix B is input in advance using signal line b and held in register 11.

[0080] Of the PE1c included in SA#1, the PE1c in the first and second columns are designated as group #1, and the PE1c in the third row, which is the boundary column with SA#2, is designated as group #2. Also, of the PE1c included in SA#2, the PE1c in the first and second columns are designated as group #1, and the PE1c in the third row, which is the boundary column with SA#3, is designated as group #3. Meanwhile, in SA#3, the PE1c in the first and second rows of all columns are designated as group #1.

[0081] PE1c indicated by symbol G2 includes a register (reg) 11, a multiplier 12, an adder 13, five FFs 14, and a selector 21. The elements indicated by the two-dot chain line in PE1c indicate elements added to the elements in PE1a when SA10 shown in FIG. 7 is divided into two horizontally.

[0082] Register 11 stores the elements of matrix B from signal line b. Multiplier 12 multiplies the elements of matrix A from signal line a by the elements of matrix B stored in register 11. Adder 13 adds the multiplication result of multiplier 12 to matrix C from signal line s.

[0083] The selector 21 selects the input from the signal line a, the input from the signal line e2 or the input from the signal line e3 in response to the sel signal and outputs the selected input to the signal line a'.

[0084] The sel signal is input as "0" to PE1c in group #1 indicated by symbol G1, as "1" to PE1c in group #2, and as "2" to PE1c in group #3.

[0085] That is, in PE1c of group #1, sel=0 is input to selector 21, so selector 21 outputs input from signal line a. Also, in PE1c of group #2, sel=1 is input to selector 21, so selector 21 outputs input from signal line e2. Furthermore, in PE1c of group #3, sel=2 is input to selector 21, so selector 21 outputs input from signal line e3.

[0086] The five FFs 14 are provided immediately before the output signal lines a', b', e2', e3', and s', and adjust the output timing of the output signals.

[0087] Symbol G3 shows the output value from each signal line according to the sel signal. When sel=0, the value a is output from signal line a'. When sel=1, the value e2 is output from signal line a'. When sel=2, the value e3 is output from signal line a'.

[0088] FIG. 11 is a block diagram schematically illustrating an example of the hardware configuration of an information processing device 3 according to the embodiment.

[0089] 11, the information processing device 3 includes a central processing unit (CPU) 31, a memory 32, a display control device 33, a storage device 34, an input interface (IF) 35, an external recording medium processing device 36, and a communication IF 37. The information processing device 3 may be a server, a supercomputer, or the like.

[0090] The memory 32 is an example of a storage unit, and is illustratively a read-only memory (ROM) and a RAM. A program such as a basic input / output system (BIOS) may be written to the ROM of the memory 32. The software program in the memory 32 may be read and executed by the CPU 31 as appropriate. The RAM of the memory 32 may be used as a temporary storage memory or a working memory.

[0091] The display control device 33 is connected to the display device 331 and controls the display device 331. The display device 331 is a liquid crystal display, an organic light-emitting diode (OLED) display, a cathode ray tube (CRT), an electronic paper display, or the like, and displays various information to the operator of the information processing device 3. The display device 331 may be combined with an input device, and may be, for example, a touch panel.

[0092] The storage device 34 may be, for example, a solid state drive (SSD), a storage class memory (SCM), or a hard disk drive (HDD).

[0093] The input IF 35 may be connected to input devices such as a mouse 351 and a keyboard 352, and may control the input devices such as the mouse 351 and the keyboard 352. The mouse 351 and the keyboard 352 are examples of input devices, and the operator of the information processing device 3 performs various input operations via these input devices.

[0094] The external recording medium processing device 36 is configured so that the recording medium 360 can be attached. The external recording medium processing device 36 is configured so that, when the recording medium 360 is attached, the information recorded on the recording medium 360 can be read. In this example, the recording medium 360 is portable. For example, the recording medium 360 is a non-transitory recording medium such as a flexible disk, an optical disk, a magnetic disk, a magneto-optical disk, or a semiconductor memory.

[0095] The communication IF 37 is an interface that enables communication with an external device.

[0096] The CPU 31 is an example of a processor, and is a processing device that performs various controls and calculations. The CPU 31 functions as the SA 10 and the control unit 100. The CPU 31 realizes various functions by executing an OS and programs loaded into the memory 32. The CPU 31 may be a multiprocessor including multiple CPUs, a multi-core processor having multiple CPU cores, or a configuration having multiple multi-core processors.

[0097] The device for controlling the overall operation of the information processing device 1 is not limited to the CPU 31, and may be, for example, any one of an MPU, a DSP, an ASIC, a PLD, and an FPGA. The device for controlling the overall operation of the information processing device 1 may also be a combination of two or more of the CPU, MPU, DSP, ASIC, PLD, and FPGA. MPU is an abbreviation for Micro Processing Unit, DSP is an abbreviation for Digital Signal Processor, and ASIC is an abbreviation for Application Specific Integrated Circuit. PLD is an abbreviation for Programmable Logic Device, and FPGA is an abbreviation for Field Programmable Gate Array.

[0098] [C] Effect FIG. 12 is a diagram comparing the matrix multiply-accumulate operation process in the related example with the matrix multiply-accumulate operation process in the embodiment.

[0099] In FIG. 12, as indicated by the symbol H1, a case will be described in which the matrix calculation of the following equation is performed in which the size N in the column direction is half the horizontal width of SA10.

[0100] A1·B1+C1=C1′ A2·B2+C2=C2′ In the related example shown by reference symbol H2, one matrix calculation is performed at a time, so the portion of SA10 enclosed by the dashed frame cannot be used. On the other hand, in the embodiment shown by reference symbol H3, two matrix calculations are performed at a time, so SA10 can be divided into SA#1 and SA#2 and the two matrix calculations can be performed in parallel.

[0101] According to the systolic array, the information processing device, and the arithmetic processing method in the above-described embodiments, the following advantageous effects can be achieved, for example.

[0102] SA10 includes SA#1 separated from the systolic array, SA#2 separated from SA10 and subsequent to SA#1, and a control unit 100. The multiple PEs 1, 1a include selectors 15-17 that select and output an output signal. The control unit 100 switches the output signals from the selectors 15-17 between the PE 1, 1a at the final stage of SA#1, the PEs 1, 1a other than the final stage of SA#1, and the PEs 1, 1a at SA#2.

[0103] This makes it possible to prevent a decrease in the calculation performance in matrix multiplication of small matrices.

[0104] When the matrix operations C1' = A1 · B1 + C1 and C2' = A2 · B2 + C2 are performed and SA#1 and SA#2 are divided vertically from SA10, the multiple PE1s are provided with a signal line that outputs the operation result C1' from the input of the constant matrix C1 and a signal line that outputs the operation result C2' from the input of the constant matrix C2.

[0105] This makes it possible to prevent a decrease in the calculation performance in the matrix multiplication of matrices that are small in the vertical direction.

[0106] When the matrix operations C1' = A1 · B1 + C1 and C2' = A2 · B2 + C2 are performed and SA#1 and SA#2 are divided horizontally from SA10, the multiple PE1a are provided with a signal line for inputting the multiplicand matrix A1 and a signal line for inputting the multiplicand matrix A2.

[0107] This makes it possible to prevent a decrease in the calculation performance in the matrix multiplication of matrices that are small in the horizontal direction.

[0108] [D] Other The disclosed technology is not limited to the above-described embodiment, and various modifications can be made without departing from the spirit of the present embodiment. The configurations and processes of the present embodiment can be selected or combined as needed.

[0109] In the above-described embodiment, an example in which SA10 is divided into two or three parts has been described, but this is not limiting. SA10 may be divided into four or more parts to perform matrix multiplication. This makes it possible to prevent a decrease in calculation performance when performing matrix multiplication on matrices that are significantly smaller than the size of SA10.

[0110] [E] Supplementary Note The following additional notes are provided regarding the above-described embodiments.

[0111] (Appendix 1) A systolic array having a plurality of processing elements, a first systolic array divided from the systolic array; a second systolic array separated from the first systolic array and located downstream of the first systolic array; a control unit, the plurality of processing elements each include a selector that selects and outputs an output signal; the control unit switches the output signal from the selector between a processing element in a final stage of the first systolic array, a processing element other than a final stage of the first systolic array, and a processing element in the second systolic array among the plurality of processing elements. Systolic array.

[0112] (Appendix 2) When matrix operations C1'=A1·B1+C1 and C2'=A2·B2+C2 are performed and the first systolic array and the second systolic array are vertically divided from the systolic array, The plurality of processing elements include a signal line that receives a constant matrix C1 as an input and outputs a calculation result C1', and a signal line that receives a constant matrix C2 as an input and outputs a calculation result C2'. 1. A systolic array as described in Appendix 1.

[0113] (Appendix 3) When matrix operations C1'=A1·B1+C1 and C2'=A2·B2+C2 are performed and the first systolic array and the second systolic array are horizontally divided from the systolic array, The plurality of processing elements include a signal line for inputting a multiplicand matrix A1 and a signal line for inputting a multiplicand matrix A2. 3. The systolic array of claim 1 or 2.

[0114] (Appendix 4) An information processing device comprising a systolic array having a plurality of processing elements, a first systolic array divided from the systolic array; a second systolic array separated from the first systolic array and located downstream of the first systolic array; a control unit, the plurality of processing elements each include a selector that selects and outputs an output signal; the control unit switches the output signal from the selector between a processing element in a final stage of the first systolic array, a processing element other than a final stage of the first systolic array, and a processing element in the second systolic array among the plurality of processing elements. Information processing device.

[0115] (Appendix 5) When matrix operations C1'=A1·B1+C1 and C2'=A2·B2+C2 are performed and the first systolic array and the second systolic array are vertically divided from the systolic array, The plurality of processing elements include a signal line that receives a constant matrix C1 as an input and outputs a calculation result C1', and a signal line that receives a constant matrix C2 as an input and outputs a calculation result C2'. 5. The information processing device according to claim 4.

[0116] (Appendix 6) When matrix operations C1'=A1·B1+C1 and C2'=A2·B2+C2 are performed and the first systolic array and the second systolic array are horizontally divided from the systolic array, The plurality of processing elements include a signal line for inputting a multiplicand matrix A1 and a signal line for inputting a multiplicand matrix A2. 6. The information processing device according to claim 4 or 5.

[0117] (Appendix 7) In a systolic array having a plurality of processing elements, a first systolic array divided from the systolic array; a second systolic array separated from the first systolic array and located downstream of the first systolic array; the plurality of processing elements each include a selector that selects and outputs an output signal; among the plurality of processing elements, the output signal from the selector is switched between the processing element in the final stage of the first systolic array, the processing elements other than the final stage of the first systolic array, and the processing elements of the second systolic array; A computational processing method in which processing is performed by a computer.

[0118] (Appendix 8) When matrix operations C1'=A1·B1+C1 and C2'=A2·B2+C2 are performed and the first systolic array and the second systolic array are vertically divided from the systolic array, The plurality of processing elements include a signal line that receives a constant matrix C1 as an input and outputs a calculation result C1', and a signal line that receives a constant matrix C2 as an input and outputs a calculation result C2'. 8. The calculation method according to claim 7.

[0119] (Appendix 9) When matrix operations C1'=A1·B1+C1 and C2'=A2·B2+C2 are performed and the first systolic array and the second systolic array are horizontally divided from the systolic array, The plurality of processing elements include a signal line for inputting a multiplicand matrix A1 and a signal line for inputting a multiplicand matrix A2. 9. The arithmetic processing method according to claim 7 or 8. [Explanation of symbols]

[0120] 10 :SA 1 :PE 11,61: Register 12,62: Multiplier 13,63: Adder 14 :FF 15~21: Selector 100: Control unit 3: Information processing equipment 31: CPU 32: Memory 33: Display control device 331:Display device 34: Storage device 35: Input IF 351: Mouse 352: Keyboard 36: External recording medium processing device 360: Recording media 37: Communication IF

Claims

1. A systolic array having a plurality of processing elements, a first systolic array divided from the systolic array; a second systolic array separated from the first systolic array and located downstream of the first systolic array; a control unit, the plurality of processing elements each include a selector that selects and outputs an output signal; the control unit switches the output signal from the selector between a processing element in a final stage of the first systolic array, a processing element other than a final stage of the first systolic array, and a processing element in the second systolic array among the plurality of processing elements. Systolic array.

2. C １ '=A １ ・B １ +C １ matrix operations and C ２ '=A ２ ・B ２ +C ２ and when the first systolic array and the second systolic array are vertically divided from the systolic array, The plurality of processing elements are １ The input of the calculation result C １ ' and a constant matrix C ２ The input of the calculation result C ２ and a signal line for outputting 10. The systolic array of claim 1.

3. C １ '=A １ ・B １ +C １ matrix operations and C ２ '=A ２ ・B ２ +C ２ and when the first systolic array and the second systolic array are horizontally divided from the systolic array, The plurality of processing elements are multiplicand matrix A １ and a signal line for inputting the multiplicand matrix A ２ and a signal line for inputting the signal.

3. A systolic array according to claim 1 or 2.

4. An information processing device comprising a systolic array having a plurality of processing elements, a first systolic array divided from the systolic array; a second systolic array separated from the first systolic array and located downstream of the first systolic array; a control unit, the plurality of processing elements each include a selector that selects and outputs an output signal; the control unit switches the output signal from the selector between a processing element in a final stage of the first systolic array, a processing element other than a final stage of the first systolic array, and a processing element in the second systolic array among the plurality of processing elements. Information processing device.

5. In a systolic array having a plurality of processing elements, a first systolic array divided from the systolic array; a second systolic array separated from the first systolic array and located downstream of the first systolic array; the plurality of processing elements each include a selector that selects and outputs an output signal; switching the output signal from the selector between the processing element in the final stage of the first systolic array, the processing elements other than the final stage of the first systolic array, and the processing elements in the second systolic array among the plurality of processing elements; A computational processing method in which processing is performed by a computer.

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