Semiconductor device and communication system

Abstract

To provide a semiconductor device capable of specifying abnormality in serial communication.SOLUTION: A semiconductor device (1) includes a receiver (11) configured to receive reception data (RX) as serial data from the outside, and an abnormality check unit (13C) configured to check the reception data to check the presence or absence of an abnormality whose cause is identified.SELECTED DRAWING: Figure 4

Description

[Technical Field]

[0001] The present disclosure relates to semiconductor devices. [Background technology]

[0002] Semiconductor devices having a serial communication function are used in a variety of applications.

[0003] An example of circuit technology relating to serial communication is disclosed in Patent Document 1. [Prior art documents] [Patent documents]

[0004] [Patent Document 1] Japanese Patent Application Publication No. 2017-224946

[0005] [overview] Here, in serial communication, anomalies may occur due to various factors.

[0006] A semiconductor device according to an aspect of the present disclosure includes: a receiving unit configured to receive received data as serial data from an external device; The data processing device is configured to include an abnormality check unit configured to check the received data to see if there is an abnormality whose cause can be identified. [Brief explanation of the drawings]

[0007] [Figure 1] FIG. 1 is a diagram illustrating a configuration of a communication system according to an example embodiment of the present disclosure. [Figure 2] FIG. 2 is a diagram illustrating a configuration of a communication system according to another example of an embodiment of the present disclosure. [Figure 3] FIG. 3 is a diagram showing the format of the received data RX during the write process. [Figure 4] FIG. 4 is a diagram showing a configuration related to communication control in the semiconductor device. [Figure 5] FIG. 5 is a diagram showing received data RX and transmitted data TX during a write process or a read process. [Figure 6] FIG. 6 is a flowchart illustrating the abnormality check process according to the first embodiment. [Figure 7A] FIG. 7A is a diagram showing a frame of received data RX in a normal case. [Figure 7B] FIG. 7B is a diagram showing a frame of received data RX in the case of an abnormality. [Figure 7C] FIG. 7C is a diagram showing a frame of received data RX in the case of an abnormality. [Figure 8A] FIG. 8A is a diagram showing a normal state during a read process in the communication system shown in FIG. [Figure 8B] FIG. 8B is a diagram showing a normal state during a read process in the communication system shown in FIG. [Figure 8C] FIG. 8C is a diagram showing an abnormal state during a read process in the communication system shown in FIG. [Figure 9] FIG. 9 is a diagram illustrating the configuration of a CAN transceiver. [Figure 10] FIG. 10 is a flowchart relating to an abnormality check according to the third embodiment. [Figure 11] FIG. 11 shows the synchronization frame SYN in normal and abnormal cases. [Figure 12] FIG. 12 is a flowchart relating to an abnormality check according to the fourth embodiment. [Figure 13] FIG. 13 is a diagram showing the synchronization frame SYN. [Figure 14] FIG. 14 is an external view showing an example of a vehicle.

[0008] [Detailed explanation] Hereinafter, exemplary embodiments of the present disclosure will be described with reference to the drawings.

[0009] <Communication Systems> 1 is a diagram illustrating a configuration of a communication system 501 according to an example of an embodiment of the present disclosure. The communication system 501 includes an MCU (Micro Controller Unit) 20 and a semiconductor device 1. Communication between the MCU 20 and the semiconductor device 1 is performed using a UART (Universal Asynchronous Receiver / Transmitter) as a communication method. UART is a format for exchanging serial data between two devices. In UART, bidirectional communication is performed between the transmitting side and the receiving side using two lines.

[0010] The semiconductor device 1 is an IC (integrated circuit) in which circuits with predetermined functions are integrated, and is configured as, for example, an LED (light emitting diode) driver IC.

[0011] An output terminal 20A of the MCU 20 is connected to an RX (received data input) terminal 1A of the semiconductor device 1. An input terminal 20B of the MCU 20 is connected to a TX (transmitted data output) terminal 1B of the semiconductor device 1. The RX terminal 1A receives the received data RX output from the output terminal 20A. The transmitted data TX transmitted from the TX terminal 1B is input to the input terminal 20B.

[0012] 2 is a diagram illustrating a configuration of a communication system 502 according to another example of an embodiment of the present disclosure. The communication system 502 includes an MCU 20, a CAN (Controller Area Network) transceiver 30, a CAN transceiver 40, and a semiconductor device 1.

[0013] Communication between the MCU 20 and the CAN transceiver 30 is performed using UART as a communication method. Communication between the CAN transceivers 30 and 40 is performed using a CAN bus 35. CAN is a serial communication protocol standardized in international standards such as ISO11898. Communication between the CAN transceiver 40 and the semiconductor device 1 is performed using UART.

[0014] The CAN transceiver 30 has a TXD (transmit data input) terminal 30A and an RXD (receive data output) terminal 30B. The TXD terminal 30A is connected to the output terminal 20A of the MCU 20. The RXD terminal 30B is connected to the input terminal 20B of the MCU 20. The CAN transceiver 30 outputs data input to the TXD terminal 30A to the CAN bus 35, and outputs data input from the CAN bus 35 from the RXD terminal 30B.

[0015] The CAN transceiver 40 has an RXD terminal 40A and a TXD terminal 40B. The CAN transceiver 40 outputs data input to the TXD terminal 40B to the CAN bus 35, and outputs data input from the CAN bus 35 from the RXD terminal 40A.

[0016] The RXD terminal 40A is connected to the RX terminal 1A of the semiconductor device 1. The TXD terminal 40B is connected to the TX terminal 1B of the semiconductor device 1. Reception data RX output from the RXD terminal 40A is input to the RX terminal 1A. Transmission data TX output from the TX terminal 1B is input to the TXD terminal 40B.

[0017] <2. Write / Read processing> Next, a description will be given of write processing and read processing for the semiconductor device 1. Write processing is processing for writing data to the semiconductor device 1, and read processing is processing for reading data from the semiconductor device 1.

[0018] FIG. 3 is a diagram showing the format of received data RX during write processing. In UART, communication is performed using data units called frames. As shown in FIG. 3, a frame FR is made up of bit data from a start bit S to a stop bit P. The start bit S is at low level, and the stop bit P is at high level. A predetermined number of bits of bit data are placed between the start bit S and the stop bit P. For example, if 8 bits of bit data are placed, the frame FR is made up of 10 bits of bit data.

[0019] As shown in FIG. 3, the received data RX includes, from the beginning, a synchronization frame SYN, a read / write etc. frame RWD, a data number frame ND, a register address frame AD, write data DT, and CRC (Cyclic Redundancy Check) data CR.

[0020] The synchronization frame SYN is bit data for setting the baud rate in the semiconductor device 1 .

[0021] The Read / Write etc. frame RWD includes a device address and a Read / Write bit. The device address is bit data (e.g., 5-bit data) indicating the address of the target device (semiconductor device 1). The Read / Write bit is bit data (1 bit) indicating Read or Write.

[0022] The data number frame ND is bit data indicating the number of frames included in the write data DT.

[0023] The register address frame AD is bit data indicating an address in a register of the semiconductor device 1. The write data DT is made up of data frames DR1 to DTn (n is an integer equal to or greater than 1).

[0024] The CRC data CR is bit data indicating an error detection code added to the frames RWD, ND, AD and Write data DT for error detection purposes. The CRC data CR has a lower CRC frame CRL and an upper CRC frame CRH.

[0025] Fig. 4 is a diagram showing a configuration related to communication control in the semiconductor device 1. Note that Fig. 4 omits configurations other than those related to communication control, and for example, when the semiconductor device 1 is an LED driver IC, the semiconductor device 1 has a configuration related to LED driving, etc.

[0026] The semiconductor device 1 includes a receiving unit 11, a transmitting unit 12, and a control unit 13. The receiving unit 11 receives reception data RX via an RX terminal 1A and performs reception processing. The receiving unit 11 includes a counter 11A that counts a clock CLK. The counter 11A is used to set a baud rate using a synchronization frame SYN, etc.

[0027] The control unit 13 has a CRC check unit 13A and a register 13B. The CRC check unit 13A performs error detection using CRC data CR. The register 13B can store various types of data, and can write data to and read data from the register 13B.

[0028] The transmitter 12 transmits the transmission data TX via the TX terminal 1B.

[0029] The abnormality check unit 13C included in the control unit 13 will be described later.

[0030] The upper part of Figure 5 shows the received data RX and transmitted data TX during write processing. First, a synchronization frame SYN is transmitted using the received data RX and received by the receiver 11. In the receiver 11, a clock CLK has a predetermined frequency (e.g., 48 MHz), and a counter 11A counts the clock CLK for a predetermined number of bits (e.g., 8 bits) of data in the synchronization frame SYN. ​​The obtained count value then gives the time for one bit, i.e., the baud rate (unit: bps). The receiver 11 sets the obtained baud rate, and performs bit-by-bit sampling on the frames following the synchronization frame SYN based on the set baud rate. This allows the bit value (0 or 1) of the bit data between the start bit S and stop bit P in each frame to be obtained.

[0031] Next, when the receiving unit 11 receives the R / W etc. frame, the bit value of the bit data representing the device address etc. between the start bit S and the stop bit P in the R / W etc. frame RWD is acquired. At this time, the Read / Write bit represents Write.

[0032] Next, when the receiving unit 11 receives the data number frame ND, the bit value of the bit data representing the number of frames included in the write data DT between the start bit S and the stop bit P in the data number frame ND is obtained.

[0033] Next, when the receiver 11 receives the register address frame AD, the bit value of the bit data representing the register address between the start bit S and the stop bit P in the register address frame AD is obtained.

[0034] Next, when the data frames DT1 to DTn are received by the receiving unit 11, the bit values ​​of the bit data representing the write data between the start bit S and the stop bit P in each of the data frames DT1 to DTn are obtained.

[0035] Next, when the receiving unit 11 receives the low-order CRC frame CRL and the high-order CRC frame CRH, the bit values ​​of the bit data representing the error detection data between the start bit S and the stop bit P in each CRC frame are obtained.

[0036] Then, the CRC check unit 13A performs error detection processing using CRC based on the error detection data obtained above. If no error is detected, the control unit 13 writes the obtained write data to the register address obtained above in the register 13B.

[0037] This completes the write process. In the case of a write process, the transmission data TX is at a fixed level and is not transmitted.

[0038] The bottom part of Figure 5 shows the received data RX and transmitted data TX during a read process. In a read process, the receiver 11 first receives a synchronization frame STN and sets the baud rate. Next, the receiver 11 receives an R / W etc. frame R / W and obtains the device address, R / W bit, etc. At this time, the R / W bit indicates a read.

[0039] Next, the register address is acquired when the register address frame AD is received by the receiving unit 11. During a read process, the data number frame ND, write data DT, and CRC data CR are not included in the received data RX.

[0040] Then, the transmitter 12 reads data from the register address acquired above in the register 13B, adds a start bit and a stop bit to the read data, and transmits data frames RDT1 to RDTn (n is an integer equal to or greater than 1) as transmission data TX.

[0041] Next, the transmitter 12 transmits the CRC data RCR added to the read data RDT consisting of the data frames RDT1 to RDTn as transmission data TX. The CRC data RCR consists of a lower CRC frame CRL2 and an upper CRC frame CRH2. This completes the read process.

[0042] <3. Abnormality check> Next, various types of abnormality checks performed by the abnormality check unit 13C will be described. The abnormalities detected by the abnormality check unit 13C are abnormalities whose causes can be identified. Note that the cause of an abnormality cannot be identified by a CRC check. <<First embodiment (noise check)>> 6 is a flowchart illustrating an abnormality check process according to the first embodiment. In this embodiment, an abnormality caused by environmental noise can be detected. An abnormality occurs in the received data RX on the wiring that transmits the received data RX between the MCU 20 and the semiconductor device 1 due to environmental noise.

[0043] 6 is performed on a frame of received data RX, which may be any frame.

[0044] When there is a falling edge in the received data RX and the start bit S in the frame is detected, the process in Fig. 6 starts. First, in step S1, it is confirmed whether there is a rising edge in the received data RX, and while there is no rising edge (N in step S1), the process returns to step S1, and when there is a rising edge (Y in step S1), the process proceeds to step S2.

[0045] Here, it is confirmed whether the time interval between the most recent falling edge and the current rising edge corresponds to a possible time interval of a predetermined pattern. For example, if 8 bits of data are arranged between the start bit S and the stop bit P, when the start bit S falls, the next rising edge will be at any one of the 1st to 8th bits or the stop bit P, and the time interval pattern corresponding to each bit will be the above-mentioned predetermined pattern. The time for one bit is determined by the baud rate. Furthermore, whether the time interval corresponds to the predetermined pattern may take into account a tolerance.

[0046] If the time interval does not match the predetermined pattern (N in step S2), the process proceeds to step S5, where it is determined that an abnormality has occurred. On the other hand, if the time interval matches the predetermined pattern (Y in step S2), the process proceeds to step S3, where it is confirmed whether there is a falling edge in the received data RX. If there is no falling edge (N in step S3), the process returns to step S3. If there is a falling edge (Y in step S3), the process proceeds to step S4.

[0047] Here, it is confirmed whether the time interval between the most recent rising edge and the current falling edge corresponds to a possible time interval of a predetermined pattern. For example, if 8 bits of data are placed between the start bit S and the stop bit P, when the first bit rises, the next falling edge will occur at any one of the second to eighth bits, and the corresponding time interval pattern will be the above-mentioned predetermined pattern.

[0048] If the time interval does not match the predetermined pattern (N in step S4), the process proceeds to step S5, where it is determined that an abnormality has occurred. On the other hand, if the time interval matches the predetermined pattern (Y in step S4), the process returns to step S1.

[0049] During the processing of FIG. 6, if a predetermined time has passed from the start bit S to the last bit between the start bit S and the stop bit P, it is determined to be normal and the processing is completed.

[0050] Here, the processing in Fig. 6 will be described using the examples of Fig. 7A to Fig. 7C. Fig. 7A shows a case where the received data RX is normal. In this case, rising and falling edges alternate from the start bit S to the stop bit P, and therefore the time intervals T1 to T9 between adjacent rising and falling edges each fall into a predetermined pattern, and the data is determined to be normal.

[0051] 7B shows a case where a short falling pulse PL1 occurs due to noise midway through the third bit (b2) of the bits between the start bit S and the stop bit P in the received data RX. In this case, the time intervals T1 to T3 corresponding to the start bit S, the first bit b0, and the second bit b1 conform to a predetermined pattern, but the time interval T4 from the rising edge of the third bit b2 to the falling edge of the pulse PL1 no longer conforms to the predetermined pattern (N in step S4), and it is determined to be abnormal (step S5).

[0052] 7C shows a case where a short falling pulse PL2 due to noise occurs midway through the fourth bit (b3) of the bits between the start bit S and the stop bit P in the received data RX. In this case, the time intervals T1 to T3 corresponding to the start bit S, the first bit b0, and the second bit b1 conform to a predetermined pattern, but the time interval T4 from the rising edge of the third bit b2 to the falling edge of the pulse PL2 no longer conforms to the predetermined pattern (N in step S4), and it is determined to be abnormal (step S5).

[0053] If a short rising pulse occurs due to noise, the time interval from the falling edge to the rising edge does not match the predetermined pattern (N in step S2), and it is determined to be abnormal (step S5).

[0054] <<Second embodiment (conflict check)>> Next, a second embodiment will be described. In this embodiment, it is possible to detect an abnormality caused by an abnormality (software abnormality) of the MCU 20. Specifically, it is determined whether the received data RX is abnormally received when the transmitted data TX is transmitted during a read process.

[0055] First, an abnormality check according to this embodiment in the communication system 501 shown in FIG. 1 will be described. FIG. 8A is a diagram showing a normal state during a read process in the communication system 501. In the read process, after the receiving unit 11 receives the received data RX from the synchronization frame SYN to the CRC frames CRL and CRH, the transmitting unit 12 transmits the data frames RDT1 to RDTn and the CRC frames CRL2 and CRH2 as readback data RBK via the transmission data TX. Here, if the data is normal, as shown in FIG. 8A, the received data RX is fixed to a high level when the readback data RBK is transmitted. On the other hand, if the data is abnormal, the received data RX includes a low level when the readback data RBK is transmitted. In this way, in this embodiment, it is confirmed whether the received data RX is fixed to a high level when the readback data RBK is transmitted, and whether the data is normal is determined.

[0056] Next, an abnormality check according to this embodiment in the communication system 502 shown in Fig. 2 will be described. Fig. 8B is a diagram showing a normal state during a read process in the communication system 502. In the read process, readback data RBK is transmitted by the transmission data TX, but the CAN transceiver 40 provided in the communication system 502 mirrors the readback data RBK to the reception data RX.

[0057] 9 is a diagram showing the configuration of a CAN transceiver 40. The CAN transceiver 40 has a driver control unit 41, a driver 42, a receiver 43, and an output unit 44. The CAN transceiver 40 also has a TXD terminal 40B, an RXD terminal 40A, a CANH terminal, and a CANL terminal.

[0058] The CANH terminal and the CANL terminal are connected to the respective lines of the CAN bus 35. Termination resistors R1 and R2 are connected in series between the CANH terminal and the CANL terminal. The resistance value of the termination resistors is specified by ISO 11898, and each of the termination resistors R1 and R2 is configured as a 60 Ω resistor. One end of the capacitor C1 is connected to a connection node N1 where the resistors R1 and R2 are connected to each other.

[0059] The driver 42 has a PMOS transistor (P-channel metal-oxide-semiconductor field-effect transistor (MOSFET)) 42A, a diode 42B, an NMOS transistor (N-channel MOSFET) 42C, and a diode 42D. The source of the PMOS transistor 42A is connected to the application terminal of the power supply voltage VCC. The drain of the PMOS transistor 42A is connected to the anode of the diode 42B. The cathode of the diode 42B is connected to the CANH terminal. The source of the NMOS transistor 42C is connected to the ground terminal. The drain of the NMOS transistor 42C is connected to the cathode of the diode 42D. The anode of the diode 42D is connected to the CANL terminal. The diodes 42B and 42D are used to prevent backflow when a surge occurs.

[0060] The driver control unit 41 receives transmission data TX from the outside via the TXD terminal. The PMOS transistor 42A and the NMOS transistor 42C are controlled to be turned on and off by the do.

[0061] More specifically, when the PMOS transistor 42A and the NMOS transistor 42C are turned on, the current flowing through the termination resistors R1 and R2 is the same, so the voltage drops across the termination resistors R1 and R2 are the same, and the high-side signal CANH generated at the CANH terminal is a voltage higher than the voltage at the connection node N1 (=midpoint voltage) by the voltage drop, while the low-side signal CANL generated at the CANL terminal is a voltage lower than the voltage at the connection node N1 (=midpoint voltage) by the voltage drop. In this case, the high-side signal CANH is at a high level, and the low-side signal CANL is at a low level.

[0062] Here, the CANH terminal and the CANL terminal are connected to the application terminal of the power supply voltage VCC2 via resistors R41 and R42, respectively. When the PMOS transistor 42A and the NMOS transistor 42C are turned off, the voltage of the connection node N1 gradually approaches the second power supply voltage VCC2 due to the action of the resistors R41 and R42, which have relatively high resistance values. The second power supply voltage VCC2 is the low level of the high-side signal CANH and the high level of the low-side signal CANL, and is the same voltage as the intermediate voltage.

[0063] In this way, the transmission data TX input to the TXD terminal is output to the CAN bus 35 from the CANH terminal and the CANL terminal.

[0064] On the other hand, the output section 44 has a PMOS transistor 44A and an NMOS transistor 44B. The source of the PMOS transistor 44A is connected to the terminal to which the power supply voltage VCC is applied. The drain of the PMOS transistor 44A is connected to the drain of the NMOS transistor 44B at a node N42. The source of the NMOS transistor 44B is connected to the ground terminal. The voltages at the CANH terminal and the CANL terminal are input to the receiver 43. The output terminal of the receiver 43 is connected to a node N41 to which the gates of the PMOS transistor 44A and NMOS transistor 44B are connected. The node N42 is connected to the RXD terminal.

[0065] The receiver 43 applies a high-level or low-level signal to the node N41 according to the difference in the input voltage. Therefore, the output unit 44 outputs a signal obtained by logically inverting the output of the receiver 43 from the RXD terminal to the outside as received data RX. In this way, the data input from the CAN bus 35 is output from the RXD terminal.

[0066] When the high-side signal CANH is high and the low-side signal CANL is low, it is called "dominant." When the high-side signal CANH is low and the low-side signal CANL is high, it is called "recessive." Dominant signals take priority over recessive signals.

[0067] 8B, when the readback data RBK is being transmitted, if normal, there is no transmission from the MCU 20 and the CAN transceiver 30 is set to recessive, so the readback data RBK can be transmitted to the CAN transceiver 30. At this time, the high-side signal CANH and the low-side signal CANL are input to the receiver 43 and output as received data RX from the output unit 44. That is, the readback data RBK is mirrored as shown in FIG. 8B to become received data RX.

[0068] On the other hand, as shown in the example of FIG. 8C, an abnormality in the MCU 20 may cause the MCU 20 to perform the next transmission while the readback data RBK is being transmitted. In this case, the readback data RBK and the received data RX are mixed, causing the received data RX to differ from the data obtained by mirroring the readback data RBK. This is because the CAN transceiver 30 side may become dominant when the high-side signal CANH and the low-side signal CANL based on the transmitted data TX are recessive.

[0069] In this manner, in this embodiment, when the read-back data RBK is transmitted, it is confirmed whether the received data RX is data that mirrors the read-back data RBK, and it is determined whether it is normal.

[0070] <<Third embodiment (synchronization frame pattern check)>> Next, a third embodiment will be described. In this embodiment, an abnormality caused by an abnormality (software abnormality) of the MCU 20 can be detected. Specifically, the synchronization frame SYN in the received data RX has a pattern in which the start bit S alternates from a low level to a high level and back again, and an abnormality related to this pattern can be detected.

[0071] Fig. 10 is a flowchart relating to an abnormality check according to this embodiment. When a falling edge (i.e., start bit S) in the synchronization frame SYN is detected, the processing in Fig. 10 starts. First, in step S11, it is confirmed whether there is a rising edge in the received data RX, and if there is no rising edge (N in step S11), the processing returns to step S11. If there is a rising edge (Y in step S11), the processing proceeds to step S12, where the time interval from the most recent falling edge to the current rising edge is acquired.

[0072] Next, in step S13, it is confirmed whether there is a falling edge in the received data RX, and if there is no falling edge (N in step S13), the process returns to step S13. If there is a falling edge (Y in step S13), the process acquires the time interval from the most recent rising edge to the current falling edge in step S14. Then, in step S15, it is confirmed whether there is a difference between the time interval acquired in step S12 and the time interval acquired in step S14. If there is a difference (Y in step S15), the process proceeds to step S19, where it is determined that there is an abnormality.

[0073] On the other hand, if there is no difference (N in step S15), in step S16 it is checked whether there is a rising edge in the received data RX, and if there is no rising edge (N in step S16), the process returns to step S16. If there is a rising edge (Y in step S16), in step S17 the time interval from the most recent falling edge to the current rising edge is acquired. Then, in step S18 it is checked whether there is a difference between the time interval acquired in step S14 and the time interval acquired in step S17. If there is a difference (Y in step S18), the process proceeds to step S19, where it is determined that there is an abnormality.

[0074] On the other hand, if there is no difference (N in step S18), the process returns to step S13, where it is confirmed whether there is a falling edge in the received data RX, and if there is a falling edge, the time interval is acquired in step S14, and it is confirmed in step S15 whether there is a difference between the time interval acquired in step S17 and the time interval acquired in step S14. Thereafter, the same operations as those described above are performed.

[0075] During the processing of Figure 10, if a rising edge due to the stop bit P is detected and there is no difference in the time interval, it is determined to be normal. Note that the confirmation of whether there is a difference in the time interval above may take into account an allowable error. In other words, even if there is a difference in the time interval, it may be considered that there is no difference as long as it is within the allowable error.

[0076] An example of a normal synchronization frame SYN is shown in the upper part of Fig. 11. In this case, it is confirmed that there is no difference between adjacent time intervals T1 to T9 from the start bit S to the last bit b7 between the start bit S and the stop bit P, and therefore it is determined to be normal.

[0077] On the other hand, the bottom part of Fig. 11 shows an example of an abnormal synchronization frame SYN. ​​Specifically, bit b2 is shifted forward in time due to jitter. This causes a difference between time intervals T2 and T3 (Y in step S18), and it is determined to be abnormal (step S19).

[0078] Furthermore, as shown by the dashed line in the lower part of Figure 11, if bit b2, which would normally be at high level, is at low level due to an abnormality, a difference occurs between the time interval T2 and the time interval T3' from the falling edge to the rising edge of the received data RX (Y in step S18), and it is determined that there is an abnormality (step S19).

[0079] 8C, if there is a transmission by the MCU 20 during transmission of readback data RBK during a read process, and a frame in the received data RX after the last frame (high-order CRC frame CRH2) of the readback data RBK is mistakenly recognized as a synchronization frame SYN, an abnormality can be detected by the abnormality check according to this embodiment. This is because the level of the incorrectly recognized frame does not necessarily change alternately for each bit, as in the synchronization frame SYN.

[0080] <<Fourth embodiment (synchronization frame stability check)>> Next, a fourth embodiment will be described. In this embodiment, it is possible to detect an abnormality caused by an abnormality (software abnormality) in the MCU 20. Specifically, it is confirmed whether the baud rate of the synchronization frame SYN is stable.

[0081] Fig. 12 is a flowchart relating to an abnormality check according to this embodiment. The process of Fig. 12 starts, and first, in step S21, a count value (a value obtained by counting the clock CLK) by the counter 11A for a predetermined number of bits in the synchronization frame SYN is obtained and saved. Here, a count value obtained by counting a predetermined number of bits (e.g., 8 bits) is used to set the baud rate using the synchronization frame SYN. ​​In the example of Fig. 13, a count value for 8 bits from the start bit S to bit b6 in the synchronization frame SYN is obtained.

[0082] Next, in step S22, the count value of the counter 11A for a predetermined number of bits in the next synchronization frame SYN is acquired and saved. Then, in step S23, it is confirmed whether the difference between the count value acquired in step S21 and the count value acquired in step S22 is equal to or greater than a threshold value. If it is equal to or greater than the threshold value (Y in step S23), it is determined to be abnormal (step S24).

[0083] On the other hand, if it is smaller than the threshold (N in step S23), the process returns to step S22, where the count value for the next synchronization frame SYN is acquired and saved. Then, in step S23, it is confirmed whether the difference between the count value acquired in the previous step S22 and the count value acquired in the current step S22 is equal to or greater than the threshold, and if it is equal to or greater than the threshold (Y in step S23), it is determined to be abnormal (step S24). On the other hand, if it is smaller than the threshold (N in step S23), the process returns to step S22.

[0084] This process checks the stability of the baud rate of the synchronization frame SYN by checking the difference between the count values ​​in the previous and current synchronization frame SYN. ​​In particular, when saving the count value, the older count value can be overwritten, so only a small storage area is required.

[0085] It is also possible to sequentially save and accumulate the count values ​​acquired in steps S21 and S22, and check the difference between the maximum and minimum values ​​of the currently saved count values ​​in step S23.

[0086] <4. Vehicles> Fig. 14 is an external view showing one configuration example of a vehicle X. The vehicle X of this configuration example is equipped with various electronic devices X11 to X18 that operate by receiving power supply from a battery (not shown). Note that the installation positions of the electronic devices X11 to X18 in Fig. 14 may differ from the actual positions for convenience of illustration.

[0087] The electronic device X11 is an engine control unit that performs engine-related controls (injection control, electronic throttle control, idling control, oxygen sensor heater control, auto-cruise control, etc.).

[0088] The electronic device X12 is a lamp control unit that controls the turning on and off of HID (high intensity discharged lamp) and DRL (daytime running lamp).

[0089] The electronic device X13 is a transmission control unit that controls transmission-related functions.

[0090] The electronic device X14 is a body control unit that performs control related to the movement of the vehicle X (ABS [anti-lock brake system] control, EPS [electric power steering] control, electronic suspension control, etc.).

[0091] The electronic device X15 is a security control unit that controls the operation of door locks, burglar alarms, and other devices.

[0092] The electronic device X16 is an electronic device that is installed in the vehicle X at the time of shipment from the factory as a standard equipment or a manufacturer option, such as a wiper, an electric door mirror, a power window, a damper (shock absorber), an electric sunroof, and an electric seat.

[0093] The electronic device X17 is an electronic device that is optionally installed in the vehicle X as a user option, such as an in-vehicle A / V (audio / visual) device, a car navigation system, and an ETC (electronic toll collection system).

[0094] The electronic device X18 is an electronic device equipped with a high-voltage motor, such as an in-vehicle blower, oil pump, water pump, or battery cooling fan.

[0095] The communication system including the MCU 20 and the semiconductor device 1 described above may be applied to any of the electronic devices X11 to X18.

[0096] <5.Other> In addition to the above-described embodiments, various modifications can be made to the various technical features disclosed in this specification without departing from the spirit of the technical creation. In other words, the above-described embodiments should be considered to be illustrative and not restrictive in all respects, and the technical scope of the present disclosure should not be limited to the above-described embodiments, but should be understood to include all modifications that fall within the meaning and scope equivalent to the claims.

[0097] <6. Notes> As described above, the semiconductor device (1) according to one embodiment of the present disclosure is a receiving unit (11) configured to receive received data (RX) as serial data from an external device; The configuration includes an abnormality check unit (13C) configured to check the received data to see if there is an abnormality whose cause can be identified (first configuration).

[0098] With this configuration, it is possible to identify an abnormality in serial communication.

[0099] In the first configuration, the factor may be environmental noise (second configuration).

[0100] In addition, in the second configuration, the abnormality check unit may be configured to check whether the time interval from a falling edge to a rising edge in the received data, or the time interval from a rising edge to a falling edge, corresponds to a possible predetermined pattern (third configuration).

[0101] In the first configuration, the cause may be an abnormality in a transmitting device (20) configured to transmit the serial data (fourth configuration).

[0102] In addition, in the fourth configuration, a transmitting unit (12) is provided, The abnormality check unit may be configured to check whether the received data is at a fixed level while readback data (RBK) is being transmitted from the transmission unit after receiving the received data in the case of a read process (fifth configuration).

[0103] In addition, in the fourth configuration, a transmitting unit (12) is provided, The abnormality check unit may be configured to check whether the received data is data that mirrors the readback data (RBK) while the readback data (RBK) is being transmitted from the transmitting unit after receiving the received data in the case of a read process (sixth configuration).

[0104] In addition, in the above fourth configuration, the abnormality check unit may be configured to check whether there is a difference between the time interval from the falling edge to the rising edge and the time interval from the rising edge to the falling edge in a synchronization frame (SYN) as the received data (seventh configuration).

[0105] In addition, in the fourth configuration, a counter (11A) configured to count a clock (CLK) is provided, The abnormality check unit may be configured to obtain a count value by the counter corresponding to a predetermined number of bits in a synchronization frame as the received data, and check a change in the count value in different synchronization frames (eighth configuration).

[0106] In the eighth configuration, the abnormality check unit may store the previous and current count values ​​and check the difference between the previous and current count values ​​(ninth configuration).

[0107] In the eighth configuration, the abnormality check unit may successively save and accumulate the count values, and check the difference between the maximum and minimum values ​​of the saved count values ​​(tenth configuration).

[0108] Furthermore, one aspect of the present disclosure includes a semiconductor device having any one of the first to tenth configurations above, and a transmitting device configured to transmit the received data (eleventh configuration).

[0109] Moreover, the eleventh configuration may be configured to be mounted on a vehicle (twelfth configuration). [Industrial Applicability]

[0110] The present disclosure can be used, for example, in communication systems for various applications. [Explanation of symbols]

[0111] 1. Semiconductor device 1A RX terminal 1B TX terminal 11 Receiving unit 11A Counter 12 Transmitter 13 Control Unit 13A CRC check section 13B Register 13C Abnormality check section 20A output terminal 20B input terminal 30,40 CAN transceiver 30A TXD terminal 30B RXD terminal 35 CAN bus 40A RXD terminal 40B TXD terminal 41 Driver control unit 42 Drivers 42A PMOS transistor 42B, 42D diodes 42C NMOS transistor 43 Receiver 44 Output section 44A PMOS transistor 44B NMOS transistor 501 Communication Systems 502 Communication Systems C1 capacitor R1, R2 terminating resistor R41, R42 resistors X vehicle X11~X18 Electronic equipment

Claims

1. a receiving unit configured to receive received data as serial data from an external device; an abnormality check unit configured to check the received data to check whether or not there is an abnormality whose cause can be identified; A semiconductor device comprising:

2. 2. The semiconductor device according to claim 1, wherein the factor is environmental noise.

3. 3. The semiconductor device according to claim 2, wherein said abnormality check section checks whether a time interval from a falling edge to a rising edge or a time interval from a rising edge to a falling edge in said received data corresponds to a predetermined pattern that can be taken.

4. 2. The semiconductor device according to claim 1, wherein the cause is an abnormality in a transmitting device configured to transmit the serial data.

5. A transmitter is provided, 5. The semiconductor device according to claim 4, wherein said abnormality check section checks whether said received data is at a fixed level while said transmission section is transmitting read-back data after receiving said received data in the case of a read process.

6. A transmitter is provided, 5. The semiconductor device according to claim 4, wherein the abnormality check section, in the case of a read process, checks whether the received data is data obtained by mirroring the readback data while readback data is being transmitted from the transmission section after receiving the received data.

7. 5. The semiconductor device according to claim 4, wherein said abnormality check section checks whether there is a difference between a time interval from a falling edge to a rising edge and a time interval from a rising edge to a falling edge in a synchronization frame as said received data.

8. a counter configured to count clocks; 5. The semiconductor device according to claim 4, wherein said abnormality check section acquires a count value of said counter corresponding to a predetermined number of bits in a synchronous frame as said received data, and checks a change in said count value in different said synchronous frames.

9. 9. The semiconductor device according to claim 8, wherein said abnormality check section stores the previous and current count values ​​and checks the difference between the previous and current count values.

10. 9. The semiconductor device according to claim 8, wherein said abnormality check section sequentially stores and accumulates the count values, and checks the difference between the maximum and minimum values ​​of the stored count values.

11. 11. A communication system comprising: the semiconductor device according to claim 1; and a transmitting device configured to transmit the received data.

12. The communication system of claim 11, which is for use in a vehicle.

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