Semiconductor memory device

Abstract

To miniaturize a semiconductor memory device.SOLUTION: The first driving transistor (M1) is provided between the first and third nodes and has a gate connected to the second node. The second driving transistor (M2) is disposed between the second and third nodes and has a gate coupled to the first node. A first pass transistor (M3) is provided between the first bit line and the first node, and a second pass transistor (M4) is provided between the second bit line and the second node. The gate of each pass transistor is connected to a word line (WL). A high level voltage (VH) and a low level voltage (VL) are set to the first and second nodes by voltage supply to the word line and each bit line. In the subsequent standby state, the leakage current (ILK3) of the first pass transistor is greater than or equal to the leakage current (ILK1) of the first driving transistor.SELECTED DRAWING: Figure 6

Description

[Technical Field]

[0001] The present disclosure relates to a semiconductor memory device. [Background technology]

[0002] Semiconductor memory devices are used in a variety of fields. One type of semiconductor memory device is a static random access memory (SRAM). Patent Document 1 below is an example of a document that discloses a semiconductor memory device. [Prior art documents] [Patent documents]

[0003] [Patent Document 1] Japanese Patent Application Laid-Open No. 2016-81549

[0004] [overview] The miniaturization of semiconductor memory devices is important.

[0005] A semiconductor memory device according to one aspect of the present disclosure includes a memory cell including: a first drive transistor disposed between a first node and a third node and having a gate connected to a second node; a second drive transistor disposed between the second node and the third node and having a gate connected to the first node; a first pass transistor disposed between a first bit line and the first node and having a gate connected to a word line; and a second pass transistor disposed between a second bit line and the second node and having a gate connected to the word line; and a word line driver configured to set the first pass transistor and the second pass transistor to on or off by driving the word line, and configured to control voltages of the first bit line and the second bit line while the first pass transistor and the second pass transistor are set to on, thereby performing a write operation in which one of the first node and the second node is set to a high level voltage and the other is set to a low level voltage, thereby writing a first value or a second value to the memory cell; and an access circuit configured to be able to execute a read operation of reading out a stored value of the memory cell based on voltages appearing on the first bit line and the second bit line by setting a first node to on, wherein the first drive transistor and the second drive transistor are each configured as N-channel MOSFETs, and the first pass transistor and the second pass transistor are each configured as P-channel MOSFETs, and the access circuit supplies the high level voltage to the first bit line and the second bit line while turning off the first pass transistor and the second pass transistor during a standby period which is different from a period during which the write operation is executed and a period during which the read operation is executed, andThe leakage current flowing between the drain and source of the second pass transistor is equal to or greater than the leakage current flowing between the drain and source of the second drive transistor.

[0006] Another semiconductor memory device according to one embodiment of the disclosure includes a memory cell including: a first drive transistor provided between a first node and a third node and having a gate connected to a second node; a second drive transistor provided between the second node and the third node and having a gate connected to the first node; a first pass transistor provided between a first bit line and the first node and having a gate connected to a word line; and a second pass transistor provided between a second bit line and the second node and having a gate connected to the word line; and a word line driver configured to control states of the first pass transistor and the second pass transistor by driving the word line, wherein the first pass transistor and the second pass transistor are set to a first on state, and by controlling voltages of the first bit line and the second bit line, a high-level voltage is set to one of the first node and the second node and a low-level voltage is set to the other, thereby writing a first value or a second value to the memory cell; and an access circuit configured to be capable of executing a read operation of reading a value stored in the memory cell based on voltages appearing on the first bit line and the second bit line by setting the first drive transistor and the second pass transistor to the first on state, wherein each of the first drive transistor and the second drive transistor is configured as an enhancement-type N-channel MOSFET, and each of the first pass transistor and the second pass transistor is configured as a depletion-type P-channel MOSFET, and the access circuit supplies the high-level voltage to the first bit line and the second bit line while setting the first pass transistor and the second pass transistor to a second on state during a standby period different from a period during which the write operation is performed and a period during which the read operation is performed, wherein a gate voltage of each pass transistor in the second on state is higher than a gate voltage of each pass transistor in the first on state, and during the standby period, in a first standby state in which the second node has the low-level voltage and the first drive transistor is off,In a second standby state in which the current flowing between the drain and source of the first pass transistor is equal to or greater than the leakage current flowing between the drain and source of the first drive transistor, and the first node has the low level voltage so that the second drive transistor is off, the current flowing between the drain and source of the second pass transistor is equal to or greater than the leakage current flowing between the drain and source of the second drive transistor. [Brief explanation of the drawings]

[0007] [Figure 1] FIG. 1 is a diagram illustrating the overall configuration of a semiconductor memory device according to an embodiment of the present disclosure. [Figure 2] FIG. 2 is a configuration diagram of a memory cell according to an embodiment of the present disclosure. [Figure 3] FIG. 3 is a diagram showing the configuration of a memory cell according to a reference configuration. [Figure 4] FIG. 4 is a diagram showing the state of a memory cell during a standby period according to a first example of the embodiment of the present disclosure. [Figure 5] FIG. 5 is an explanatory diagram of a first write operation according to a first example of the embodiment of the present disclosure. [Figure 6] FIG. 6 relates to a first example belonging to an embodiment of the present disclosure and is an explanatory diagram of a standby state (first standby state) after a first write operation. [Figure 7] FIG. 7 is an explanatory diagram of a first read operation according to a first example of an embodiment of the present disclosure. [Figure 8] FIG. 8 is an explanatory diagram of a second write operation according to a first example of the embodiment of the present disclosure. [Figure 9] FIG. 9 relates to a first example belonging to an embodiment of the present disclosure and is an explanatory diagram of a standby state (second standby state) after a second write operation. [Figure 10] FIG. 10 is an explanatory diagram of a second read operation according to a first example of an embodiment of the present disclosure. [Figure 11]FIG. 11 is a diagram illustrating the gate length and gate width of a MOSFET according to a second example of the embodiment of the present disclosure. [Figure 12] FIG. 12 is a configuration diagram for imparting a substrate bias effect to each transistor according to a second example of the embodiment of the present disclosure. [Figure 13] FIG. 13 is a configuration diagram of a memory cell according to a third example belonging to the embodiment of the present disclosure.

[0008] [Detailed explanation] Hereinafter, examples of embodiments of the present disclosure will be described in detail with reference to the drawings. In each of the drawings, identical parts are designated by the same reference numerals, and redundant descriptions of identical parts will be omitted as a general rule. For the sake of simplicity, the present specification may use symbols or signs referring to information, signals, physical quantities, functional units, circuits, elements, or components, and the names of the information, signals, physical quantities, functional units, circuits, elements, or components corresponding to the symbols or signs may be omitted or abbreviated. For example, the drive transistor referred to by "M1" (see FIG. 2) described below may be written as drive transistor M1 or abbreviated as transistor M1, but these all refer to the same thing.

[0009] First, some terms used in describing the embodiments of the present disclosure will be explained. Ground refers to a reference conductor having a reference electric potential of 0 V (zero volts), or refers to the 0 V potential itself. The reference conductor may be formed using a conductor such as metal. The 0 V potential is sometimes referred to as ground potential. In the embodiments of the present disclosure, a voltage indicated without a specific reference represents a potential seen from ground. Level refers to the level (height) of the potential, and for any given signal or voltage, a high level has a higher potential than a low level.

[0010] For any transistor configured as a FET (field-effect transistor), such as a MOSFET, the on state refers to a state in which the drain and source of the transistor are conductive, and the off state refers to a state in which the drain and source of the transistor are non-conductive (cut-off state). The same applies to transistors not classified as FETs. MOSFET is an abbreviation for "metal-oxide-semiconductor field-effect transistor." Unless otherwise specified, the back gate of any MOSFET can be considered shorted to the source.

[0011] The electrical characteristics of a MOSFET include a gate threshold voltage. For any N-channel enhancement MOSFET transistor, when the gate potential of the transistor is higher than the source potential of the transistor and the magnitude of the gate-source voltage (gate potential viewed from the source potential) of the transistor is equal to or greater than the gate threshold voltage of the transistor, the transistor is in an on state; otherwise, the transistor is in an off state. For any P-channel enhancement MOSFET transistor, when the gate potential of the transistor is lower than the source potential of the transistor and the magnitude of the gate-source voltage (gate potential viewed from the source potential) of the transistor is equal to or greater than the gate threshold voltage of the transistor, the transistor is in an on state; otherwise, the transistor is in an off state. In an N-channel enhancement MOSFET, the gate threshold voltage has a positive voltage value, and in a P-channel enhancement MOSFET, the gate threshold voltage has a negative voltage value.

[0012] For any FET, the gate threshold voltage is defined as the gate-source voltage required to pass a given amount of drain current when a given voltage is applied between the drain and source of the FET at a given ambient temperature.

[0013] For any transistor, the period during which the transistor is in the on state is referred to as the on period, and the period during which the transistor is in the off state is referred to as the off period. Hereinafter, for any transistor, the on state and the off state may also be simply expressed as on and off, respectively.

[0014] The connection between a plurality of parts forming a circuit, such as any circuit element, wiring, node, etc., may be understood to refer to an electrical connection unless otherwise specified.

[0015] When any two voltages to be compared are voltage v1 and v2, "v1>v2" represents that voltage v1 is higher than voltage v2, "v1<v2" represents that voltage v1 is lower than voltage v2, and "v1=v2" represents that the value of voltage v1 is the same as the value of voltage v2. The same applies to other expressions including physical quantities other than voltage.

[0016] FIG. 1 shows the overall configuration of a semiconductor memory device 100 according to an embodiment of the present disclosure. The semiconductor memory device 100 includes a memory block 1 and a memory controller 2. The semiconductor memory device 100 is a SRAM (Static Random Access Memory). The semiconductor memory device 100 can be configured by a semiconductor integrated circuit.

[0017] The memory block 1 is a circuit block that stores multi-bit data. A memory cell array 10 is provided in the memory block 1. The memory cell array 10 includes a plurality of memory cells 11 arranged in a matrix. To each memory cell 11, a word line WL for access control during a read operation or a write operation, a bit line BL for data transmission during a read operation or a write operation, an inverted bit line XBL, etc. are connected (see FIG. 2). The configuration and operation of the memory cell 11 will be described in detail later. The memory controller 2 is a circuit block that controls the operation of the memory block 1 and is configured to have, for example, a MPU (Micro Processing Unit).

[0018] The memory block 1 is provided with an access circuit 20 as a circuit for accessing each memory cell 11 .

[0019] There are two operations for accessing a memory cell 11: a write operation and a read operation. Each memory cell 11 is a 1-bit memory that stores a first value or a second value. Hereinafter, the first value will be referred to as value VAL1, and the second value will be referred to as value VAL2. Values ​​VAL1 and VAL2 are different from each other. One of values ​​VAL1 and VAL2 is "0" and the other is "1."

[0020] The memory cell 11 that is the target of a write operation is referred to as the write target memory cell 11. The memory cell 11 that is the target of a read operation is referred to as the read target memory cell 11. The memory controller 2 specifies the write target memory cell 11 or the read target memory cell 11 from among all the memory cells 11 provided in the memory cell array 10. The access circuit 20 writes a value VAL1 or VAL2 to the write target memory cell 11 in a write operation. The value to be written to the write target memory cell 11 is specified by the memory controller 2. The access circuit 20 reads the stored value of the read target memory cell 11 in a read operation. The read stored value is supplied to the memory controller 2 and transmitted to a circuit (not shown) that requires the stored value via the memory controller 2.

[0021] The access circuit 20 includes an X decoder 21 , a word line driver 22 , a Y decoder 23 , a write circuit 24 , and a read circuit 25 .

[0022] The X decoder 21 drives the word line driver 22 in response to an instruction from the memory controller 2. The word line driver 22 drives the word line WL connected to the memory cell 11 to be written or read in response to an instruction from the X decoder 21 (and therefore in response to an instruction from the memory controller 2).

[0023] In response to an instruction from the memory controller 2, the Y decoder 23 connects the bit line BL and inverted bit line XBL connected to the memory cell 11 to be written to the write circuit 24. Alternatively, in response to an instruction from the memory controller 2, the Y decoder 23 connects the bit line BL and inverted bit line XBL connected to the memory cell 11 to be read to the read circuit 25.

[0024] The write circuit 24 performs the above-mentioned write operation in cooperation with the X decoder 21, the word line driver 22, and the Y decoder 23. In the write operation, the write circuit 24 drives the bit line BL and the inverted bit line XBL in accordance with the value to be written to the memory cell 11 to be written. The write circuit 24 includes a bit line driver 24a.

[0025] The read circuit 25 performs the above-mentioned read operation in cooperation with the X decoder 21, the word line driver 22, and the Y decoder 23. The read circuit 25 has a sense amplifier SA for reading out the stored value of the memory cell 11 that is the read target in the read operation.

[0026] Figure 2 shows the configuration of one memory cell 11. The memory cell 11 includes drive transistors M1 and M2 and pass transistors M3 and M4. A word line WL, a bit line BL, and an inverted bit line XBL corresponding to the memory cell 11 of Figure 2 are connected to the memory cell 11 of Figure 2. The drive transistors M1 and M2 are MOSFETs having the same structure and electrical characteristics. The pass transistors M3 and M4 are MOSFETs having the same structure and electrical characteristics.

[0027] All memory cells 11 provided in the memory cell array 10 have the same configuration. In the following, any one memory cell 11 of interest will be referred to as the memory cell of interest 11. Unless otherwise specified in the following description, the drive transistors M1 and M2 and the pass transistors M3 and M4 refer to the drive transistors M1 and M2 and the pass transistors M3 and M4 provided in the memory cell of interest 11, and the word line WL, the bit line BL, and the inverted bit line XBL refer to the word line WL, the bit line BL, and the inverted bit line XBL connected to the memory cell of interest 11.

[0028] The drive transistors M1 and M2 are each an N-channel MOSFET, and the pass transistors M3 and M4 are each a P-channel MOSFET.

[0029] The driving transistor M1 is provided between nodes ND1 and ND3, and the driving transistor M2 is provided between nodes ND2 and ND3. More specifically, the drain of the driving transistor M1 is connected to node ND1, and the source of the driving transistor M1 is connected to node ND3. The drain of the driving transistor M2 is connected to node ND2, and the source of the driving transistor M2 is connected to node ND3. The gate of the driving transistor M1 is connected to node ND2, and the gate of the driving transistor M2 is connected to node ND1. Node ND3 is connected to ground.

[0030] The pass transistor M3 is provided between the bit line BL and the node ND1, and the pass transistor M4 is provided between the inverted bit line XBL and the node ND2. More specifically, the source of the pass transistor M3 is connected to the bit line BL, and the drain of the pass transistor M3 is connected to the node ND1. The source of the pass transistor M4 is connected to the inverted bit line XBL, and the drain of the pass transistor M4 is connected to the node ND2. The gates of the pass transistors M3 and M4 are connected to the word line WL.

[0031] A typical SRAM memory cell has a 6T structure (a structure formed by six transistors). FIG. 3 shows a memory cell 911 with a 6T structure according to a reference configuration. The memory cell 911 with a 6T structure includes drive transistors 921 and 922, pass transistors 923 and 924, and load transistors 925 and 926. The drive transistors 921 and 922 and the load transistors 925 and 926 form two inverter circuits cross-connected to each other. In contrast, the memory cell 11 in FIG. 2 has a 4T structure (a structure formed by four transistors) that does not include a load transistor. In other words, compared to the memory cell 911, the memory cell 11 does not include a load transistor, and therefore the memory cell 11 can be used to reduce the size of a semiconductor memory device (reducing the chip area when the semiconductor memory device is formed as a semiconductor integrated circuit).

[0032] Below, among the multiple embodiments, more specific configuration examples, operation examples, application techniques, modified techniques, etc. of the semiconductor memory device 100 will be described. The matters described above in this embodiment are applied to each of the following embodiments unless otherwise specified and unless contradicted (except for the matters related to FIG. 3). If there are any matters in each embodiment that contradict the matters described above, the description in that embodiment may take precedence. Furthermore, unless contradicted, matters described in any of the multiple embodiments described below can also be applied to any of the other embodiments (i.e., any two or more of the multiple embodiments can be combined).

[0033] <<First Example>> A first embodiment will be described. In the first embodiment, the drive transistors M1 and M2 are each an enhancement-type N-channel MOSFET, and the pass transistors M3 and M4 are each an enhancement-type P-channel MOSFET. The word line driver 22 drives the word line WL in accordance with instructions from the X-decoder 21 (and therefore in accordance with instructions from the memory controller 2), thereby turning on or off the pass transistors M3 and M4. A high-level voltage VH and a low-level voltage VL, which will be described later, are supplied to the word line WL by the word line driver 22. A high-level voltage VH and a low-level voltage VL, which will be described later, are supplied to the bit line BL and the inverted bit line XBL by the bit line driver 24a.

[0034] A period during which neither a write operation nor a read operation is performed on the memory cell of interest 11 is called a standby period, and the state of the memory cell of interest 11 during the standby period is called a standby state. Figure 4 shows the state of the memory cell of interest 11 in the standby state. During the standby period, the bit line driver 24a is conductive to the bit line BL and inverted bit line XBL corresponding to the memory cell of interest 11.

[0035] In the standby state, the access circuit 20 uses the word line driver 22 to supply a high-level voltage VH to the word line WL corresponding to the memory cell 11 of interest, and also uses the bit line driver 24a to supply a high-level voltage VH to the bit line BL and inverted bit line XBL corresponding to the memory cell 11 of interest. During the standby period, the pass transistors M3 and M4 are turned off because the gate-source voltage of each of the pass transistors M3 and M4 is 0V. The voltages of the nodes ND1 and ND2 and the states of the drive transistors M1 and M2 during the standby period depend on the stored value of the memory cell 11 of interest.

[0036] When the memory cell 11 of interest is set as the memory cell 11 to be written to, the write circuit 24 executes the first write operation or the second write operation as the write operation on the memory cell 11 of interest.

[0037] --First write operation (Figure 5)-- The first write operation will be described with reference to Fig. 5. The first write operation is a write operation for writing a value VAL1 to the target memory cell 11. During the execution period of the first write operation, the Y decoder 23 causes the bit line driver 24a to be conductive to the bit line BL and inverted bit line XBL corresponding to the target memory cell 11.

[0038] In a first write operation for the memory cell 11 of interest, starting from the standby state, the supply voltage to the word line WL corresponding to the memory cell 11 is switched from the high level voltage VH to the low level voltage VL, and the high level voltage VH is supplied to the bit line BL corresponding to the memory cell 11, while the supply voltage to the inverted bit line XBL corresponding to the memory cell 11 is switched from the high level voltage VH to the low level voltage VL. That is, in the first write operation for the memory cell 11 of interest, in a state in which the low level voltage VL is supplied to the word line WL, the high level voltage VH is supplied to the bit line BL, and the low level voltage VL is supplied to the inverted bit line XBL.

[0039] The high-level voltage VH is higher than the low-level voltage VL. The low-level voltage VL may deviate from 0V, but is assumed to be 0V here. The high-level voltage VH has a positive voltage value, e.g., 5V. The difference between the high-level voltage VH and the low-level voltage VL is greater than the absolute value of the gate threshold voltages of the pass transistors M3 and M4. Therefore, the pass transistors M3 and M4 are in the ON state during the first write operation. As a result, during the first write operation, the write circuit 24 (bit line driver 24a) sets the voltage of node ND1 to the high-level voltage VH and the voltage of node ND2 to the low-level voltage VL. The high-level voltage VH is higher than the gate threshold voltages of the drive transistors M1 and M2. Therefore, when the voltage of node ND1 is the high-level voltage VH, the drive transistor M2 is in the ON state. On the other hand, when the voltage of node ND2 is the low-level voltage VL, the drive transistor M1 is in the OFF state.

[0040] In the first write operation, a state in which a low-level voltage VL is supplied to the word line WL and the inverted bit line XBL and a high-level voltage VH is supplied to the bit line BL is maintained for a predetermined write time, and then the voltage supplied to the word line WL is returned from the low-level voltage VL to the high-level voltage VH. This ends the first write operation. At the end of the first write operation, the voltage of node ND1 is the high-level voltage VH and the voltage of node ND2 is the low-level voltage VL. The state in which the voltage of node ND1 is the high-level voltage VH and the voltage of node ND2 is the low-level voltage VL corresponds to a state in which the value VAL1 is stored in the target memory cell 11.

[0041] --First standby state (Figure 6)-- After the first write operation is completed, the state of the target memory cell 11 is set to a standby state by the access circuit 20. The standby state after the first write operation is particularly referred to as the first standby state. After the first write operation is completed, the first standby state is reached without the second write operation being executed. Figure 6 shows how the state of the target memory cell 11 transitions to the first standby state after the first write operation. The period during which the state of the target memory cell 11 is set to the first standby state is referred to as the first standby period.

[0042] After the first write operation is completed, the voltage supplied to the inverted bit line XBL is switched from the low-level voltage VL to the high-level voltage VH, thereby transitioning to a first standby state. That is, in the first standby state, the access circuit 20 supplies the high-level voltage VH to the word line WL corresponding to the memory cell 11 of interest, and also supplies the high-level voltage VH to the bit line BL and inverted bit line XBL corresponding to the memory cell 11 of interest. During the first standby period, the bit line driver 24a is made conductive to the bit line BL and inverted bit line XBL corresponding to the memory cell 11 of interest, and the bit line driver 24a supplies the high-level voltage VH to the bit line BL and inverted bit line XBL.

[0043] During the first standby period, the pass transistors M3 and M4 are off because the gate-source voltage of each of them is 0 V. Also during the first standby period, the node ND2 has a low-level voltage VL, so the drive transistor M1 is off, and the node ND1 has a high-level voltage VH, so the drive transistor M2 is on.

[0044] However, during the first standby period, a current I flows between the drain and source of the driving transistor M1 from the node ND1 to the node ND3. LK1 During the first standby period, the driving transistor M1 is kept off, so that the current I LK1 is the leakage current that occurs during the off period of the drive transistor M1. The leakage current (I LK1 ) acts to decrease the voltage of the node ND1. However, the voltage decrease of the node ND1 during the first standby period causes the current I LK3 Generates a current I LK3 is a current flowing between the drain and source of the pass transistor M3 and flowing from the bit line BL to the node ND1. Since the pass transistor M3 is kept off during the first standby period, the current I LK3 is the leakage current that occurs during the off period of the pass transistor M3.

[0045] During the first standby period, the current I LK3 is the current I LK1 The drive transistor M1 and the pass transistor M3 are configured so that the above is the case. During the first standby period, the voltage of the node ND1 does not become higher than the voltage (VH) of the bit line BL, so that the voltage of the node ND1 is substantially equal to "I LK3 =I LK1 " but in the transitional period, "I LK3 >I LK1 ". That is, in the first standby period, the current I LK3 is the current I LK1By this, the voltage of the node ND1 is maintained at the high level voltage VH. The concept of maintaining the voltage of the node ND1 at the high level voltage VH includes the possibility that there may be a slight difference between the voltage of the node ND1 and the high level voltage VH. Strictly speaking, the voltage of the node ND1 may become slightly lower than the voltage of the bit line BL during the first standby period, but the voltage of the node ND1 keeps the drive transistor M2 on with a sufficient margin. In other words, during the first standby period, the current I LK3 is the current I LK1 As a result, the voltage of node ND1 seen from the potential of node ND3 (i.e., the gate-source voltage of drive transistor M2) is kept higher than the gate threshold voltage of drive transistor M2. In the following, it is considered that the voltage of node ND1 is kept at the high-level voltage VH during the first standby period.

[0046] During the first standby period, a leakage current also occurs in the pass transistor M4, and the leakage current of the pass transistor M4 flows from the inverted bit line XBL to the node ND2. However, during the first standby period, the drive transistor M2 is on, so the leakage current of the pass transistor M4 flows to ground through the drive transistor M2, and as a result, it does not substantially affect the voltage of the node ND2 (the voltage of the node ND2 is maintained at the low-level voltage VL).

[0047] Because of the above characteristics, the value VAL1 can be kept held in the memory cell 11 of interest during the first standby period.

[0048] --First read operation (Figure 7)-- When the memory cell of interest 11 is set as the memory cell 11 to be read, the read circuit 25 executes a read operation on the memory cell of interest 11. For the sake of concreteness of explanation, a read operation executed when the value VAL1 is stored in the memory cell of interest 11 will be referred to as a first read operation. A read operation executed after the first write operation and via a first standby state without going through a second write operation (described later) is the first read operation.

[0049] The first read operation will be described with reference to FIG. 7. During the first read operation, the access circuit 20 disconnects the bit line driver 24a from the bit line BL and the inverted bit line XBL, and instead makes the sense amplifier SA conductive to the bit line BL and the inverted bit line XBL. The input impedance to the sense amplifier SA as seen from the bit line BL and the inverted bit line XBL is sufficiently high, so the sense amplifier SA does not substantially affect the potentials of the bit line BL and the inverted bit line XBL. When the bit line BL and the inverted bit line XBL are connected to the bit line driver 24a, the bit line driver 24a performs a voltage supply operation in which it supplies a high-level voltage VH or a low-level voltage VL to the bit line BL and a high-level voltage VH or a low-level voltage VL to the inverted bit line XBL. When the bit line BL and the inverted bit line XBL are connected to the sense amplifier SA, the voltage supply operation is stopped, and the voltage of the bit line BL varies only due to the current passing through the pass transistor M3, and the voltage of the inverted bit line XBL varies only due to the current passing through the pass transistor M4. Note that the operation of supplying a high-level voltage VH to the bit line BL and the inverted bit line XBL by the bit line driver 24a in the first standby state or the second standby state described below is called a charge operation.

[0050] In the first read operation, the voltage supplied to the word line WL corresponding to the target memory 11 is switched from a high-level voltage VH to a low-level voltage VL. However, immediately before this switching, the bit line BL and the inverted bit line XBL are opened, and the input and output of charges between the bit line driver 24a and the bit line BL and the inverted bit line XBL is stopped. That is, after the high-level voltage VH is supplied to the bit line BL and the inverted bit line XBL in the charge operation in the first standby state, the bit line driver 24a is disconnected from the bit line BL and the inverted bit line XBL, thereby opening the bit line BL and the inverted bit line XBL. The first read operation is then performed. In the first read operation, the sense amplifier SA is made conductive to the bit line BL and the inverted bit line XBL. In the first read operation, the voltage supplied to the word line WL corresponding to the target memory 11 is switched from a high-level voltage VH to a low-level voltage VL. This switches the pass transistors M3 and M4 from off to on. Because the voltage at node ND1 is high-level voltage VH immediately before pass transistor M3 is switched on, there is no substantial change in the potential of bit line BL before and after pass transistor M3 is switched from off to on. Therefore, the voltages of bit line BL and node ND1 are high-level voltage VH after pass transistor M3 is switched from off to on. Therefore, drive transistor M2 remains on during the first read operation, continuing from the first standby period. As a result, when pass transistor M4 is switched from off to on during the first read operation, the charge on inverted bit line XBL is extracted to ground through pass transistor M4 and drive transistor M2, causing the voltage on inverted bit line XBL to decrease from high-level voltage VH toward low-level voltage VL.

[0051] In the first read operation or the second read operation described below, the point in time when a predetermined waiting time has elapsed since the voltage supplied to the word line WL was switched from the high-level voltage VH to the low-level voltage VL is referred to as the read timing. The sense amplifier SA reads the stored value of the target memory cell 11 based on the comparison result between the voltage of the bit line BL and the voltage of the inverted bit line XBL at the read timing, i.e., determines whether the stored value of the target memory cell 11 is value VAL1 or VAL2. In this case, if the voltage of the bit line BL is higher than the voltage of the inverted bit line XBL at the read timing, the sense amplifier SA determines that the stored value of the target memory cell 11 is value VAL1. Conversely, if the voltage of the bit line BL is lower than the voltage of the inverted bit line XBL at the read timing, the sense amplifier SA determines that the stored value of the target memory cell 11 is value VAL2. Since the voltage of the bit line BL is higher than the voltage of the inverted bit line XBL at the read timing in the first read operation, the stored value of the target memory cell 11 is determined to be value VAL1.

[0052] In the first read operation, after the read timing, the word line driver 22 changes the voltage supplied to the word line WL back from the low level voltage VL to the high level voltage VH, thereby completing the first read operation. After the first read operation is completed, the access circuit 20 continues to supply the high level voltage VH to the word line WL, while switching the conduction destination of the bit line BL and the inverted bit line XBL from the sense amplifier SA to the bit line driver 24a, thereby returning the state of the target memory cell 11 to the standby state (see FIG. 4). Immediately after returning to the standby state, the bit line driver 24a supplies the high level voltage VH to the bit line BL and the inverted bit line XBL.

[0053] --Second write operation (Figure 8)-- The second write operation will be described with reference to Figure 8. The second write operation is a write operation that writes a value VAL2 to the target memory cell 11. During the execution of the second write operation, the Y decoder 23 causes the bit line driver 24a to be conductive to the bit line BL and inverted bit line XBL corresponding to the target memory cell 11.

[0054] In the second write operation for the memory cell 11 of interest, starting from the standby state, the supply voltage to the word line WL corresponding to the memory cell 11 is switched from the high level voltage VH to the low level voltage VL, and the high level voltage VH is supplied to the inverted bit line XBL corresponding to the memory cell 11, while the supply voltage to the bit line BL corresponding to the memory cell 11 is switched from the high level voltage VH to the low level voltage VL. That is, in the second write operation for the memory cell 11 of interest, in a state in which the low level voltage VL is supplied to the word line WL, the high level voltage VH is supplied to the inverted bit line XBL, and the low level voltage VL is supplied to the bit line BL.

[0055] As described above, since the difference between the high-level voltage VH and the low-level voltage VL is greater than the absolute value of the gate threshold voltages of the pass transistors M3 and M4, the pass transistors M3 and M4 are turned on during the second write operation. As a result, during the second write operation, the write circuit 24 (bit line driver 24a) sets the voltage of node ND2 to the high-level voltage VH and the voltage of node ND1 to the low-level voltage VL. The high-level voltage VH is higher than the gate threshold voltages of the drive transistors M1 and M2. Therefore, when the voltage of node ND2 is the high-level voltage VH, the drive transistor M1 is turned on. On the other hand, when the voltage of node ND1 is the low-level voltage VL, the drive transistor M2 is turned off.

[0056] In the second write operation, a low-level voltage VL is supplied to the word line WL and the bit line BL, and a high-level voltage VH is supplied to the inverted bit line XBL. This state is maintained for a predetermined write time, and then the voltage supplied to the word line WL is returned from the low-level voltage VL to the high-level voltage VH. This completes the second write operation. At the end of the second write operation, the voltage of node ND2 is the high-level voltage VH, and the voltage of node ND1 is the low-level voltage VL. The state in which the voltage of node ND2 is the high-level voltage VH and the voltage of node ND1 is the low-level voltage VL corresponds to a state in which the value VAL2 is stored in the target memory cell 11.

[0057] --Second standby state (Figure 9)-- After the second write operation is completed, the state of the target memory cell 11 is set to a standby state by the access circuit 20. The standby state after the second write operation is particularly referred to as the second standby state. After the second write operation is completed, the second standby state is reached without the first write operation being executed. Figure 9 shows how the state of the target memory cell 11 transitions to the second standby state after the second write operation. The period during which the state of the target memory cell 11 is set to the second standby state is referred to as the second standby period.

[0058] After the second write operation is completed, the voltage supplied to the bit line BL is switched from the low-level voltage VL to the high-level voltage VH, thereby transitioning to a second standby state. That is, in the second standby state, the access circuit 20 supplies the high-level voltage VH to the word line WL corresponding to the memory cell 11 of interest, and also supplies the high-level voltage VH to the bit line BL and inverted bit line XBL corresponding to the memory cell 11 of interest. During the second standby period, the bit line driver 24a is made conductive to the bit line BL and inverted bit line XBL corresponding to the memory cell 11 of interest, and the bit line driver 24a supplies the high-level voltage VH to the bit line BL and inverted bit line XBL.

[0059] During the second standby period, the pass transistors M3 and M4 are off because the gate-source voltage of each of them is 0 V. Also during the second standby period, the node ND1 has a low-level voltage VL, so the drive transistor M2 is off, and the node ND2 has a high-level voltage VH, so the drive transistor M1 is on.

[0060] However, during the second standby period, a current I flows between the drain and source of the driving transistor M2 from the node ND2 to the node ND3. LK2 During the second standby period, the driving transistor M2 is kept off, so that the current I LK2 is the leakage current that occurs during the off period of the drive transistor M2. The leakage current (I LK2 ) acts to decrease the voltage of node ND2. However, the voltage decrease of node ND2 during the second standby period causes a current I LK4 Generates a current I LK4 is a current flowing between the drain and source of the pass transistor M4 and flows from the inverted bit line XBL to the node ND2. During the second standby period, the pass transistor M4 is maintained in an off state, so that the current I LK4 is the leakage current that occurs during the off period of the pass transistor M4.

[0061] During the second standby period, the current I LK4 is the current I LK2 The drive transistor M2 and the pass transistor M4 are formed so that the above is the case. During the second standby period, the voltage of the node ND2 does not become higher than the voltage (VH) of the inverted bit line XBL, so that the voltage of the node ND2 is substantially equal to "I LK4 =I LK2 " but in the transitional period, "I LK4 >I LK2 ". That is, in the second standby period, the current I LK4 is the current I LK2By this, the voltage of the node ND2 is maintained at the high level voltage VH. The concept of maintaining the voltage of the node ND2 at the high level voltage VH includes the possibility that there may be a slight difference between the voltage of the node ND2 and the high level voltage VH. Strictly speaking, the voltage of the node ND2 may become slightly lower than the voltage of the inverted bit line XBL during the second standby period, but the voltage of the node ND2 maintains the drive transistor M1 on with a sufficient margin. In other words, during the second standby period, the current I LK4 is the current I LK2 As a result, the voltage of node ND2 seen from the potential of node ND3 (i.e., the gate-source voltage of the driving transistor M1) is kept higher than the gate threshold voltage of the driving transistor M1. In the following, it is considered that the voltage of node ND2 is kept at the high-level voltage VH during the second standby period.

[0062] During the second standby period, a leakage current also occurs in the pass transistor M3, and the leakage current of the pass transistor M3 flows from the bit line BL to the node ND1. However, during the second standby period, the drive transistor M1 is on, so the leakage current of the pass transistor M3 flows to ground through the drive transistor M1, and as a result, it does not substantially affect the voltage of the node ND1 (the voltage of the node ND1 is maintained at the low-level voltage VL).

[0063] Because of the above characteristics, the value VAL2 can be kept held in the memory cell 11 of interest during the second standby period.

[0064] --Second read operation (Figure 10)-- When the memory cell of interest 11 is set as the memory cell 11 to be read, the read circuit 25 executes a read operation on the memory cell of interest 11. For the sake of concreteness, the read operation executed when the value VAL2 is stored in the memory cell of interest 11 is referred to as the second read operation. The read operation executed after the second write operation and via the second standby state without going through the first write operation described above is the second read operation.

[0065] The second read operation will be described with reference to Figure 10. During the execution of the second read operation, the access circuit 20 disconnects the bit line driver 24a from the bit line BL and the inverted bit line XBL, and instead makes the sense amplifier SA conductive to the bit line BL and the inverted bit line XBL. The input impedance to the sense amplifier SA as seen from the bit line BL and the inverted bit line XBL is sufficiently high, so the sense amplifier SA does not substantially affect the potentials of the bit line BL and the inverted bit line XBL.

[0066] In the second read operation, the voltage supplied to the word line WL corresponding to the target memory 11 is switched from a high-level voltage VH to a low-level voltage VL. However, immediately before this switching, the bit line BL and the inverted bit line XBL are opened, and the input and output of charges between the bit line driver 24a and the bit line BL and the inverted bit line XBL are stopped. That is, after the high-level voltage VH is supplied to the bit line BL and the inverted bit line XBL in the charge operation in the second standby state, the bit line driver 24a is disconnected from the bit line BL and the inverted bit line XBL, thereby opening the bit line BL and the inverted bit line XBL. The second read operation is then performed. In the second read operation, the sense amplifier SA is made conductive to the bit line BL and the inverted bit line XBL. In the second read operation, the voltage supplied to the word line WL corresponding to the target memory 11 is switched from a high-level voltage VH to a low-level voltage VL. This switches the pass transistors M3 and M4 from off to on. Because the voltage at node ND2 is high voltage VH immediately before pass transistor M4 is switched on, there is no substantial change in the potential of inverted bit line XBL before and after pass transistor M4 is switched on. Therefore, the voltages of inverted bit line XBL and node ND2 are high voltage VH after pass transistor M4 is switched on. Therefore, drive transistor M1 is maintained in the on state during the second read operation, continuing from the second standby period. As a result, when pass transistor M3 is switched on during the second read operation, the charge on bit line BL is extracted to ground through pass transistor M3 and drive transistor M1, causing the voltage on bit line BL to decrease from high voltage VH to low voltage VL.

[0067] In the second read operation or the first read operation described above, the read timing is the point in time when a predetermined waiting time has elapsed since the voltage supplied to the word line WL was switched from the high-level voltage VH to the low-level voltage VL. The sense amplifier SA reads the stored value of the target memory cell 11 based on the comparison result between the voltage of the bit line BL and the voltage of the inverted bit line XBL at the read timing, i.e., determines whether the stored value of the target memory cell 11 is value VAL1 or VAL2. In this case, if the voltage of the bit line BL is higher than the voltage of the inverted bit line XBL at the read timing, the sense amplifier SA determines that the stored value of the target memory cell 11 is value VAL1. Conversely, if the voltage of the bit line BL is lower than the voltage of the inverted bit line XBL at the read timing, the sense amplifier SA determines that the stored value of the target memory cell 11 is value VAL2. Since the voltage of the bit line BL is lower than the voltage of the inverted bit line XBL at the read timing in the second read operation, the stored value of the target memory cell 11 is determined to be value VAL2.

[0068] In the second read operation, after the read timing, the word line driver 22 changes the voltage supplied to the word line WL back from the low level voltage VL to the high level voltage VH, thereby completing the second read operation. After the second read operation is completed, the access circuit 20 continues to supply the high level voltage VH to the word line WL, and switches the conduction destination of the bit line BL and the inverted bit line XBL from the sense amplifier SA to the bit line driver 24a, thereby returning the state of the target memory cell 11 to the standby state (see FIG. 4). Immediately after returning to the standby state, the bit line driver 24a supplies the high level voltage VH to the bit line BL and the inverted bit line XBL.

[0069] <<Second Example>> A second embodiment will be described. The second embodiment is implemented in combination with the first embodiment. In the second embodiment, the "I LK3 ≧I LK1 " and the method for realizing "I LK4 ≧I LK2" will be explained. The methods for achieving this will include size adjustment and Vth adjustment.

[0070] First, we will explain how to adjust the size. In the first standby state, LK3 ≧I LK1 The sizes of the drive transistor M1 and the pass transistor M3 are made different from each other so that "I LK4 ≧I LK2 The sizes of the drive transistor M2 and the pass transistor M4 are made different from each other so that the following expression is satisfied. Specifically, the ratio (W / L) of each transistor may be set as follows:

[0071] Refer to FIG. 11, which schematically illustrates the structure of a MOSFET. Circuit elements within a semiconductor memory device 100 are integrated on a semiconductor substrate, and the structure of any transistor formed as a MOSFET on the semiconductor substrate is characterized by a gate width W and a gate length L. Any transistor formed as a MOSFET has a gate electrode GG that functions as a gate. The gate width W and gate length L represent the size of the gate electrode GG in a direction parallel to the surface (front and back) of the semiconductor substrate. Of these, the gate length L represents the distance between the drain and source of the transistor (the length of the gate electrode GG in the direction connecting the drain and source). The gate width W represents the length of the gate electrode GG in a direction perpendicular to the direction in which the gate length L is defined (the direction connecting the drain and source) and also perpendicular to the normal direction of the semiconductor substrate (the direction perpendicular to the front and back surfaces of the semiconductor substrate). For any MOSFET, the magnitude of the leakage current depends on the ratio of the gate width W to the gate length L, i.e., the ratio (W / L). For any MOSFET, under certain environmental conditions, the leakage current increases as the ratio (W / L) increases.

[0072] Therefore, in the size adjustment method, in the first standby state, LK3 ≧I LK1In order to establish the above-mentioned condition, the ratio (W / L) in the pass transistor M3 is set to be larger than the ratio (W / L) in the drive transistor M1. LK4 ≧I LK2 In order to satisfy the above condition, the ratio (W / L) in the pass transistor M4 is set to be larger than the ratio (W / L) in the drive transistor M2. In the manufacturing process for forming the memory cell array 10 on the semiconductor substrate, the gate length L of the MOSFET that can be manufactured has a lower limit (hereinafter, the lower limit length L MIN ) and there is a lower limit to the gate width W of the MOSFET that can be manufactured (hereinafter referred to as the lower limit width W MIN The gate length L of each MOSFET in the memory cell array 10 is the lower limit length L MIN Therefore, the gate length L of each of the drive transistors M1 and M2 and the pass transistors M3 and M4 is limited to a lower limit L MIN In addition, for example, the gate width W of each of the drive transistors M1 and M2 may be set to a lower limit width W MIN While setting the gate width W of each of the pass transistors M3 and M4 to the lower limit width W MIN It is better to set it to a larger value.

[0073] Next, the Vth adjustment method will be explained. In the Vth adjustment method, in the first standby state, LK3 ≧I LK1 The gate threshold voltages of the drive transistor M1 and the pass transistor M3 are set to be different from each other so that "I LK4 ≧I LK2 The gate threshold voltages of the drive transistor M2 and the pass transistor M4 are made different from each other so that "I" holds. Under certain conditions in which the MOSFET is turned off, the smaller the gate threshold voltage of the MOSFET, the larger the leakage current. Therefore, in the Vth adjustment method, LK3 ≧I LK1 " is established, the magnitude (absolute value) of the gate threshold voltage of the pass transistor M3 is set to be smaller than the magnitude of the gate threshold voltage of the drive transistor M1, and "I LK4 ≧I LK2" is set so that the magnitude (absolute value) of the gate threshold voltage of the pass transistor M4 is smaller than the magnitude of the gate threshold voltage of the drive transistor M2.

[0074] Any known method can be used to adjust the gate threshold voltages of the transistors M1 to M4 as desired. For example, an ion implantation step (impurity implantation step) may be added to the manufacturing process of the memory cell array 10 to set the gate threshold voltage of the pass transistor M3 to be smaller than that of the drive transistor M1, and to set the gate threshold voltage of the pass transistor M4 to be smaller than that of the drive transistor M2.

[0075] Alternatively, the gate threshold voltages of the transistors M1 to M4 may be adjusted as desired by utilizing the substrate bias effect. Specifically, by applying a negative substrate bias voltage to the N-channel MOSFET driver transistors M1 and M2, the gate threshold voltages of the driver transistors M1 and M2 are set to voltage Vth_n, while by applying a negative substrate bias voltage to the P-channel MOSFET pass transistors M3 and M4, the gate threshold voltages of the pass transistors M3 and M4 are set to voltage Vth_p (here, voltage Vth_p is smaller than voltage Vth_n). To achieve this, as shown in FIG. 12 , a negative voltage VBS_n (corresponding to a negative substrate bias voltage) is applied to the back gates of the driver transistors M1 and M2 without shorting the back gates to the sources of the driver transistors M1 and M2, and a negative voltage VBS_p (corresponding to a negative substrate bias voltage) is applied to the back gates of the pass transistors M3 and M4 without shorting the back gates to the sources of the pass transistors M3 and M4.

[0076] <<Third Example>> The third embodiment will be described. The third embodiment is based on the first embodiment, and the description of the first embodiment also applies to the third embodiment unless otherwise specified. FIG. 13 shows the configuration of a memory cell 11 according to the third embodiment. In the third embodiment, the "I LK3 ≧I LK1 " and "I" in the second standby state LK4 ≧I LK2 In order to realize the above, the pass transistors M3 and M4 are formed of depletion-mode MOSFETs. That is, in the third embodiment, the drive transistors M1 and M2 are each an enhancement-mode N-channel MOSFET, and the pass transistors M3 and M4 are each a depletion-mode P-channel MOSFET.

[0077] Therefore, in the third embodiment, when a high-level voltage VH is supplied to the word line WL corresponding to the target memory cell 11, the pass transistors M3 and M4 remain in the on state even during a period when the gate-source voltages of the pass transistors M3 and M4 are 0V. For the sake of clarity, the on states of the pass transistors M3 and M4 are defined as a first on state and a second on state. In the first on state, a low-level voltage VL is supplied to the word line WL, and in the second on state, a high-level voltage VH is supplied to the word line WL. That is, the gate voltages (VH) of the pass transistors M3 and M4 in the second on state are higher than the gate voltages (VL) of the pass transistors M3 and M4 in the first on state. The word line driver 22 drives the word line WL to control (set) the states of the pass transistors M3 and M4 to the first on state or the second on state.

[0078] In the first on-state, the pass transistor M3 provides conduction between the bit line BL and the node ND1 with a sufficiently low on-resistance. In the second on-state, the pass transistor M3 provides conduction between the bit line BL and the node ND1 with a higher on-resistance than in the first on-state. Similarly, in the first on-state, the pass transistor M4 provides conduction between the inverted bit line XBL and the node ND2 with a sufficiently low on-resistance. In the second on-state, the pass transistor M4 provides conduction between the inverted bit line XBL and the node ND2 with a higher on-resistance than in the first on-state.

[0079] The contents of the first and second write operations are the same as those of Example 1. However, during the execution period of the first or second write operation, when a low-level voltage VL is supplied to the word line WL, the pass transistors M3 and M4 of Example 3 are in the first on state.

[0080] The first and second read operations are the same as those in the first embodiment. However, during the execution of the first or second read operation, when a low-level voltage VL is supplied to the word line WL, the pass transistors M3 and M4 in the third embodiment are in a first on state. During the first read operation (see FIG. 7), the voltage supplied to the word line WL corresponding to the target memory 11 is switched from a high-level voltage VH to a low-level voltage VL, switching the states of the pass transistors M3 and M4 from a second on state to a first on state. At the same time, the conduction destinations of the bit line BL and the inverted bit line XBL are switched from the bit line driver 24a to the sense amplifier SA. As a result, the charge on the inverted bit line XBL is extracted to ground through the pass transistor M4 and the drive transistor M2, causing the voltage on the inverted bit line XBL to decrease from the high-level voltage VH to the low-level voltage VL. Similarly, in the second read operation (see Figure 10), the supply voltage to the word line WL corresponding to the target memory 11 is switched from the high-level voltage VH to the low-level voltage VL, which switches the state of the pass transistors M3 and M4 from the second on state to the first on state, and the conduction destination of the bit line BL and the inverted bit line XBL is switched from the bit line driver 24a to the sense amplifier SA, and the charge on the bit line BL is extracted to ground through the pass transistor M3 and the drive transistor M1, causing the voltage on the bit line BL to decrease from the high-level voltage VH to the low-level voltage VL.

[0081] The behavior of the memory cell 11 during the first standby period is the same as that of the first embodiment (see FIG. 6). However, during the first standby period, the pass transistors M3 and M4 are in the second on state, and the current I LK1 is the leakage current that occurs during the off period of the drive transistor M1, while the current I LK3 is the drain current of pass transistor M3 in the second on-state.

[0082] During the first standby period, the current I LK3 is the current I LK1That is all. During the first standby period, the voltage of the node ND1 does not become higher than the voltage (VH) of the bit line BL, so that the voltage of the node ND1 is substantially equal to "I LK3 =I LK1 " but in the transitional period, "I LK3 >I LK1 ". That is, in the first standby period, the current I LK3 is the current I LK1 By this, the voltage of the node ND1 is maintained at the high-level voltage VH. LK3 is the current I LK1 As a result, the voltage of node ND1 seen from the potential of node ND3 (i.e., the gate-source voltage of drive transistor M2) is maintained higher than the gate threshold voltage of drive transistor M2. Note that during the first standby period, a drain current is also generated in pass transistor M4, and the drain current of pass transistor M4 flows from the inverted bit line XBL to node ND2. However, since drive transistor M2 is on during the first standby period, the drain current of pass transistor M4 flows to ground through drive transistor M2, and as a result, there is no substantial effect on the voltage of node ND2 (the voltage of node ND2 is maintained at the low-level voltage VL). Due to the above characteristics, it is possible to cause the memory cell of interest 11 to continue to hold the value VAL1 during the first standby period.

[0083] The behavior of the memory cell 11 during the second standby period is also the same as that of the first embodiment (see FIG. 9). However, during the second standby period, the pass transistors M3 and M4 are in the second on state, and the current I LK2 is the leakage current that occurs during the off period of the drive transistor M2, while the current I LK4 is the drain current of pass transistor M4 in the second on-state.

[0084] During the second standby period, the current I LK4 is the current I LK2 That is all. During the second standby period, the voltage of the node ND2 does not become higher than the voltage (VH) of the inverted bit line XBL, so that the voltage of the node ND2 is substantially equal to the voltage of the inverted bit line XBL.LK4 =I LK2 " but in the transitional period, "I LK4 >I LK2 ". That is, in the second standby period, the current I LK4 is the current I LK2 By this, the voltage of the node ND2 is maintained at the high-level voltage VH. LK4 is the current I LK2 As a result, the voltage of node ND2 seen from the potential of node ND3 (i.e., the gate-source voltage of drive transistor M1) is maintained higher than the gate threshold voltage of drive transistor M1. Note that during the second standby period, a drain current is also generated in pass transistor M3, and the drain current of pass transistor M3 flows from bit line BL to node ND1. However, during the second standby period, since drive transistor M1 is on, the drain current of pass transistor M3 flows to ground through drive transistor M1, and as a result, there is no substantial effect on the voltage of node ND1 (the voltage of node ND1 is maintained at low-level voltage VL). Due to the above characteristics, it is possible to cause the memory cell of interest 11 to continue to hold the value VAL2 during the second standby period.

[0085] <<Supplementary Information>> 1 can be mounted in any electrical device, such as an electrical component mounted in a vehicle such as an automobile, a computer, a home appliance, or an industrial device.

[0086] The embodiments of the present disclosure can be modified in various ways as appropriate within the scope of the technical ideas set forth in the claims. The above-described embodiments are merely examples of the present disclosure, and the meanings of the terms of the present disclosure and each constituent element are not limited to those described in the above-described embodiments. The specific numerical values ​​shown in the above description are merely examples, and as a matter of course, they can be changed to various numerical values.

[0087] <<Additional Notes>> A supplementary note will be provided for the present disclosure, the specific configuration examples of which have been shown in the above-described embodiments.

[0088] A semiconductor memory device (100) according to one aspect of the present disclosure includes a memory cell (11) including: a first drive transistor (M1) provided between a first node (ND1) and a third node (ND2) and having a gate connected to a second node (ND2); a second drive transistor (M2) provided between the second node and the third node and having a gate connected to the first node; a first pass transistor (M3) provided between a first bit line (BL) and the first node and having a gate connected to a word line (WL); and a second pass transistor (M4) provided between a second bit line (XBL) and the second node and having a gate connected to the word line; and a word line driver (22) configured to set the first pass transistor and the second pass transistor to on or off by driving the word line, and by controlling the voltages of the first bit line and the second bit line while the first pass transistor and the second pass transistor are set to on, a high-level voltage is applied to one of the first node and the second node and a low-level voltage is applied to the other. and an access circuit (20) configured to be able to perform a write operation of setting a base voltage to write a first value or a second value to the memory cell thereby, and a read operation of reading a stored value of the memory cell based on voltages appearing on the first bit line and the second bit line by turning on the first pass transistor and the second pass transistor, wherein the first drive transistor and the second drive transistor are each configured as an N-channel MOSFET, and the first pass transistor and the second pass transistor are each configured as a P-channel MOSFET, and the access circuit supplies the high-level voltage to the first bit line and the second bit line while turning off the first pass transistor and the second pass transistor during a standby period different from a period during which the write operation is performed and a period during which the read operation is performed, and during the standby period, in a first standby state in which the second node has the low-level voltage and the first drive transistor is turned off, a leakage current (I LK3) flows between the drain and source of the first driving transistor. LK1 ) or more, and in a second standby state in which the first node has the low-level voltage and the second drive transistor is off, a leakage current (I LK4 ) flows between the drain and source of the second driving transistor. LK2 ) or more (first configuration).

[0089] This allows a memory cell to be configured using four transistors, thereby enabling the semiconductor memory device to be made smaller.

[0090] In the semiconductor memory device according to the first configuration, after the high-level voltage is set to the first node and the low-level voltage is set to the second node by the write operation, during the standby period (see FIG. 6), the first drive transistor is off and the second drive transistor is on, and a leakage current flowing between the drain and source of the first pass transistor is equal to or greater than a leakage current flowing between the drain and source of the first drive transistor, so that the voltage of the first node is maintained higher than a gate threshold voltage of the second drive transistor, and the second drive transistor is on, so that the voltage of the second node is maintained at the low-level voltage. After the write operation sets the low level voltage to the first node and the high level voltage to the second node, during the standby period (see FIG. 9), the second drive transistor is off and the first drive transistor is on, and a leakage current flowing between the drain and source of the second pass transistor is equal to or greater than a leakage current flowing between the drain and source of the second drive transistor, so that the voltage of the second node is maintained higher than a gate threshold voltage of the first drive transistor, and the first drive transistor is on, so that the voltage of the first node is maintained at the low level voltage (second configuration).

[0091] In the semiconductor memory device according to the first or second configuration, a configuration (third configuration) may be adopted in which the ratio of the gate width to the gate length of the first pass transistor is set to be larger than the ratio of the gate width to the gate length of the first drive transistor so that the leakage current flowing between the drain and source of the first pass transistor in the first standby state is equal to or larger than the leakage current flowing between the drain and source of the first drive transistor, and the ratio of the gate width to the gate length of the second pass transistor is set to be larger than the ratio of the gate width to the gate length of the second drive transistor so that the leakage current flowing between the drain and source of the second pass transistor in the second standby state is equal to or larger than the leakage current flowing between the drain and source of the second drive transistor.

[0092] In the semiconductor memory device according to the first or second configuration, the gate threshold voltage of the first pass transistor may be set to be smaller than the gate threshold voltage of the first drive transistor so that the leakage current flowing between the drain and source of the first pass transistor in the first standby state is equal to or larger than the leakage current flowing between the drain and source of the first drive transistor, and the gate threshold voltage of the second pass transistor may be set to be smaller than the gate threshold voltage of the second drive transistor so that the leakage current flowing between the drain and source of the second pass transistor in the second standby state is equal to or larger than the leakage current flowing between the drain and source of the second drive transistor (fourth configuration).

[0093] In the semiconductor memory device according to any one of the first to fourth configurations, each of the drive transistors and each of the pass transistors may be configured by an enhancement type MOSFET (fifth configuration).

[0094] A semiconductor memory device (100) according to another aspect of the present disclosure includes a memory cell (11) including: a first drive transistor (M1) provided between a first node (ND1) and a third node (ND2) and having a gate connected to a second node (ND2); a second drive transistor (M2) provided between the second node and the third node and having a gate connected to the first node; a first pass transistor (M3) provided between a first bit line (BL) and the first node and having a gate connected to a word line (WL); and a second pass transistor (M4) provided between a second bit line (XBL) and the second node and having a gate connected to the word line; and a word line driver (22) configured to control states of the first pass transistor and the second pass transistor by driving the word line, and by controlling the voltages of the first bit line and the second bit line with the first pass transistor and the second pass transistor set to a first on state, a high-level voltage is applied to one of the first node and the second node and a low-level voltage is applied to the other. and an access circuit (20) configured to be able to perform a write operation of setting a high-level voltage to the memory cell, thereby writing a first value or a second value to the memory cell, and a read operation of reading a value stored in the memory cell based on the voltages appearing on the first bit line and the second bit line by setting the first pass transistor and the second pass transistor to the first on state, wherein the first drive transistor and the second drive transistor are each configured as an enhancement-type N-channel MOSFET, and the first pass transistor and the second pass transistor are each configured as a depletion-type P-channel MOSFET, and the access circuit supplies the high-level voltage to the first bit line and the second bit line while setting the first pass transistor and the second pass transistor to a second on state during a standby period different from a period during which the write operation is performed and a period during which the read operation is performed, and wherein a gate voltage of each pass transistor in the second on state is higher than a gate voltage of each pass transistor in the first on state, and during the standby period,In a first standby state in which the second node has the low level voltage and the first drive transistor is off, a current (I, LK3 ) flows between the drain and source of the first driving transistor. LK1 ) or more, and in a second standby state in which the first node has the low level voltage and the second drive transistor is off, a current (I LK4 ) flows between the drain and source of the second driving transistor. LK2 ) or more (sixth configuration).

[0095] This allows a memory cell to be configured using four transistors, thereby enabling the semiconductor memory device to be made smaller.

[0096] In the semiconductor memory device according to the sixth configuration, after the high-level voltage is set to the first node and the low-level voltage is set to the second node by the write operation, during the standby period (see FIG. 6), the first drive transistor is off and the second drive transistor is on, and the current flowing between the drain and source of the first pass transistor is equal to or greater than the leakage current flowing between the drain and source of the first drive transistor, so that the voltage of the first node is maintained higher than the gate threshold voltage of the second drive transistor, and the second drive transistor is on, so that the voltage of the second node is maintained at the low-level voltage. and after the low level voltage is set to the first node and the high level voltage is set to the second node by the write operation, during the standby period (see FIG. 9), the second drive transistor is off and the first drive transistor is on, and the current flowing between the drain and source of the second pass transistor is equal to or greater than the leakage current flowing between the drain and source of the second drive transistor, so that the voltage of the second node is kept higher than the gate threshold voltage of the first drive transistor, and the first drive transistor is on, so that the voltage of the first node is kept at the low level voltage (seventh configuration).

[0097] In the semiconductor memory device according to any one of the first to seventh configurations, the semiconductor memory device may be configured (eighth configuration) to include a plurality of the memory cells, and the access circuit may perform the write operation and the read operation on any one of the plurality of memory cells, and to realize the first standby state or the second standby state during the standby period. [Explanation of symbols]

[0098] 100 Semiconductor memory device 1 memory block 2 Memory Controller 10 Memory Cell Array 11 memory cells 20 Access Circuit 21X Decoder 22 Word Line Driver 23 Y decoder 24 Light Circuit 25 Lead Circuit 24a bit line driver SA Sense Amplifier M1, M2 drive transistors M3, M4 pass transistors CG gate electrode W gate width L gate length 911 memory cells 921, 922 Drive transistor 923, 924 Pass transistor 925, 926 Load transistor

Claims

1. a memory cell comprising: a first drive transistor disposed between a first node and a third node and having a gate connected to a second node; a second drive transistor disposed between the second node and the third node and having a gate connected to the first node; a first pass transistor disposed between a first bit line and the first node and having a gate connected to a word line; and a second pass transistor disposed between a second bit line and the second node and having a gate connected to the word line; an access circuit configured to execute a write operation of writing a first value or a second value to the memory cell by controlling the voltages of the first bit line and the second bit line with the first pass transistor and the second pass transistor set to on, thereby setting a high level voltage to one of the first node and the second node and a low level voltage to the other of the first node and the second node, and to execute a read operation of reading a value stored in the memory cell based on the voltages appearing on the first bit line and the second bit line by setting the first pass transistor and the second pass transistor to on, the first driving transistor and the second driving transistor are each configured as an N-channel MOSFET; the first pass transistor and the second pass transistor are each configured as a P-channel MOSFET; the access circuit supplies the high-level voltage to the first bit line and the second bit line while turning off the first pass transistor and the second pass transistor during a standby period different from a period during which the write operation is performed and a period during which the read operation is performed; During the standby period, In a first standby state in which the second node has the low level voltage and the first drive transistor is off, a leakage current flowing between the drain and source of the first pass transistor is equal to or greater than a leakage current flowing between the drain and source of the first drive transistor; In a second standby state in which the first node has the low level voltage and the second drive transistor is off, a leakage current flowing between the drain and source of the second pass transistor is equal to or greater than a leakage current flowing between the drain and source of the second drive transistor. , semiconductor memory device.

2. After the write operation sets the high level voltage to the first node and the low level voltage to the second node, during the standby period, the first drive transistor is off and the second drive transistor is on, and a leakage current flowing between the drain and source of the first pass transistor is equal to or greater than a leakage current flowing between the drain and source of the first drive transistor, so that the voltage of the first node is maintained higher than a gate threshold voltage of the second drive transistor, and the second drive transistor is on, so that the voltage of the second node is maintained at the low level voltage; After the low-level voltage is set to the first node and the high-level voltage is set to the second node by the write operation, during the standby period, the second drive transistor is off and the first drive transistor is on, and a leakage current flowing between the drain and source of the second pass transistor is equal to or greater than a leakage current flowing between the drain and source of the second drive transistor, so that the voltage of the second node is maintained higher than a gate threshold voltage of the first drive transistor, and the first drive transistor is on, so that the voltage of the first node is maintained at the low-level voltage.

2. The semiconductor memory device according to claim 1.

3. a ratio of a gate width to a gate length of the first pass transistor is set to be larger than a ratio of a gate width to a gate length of the first drive transistor so that a leakage current flowing between the drain and source of the first pass transistor in the first standby state is equal to or larger than a leakage current flowing between the drain and source of the first drive transistor; a ratio of a gate width to a gate length of the second pass transistor is set to be larger than a ratio of a gate width to a gate length of the second drive transistor so that a leakage current flowing between the drain and source of the second pass transistor in the second standby state is equal to or larger than a leakage current flowing between the drain and source of the second drive transistor; 3. The semiconductor memory device according to claim 1.

4. setting a gate threshold voltage of the first pass transistor to be smaller than a gate threshold voltage of the first drive transistor so that a leakage current flowing between the drain and source of the first pass transistor in the first standby state is equal to or greater than a leakage current flowing between the drain and source of the first drive transistor; The magnitude of the gate threshold voltage of the second pass transistor is set to be smaller than the magnitude of the gate threshold voltage of the second drive transistor so that the leakage current flowing between the drain and source of the second pass transistor in the second standby state is equal to or greater than the leakage current flowing between the drain and source of the second drive transistor.

3. The semiconductor memory device according to claim 1.

5. Each drive transistor and each pass transistor is formed of an enhancement type MOSFET.

3. The semiconductor memory device according to claim 1.

6. a memory cell comprising: a first drive transistor disposed between a first node and a third node and having a gate connected to a second node; a second drive transistor disposed between the second node and the third node and having a gate connected to the first node; a first pass transistor disposed between a first bit line and the first node and having a gate connected to a word line; and a second pass transistor disposed between a second bit line and the second node and having a gate connected to the word line; an access circuit configured to control the states of the first pass transistor and the second pass transistor by driving the word line, and to control the voltages of the first bit line and the second bit line with the first pass transistor and the second pass transistor set to a first on state, thereby setting one of the first node and the second node to a high level voltage and the other to a low level voltage, thereby performing a write operation of writing a first value or a second value to the memory cell, and a read operation of reading a value stored in the memory cell based on the voltages appearing on the first bit line and the second bit line by setting the first pass transistor and the second pass transistor to the first on state; the first driving transistor and the second driving transistor are each configured as an enhancement type N-channel MOSFET; the first pass transistor and the second pass transistor are each configured as a depletion-type P-channel MOSFET; the access circuit supplies the high-level voltage to the first bit line and the second bit line while setting the first pass transistor and the second pass transistor to a second on state during a standby period different from a period during which the write operation is performed and a period during which the read operation is performed; a gate voltage of each pass transistor in the second on state is higher than a gate voltage of each pass transistor in the first on state; During the standby period, In a first standby state in which the second node has the low level voltage and the first drive transistor is off, a current flowing between the drain and source of the first pass transistor is equal to or greater than a leakage current flowing between the drain and source of the first drive transistor; In a second standby state in which the first node has the low level voltage and the second driver transistor is off, a current flowing between the drain and source of the second pass transistor is equal to or greater than a leakage current flowing between the drain and source of the second driver transistor. , semiconductor memory device.

7. After the high level voltage is set to the first node and the low level voltage is set to the second node by the write operation, during the standby period, the first drive transistor is off and the second drive transistor is on, and a current flowing between the drain and source of the first pass transistor is equal to or greater than a leakage current flowing between the drain and source of the first drive transistor, so that the voltage of the first node is maintained higher than a gate threshold voltage of the second drive transistor, and the second drive transistor is on, so that the voltage of the second node is maintained at the low level voltage; After the low level voltage is set to the first node and the high level voltage is set to the second node by the write operation, during the standby period, the second drive transistor is off and the first drive transistor is on, and the current flowing between the drain and source of the second pass transistor is equal to or greater than the leakage current flowing between the drain and source of the second drive transistor, so that the voltage of the second node is maintained higher than the gate threshold voltage of the first drive transistor, and the first drive transistor is on, so that the voltage of the first node is maintained at the low level voltage.

7. The semiconductor memory device according to claim 6.

8. a plurality of the memory cells; The access circuit executes the write operation and the read operation for any of a plurality of memory cells and realizes the first standby state or the second standby state during the standby period.

8. The semiconductor memory device according to claim 1, 2, 6 or 7.

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