Imaging apparatus

Abstract

To provide an imaging apparatus for generating a high dynamic range image.SOLUTION: The imaging device includes a first photoelectric conversion element TX1 connected to a first terminal of a split transistor SPX through a first transfer transistor PD1 and included in the first pixel, a second photoelectric conversion element TX2 connected to a second terminal of the split transistor SPX through a second transfer transistor PD2 and included in the second pixel, a floating diffusion region FD configured to accumulate photocharges generated by the first photoelectric conversion element PD1 or the second photoelectric conversion element PD2, a capacitor C configured to adjust a capacitance of the floating diffusion region FD, and a DCG transistor DCX connected between the capacitor C and the floating diffusion region FD and configured to control the capacitance of the floating diffusion region FD.SELECTED DRAWING: Figure 3a

Description

[Technical Field]

[0001] The present invention relates to an imaging device that produces high dynamic range (HDR) images. [Background technology]

[0002] Image sensing devices are devices that capture optical images using the properties of photosensitive semiconductor materials that react to light. With the development of industries such as automobiles, medicine, computers, and communications, there is an increasing demand for high-performance image sensing devices in various fields such as smartphones, digital cameras, game consoles, the Internet of Things, robots, security cameras, and medical micro cameras.

[0003] Image sensing devices can be broadly divided into charge-coupled device (CCD) image sensing devices and complementary metal oxide semiconductor (CMOS) image sensing devices. CCD image sensing devices provide better image quality than CMOS image sensing devices, but tend to be larger in size and consume more power. In contrast, CMOS image sensing devices can be smaller in size and consume less power than CCD image sensing devices. Furthermore, because CMOS image sensing devices are fabricated using CMOS fabrication technology, the light-sensing element and signal processing circuitry can be integrated onto a single chip, making it possible to produce inexpensive and compact image sensing devices. For this reason, CMOS image sensing devices are being developed for many applications, including mobile devices. Summary of the Invention [Problem to be solved by the invention]

[0004] The technical idea of ​​the present invention can provide an imaging device that generates an HDR image using an optimal method among various methods. The technical problems of the present invention are not limited to those mentioned above, and other technical problems not mentioned will be clearly understood by those skilled in the art from the following description. [Means for solving the problem]

[0005] An imaging device according to one embodiment of the present invention disclosed herein may include: a split transistor for separating a first time point at which first pixel data of a first pixel is generated from a second time point at which second pixel data of one or more second pixels is generated; a first photoelectric conversion element included in the first pixel and connected to a first electrode of the split transistor via a first transfer transistor; a second photoelectric conversion element included in the second pixel and connected to a second electrode of the split transistor via a second transfer transistor; a floating diffusion region for accumulating photocharges generated by the first photoelectric conversion element or the second photoelectric conversion element; a capacitor for adjusting the capacitance of the floating diffusion region; and a DCG (Dual Conversion Gain) transistor connected between the capacitor and the floating diffusion region and for controlling the capacitance of the floating diffusion region.

[0006] An imaging device according to an embodiment of the present invention disclosed herein may include a multi-pixel including: a split transistor for separating a first time point at which first pixel data of a first pixel is generated from a second time point at which second pixel data of one or more second pixels is generated; a first photoelectric conversion element included in the first pixel and connected to a first electrode of the split transistor via a first transfer transistor; a second photoelectric conversion element included in the second pixel and connected to a second electrode of the split transistor via a second transfer transistor; a floating diffusion region for accumulating photocharges generated by the first photoelectric conversion element or the second photoelectric conversion element; a capacitor for adjusting capacitance of the floating diffusion region; and a DCG transistor connected between the capacitor and the floating diffusion region for controlling the capacitance of the floating diffusion region; a signal controller for generating control signals to control each of the split transistor and the DCG transistor; and an image combiner for combining first image data generated based on the first pixel and second image data generated based on the one or more second pixels to generate a High Dynamic Range (HDR) image.

[0007] An image sensing method according to one embodiment of the present invention disclosed herein may include the steps of: generating first pixel data based on first photocharges generated by the first photoelectric conversion element when a split transistor separating the first photoelectric conversion element from one or more second photoelectric conversion elements is turned off and a DCG transistor is turned on; adjusting a capacitance of a floating diffusion region that accumulates second photocharges generated by the one or more second photoelectric conversion elements to a first capacitance by turning on the split transistor and the DCG transistor; generating second pixel data corresponding to a first conversion gain (Low Conversion Gain) based on the second photocharges generated by the one or more second photoelectric conversion elements; turning on the split transistor and the DCG transistor and adjusting the capacitance to a second capacitance; and generating third pixel data corresponding to a second conversion gain based on the second photocharges generated by the one or more second photoelectric conversion elements. [Effects of the Invention]

[0008] According to the embodiments disclosed herein, an imaging device can generate HDR images efficiently and with the largest dynamic range by using a single shared capacitor to control the overflow charge of low-transmittance photoelectric conversion elements and to control the capacitance of the floating diffusion (FD) region of high-transmittance photoelectric conversion elements. In addition, this document can provide various other benefits that can be perceived directly or indirectly. [Brief explanation of the drawings]

[0009] [Figure 1] 1 is a block diagram illustrating a configuration of an imaging device according to an embodiment of the present disclosure. [Figure 2] FIG. 10 illustrates the response of a high-sensitivity pixel and a low-sensitivity pixel to illumination intensity according to an embodiment of the present disclosure. [Figure 3a] FIG. 2 is a circuit diagram illustrating a pixel group according to an embodiment of the present disclosure. [Figure 3b] FIG. 2 is a circuit diagram illustrating a pixel group according to an embodiment of the present disclosure. [Figure 4] FIG. 2 illustrates a pixel group, a microlens, an ADC, and corresponding pixels according to one embodiment of the present disclosure. [Figure 5] 1A and 1B illustrate cross sections of a high-transmittance pixel and a low-transmittance pixel according to an embodiment of the present disclosure. [Figure 6] FIG. 3b is a timing diagram corresponding to the circuit diagram of FIG. 3a according to one embodiment of the present disclosure. [Figure 7] FIG. 10 is a diagram for explaining the operation of an image synthesis unit according to an embodiment of the present disclosure. [Figure 8] 2 is a block diagram illustrating an example of a computing device corresponding to the image signal processor of FIG. 1. DETAILED DESCRIPTION OF THE INVENTION

[0010] Various embodiments will be described below with reference to the accompanying drawings. However, it should be understood that the present disclosure is not limited to specific embodiments and includes various modifications, equivalents, and / or alternatives of the embodiments. The embodiments of the present disclosure can provide various effects that can be recognized directly or indirectly by the present disclosure.

[0011] FIG. 1 is a block diagram showing a configuration of an imaging device according to an embodiment of the present disclosure. 1, the imaging device 10 may refer to a device such as a digital still camera that takes still images or a digital video camera that takes moving images. For example, the imaging device 10 may be realized as a digital single lens reflex (DSLR) camera, a mirrorless camera, or a smartphone, but is not limited thereto. The imaging device 10 may be a concept that includes a device that includes a lens and an image sensor and can capture an object and generate an image.

[0012] According to one embodiment, the imaging device 10 may include an image sensing device 100 and an image signal processor 200 . According to one embodiment, the image sensing device 100 may be a complementary metal oxide semiconductor image sensor (CIS) that converts incident light into an electrical signal. The image sensing device 100 may have its on / off, exposure time, conversion gain, analog gain, and the like controlled by the image signal processor 200. The image sensing device 100 generates image data IDATA by converting incident light into an electrical signal on a pixel-by-pixel basis. The image sensing device 100 may include a plurality of pixels with different sensitivities. Here, sensitivity may refer to the increase in image data IDATA (or the increase in response) with respect to an increase in the intensity of incident light. That is, the higher the sensitivity, the greater the increase in image data IDATA with respect to an increase in the intensity of incident light, and the lower the sensitivity, the smaller the increase in image data IDATA with respect to an increase in the intensity of incident light. The sensitivity may be determined by light transmittance, conversion gain, exposure time, analog gain, and the like.

[0013] According to one embodiment, the image sensing device 100 may include a pixel array 110, a row driver 120, a correlated double sampler (CDS) 130, a ramp generator 135, an analog-to-digital converter (ADC) 140, an output buffer 150, a column driver 160, and a timing controller 170. Here, each component of the image sensing device 100 is merely exemplary, and at least some components may be added or omitted as necessary.

[0014] According to one embodiment, the pixel array 110 may include a plurality of pixels arranged in a plurality of rows and a plurality of columns. In one embodiment, the plurality of pixels may be arranged in a two-dimensional pixel array including rows and columns. In another embodiment, the plurality of unit image pixels may be arranged in a three-dimensional pixel array. The plurality of pixels may convert optical signals into electrical signals on a pixel-by-pixel basis or on a pixel group basis, and the unit pixels within a pixel group may share at least certain internal circuits. The pixel array 110 may receive pixel control signals, including a row select signal, a pixel reset signal, and a transfer signal, from the row driver 120. The pixel control signals may activate the corresponding unit pixels of the pixel array 110 to perform operations corresponding to the row select signal, the pixel reset signal, and the transfer signal.

[0015] According to one embodiment, the row driver 120 can activate the pixel array 110 to perform a specific operation on the unit pixels included in the row based on commands and control signals provided by the timing controller 170. In one embodiment, the row driver 120 can select at least one unit pixel arranged in at least one row of the pixel array 110. The row driver 120 can generate a row selection signal to select at least one row from among a plurality of rows. The row driver 120 can sequentially enable pixel reset signals and transfer signals for pixels corresponding to the selected at least one row. Alternatively, the row driver 120 can sequentially enable pixel transfer signals and reset signals for pixels corresponding to the selected at least one row. This allows analog reference signals and image signals generated from each pixel of the selected row to be sequentially transmitted to the correlated double sampler 130. Here, the reference signal may be an electrical signal provided to the correlated double sampler 130 when a sensing node (e.g., a floating diffusion node) of a unit pixel is reset, and the image signal may be an electrical signal provided to the correlated double sampler 130 when photocharges generated by the unit pixel are accumulated in the sensing node. The reference signal indicating pixel-specific reset noise and the image signal indicating the intensity of incident light may be commonly referred to as pixel signals.

[0016] According to one embodiment, a CMOS image sensing device can use correlated double sampling to remove unwanted pixel offsets, such as fixed pattern noise, by sampling a pixel signal twice to remove the difference between the two samples. For example, correlated double sampling can remove unwanted offsets and measure pixel output voltages based solely on incident light by comparing pixel output voltages acquired before and after photocharges generated by incident light are accumulated in the sensing node. In one embodiment, the correlated double sampler 130 can sequentially sample and hold the reference signal and image signal provided to each of a plurality of column lines from the pixel array 110. That is, the correlated double sampler 130 can sample and hold the levels of the reference signal and image signal corresponding to each column of the pixel array 110.

[0017] According to an embodiment, the correlated double sampler 130 can transmit the reference signal and the image signal of each column to the ADC 140 as correlated double sampling signals based on a control signal from the timing controller 170 .

[0018] The ramp generator 135 can generate a ramp signal required for the analog-to-digital conversion operation of the ADC 140 in response to a control signal from the timing controller 170 and supply the ramp signal to the ADC 140. The ramp generator 135 (also referred to as a ramp signal generating circuit) can generate a ramp signal (or a ramp voltage) whose level increases (rises) or decreases (falls) at a constant slope. The slope of the ramp signal can vary depending on the analog gain setting. The ramp signal can be provided to the ADC 140 as a reference voltage.

[0019] According to one embodiment, the ADC 140 may convert the correlated double sampled signal for each column output from the correlated double sampler 130 into a digital signal and output the digital signal. In one embodiment, the ADC 140 may convert the correlated double sampled signal generated by the correlated double sampler 130 for each column into a digital signal and output the digital signal.

[0020] According to one embodiment, the ADC 140 can convert the CDS signals for each column of the CDS circuit 130 into digital signals based on a ramp signal provided by the ramp generator 135. The ADC 140 can include multiple column counters corresponding to the columns of the pixel array 110. Each column of the pixel array 110 is coupled to a corresponding column counter, and image data can be generated by converting the correlated double sampled signals corresponding to each column into digital signals using the column counters. According to another embodiment, the ADC 140 can include one global counter and convert the correlated double sampled signals corresponding to each column into digital signals using a global code provided by the global counter.

[0021] According to an embodiment, the output buffer 150 may temporarily hold and output image data IDATA in units of columns provided from the ADC 140. The output buffer 150 may temporarily store the image data IDATA output from the ADC 140 based on a control signal from the timing controller 170. The output buffer 150 may operate as an interface that compensates for differences in transfer speed (or processing speed) between the image sensing device 100 and other devices connected thereto.

[0022] According to one embodiment, the column driver 160 may select a column of the output buffer 150 based on a control signal from the timing controller 170, and control the image data IDATA temporarily stored in the selected column of the output buffer 150 to be sequentially output. In one embodiment, the column driver 160 may receive an address signal from the timing controller 170, and may generate a column selection signal based on the address signal to select a column of the output buffer 150, thereby controlling the image data IDATA to be output from the selected column of the output buffer 150 to the outside.

[0023] In one embodiment, the timing controller 170 may control at least one of the row driver 120 , the correlated double sampler 130 , the ADC 140 , the output buffer 150 , and the column driver 160 .

[0024] According to one embodiment, the timing controller 170 may provide clock signals required for the operation of each component of the image sensing device 100, control signals for timing control, and address signals for selecting rows or columns to at least one of the row driver 120, the correlated double sampler 130, the ADC 140, the output buffer 150, and the column driver 160. According to one embodiment, the timing controller 170 may include a logic control circuit, a phase lock loop (PLL) circuit, a timing control circuit, a communication interface circuit, etc.

[0025] According to one embodiment, the timing controller 170 can control the sensitivity of each pixel of the pixel array 110. The sensitivity of each pixel can be determined by its light transmittance and conversion gain. The light transmittance may refer to the ratio of the intensity of light reaching an element (a photoelectric conversion element, described below) that converts light into electric charges within the pixel to the intensity of light incident on the pixel. The conversion gain may refer to the ratio of the level (i.e., voltage) of the pixel signal into which the electric charges are converted to the amount of electric charges generated in the pixel. The higher the light transmittance or the higher the conversion gain, the higher the sensitivity of the pixel. Conversely, the lower the light transmittance or the lower the conversion gain, the lower the sensitivity of the pixel.

[0026] According to one embodiment, the light transmittance may be fixed in advance for each pixel, and the conversion gain may be a controllable item. The timing controller 170 may control the row driver 120 that supplies control signals to the pixel array 110 to distinguish pixel signals of pixels with high light transmittance from those with low light transmittance. The timing controller 170 may also control the row driver 120 that supplies control signals to the pixel array 110 to control the conversion gain of each pixel. As an example, a method in which the timing controller 170 selects pixels with high light transmittance from those with low light transmittance and a method in which the timing controller 170 controls the conversion gain to control the sensitivity of each pixel will be described below with reference to FIGS. 3A and 3B.

[0027] According to an embodiment, the image signal processor 200 processes image data IDATA input from the image sensing device 100 and controls each component of the imaging device 10 according to the processing result or an external input signal. The image signal processor 200 may perform image signal processing on the image data IDATA to reduce noise and improve image quality, such as gamma correction, color filter array interpolation, color matrix, color correction, and color enhancement. The image data generated through the image signal processing for improving image quality may be compressed to generate an image file, or the image data may be restored from the image file. The image compression format may be lossless or lossy. For example, for still images, the Joint Photographic Experts Group (JPEG) format or JPEG2000 format may be used. For moving images, a moving image file may be generated by compressing multiple frames according to the Moving Picture Experts Group (MPEG) standard. For example, the image file may be generated according to the Exchangeable Image File Format (Exif) standard.

[0028] According to one embodiment, the HDR image output from the image signal processor 200 may be stored in the internal memory or external memory of the imaging device 10, or displayed via a display, depending on a user's request or automatically. The image signal processor 200 may also perform blurring, blurring, edge enhancement, image analysis, image recognition, image effect processing, and the like.

[0029] According to one embodiment, the image signal processor 200 can perform display image signal processing for a display, such as brightness level adjustment, color correction, contrast adjustment, edge enhancement adjustment, screen division processing, character image generation, and image synthesis processing.

[0030] According to an embodiment, the image signal processor 200 may include an HDR controller 300, an overflow detection unit 310, and an image synthesis unit 320. For example, the HDR controller 300, the overflow detection unit 310, and the image synthesis unit 320 may be implemented independently of the image signal processor 200. In the present disclosure, each component of the image signal processor 200 may be added or omitted. For example, the HDR controller 300 may be included in the image sensing device 100. For example, the HDR controller 300 may correspond to a signal control unit that controls a signal generated by the timing controller 170 in response to a control signal. For example, the overflow detection unit 310 may be included in or omitted from the image sensing device 100.

[0031] According to an embodiment, the HDR controller 300 may control at least one of the components of the image sensing device 100 so that pixels of the image sensing device 100 have an optimal dynamic range. As an example, the HDR controller 300 may transmit a control signal to the timing controller 170 to control each component of the image sensing device 100. For example, the HDR controller 300 may control the timing controller 170 of the image sensing device 100.

[0032] According to an embodiment, the overflow detection unit 310 may detect that photocharges equal to or greater than a threshold value are generated from pixels included in the pixel array 110. As an example, the overflow detection unit 310 may transmit a detection signal to the HDR controller 300 based on detecting that photocharges equal to or greater than a threshold value are generated from pixels included in the pixel array 110.

[0033] According to one embodiment, the image synthesis unit 320 may generate an HDR image by synthesizing at least two or more images having different sensitivities. For example, the image sensing device 100 may output a reduced-level image generated from pixels having relatively low sensitivity (reduced-level pixels) and a high-sensitivity image generated from pixels having relatively high sensitivity (high-sensitivity pixels), and the image synthesis unit 320 may synthesize the reduced-level image and the high-sensitivity image to generate an HDR image. Here, the reduced level and the high sensitivity are relative concepts, and the image sensing device 100 may generate n or more image data IDATA (n is an integer greater than or equal to 2) having different sensitivities, and the image synthesis unit 320 may generate an HDR image using these.

[0034] FIG. 2 is a diagram illustrating the response of a high-sensitivity pixel and a low-sensitivity pixel to illumination intensity according to one embodiment of the present disclosure. 2, the response of a high-sensitivity pixel, which is a pixel whose response increases relatively greatly with an increase in the intensity of incident light, and the response of a low-sensitivity pixel, which is a pixel whose response increases relatively little with an increase in the intensity of incident light, are shown, along with the response of the low-sensitivity pixel depending on the intensity of incident light incident on the pixel. Here, the response may refer to the image data IDATA of the pixel. As an example, the response may have a signal-to-noise ratio (SNR) limit level and a saturation level.

[0035] According to one embodiment, the SNR limit level may refer to a threshold value of a response that can satisfy a predetermined reference SNR. A response below the SNR limit level may be an invalid response that cannot satisfy the reference SNR, and a response above the SNR limit level may be a valid response that can satisfy the reference SNR. The reference SNR may be a value determined experimentally in consideration of the characteristics of the image sensing device 100 and the required specifications of the system.

[0036] According to one embodiment, the saturation level may refer to the maximum response that can represent the intensity of incident light. The saturation level may be determined by the pixel's ability to convert the intensity of incident light into photocharges (e.g., the capacitance of the photoelectric conversion element), its ability to convert the photocharges into analog signals (e.g., the capacitance of the floating diffusion region), and its ability to convert the analog signals into digital signals (e.g., the input range of the analog-to-digital converter). As the intensity of incident light increases, the response may increase in accordance with the intensity of the incident light until it reaches the saturation level. However, after the response reaches the saturation level, even if the intensity of incident light increases, the response cannot increase beyond the saturation level and may have the same value as the saturation level.

[0037] According to one embodiment, if the effective response of a pixel is defined as a response that satisfies a reference SNR and can indicate the intensity of incident light, the range of the intensity of incident light corresponding to the effective response of the pixel can be defined as the dynamic range of the pixel, i.e., the dynamic range of a pixel can refer to the range of the intensity of incident light for which the pixel can have an effective response.

[0038] According to one embodiment, the response of a high-sensitivity pixel, which is a pixel that exhibits a relatively large increase in response with an increase in the intensity of incident light, increases at a relatively high slope in response to an increase in the intensity of incident light, and after reaching a saturation level, can have a level corresponding to the saturation level regardless of the intensity of the incident light.

[0039] According to one embodiment, the response of a reduced pixel, which is a pixel whose response increases relatively little with an increase in the intensity of incident light, increases at a relatively low slope in response to an increase in the intensity of incident light, and after reaching a saturation level, can have a level corresponding to the saturation level regardless of the intensity of the incident light.

[0040] 2, the lower limit of the dynamic range DR_H of the high-sensitivity pixel may be smaller than the lower limit of the dynamic range DR_L of the low-sensitivity pixel, and the upper limit of the dynamic range DR_H of the high-sensitivity pixel may be smaller than the upper limit of the dynamic range DR_L of the low-sensitivity pixel. Therefore, in an illumination range where the intensity of incident light is relatively low (low illumination), the high-sensitivity pixel is more suitable for detecting the intensity of incident light, and in an illumination range where the intensity of incident light is relatively high (high illumination), the low-sensitivity pixel is more suitable for detecting the intensity of incident light.

[0041] According to one embodiment, HDR can be achieved using the respective responses of high-sensitivity pixels suitable for low illumination and low-sensitivity pixels suitable for high illumination. That is, compared to using only one of high-sensitivity pixels or low-sensitivity pixels, using both high-sensitivity pixels and low-sensitivity pixels can result in the entire pixel array having a high dynamic range ranging from the lower limit of the dynamic range of the high-sensitivity pixels to the upper limit of the dynamic range of the low-sensitivity pixels. For this reason, at least a portion of the dynamic range of the high-sensitivity pixels and at least a portion of the dynamic range of the low-sensitivity pixels can overlap with each other.

[0042] According to one embodiment, a method for synthesizing an HDR image corresponding to a high dynamic range using high-sensitivity pixels and low-sensitivity pixels may include a method of interpolating and calculating (e.g., adding) the responses of the high-sensitivity pixels and the low-sensitivity pixels, or a method of generating an image based on the response of the high-sensitivity pixels in low illumination and generating an image based on the response of the low-sensitivity pixels in high illumination, but the scope of the present invention is not limited thereto.

[0043] According to one embodiment, as shown in FIG. 2, adjusting the sensitivity (i.e., response slope) of a pixel can adjust the dynamic range of the pixel. The sensitivity of a pixel can be determined by at least one of light transmittance and conversion gain, which are sensitivity items that determine the sensitivity of the pixel. Therefore, the HDR controller 300 can adjust the dynamic range of a pixel by adjusting the controllable item of light transmittance and conversion gain.

[0044] According to one embodiment, the HDR controller 300 can control at least one of the image sensing devices 100 so that the pixels of the image sensing devices 100 have an optimal dynamic range based on the characteristics of the scene and the characteristics of the controllable items.

[0045] 3a and 3b are circuit diagrams illustrating pixel groups according to one embodiment of the present disclosure. Referring to FIG. 3a, a multi-pixel MPX may be any one of pixel groups including one or more pixels included in pixel array 110, and although FIG. 3a describes one multi-pixel MPX, other pixel groups may also have a substantially similar structure or perform a similar operation to the multi-pixel MPX.

[0046] According to one embodiment, the multi-pixel MPX may include photoelectric conversion elements PD1 to PD8, transfer transistors TX1 to TX8, drain transistor DX, split transistor SPX, reset transistor RX, floating diffusion region FD, dual conversion gain (DCG) transistor DCX, capacitor C, source follower transistor SF, and selection transistor SX. For example, the source follower transistor SF and selection transistor SX may correspond to a read controller that activates and reads the multi-pixel MPX (e.g., selects a row including the multi-pixel MPX). While FIG. 3A illustrates the multi-pixel MPX as including eight photoelectric conversion elements PD1 to PD8, other embodiments may have a structure including one or more photoelectric conversion elements. In this case, one or more transfer transistors may be provided corresponding to one or more photoelectric conversion elements.

[0047] According to one embodiment, the multi-pixel MPX may have a structure including one or more pixels. For example, the multi-pixel MPX may include a first pixel and one or more second pixels. For example, the first pixel of the multi-pixel MPX may include a first photoelectric conversion element PD1, a floating diffusion region FD, a split transistor SPX, a capacitor C, a DCG transistor DCX, and a reset transistor RX. The second pixel of the multi-pixel MPX may include a second photoelectric conversion element PD2, a floating diffusion region FD, a split transistor SPX, a capacitor C, a DCG transistor DCX, and a reset transistor RX. That is, the multi-pixel MPX may have a configuration in which the first pixel and the second pixel share the split transistor SPX, the floating diffusion region FD, the capacitor C, and the DCG transistor DCX. For example, the multi-pixel MPX may include one or more second pixels. For example, the one or more second pixels may include a pixel including a second photoelectric conversion element PD2, a pixel including a third photoelectric conversion element PD3, a pixel including a fourth photoelectric conversion element PD4, a pixel including a fifth photoelectric conversion element PD5, a pixel including a sixth photoelectric conversion element PD6, a pixel including a seventh photoelectric conversion element PD7, and a pixel including an eighth photoelectric conversion element PD8.

[0048] According to one embodiment, the multi-pixel MPX may include a first photoelectric conversion element PD1 connected to a first electrode of the split transistor SPX via a first transfer transistor TX1, second to eighth photoelectric conversion elements PD2 to PD8 connected to a second electrode ET of the split transistor SPX via second to eighth transfer transistors TX2 to TX8, a capacitor C for adjusting the capacitance of the floating diffusion region FD, and a DCG transistor DCX connected between the capacitor C and the first electrode and for controlling the capacitance of the floating diffusion region FD that accumulates photocharges generated by the second to eighth photoelectric conversion elements PD2 to PD8. For example, the first electrode may correspond to a location where the split transistor SPX and the floating diffusion region FD are connected.

[0049] According to an embodiment, the split transistor SPX may be turned on or off based on a split control signal SPG. For example, the HDR controller 300 may transmit a control signal to the timing controller 170, and the timing controller 170 may transmit a split control signal SPG of a logic high level or a logic low level to the split transistor SPX based on the control signal.

[0050] According to an embodiment, the HDR controller 300 may transmit a control signal to the timing controller 170 to turn on the split transistor SPX based on the ISP 200 detecting a low-illuminance environment, and may transmit a control signal to the timing controller 170 to turn on the split transistor SPX based on the ISP 200 detecting a high-illuminance environment. As an example, the ISP 200 may change the analog gain mode based on whether the environment is a high-illuminance environment or a low-illuminance environment. Furthermore, the split transistor SPX may be turned on or off depending on the analog gain mode.

[0051] According to one embodiment, the photoelectric conversion elements PD1 to PD8 can generate and accumulate photocharges corresponding to the intensity of incident light. For example, the photoelectric conversion elements PD1 to PD8 can be realized as photodiodes, phototransistors, photogates, pinned photodiodes, or a combination thereof. As an example, when the photoelectric conversion elements PD1 to PD8 are realized as photodiodes, the region receiving the incident light can be a region doped with impurities of a second conductivity type (e.g., N-type) in a substrate having a first conductivity type (e.g., P-type).

[0052] According to one embodiment, the first photoelectric conversion element PD1 may have a lower light transmittance than the second to eighth photoelectric conversion elements PD2 to PD8. As an example, a pixel structure including the first photoelectric conversion element PD1 may include a light blocking structure that blocks at least a portion of incident light. For example, the first pixel including the first photoelectric conversion element PD1 may further include a microlens, an optical filter, a light blocking structure, and a substrate in addition to the first photoelectric conversion element PD1.

[0053] According to one embodiment, the second photoelectric conversion element PD2 may support a higher light transmittance than the first photoelectric conversion element PD1. For example, unlike the first photoelectric conversion element PD1, the pixel structure including the second photoelectric conversion element PD2 may not include a light blocking structure that blocks at least a portion of incident light. For example, the second pixel including the second photoelectric conversion element PD2 may further include a microlens, an optical filter, and a substrate in addition to the second photoelectric conversion element PD2. For example, the third to eighth photoelectric conversion elements PD3 to PD8 may be understood to be the same as the second photoelectric conversion element PD2. For example, the third to eighth photoelectric conversion elements PD3 to PD8 may support a higher light transmittance than the first photoelectric conversion element PD1. For example, the third to eighth photoelectric conversion elements PD3 to PD8 may support the same or similar light transmittance as the second photoelectric conversion element PD2. A more detailed description of light transmittance will be provided below with reference to FIG. 5.

[0054] According to one embodiment, the first transfer transistor TX1 may be connected between the first photoelectric conversion element PD1 and the floating diffusion region FD. The second to eighth transfer transistors TX2 to TX8 may be connected between the second to eighth photoelectric conversion elements PD2 to PD8 and the split transistor SPX. The transfer transistors TX1 to TX8 may be turned on or off in response to transfer signals TG1 to TG8. The turned-on transfer transistors TX1 to TX8 may transfer photocharges accumulated in the photoelectric conversion elements PD1 to PD8 to the floating diffusion region FD. For example, when the split transistor SPX is turned on, the turned-on second to eighth transfer transistors TX2 to TX8 may transfer photocharges accumulated in the second to eighth photoelectric conversion elements PD2 to PD8 to the floating diffusion region FD.

[0055] According to an embodiment, the first to eighth transfer transistors TX1 to TX8 may be turned on or off based on the first to eighth transfer signals TG1 to TG8. For example, the HDR controller 300 may transmit a control signal to the timing controller 170, and the timing controller 170 may transmit the first to eighth transfer signals TG1 to TG8 of a logic high level or a logic low level to the first to eighth transfer transistors TX1 to TX8 based on the control signal.

[0056] According to one embodiment, the drain transistor DX may be connected between a power supply voltage VDD and the second to eighth transfer transistors TX2 to TX8. For example, if overflow charges are generated in the second to eighth photoelectric conversion elements PD2 to PD8 due to excessively bright light or crosstalk, the drain transistor DX may be turned on to discharge the overflow charges generated in the second to eighth photoelectric conversion elements PD2 to PD8.

[0057] According to an embodiment, the drain transistor DX may be turned on or off based on a drain control signal DG. For example, the HDR controller 300 may transmit a control signal to the timing controller 170, and the timing controller 170 may transmit a drain control signal DG of a logic high level or a logic low level to the drain transistor DX based on the control signal. For example, the HDR controller 300 may control the drain transistor DX to be turned on based on the overflow detection unit 310 detecting that photocharges greater than or equal to a threshold are generated from one or more second pixels.

[0058] According to one embodiment, the split transistor SPX may be connected between the first transfer transistor TX1 and the second to eighth transfer transistors TX2 to TX8. For example, the split transistor SPX may be turned on or off with a time lag to distinguish between the time when the photocharges generated by the first photoelectric conversion element PD1 are accumulated in the floating diffusion region FD and the time when the photocharges generated by the second to eighth photoelectric conversion elements PD2 to PD8 are accumulated in the floating diffusion region FD. For example, when the split transistor SPX is turned off, the first transfer transistor TX1 is turned on, so that the photocharges accumulated in the first photoelectric conversion element PD1 can be transferred to the floating diffusion region FD. In this case, the pixel signal generated by the multi-pixel MPX may correspond to pixel data of the first pixel. For example, when the first transfer transistor TX1 is turned off, the split transistor SPX and the second to eighth transfer transistors TX2 to TX8 are turned on, so that the photoelectric charges accumulated in the second to eighth photoelectric conversion elements PD2 to PD8 can be transferred to the floating diffusion region FD. In this case, the pixel signal generated by the multi-pixel MPX can correspond to pixel data of one or more second pixels.

[0059] According to one embodiment, the reset transistor RX may be connected between a power supply voltage VDD and the DCG transistor DCX. For example, when the DCG transistor DCX is turned on in response to the DCG control signal DCG, the reset transistor RX may reset the voltage of the floating diffusion region FD to the power supply voltage VDD in response to the reset control signal RG. For example, the power supply voltage VDD may correspond to a preset value.

[0060] According to one embodiment, the reset transistor RX may be turned on or off based on a reset control signal RG. For example, the reset transistor RX may transmit a control signal to the timing controller 170, and the timing controller 170 may transmit a reset control signal RG of a logic high level or a logic low level to the reset transistor RX based on the control signal.

[0061] According to one embodiment, the floating diffusion region FD may accumulate photocharges transferred from the transfer transistors TX1 to TX8. The floating diffusion region FD may be connected to the capacitor C via the DCG transistor DCX. For example, the floating diffusion region FD may be a region doped with impurities of a second conductivity type (e.g., N-type) in a substrate having a first conductivity type (e.g., P-type). For example, the capacitor C may be at least one of a metal-insulator-metal (MIM) capacitor, a metal-insulator-polysilicon (MIP) capacitor, a metal-oxide-semiconductor (MOS) capacitor, and a junction capacitor.

[0062] According to one embodiment, the floating diffusion region FD can accumulate photocharges generated by the first photoelectric conversion element PD1 when the first transfer transistor TX1 is turned on and the split transistor SPX is turned off. As an example, when the first transfer transistor TX1 is turned off and the split transistor SPX is turned on, the floating diffusion region FD can accumulate photocharges generated by the second to eighth photoelectric conversion elements PD2 to PD8 as a result of the second to eighth transfer transistors TX2 to TX8 being turned on.

[0063] According to one embodiment, the DCG transistor DCX is connected between the floating diffusion region FD and the capacitor C and may selectively connect the capacitor C to the floating diffusion region FD in response to a DCG control signal DCG. For example, when the DCG transistor DCX is turned on, the floating diffusion region FD may have an increased capacitance compared to when the DCG transistor DCX is turned off. That is, the DCG transistor DCX may control the capacitance of the floating diffusion region FD. For example, although FIG. 3A illustrates an example in which there is one DCG transistor DCX, according to other embodiments, there may be multiple DCG transistors. In this case, the capacitance of the floating diffusion region FD may have a more variable value.

[0064] According to one embodiment, the capacitor C may be connected between the power supply voltage VDD and the DCG transistor DCX. For example, when overflow charges are generated by the first photoelectric conversion element PD1 due to excessive light or crosstalk, the capacitor C may store the generated overflow charges. For example, when the split transistor SPX is turned off, the DCG transistor DCX is turned on, and the reset transistor RX is turned off, the overflow charges generated by the first photoelectric conversion element PD1 may be stored in the capacitor C.

[0065] According to one embodiment, the capacitor C may be selectively coupled to the floating diffusion region FD in response to turning on or off of the DCG transistor DCX. For example, when the DCG transistor DCX is turned off, the floating diffusion region FD may have a reduced capacitance compared to when the DCG transistor DCX is turned on.

[0066] According to one embodiment, the source follower transistor SF is connected between the power supply voltage VDD and the selection transistor SX, and can amplify and transmit to the selection transistor SX a change in the electrical potential of the floating diffusion region FD that receives the photocharges accumulated in the first to eighth photoelectric conversion elements PD1 to PD8.

[0067] According to one embodiment, the selection transistor SX is connected between the source follower transistor SF and an output signal line, and is turned on by a selection control signal SEL to output the electrical signal transmitted from the source follower transistor SF as a pixel signal PS.

[0068] According to an embodiment, the selection transistor SX may be turned on or off based on a selection control signal SEL. For example, the selection transistor SX may transmit a control signal to the timing controller 170, and the timing controller 170 may transmit a selection control signal SEL of a logic high level or a logic low level to the selection transistor SX based on the control signal.

[0069] Referring to Figure 3b, the second multi-pixel MPX2 may be any one of a pixel group including one or more pixels included in the pixel array 110, and although Figure 3b describes one second multi-pixel MPX2, other pixel groups may also have a structure and operation substantially similar to the second multi-pixel MPX2.

[0070] According to one embodiment, the second multi-pixel MPX2 may include photoelectric conversion elements PD1-PD4, transfer transistors TX1-TX4, drain transistor DX, split transistor SPX, reset transistor RX, floating diffusion region FD, DCG transistor DCX, capacitor C, source follower transistor SF, and selection transistor SX. While FIG. 3b illustrates the second multi-pixel MPX2 as including four photoelectric conversion elements PD1-PD4, other embodiments may have a structure having only two photoelectric conversion elements. For example, the second multi-pixel MPX2 may omit the third photoelectric conversion element PD3, the third transfer transistor TX3, the fourth photoelectric conversion element PD4, and the fourth transfer transistor TX4.

[0071] According to one embodiment, the second multi-pixel MPX2 may include a first photoelectric conversion element PD1 corresponding to low light transmittance and connected to a first electrode ET of the split transistor SPX via a first transfer transistor TX1, second to fourth photoelectric conversion elements PD2 to PD4 corresponding to high light transmittance and connected to a second electrode ET of the split transistor SPX via second to fourth transfer transistors TX2 to TX4, a capacitor C capable of accommodating overflow charges of the first photoelectric conversion element PD1 corresponding to low light transmittance, and a DCG transistor DCX connected between the capacitor C and the first electrode and controlling the capacitance of a floating diffusion region FD that accumulates photocharges generated by the second to fourth photoelectric conversion elements PD2 to PD4 corresponding to high light transmittance. For example, the first electrode may correspond to a location where the split transistor SPX and the floating diffusion region FD are connected.

[0072] According to one embodiment, the photoelectric conversion elements PD1 to PD4 can generate and accumulate photocharges corresponding to the intensity of incident light. For example, the photoelectric conversion elements PD1 to PD4 can be realized as photodiodes, phototransistors, photogates, pinned photodiodes, or a combination thereof. As an example, when the photoelectric conversion elements PD1 to PD4 are realized as photodiodes, the region receiving the incident light can be a region doped with impurities of a second conductivity type (e.g., N-type) in a substrate having a first conductivity type (e.g., P-type).

[0073] According to one embodiment, the first photoelectric conversion element PD1 can support a lower light transmittance than the second to fourth photoelectric conversion elements PD2 to PD4. As an example, the pixel structure including the first photoelectric conversion element PD1 can include a light blocking structure that blocks at least a portion of incident light. For example, the pixel structure including the first photoelectric conversion element PD1 can further include a microlens, an optical filter, a light blocking structure, and a substrate in addition to the first photoelectric conversion element PD1.

[0074] According to one embodiment, the second photoelectric conversion element PD2 may support a higher light transmittance than the first photoelectric conversion element PD1. For example, unlike the first photoelectric conversion element PD1, the pixel structure including the second photoelectric conversion element PD2 may not include a light blocking structure that blocks at least a portion of incident light. For example, the pixel structure including the second photoelectric conversion element PD2 may further include a microlens, an optical filter, and a substrate in addition to the second photoelectric conversion element PD2. For example, the third and fourth photoelectric conversion elements PD3 and PD4 may be understood to be the same as the second photoelectric conversion element PD2. For example, the third and fourth photoelectric conversion elements PD3 and PD4 may support a higher light transmittance than the first photoelectric conversion element PD1. For example, the third and fourth photoelectric conversion elements PD3 and PD4 may support the same or similar light transmittance as the second photoelectric conversion element PD2. A more detailed description of light transmittance will be provided below with reference to FIG. 5.

[0075] According to one embodiment, the multi-pixel MPX of Fig. 3b may correspond to a structure in which the fifth to eighth photoelectric conversion elements PD5 to PD8 and the fifth to eighth transfer transistors TX5 to TX8 are omitted from the multi-pixel MPX of Fig. 3a. As an example, the first to fourth transfer transistors TX1 to TX4, drain transistor DX, split transistor SPX, reset transistor RX, floating diffusion region FD, DCG (Dual Conversion Gain) transistor DCX, capacitor C, source follower transistor SF, and selection transistor SX of Fig. 3b can be understood in the same way as in Fig. 3a. Explanations overlapping with Fig. 3a will be omitted.

[0076] FIG. 4 is a diagram illustrating a pixel group, a microlens, an ADC, and corresponding pixels according to one embodiment of the present disclosure. Referring to FIG. 4, the image sensing device 100 may correspond to an A4C (All 4-Coupled) type sensor. As an example, the A4C sensor may detect a phase difference while acquiring a color image in all pixels. As an example, the A4C sensor may include a configuration in which pixels (e.g., G11, G12, G21, and G22) arranged in a 2×2 matrix share one microlens (e.g., ML1). As an example, the centers of the pixels (e.g., G11, G12, G21, and G22) sharing the microlens (e.g., ML1) may be located at the same distance from the center of the microlens (e.g., ML1) shared by the pixels (e.g., G11, G12, G21, and G22).

[0077] According to one embodiment, the pixels included in the pixel array 110 may be divided into two green filter regions, one blue filter region, and one red filter region, and may be arranged in a Bayer pattern. As an example, the pixels included in the pixel array 110 may form a unit Bayer pattern for each 8x8 pixel. For example, among the pixels included in the unit Bayer pattern, the upper left 4x4 pixels G11, G12, G13, G14, G21, G22, G23, G24, G31, G32, G33, G34, G41, G42, G43, and G44 and the lower right 4x4 pixels G55, G56, G57, G58, G65, G66, G67, G68, G75, G76, G77, G78, G85, G86, G87, and G88 correspond to green filters. The 4x4 pixels on the upper right side, B15, B16, B17, B18, B25, B26, B27, B28, B35, B36, B37, B38, B45, B46, B47, and B48, correspond to a blue filter, and the 4x4 pixels on the lower left side, R51, R52, R53, R54, R61, R62, R63, R64, R71, R72, R73, R74, R81, R82, R83, and R84, correspond to a red filter.

[0078] According to one embodiment, among the pixels included in the pixel array 110 of the image sensing device 100, eight pixels corresponding to the same color filter may be grouped in the form of a column and organized into one pixel group (e.g., PG1 or PG2). For example, the eight pixels may include seven pixels corresponding to high light transmittance and one pixel corresponding to low light transmittance. For example, one pixel group (e.g., PG1 or PG2) may be connected to a corresponding ADC (e.g., ADC1 or ADC2), and the connected ADC may receive pixel signals PS of the eight pixels included in the pixel group. For example, a correlated double sampler 130 may be connected between the pixel array 110 and the ADCs (e.g., ADC1 to ADC8), but is omitted from FIG. 4 for convenience of explanation.

[0079] According to one embodiment, the first pixel group PG1 of the pixel array 110 may include pixels G11, G12, G21, G22, G31, G32, G41, and G42 corresponding to eight identical color filters. For example, the eight pixels G11, G12, G21, G22, G31, G32, G41, and G42 included in the first pixel group PG1 may be divided into seven pixels G11, G12, G21, G22, G31, G32, and G42 corresponding to high light transmittance and one pixel G41 corresponding to low transmittance. As an example, referring also to Figure 3a, seven pixels G11, G12, G21, G22, G31, G32, and G42 corresponding to high light transmittance include the second to eighth photoelectric conversion elements PD2 to PD8 of Figure 3a, respectively, and one pixel G41 corresponding to low light transmittance includes the first photoelectric conversion element PD1 of Figure 3a.

[0080] According to one embodiment, the first pixel group PG1 may include a first microlens ML1 and a fifth microlens ML5. The first microlens ML1 may correspond to four pixels G11, G12, G21, and G22 corresponding to high light transmittance, and the fifth microlens ML5 may correspond to one pixel G41 corresponding to low light transmittance and three pixels G31, G32, and G42 corresponding to high light transmittance. For example, a first ADC (ADC1) may be connected to the first pixel group PG1 and receive pixel signals generated from the first pixel group PG1. For example, the first ADC (ADC1) may receive a pixel signal obtained by summing pixel signals from seven pixels G11, G12, G21, G22, G31, G32, and G42 corresponding to high light transmittance. The image signal processor 200 may calculate pixel data for a low-light image based on the summed pixel signal.

[0081] According to one embodiment, the second pixel group PG2 of the pixel array 110 may include pixels G13, G14, G23, G24, G33, G34, G43, and G44 corresponding to eight identical color filters. For example, the eight pixels G13, G14, G23, G24, G33, G34, G43, and G44 included in the second pixel group PG2 may be divided into seven pixels G13, G14, G23, G24, G33, G34, and G44 corresponding to high light transmittance and one pixel G43 corresponding to low light transmittance.

[0082] According to one embodiment, the second pixel group PG2 may include a second microlens ML2 and a sixth microlens ML6. The second microlens ML2 may correspond to four pixels G13, G14, G23, and G24 corresponding to high light transmittance, and the sixth microlens ML6 may correspond to one pixel G43 corresponding to low light transmittance and three pixels G33, G34, and G44 corresponding to high light transmittance. For example, a second ADC (ADC2) may be connected to the second pixel group PG2 and receive pixel signals generated from the second pixel group PG2. For example, the second ADC (ADC2) may receive a pixel signal obtained by summing pixel signals from seven pixels G13, G14, G23, G24, G33, G34, and G44 corresponding to high light transmittance. The image signal processor 200 may calculate pixel data for a low-light image based on the summed pixel signal.

[0083] According to one embodiment, for the remaining pixels, pixels corresponding to eight identical color filters may be grouped into one pixel group and connected to one ADC (e.g., ADC3, ADC4, ADC5, ADC6, ADC7, or ADC8), and redundant description will be omitted.

[0084] According to one embodiment, the pixel receiving unit of the first ADC (ADC1) and the pixel receiving unit of the second ADC (ADC2) may be selectively connected to each other by a first switch SW1. For example, the first switch SW1 may be opened or closed based on a first switch control signal SC1. For example, when the first switch SW1 is open, the first ADC (ADC1) may receive pixel signals from the first pixel group PG1. Also, the second ADC (ADC2) may receive pixel signals from the second pixel group PG2. For example, when the first switch SW1 is open, the first ADC (ADC1) may receive pixel signals from seven pixels G11, G12, G21, G22, G31, G32, and G42 corresponding to high light transmittance and / or a pixel signal from one pixel G41 corresponding to low light transmittance from the first pixel group PG1. In addition, the second ADC (ADC2) can receive pixel signals from seven pixels G13, G14, G23, G24, G33, G34, and G44 corresponding to high light transmittance from the second pixel group PG2, and / or pixel signals from one pixel G43 corresponding to low light transmittance.

[0085] According to one embodiment, when the first switch SW1 is closed, the first ADC (ADC1) or the second ADC (ADC2) may receive a signal obtained by summing pixel signals of seven pixels G11, G12, G21, G22, G31, G32, and G42 corresponding to the high light transmittance of the first pixel group PG1 and pixel signals of seven pixels G13, G14, G23, G24, G33, G34, and G44 corresponding to the high light transmittance of the second pixel group PG2. The first ADC (ADC1) or the second ADC (ADC2) may also receive a signal obtained by summing pixel signals of one pixel G41 corresponding to the low light transmittance of the first pixel group PG1 and one pixel G43 corresponding to the low light transmittance of the second pixel group PG2. For example, when the first switch SW1 is closed, one of the first ADC (ADC1) or the second ADC (ADC2) is deactivated, and the activated ADC can be used to receive pixel signals. For example, the imaging device 10 can operate the deactivated ADC in a low-power mode.

[0086] According to one embodiment, when the first switch SW1 is closed, the pixel signals of the first pixel group PG1 and the pixel signals of the second pixel group PG2 are summed, thereby improving the speed at which image data IDATA is generated using the pixel signals. Conversely, when the first switch SW1 is open, the pixel signals of the first pixel group PG1 and the pixel signals of the second pixel group PG2 are processed separately, thereby improving the resolution of the image data IDATA. For example, when the first image switch SW1 is closed, the image signal processor 200 may calculate an average of the pixel signals of the first pixel group PG1 and the pixel signals of the second pixel group PG2 to reduce noise components in the pixel signals. The operations and effects of the second switch SW2, the third switch SW3, and the fourth switch SW4 can be understood in the same way as the operation and effect of the first switch SW1, and redundant description will be omitted.

[0087] According to one embodiment, the pixel array 110 may be arranged in a Bayer pattern, and the pixels included in the pixel array 110 may form a unit Bayer pattern for each 4x4 pixel. For example, among the pixels included in the unit Bayer pattern, the upper left 2x2 pixels and the lower right 2x2 pixels may correspond to a green filter, the upper right 2x2 pixels may correspond to a blue filter, and the lower left 2x2 pixels may correspond to a red filter.

[0088] According to one embodiment, among the pixels included in the pixel array 110 of the image sensing device 100, pixels corresponding to four identical color filters may be grouped and organized into one pixel group unit. For example, the four pixels may include three pixels corresponding to high light transmittance and one pixel corresponding to low light transmittance. For example, one pixel group may be connected to a corresponding ADC, and the connected ADC may receive pixel signals PS of the four pixels included in the pixel group. For example, referring also to FIG. 3b, among the four pixels, the three pixels corresponding to high light transmittance may include the second to fourth photoelectric conversion elements PD2 to PD4 of FIG. 3b, respectively, and the one pixel corresponding to low light transmittance may include the first photoelectric conversion element PD1 of FIG. 3b.

[0089] FIG. 5 is a diagram illustrating a cross section of a high-transmittance pixel and a low-transmittance pixel according to one embodiment of the present disclosure. Referring to FIG. 5, the left side of FIG. 5 illustrates an embodiment in which a low-transmittance pixel LPX having a relatively low light transmittance and a high-transmittance pixel HPX having a relatively high light transmittance are arranged. That is, the configuration illustrated on the left side of FIG. 5 may correspond to a pixel group 500 in which one low-transmittance pixel LPX and seven high-transmittance pixels HPX are arranged in a 4×2 matrix. As an example, the pixel group 500 may correspond to the multi-pixel MPX of FIG. 3a or the first pixel group PG1 of FIG. 4. As an example, the low-transmittance pixel LPX of FIG. 5 may correspond to the first photoelectric conversion element PD1 of FIG. 3a or the pixel G41 corresponding to the low light transmittance of FIG. 4.

[0090] According to one embodiment, the low-transmittance pixel LPX and each of the plurality of high-transmittance pixels HPX may have a structure corresponding to FIG. 3a. As an example, each of the low-transmittance pixel LPX and the high-transmittance pixel HPX may independently include a photoelectric conversion element and a transfer transistor, and other components (e.g., drain transistor DX, split transistor SPX, reset transistor RX, floating diffusion region FD, DCG transistor DCX, capacitor C, source follower transistor SF, and selection transistor SX) may be realized as a shared pixel structure shared by eight pixels. As an example, the low-transmittance pixel LPX and the high-transmittance pixel HPX may be pixels that detect light of the same color (e.g., red, blue, or green).

[0091] 5 shows an example of a cross section taken along the line A-A' of a low-transmittance pixel LPX and a high-transmittance pixel HPX that are adjacent to each other among the pixels included in the pixel group 500. As an example, the cross section of the high-transmittance pixel HPX includes a substrate 510, a photoelectric conversion element 520, an optical filter 530, and a microlens 540, and the low-transmittance pixel LPX may further include a light-blocking structure 550 in addition to the above.

[0092] In one embodiment, the substrate 510 is a semiconductor substrate, and may be, for example, a P-type or N-type bulk substrate, a P-type bulk substrate with a P-type or N-type epitaxial layer grown thereon, or an N-type bulk substrate with a P-type or N-type epitaxial layer grown thereon.

[0093] According to one embodiment, the photoelectric conversion element 520 may be formed inside the substrate 510 and may correspond to the photoelectric conversion element PD of Figures 3a and 3b. That is, the photoelectric conversion element 520 may generate and accumulate photocharges corresponding to the intensity of incident light that has passed through the microlens 540 and the optical filter 530.

[0094] According to one embodiment, the optical filter 530 can selectively transmit light of a transmission wavelength band (e.g., red, green, blue, magenta, yellow, cyan, infrared, etc.). Here, the transmission wavelength band may refer to a wavelength band corresponding to light that the optical filter is to selectively transmit. For example, the optical filter 530 may include colored photosensitive materials corresponding to specific colors or may include alternating thin film layers. The optical filters included in the pixel array 110 may be arranged corresponding to pixels arranged in a matrix including a plurality of rows and a plurality of columns, thereby forming an optical filter array.

[0095] According to an embodiment, the microlens 540 may be formed on the optical filter 530 to increase the light gathering power for incident light and improve the light receiving efficiency of the photoelectric conversion element 520 .

[0096] According to an embodiment, the light-blocking structure 550 may be disposed between one surface of the substrate 510 and the optical filter 530 in the low-transmittance pixel LPX to block at least a portion of incident light passing through the optical filter 530 and prevent it from being transmitted to the photoelectric conversion element 520. The light-blocking structure 550 may include at least one of a material with high light reflectivity (e.g., silver or aluminum) and a material with high light absorption (e.g., tungsten). For example, the light-blocking structure 550 may include a half shield structure, a neutral-density (ND) filter, or a gray filter.

[0097] According to an embodiment, the total area of ​​the low-transmittance pixel LPX may be defined as the sum of the blocking area of ​​the region where the light-blocking structure 550 is not disposed and the open area of ​​the region where the light-blocking structure 550 is disposed. The light transmittance of the low-transmittance pixel LPX may be determined according to the ratio of the blocking area to the open area.

[0098] According to one embodiment, the light transmittance of the high-transmittance pixel HPX that does not include the light-blocking structure 550 may be higher than the light transmittance of the low-transmittance pixel LPX that includes the light-blocking structure 550. That is, when incident light of the same intensity is incident on the high-transmittance pixel HPX and the low-transmittance pixel LPX, the intensity of the light transmitted to the photoelectric conversion element 520 of the low-transmittance pixel LPX may be lower than the intensity of the light transmitted to the photoelectric conversion element 520 of the high-transmittance pixel HPX.

[0099] According to one embodiment, the intensity of light transmitted to the photoelectric conversion element 520 of the low transmittance pixel LPX increases at a relatively low slope in response to an increase in the intensity of the incident light, and the intensity of light transmitted to the photoelectric conversion element 520 of the high transmittance pixel HPX increases at a relatively high slope in response to an increase in the intensity of the incident light.

[0100] According to one embodiment, the intensity of light transmitted to the photoelectric conversion element 520 of the low-transmittance pixel LPX and the intensity of light transmitted to the photoelectric conversion element 520 of the high-transmittance pixel HPX are respectively converted into pixel signals, so that the response of the low-transmittance pixel LPX follows the response of the low-sensitivity pixel shown in FIG. 2, and the response of the high-transmittance pixel HPX follows the response of the high-sensitivity pixel shown in FIG. 2.

[0101] According to one embodiment, FIG. 5 shows the light-blocking structure 550 disposed at the end of the low-transmittance pixel LPX, but the scope of the present invention is not limited thereto. For example, the light-blocking structure 550 may be disposed at any position of the low-transmittance pixel LPX, or may be disposed over the entire area of ​​the low-transmittance pixel LPX without leaving any portion open.

[0102] According to an embodiment, the image sensing device 100 may implement both low-sensitivity pixels and high-sensitivity pixels within a single pixel array 110, thereby generating an HDR image from a single image.

[0103] FIG. 6 is a timing diagram corresponding to the circuit diagram of FIG. 3a according to one embodiment of the present disclosure. 6, each component of the multi-pixel MPX corresponding to one pixel group of the pixel array 110 may receive a reset control signal RG, a drain control signal DG, a DCG control signal DCG, first to eighth transfer signals TG1 to TG8, a split control signal SPG, and a selection control signal SEL. As an example, each component of the multi-pixel MPX may be turned on when the received signal is a logic high level (H) and turned off when the received signal is a logic low level (L). For example, the reset control signal RG, the drain control signal DG, the DCG control signal DCG, the first to eighth transfer signals TG1 to TG8, the split control signal SPG, and the selection control signal SEL may have a logic low level (L) and a logic high level (H), respectively, such that a transistor receiving a signal having a logic low level (L) is turned off and a transistor receiving a signal having a logic high level (H) is turned on.

[0104] According to an embodiment, the operation of the multi-pixel MPX may be performed during a multi-pixel readout period MPRO. For example, the first phase may correspond to a left phase, and the second phase may correspond to a right phase. For example, the HDR controller 300 may divide the operation period of the multi-pixel MPX and control signals input to each component of the multi-pixel MPX so that the pixels of the image sensing device 100 have an optimal dynamic range. For example, the HDR controller 300 may control the timing controller 170 of the image sensing device 100.

[0105] According to one embodiment, the multi-pixel readout interval MPRO may include a summation interval ITG, a first readout interval 1RO, a first-phase readout interval 1PRO, and a second-phase readout interval 2PRO. For example, referring also to FIG. 3A, during the multi-pixel readout interval MPRO, the selection control signal SEL may be at a logic high level (H). For example, the pixel array 110 may be driven row by row by the row driver 120. Therefore, the multi-pixel readout interval MPRO may correspond to a period during which a row corresponding to a multi-pixel MPX in the pixel array 110 is selected and pixel signals generated by the multi-pixel MPX are read out.

[0106] According to one embodiment, the summing interval ITG may include an interval in which photoelectric charges accumulated in all photoelectric conversion elements included in the multi-pixel MPX are reset before pixel signals are read out. For example, the summing interval ITG may include an interval in which the reset control signal RG, the drain control signal DG, the DCG control signal DCG, and the first to eighth transfer signals TG1 to TG8 are at a logic high level (H). Also, during the summing interval ITG, the split control signal SPG may be at a logic low level (L).

[0107] According to one embodiment, the summing interval ITG may include an interval in which the photoelectric charges accumulated in the first photoelectric conversion element PD1 are transferred to the floating diffusion region FD. For example, during the interval in which the first transfer signal TG1 and the DCG control signal DCG are at a logic high level (H), the photoelectric charges accumulated in the first photoelectric conversion element PD1 may be transferred to the floating diffusion region FD. At this time, since the DCG control signal DCG is at a logic high level, the capacitance of the floating diffusion region FD may be increased by the capacitor C. For example, if the first photoelectric conversion element PD1 receives bright light and overflows charges occur, the DCG control signal DCG may be at a logic high level, so the overflow charges of the first photoelectric conversion element PD1 may be stored in the capacitor C. For example, if the second to eighth photoelectric conversion elements PD2 to PD8 receive bright light and overflows charges occur, the drain control signal DG may be at a logic high level, so the overflow charges of the second to eighth photoelectric conversion elements PD2 to PD8 may be discharged by the power supply voltage VDD.

[0108] According to one embodiment, the first readout section 1RO may include a first pixel signal section 1PS, a reset section 1RS, and a first reset signal section 1PR. Referring also to FIG. 3A, during the first readout section 1RO, the split control signal SPG may be at a logic low level (L). Therefore, the first readout section 1RO may correspond to a section in which a pixel signal is generated based on photocharges generated by the first photoelectric conversion element PD1.

[0109] According to an embodiment, during the first pixel signal period 1PS, the multi-pixel MPX may generate an electrical signal corresponding to the photocharges generated by the first photoelectric conversion element 1PD and output the electrical signal as the first pixel signal. For example, during the first readout period 1RO, the first pixel signal period 1PS may correspond to the period from when the first transfer signal TG1 transitions from a logic high level (H) to a logic low level (L) to when the reset control signal RG transitions from a logic low level (L) to a logic high level (H). For example, the first pixel signal period 1PS may be the period during the summation period ITG from when the first transfer signal TG1 transitions from a logic low level (L) to a logic high level (H) to when the first transfer signal TG1 transitions from a logic high level (H) to a logic low level (L) in which the electrical signal corresponding to the photocharges accumulated in the floating diffusion region FD is output as the first pixel signal.

[0110] According to one embodiment, during the reset period 1RS, the multi-pixel MPX may remove photocharges remaining in the first photoelectric conversion element and the multi-pixel MPX and reset the floating diffusion region FD to the power supply voltage VDD. For example, during the first readout period 1RO, the reset period 1RS may correspond to the period from when the reset control signal RG transitions from a logic low level (L) to a logic high level (H) to when the reset control signal RG transitions from a logic high level (H) to a logic low level (L).

[0111] According to one embodiment, during the first reset signal section 1PR, the multi-pixel MPX may output a first reset signal when the first photoelectric conversion element 1PD and the floating diffusion region FD are in a reset state. For example, during the first readout section 1RO, the first reset signal section 1PR may correspond to the period from when the reset control signal RG transitions from a logic high level (H) to a logic low level (L) to when the reset control signal RG transitions from a logic low level (L) to a logic high level (H). For example, the first reset signal section 1PR may be a section in which an electrical signal corresponding to photocharges accumulated in the floating diffusion region FD in the reset state is output as the first reset signal.

[0112] According to one embodiment, the first pixel signal and the first reset signal generated during the first readout period 1RO can be converted into a digital value of the pixel signal corresponding to the first readout period 1RO via the correlated double sampler 130 and the ADC 140.

[0113] According to one embodiment, the first readout period 1RO may correspond to a period in which a pixel signal is generated based on photocharges generated by the first photoelectric conversion element PD1 corresponding to a relatively low light transmittance. That is, when incident light of the same intensity is incident on the first photoelectric conversion element PD1 and the second to eighth photoelectric conversion elements PD2 to PD8, the amount of photocharges of the first photoelectric conversion element PD1 accumulated in the floating diffusion region FD may be smaller than the amount of photocharges of the second to eighth photoelectric conversion elements PD2 to PD8 accumulated in the floating diffusion region FD.

[0114] According to one embodiment, the amount of photocharge accumulated in the floating diffusion region FD of the first photoelectric conversion element PD1 increases at a relatively low slope in response to an increase in the intensity of the incident light, and the amount of photocharge accumulated in the floating diffusion regions FD of the second to eighth photoelectric conversion elements PD2 to PD8 described below increases at a relatively high slope in response to an increase in the intensity of the incident light.

[0115] 2, according to one embodiment, the amount of photocharge accumulated in the floating diffusion region FD of the first photoelectric conversion element PD1 and the amount of photocharge accumulated in the floating diffusion region FD of second to eighth photoelectric conversion elements PD2 to PD8 (described later) are each converted into pixel signals, so that the pixel signal corresponding to the first photoelectric conversion element PD1 follows the response of the low-sensitivity pixel shown in Fig. 2, and the pixel signals corresponding to second to eighth photoelectric conversion elements PD2 to PD8 (described later) follow the response of the high-sensitivity pixel shown in Fig. 2. As an example, according to the image sensing device 100 according to another embodiment of the present invention, both the low-sensitivity pixel and the high-sensitivity pixel can be realized within one pixel array 110, so that an HDR image can be generated from a single image.

[0116] According to one embodiment, the first-phase readout section 1PRO may include a first-phase reset section 1PRS, a first-phase LCG (Low Conversion Gain) reset signal section 1PLR, a first-phase HCG (High Conversion Gain) reset signal section 1PHR, a first-phase HCG pixel signal section 1PHS, and a first-phase LCG pixel signal section 1PLS. Referring also to FIG. 3a, during the first-phase readout section 1PRO, the split control signal SPG may be in a logic high (H) state, and the first transfer signal TG1, the second transfer signal TG2, the fourth transfer signal TG4, the sixth transfer signal TG6, and the eighth transfer signal TG8 may be in a logic low (L) state. Therefore, the first-phase readout section 1PRO may correspond to a section in which pixel signals are generated based on photocharges generated by the third, fifth, and seventh photoelectric conversion elements PD3, PD5, and PD7.

[0117] According to one embodiment, the first phase readout section 1PRO may correspond to a section for generating pixel signals for generating a phase difference image in a first direction. For example, the first direction may correspond to the left direction. For example, referring to FIG. 4 , the multi-pixel MPX may correspond to the first pixel group PG1, and the third photoelectric conversion element PD3, the fifth photoelectric conversion element PD5, and the seventh photoelectric conversion element PD7 may correspond to the pixel G31 located in the left region of the fifth microlens ML5 and corresponding to high light transmittance, and the pixels G21 and G11 located in the left region of the first microlens ML1 and corresponding to high transmittance, respectively. For example, the image signal processor 200 may generate a left-right phase difference image based on the left phase difference image and the right phase difference image and calculate a phase difference based on the disparity of the left-right phase difference image.

[0118] According to one embodiment, during the first phase reset period 1PRS, the multi-pixel MPX may remove photocharges remaining in the third photoelectric conversion element PD3, the fifth photoelectric conversion element PD5, the seventh photoelectric conversion element PD7, and the multi-pixel MPX, and reset the floating diffusion region FD to the power supply voltage VDD. For example, during the first phase readout period 1PRO, the first phase reset period 1PRS may correspond to the period from when the reset control signal RG transitions from a logic low level (L) to a logic high level (H) to when the reset control signal RG transitions from a logic high level (H) to a logic low level (L).

[0119] According to an embodiment, during the first-phase LCG reset signal section 1PLR, the multi-pixel MPX may output a first-phase LCG reset signal, which is a pixel signal when the third photoelectric conversion element PD3, the fifth photoelectric conversion element PD5, the seventh photoelectric conversion element PD7, and the floating diffusion region FD are in a reset state. At this time, since the DCG control signal DCG is at a logic high level (H), the capacitance of the floating diffusion region FD may be increased by the capacitor C. For example, during the first-phase readout section 1PRO, the first-phase LCG reset signal section 1PLR may correspond to the period from when the reset control signal RG transitions from a logic high level (H) to a logic low level (L) to when the DCG control signal DCG transitions from a logic high level (H) to a logic low level (L). For example, the first-phase LCG reset signal section 1PLR may be a section in which an electrical signal corresponding to photocharges accumulated in the floating diffusion region FD, whose capacitance has increased in the reset state, is output as the first-phase LCG reset signal.

[0120] According to one embodiment, during the first-phase HCG reset signal period 1PHR, the multi-pixel MPX may output a first-phase HCG reset signal, which is a pixel signal when the third photoelectric conversion element PD3, the fifth photoelectric conversion element PD5, the seventh photoelectric conversion element PD7, and the floating diffusion region FD are in a reset state. Since the DCG control signal DCG is at a logic low level (L), the capacitance of the floating diffusion region FD may be reduced compared to when the DCG control signal DCG is at a logic high level (H). For example, during the first-phase readout period 1PRO, the first-phase HCG reset signal period 1PHR may be from when the DCG control signal DCG transitions from a logic high level (H) to a logic low level (L) to when the third transfer signal TG3, the fifth transfer signal TG5, and the seventh transfer signal TG7 transition from a logic low level (L) to a logic high level (H). For example, the first phase HCG reset signal section 1PHR may be a section in which, in the reset state, an electrical signal corresponding to the photocharges accumulated in the floating diffusion region FD whose capacitance has decreased is output as the first phase HCG reset signal.

[0121] According to one embodiment, during the first-phase HCG pixel signal period 1PHS, the multi-pixel MPX generates electrical signals corresponding to the photocharges generated by the third photoelectric conversion element PD3, the fifth photoelectric conversion element PD5, and the seventh photoelectric conversion element PD7, and outputs the electrical signals as the first-phase HCG pixel signal. At this time, because the DCG control signal DCG is at a logic low level (L), the capacitance of the floating diffusion region FD may be reduced compared to when the DCG control signal DCG is at a logic high level (H). For example, during the first-phase readout period 1PRO, the first-phase HCG pixel signal period 1PHS may correspond to the period from when the third transfer signal TG3, the fifth transfer signal TG5, and the seventh transfer signal TG7 transition from a logic high level (H) to a logic low level (L) to when the DCG control signal DCG transitions from a logic low level (L) to a logic high level (H). For example, the first-phase HCG pixel signal section 1PHS may be a section in which an electrical signal corresponding to photocharges accumulated in the floating diffusion region FD, whose capacitance has decreased, is output as the first-phase HCG pixel signal. In this case, the photocharges accumulated in the floating diffusion region FD may correspond to photocharges transferred to the floating diffusion region FD from the time when the third transfer signal TG3, the fifth transfer signal TG5, and the seventh transfer signal TG7 transition from a logic low level (L) to a logic high level (H) to the time when the third transfer signal TG3, the fifth transfer signal TG5, and the seventh transfer signal TG7 transition from a logic high level (H) to a logic low level (L).

[0122] According to an embodiment, during the first-phase LCG pixel signal period 1PLS, the multi-pixel MPX may generate an electrical signal corresponding to the photocharges generated by the third photoelectric conversion element PD3, the fifth photoelectric conversion element PD5, and the seventh photoelectric conversion element PD7 and output the electrical signal as the first-phase LCG pixel signal. At this time, since the DCG control signal DCG is at a logic high level (H), the capacitance of the floating diffusion region FD may be increased by the capacitor C. For example, during the first-phase readout period 1PRO, the first-phase LCG pixel signal period 1PLS may correspond to the period from when the DCG control signal DCG transitions from a logic low level (L) to a logic high level (H) to when the reset control signal RG transitions from a logic low level (L) to a logic high level (H). For example, the first-phase LCG pixel signal period 1PLS may be a period in which an electrical signal corresponding to the photocharges accumulated in the floating diffusion region FD, whose capacitance has increased, is output as the first-phase LCG pixel signal. At this time, the photocharges accumulated in the floating diffusion region FD may correspond to the photocharges transferred to the floating diffusion region FD from the time when the third transfer signal TG3, the fifth transfer signal TG5, and the seventh transfer signal TG7 transition from a logic low level (L) to a logic high level (H) to the time when the third transfer signal TG3, the fifth transfer signal TG5, and the seventh transfer signal TG7 transition from a logic high level (H) to a logic low level (L).

[0123] According to one embodiment, the first-phase LCG reset signal and the first-phase LCG pixel signal generated during the first-phase readout period 1PRO may be converted into a digital value of the first-phase LCG signal, which is a pixel signal corresponding to the first-phase readout period 1PRO, via the correlated double sampler 130 and the ADC 140. As an example, the first-phase HCG reset signal and the first-phase HCG pixel signal generated during the first-phase readout period 1PRO may be converted into a digital value of the first-phase HCG signal, which is a pixel signal corresponding to the first-phase readout period 1PRO, via the correlated double sampler 130 and the ADC 140.

[0124] According to one embodiment, in the first-phase readout period 1PRO, photocharges accumulated in the floating diffusion region FD generate a voltage change in the floating diffusion region FD, which may be converted into an electrical signal by the source follower transistor SF. In this case, the degree of the voltage change in the floating diffusion region FD may be determined by the capacitance of the floating diffusion region FD. For the same amount of photocharges, the smaller the capacitance of the floating diffusion region FD, the larger the voltage change in the floating diffusion region FD, and the larger the capacitance of the floating diffusion region FD, the smaller the voltage change in the floating diffusion region FD. That is, when the same amount of photocharges is transmitted from the third photoelectric conversion element PD3, the fifth photoelectric conversion element PD5, and the seventh photoelectric conversion element PD7 to the floating diffusion region FD, the magnitude of the first-phase HCG signal when the DCG control signal is at a logic low level (L) can be greater than the magnitude of the first-phase LCG signal when the DCG control signal is at a logic high level (H).

[0125] According to one embodiment, when the DCG control signal is at a logic high level (H), the magnitude of the first-phase LCG signal increases at a relatively low slope in response to an increase in photocharge, and when the DCG control signal is at a logic low level (L), the magnitude of the first-phase HCG signal increases at a relatively high slope in response to an increase in photocharge. For example, referring also to FIG. 2, the magnitude of the first-phase LCG signal and the magnitude of the first-phase HCG signal are converted into image data IDATA, so that the response of the first-phase LCG signal follows the response of the low-sensitivity pixel shown in FIG. 2, and the response of the first-phase HCG signal follows the response of the high-sensitivity pixel shown in FIG. 2. For example, according to an image sensing device 100 according to another embodiment of the present invention, both low-sensitivity pixels and high-sensitivity pixels can be implemented within one pixel array 110, thereby generating an HDR image from a single image.

[0126] According to one embodiment, the second-phase readout section 2PRO may include a second-phase reset section 2PRS, a second-phase LCG reset signal section 2PLR, a second-phase HCG reset signal section 2PHR, a second-phase HCG pixel signal section 2PHS, and a second-phase LCG pixel signal section 2PLS. Referring also to FIG. 3a, during the second-phase readout section 2PRO, the split control signal SPG may be in a logic high (H) state, and the first transfer signal TG1, the third transfer signal TG3, the fifth transfer signal TG5, and the seventh transfer signal TG7 may be in a logic low (L) state. Therefore, the second-phase readout section 2PRO may correspond to a section in which pixel signals are generated based on photocharges generated by the second, fourth, sixth, and eighth photoelectric conversion elements PD2, PD4, PD6, and PD8.

[0127] According to one embodiment, the second phase readout section 2PRO may correspond to a section for generating pixel signals for generating a phase difference image in a second direction. For example, the second direction may correspond to the right direction. For example, referring to FIG. 4 , the multi-pixel MPX may correspond to the first pixel group PG1, and the second photoelectric conversion element PD2, the fourth photoelectric conversion element PD4, the sixth photoelectric conversion element PD6, and the eighth photoelectric conversion element PD8 may correspond to the pixels G42 and G43 corresponding to high light transmittance located in the right region of the fifth microlens ML5 and the pixels G22 and G12 corresponding to high light transmittance located in the right region of the first microlens ML1, respectively. For example, the image signal processor 200 may generate a left-right phase difference image based on the left phase difference image and the right phase difference image and calculate the phase difference of the image based on the disparity of the left-right phase difference image.

[0128] According to one embodiment, during the second phase reset period 2PRS, the multi-pixel MPX may remove photocharges remaining in the second photoelectric conversion element PD2, the fourth photoelectric conversion element PD4, the sixth photoelectric conversion element PD6, the eighth photoelectric conversion element PD8, and the multi-pixel MPX, and reset the floating diffusion region FD to the power supply voltage VDD. For example, during the second phase readout period 2PRO, the second phase reset period 2PRS may correspond to the period from when the reset control signal RG transitions from a logic low level (L) to a logic high level (H) to when the reset control signal RG transitions from a logic high level (H) to a logic low level (L).

[0129] According to one embodiment, during the second-phase LCG reset signal section 2PLR, the multi-pixel MPX may output a second-phase LCG reset signal, which is a pixel signal when the second, fourth, sixth, eighth photoelectric conversion elements PD2, PD4, PD6, and PD8 photoelectric conversion elements, and the floating diffusion region FD are in a reset state. At this time, because the DCG control signal DCG is at a logic high level (H), the capacitance of the floating diffusion region FD may be increased by the capacitor C. For example, during the second-phase readout section 2PRO, the second-phase LCG reset signal section 2PLR ​​may correspond to the period from when the reset control signal RG transitions from a logic high level (H) to a logic low level (L) to when the DCG control signal DCG transitions from a logic high level (H) to a logic low level (L). For example, the second-phase LCG reset signal section 2PLR ​​may be a section in which, in the reset state, an electrical signal corresponding to the photocharges accumulated in the floating diffusion region FD, whose capacitance has increased, is output as the second-phase LCG reset signal.

[0130] According to one embodiment, during the second-phase HCG reset signal section 2PHR, the multi-pixel MPX may output a second-phase HCG reset signal, which is a pixel signal when the second, fourth, sixth, eighth photoelectric conversion elements PD2, PD4, PD6, PD8, and floating diffusion region FD are in a reset state. Since the DCG control signal DCG is at a logic low level (L), the capacitance of the floating diffusion region FD may be reduced compared to when the DCG control signal DCG is at a logic high level (H). For example, during the second-phase readout section 2PRO, the second-phase HCG reset signal section 2PHR may correspond to the period from when the DCG control signal DCG transitions from a logic high level (H) to a logic low level (L) to when the second, fourth, sixth, TG6, and eighth transfer signals TG8 transition from a logic low level (L). For example, the second phase HCG reset signal section 2PHR may be a section in which, in the reset state, an electrical signal corresponding to the photocharges accumulated in the floating diffusion region FD whose capacitance has decreased is output as the second phase HCG reset signal.

[0131] According to an embodiment, during the second-phase HCG pixel signal period 2PHS, the multi-pixel MPX generates electrical signals corresponding to the photocharges generated by the second, fourth, sixth, and eighth photoelectric conversion elements PD2, PD4, PD6, and PD8, and outputs the electrical signals as second-phase HCG pixel signals. Here, because the DCG control signal DCG is at a logic low level (L), the capacitance of the floating diffusion region FD may be reduced by the capacitance of the capacitor C compared to when the DCG control signal DCG is at a logic high level (H). For example, during the second-phase readout period 2PRO, the second-phase HCG pixel signal period 2PHS may be the period from when the second, fourth, sixth, and eighth transfer signals TG2, TG4, TG6, and TG8 transition from a logic high level (H) to a logic low level (L) until the DCG control signal DCG transitions from a logic low level (L) to a logic high level (H). For example, the second-phase HCG pixel signal section 2PHS may be a section in which an electrical signal corresponding to photocharges accumulated in the floating diffusion region FD, whose capacitance has decreased, is output as the second-phase HCG pixel signal. In this case, the photocharges accumulated in the floating diffusion region FD may correspond to photocharges transferred to the floating diffusion region FD from the time when the second transfer signal TG2, the fourth transfer signal TG4, the sixth transfer signal TG6, and the eighth transfer signal TG8 transition from a logic low level (L) to a logic high level (H) to the time when the second transfer signal TG2, the fourth transfer signal TG4, the sixth transfer signal TG6, and the eighth transfer signal TG8 transition from a logic high level (H) to a logic low level (L).

[0132] According to an embodiment, during the second-phase LCG pixel signal period 2PLS, the multi-pixel MPX may generate an electrical signal corresponding to the photocharges generated by the second, fourth, sixth, and eighth photoelectric conversion elements PD2, PD4, PD6, and PD8, and output the electrical signal as the second-phase LCG pixel signal. At this time, since the DCG control signal DCG is at a logic high level (H), the capacitance of the floating diffusion region FD may be increased by the capacitor C. For example, during the second-phase readout period 2PRO, the second-phase LCG pixel signal period 2PLS may correspond to the period from when the DCG control signal DCG transitions from a logic low level (L) to a logic high level (H) to when the reset control signal RG transitions from a logic low level (L) to a logic high level (H). For example, the second-phase LCG pixel signal period 2PLS may be a period in which an electrical signal corresponding to the photocharges accumulated in the floating diffusion region FD, whose capacitance has increased, is output as the second-phase LCG pixel signal. At this time, the photocharges accumulated in the floating diffusion region FD may correspond to the photocharges transferred to the floating diffusion region FD from the time when the second transfer signal TG2, the fourth transfer signal TG4, the sixth transfer signal TG6, and the eighth transfer signal TG8 transition from a logic low level (L) to a logic high level (H) to the time when the second transfer signal TG2, the fourth transfer signal TG4, the sixth transfer signal TG6, and the eighth transfer signal TG8 transition from a logic high level (H) to a logic low level (L).

[0133] According to one embodiment, the second-phase LCG reset signal and the second-phase LCG pixel signal generated during the second-phase readout period 2PRO may be converted into a digital value of the second-phase LCG signal, which is a pixel signal corresponding to the second-phase readout period 2PRO, via the correlated double sampler 130 and the ADC 140. As an example, the second-phase HCG reset signal and the second-phase HCG pixel signal generated during the second-phase readout period 2PRO may be converted into a digital value of the second-phase HCG signal, which is a pixel signal corresponding to the second-phase readout period 2PRO, via the correlated double sampler 130 and the ADC 140.

[0134] According to one embodiment, in the second-phase readout period 2PRO, photocharges accumulated in the floating diffusion region FD generate a voltage change in the floating diffusion region FD, which may be converted into an electrical signal by the source follower transistor SF. In this case, the degree of the voltage change in the floating diffusion region FD may be determined by the capacitance of the floating diffusion region FD. For the same amount of photocharges, the smaller the capacitance of the floating diffusion region FD, the larger the voltage change in the floating diffusion region FD, and the larger the capacitance of the floating diffusion region FD, the smaller the voltage change in the floating diffusion region FD. That is, when the same amount of photocharges is transmitted from the second photoelectric conversion element PD2, the fourth photoelectric conversion element PD4, the sixth photoelectric conversion element PD6, and the eighth photoelectric conversion element PD8 to the floating diffusion region FD, the magnitude of the second-phase HCG signal when the DCG control signal is at a logic low level (L) may be greater than the magnitude of the second-phase LCG signal when the DCG control signal is at a logic high level (H).

[0135] According to one embodiment, when the DCG control signal is at a logic high level (H), the magnitude of the second-phase LCG signal increases at a relatively low slope in response to an increase in photocharge, and when the DCG control signal is at a logic low level (L), the magnitude of the second-phase HCG signal increases at a relatively high slope in response to an increase in photocharge. For example, referring also to FIG. 2, the magnitude of the second-phase LCG signal and the magnitude of the second-phase HCG signal are converted into image data IDATA, so that the response of the second-phase LCG signal follows the response of the low-sensitivity pixel shown in FIG. 2, and the response of the second-phase HCG signal follows the response of the high-sensitivity pixel shown in FIG. 2. For example, according to an image sensing device 100 according to another embodiment of the present invention, both low-sensitivity pixels and high-sensitivity pixels can be implemented within a single pixel array 110, thereby generating an HDR image from a single image.

[0136] Since the pixel array 110 is driven row by row by the row driver 120, a pixel including the first photoelectric conversion element PD1 (e.g., a first pixel) and pixels including the second to eighth photoelectric conversion elements PD2 to PD8 (e.g., one or more second pixels) can receive the same reset signal RG and selection control signal SEL.

[0137] According to an embodiment, among the pixels included in the multi-pixel MPX, a pixel including the first photoelectric conversion element PD1 (e.g., a first pixel) and pixels including the second to eighth photoelectric conversion elements PD2 to PD8 (e.g., one or more second pixels) may distinguish the time points at which photocharges generated from each pixel are transferred to the floating diffusion region FD. For example, the multi-pixel MPX may receive a first transfer signal TG1 and second to eighth transfer signals TG2 to TG8 that are different from each other.

[0138] According to an embodiment, the HDR controller 300 may control the timing controller 170 using a control signal. In this case, the timing controller 170 may distinguish the time to transmit the first transfer signal TG1 at a logic high level (H) to the multi-pixel MPX, the time to transmit the third, fifth, and seventh transfer signals TG3, TG5, and TG7 at a logic high level (H) to the multi-pixel MPX, and the time to transmit the second, fourth, sixth, and eighth transfer signals TG2, TG4, TG6, and TG8 at a logic high level (H) to the multi-pixel MPX. According to an embodiment, the imaging device 10 according to the present disclosure may generate a phase difference image based on a third phase readout period and a fourth phase readout period. For example, the third phase may correspond to a lower phase, and the fourth phase may correspond to an upper phase. 4, for example, the multi-pixel MPX corresponds to the first pixel group PG1, and the third photoelectric conversion element PD3, the fourth photoelectric conversion element PD4, the seventh photoelectric conversion element PD7, and the eighth photoelectric conversion element PD8 may correspond to the pixels G31 and G32 located in the upper region of the fifth microlens ML5 and corresponding to high light transmittance, respectively, and the pixels G11 and G12 located in the upper region of the first microlens ML1 and corresponding to high light transmittance, respectively. Also, the second photoelectric conversion element PD2, the fifth photoelectric conversion element PD5, and the sixth photoelectric conversion element PD6 may correspond to the pixel G42 located in the lower region of the fifth microlens ML5 and corresponding to high light transmittance, respectively, and the pixels G21 and G22 located in the lower region of the first microlens ML1 and corresponding to high light transmittance, respectively.

[0139] According to one embodiment, the operations of the third and fourth phase readout periods can be understood to correspond to the operations of the first and second phase readout periods 1PRO and 2PRO in FIG. 6 . For example, the second transfer signal TG2, the fifth transfer signal TG5, and the sixth transfer signal TG6 in the third phase readout period can be understood to perform the same operations as the third transfer signal TG3, the fifth transfer signal TG5, and the seventh transfer signal TG7 in the first phase readout period 1PRO. For example, the third transfer signal TG3, the fourth transfer signal TG4, the seventh transfer signal TG7, and the eighth transfer signal TG8 in the fourth phase readout period can be understood to perform the same operations as the second transfer signal TG2, the fourth transfer signal TG4, the sixth transfer signal TG6, and the eighth transfer signal TG8 in the second phase readout period 2PRO. Duplicate descriptions of the remaining signals (e.g., RG, DG, DCG, TG1, and SPG) will be omitted.

[0140] According to one embodiment, the first phase readout section 1PRO may correspond to a section for generating pixel signals for generating a phase difference image in a first direction. For example, the first direction may correspond to the left direction. For example, referring to FIG. 4 , the multi-pixel MPX may correspond to the first pixel group PG1, and the third photoelectric conversion element PD3, the fifth photoelectric conversion element PD5, and the seventh photoelectric conversion element PD7 may correspond to the pixel G31 located in the left region of the fifth microlens ML5 and corresponding to high light transmittance, and the pixels G21 and G11 located in the left region of the first microlens ML1 and corresponding to high transmittance, respectively. For example, the image signal processor 200 may generate a left-right phase difference image based on the left phase difference image and the right phase difference image and calculate a phase difference based on the disparity of the left-right phase difference image.

[0141] According to an embodiment, the multi-pixel MPX may correspond to a section that generates pixel signals for generating left / right or top / bottom phase-contrast images. For example, referring also to FIG. 4, the multi-pixel MPX may correspond to a first pixel group PG1. For example, the multi-pixel MPX may generate a left phase-contrast image based on pixels G11, G21, G31, and G41 located in the left region, and generate a right phase-contrast image based on pixels G12, G22, G32, and G42 located in the right region.

[0142] According to an embodiment, the image signal processor 200 may generate a left-right phase difference image based on a left phase difference image and a right phase difference image. Alternatively, the image signal processor 200 may generate a top-bottom phase difference image based on an top-bottom phase difference image and a bottom-bottom phase difference image. For example, the image signal processor 200 may calculate a phase difference based on the disparity of the left-right phase difference image or the top-bottom phase difference image. For example, the image signal processor 200 may correct pixel data of the low-sensitivity pixel G41 corresponding to the high-sensitivity pixels G11, G21, G31, and G41.

[0143] FIG. 7 is a diagram for explaining the operation of the image composition unit according to an embodiment of the present disclosure. 1 and 7, the image combiner 320 of the image signal processor 200 may generate an HDR image by combining at least two or more images having different sensitivities. For example, the image combiner 320 may perform an HDR fusion operation in which the slope of an output value according to the light intensity of a reduced-level pixel and the slope of an output value according to the light intensity of a high-sensitivity pixel are matched. For example, the slopes of the output value according to the light intensity of a reduced-level pixel and the slopes of the output value according to the light intensity of a high-sensitivity pixel may be different. For example, referring also to FIG. 2, for the same light intensity, a pixel signal generated by a high-sensitivity pixel may have a high output value, and a pixel signal generated by a reduced-level pixel may have a low output value.

[0144] According to an embodiment, the image synthesis unit 320 may match the ratio of output values ​​according to the light intensity of low-sensitivity pixels to the ratio of output values ​​according to the light intensity of high-sensitivity pixels in order to synthesize at least two or more images having different sensitivities to generate an HDR image, because the HDR image must be synthesized into a single image whose brightness increases steadily as the light intensity increases.

[0145] According to one embodiment, when a pixel signal is output based on one photoelectric conversion element receiving incident light when the DCG capacitor is turned off, the output value of the pixel signal according to the light intensity may exhibit values ​​such as a first curve 501. In this case, the range of light intensity shown in the image corresponding to the first curve 501 may correspond to BR1.

[0146] According to an embodiment, when the DCG transistor DCX is turned on and outputs a pixel signal based on one photoelectric conversion element receiving incident light, the output value of the pixel signal according to the light intensity may exhibit a value such as that of the second curve 511. As an example, the image synthesis unit 320 may adjust the slope of the second curve 511 to convert the output value of the pixel signal according to the light intensity to exhibit a value such as that of the third curve 513. In this case, the range of light intensity represented in the HDR image generated by the image synthesis unit 320 synthesizing the image corresponding to the first curve 501 and the image corresponding to the third curve 513 may correspond to BR2. As an example, the imaging device 10 may obtain an image corresponding to the second curve 511 by adjusting the analog gain of the ADC 140.

[0147] According to an embodiment, when a pixel signal is output based on one low-transmittance photoelectric conversion element (e.g., PD1) receiving low-illumination incident light, the output value of the pixel signal according to the light intensity may exhibit values ​​such as a fourth curve 521. As an example, the image synthesis unit 320 may adjust the slope of the fourth curve 521 to convert the output value of the pixel signal according to the light intensity to exhibit values ​​such as a fifth curve 523. In this case, the range of light intensity represented by the HDR image generated by the image synthesis unit 320 by synthesizing the image corresponding to the first curve 501, the image corresponding to the third curve 513, and the image corresponding to the fifth curve 523 may correspond to BR3. As an example, the imaging device 10 may obtain an image corresponding to the third curve 521 by summing photoelectric charges generated by a plurality of photoelectric conversion elements (e.g., PD2 to PD8) corresponding to high light transmittances to output one pixel signal and / or by using a capacitor C to store overflow charges of a photoelectric conversion element (e.g., PD1) corresponding to low light transmittance.

[0148] FIG. 8 is a block diagram illustrating an example of a computing device that corresponds to the image processing device of FIG. Referring to FIG. 8, a computing device 800 may represent one embodiment of a hardware configuration for performing the operations of the image signal processor 200 of FIG.

[0149] The computing device 800 may be mounted on a chip separate from the chip on which the image sensing device is mounted. According to one embodiment, the chip on which the image sensing device is mounted and the chip on which the computing device 800 is mounted may be implemented in a single package, for example, a multi-chip package (MCP), although the scope of the present invention is not limited thereto.

[0150] Furthermore, the internal configurations or arrangements of the computing device 800 and the image sensing device may vary depending on the embodiment. For example, at least a portion of the configuration of the image sensing device may be included in the computing device 800. Alternatively, at least a portion of the configuration of the computing device 800 may be included in the image sensing device. In this case, at least a portion of the configuration of the computing device 800 may be mounted on a chip on which the image sensing device is mounted.

[0151] Computing device 800 may include a processor 810 , a memory 820 , an input / output interface 830 , and a communication interface 840 .

[0152] The processor 810 can process data and / or instructions necessary to perform the operations of the components 110 and 120 of the image signal processor 200 described in Figure 1. In other words, the processor 810 may refer to the image signal processor 200 itself, although the scope of the present invention is not limited thereto.

[0153] The memory 820 can store data and / or instructions necessary to perform the operations of the configuration 300 of the image signal processor 200 and can be accessed by the processor 810. For example, the memory 820 can be implemented with volatile memory (e.g., Dynamic Random Access Memory (DRAM), Static Random Access Memory (SRAM), etc.) or non-volatile memory (e.g., Programmable Read Only Memory (PROM), Erasable PROM (EPROM), Electrically Erasable PROM (EEPROM), flash memory, etc.).

[0154] In other words, a computer program for performing the operations of the image signal processor 200 disclosed in this document can be recorded in memory 820 and executed and processed by the processor 810 to realize the operations of the image signal processor 200.

[0155] The input / output interface 830 may provide an interface that connects an external input device (e.g., a keyboard, a mouse, a touch panel, etc.) and / or an external output device (e.g., a display) to the processor 810, enabling data to be transmitted and received.

[0156] The communication interface 840 is configured to be able to send and receive various data to and from external devices (for example, an application processor, an external memory, etc.), and may be a device that can support wired or wireless communication.

Claims

1. a split transistor for separating a first time point for generating first pixel data for a first pixel from a second time point for generating second pixel data for one or more second pixels; a first photoelectric conversion element included in the first pixel, the first photoelectric conversion element being connected to a first electrode of the split transistor via a first transfer transistor; a second photoelectric conversion element included in the second pixel, the second photoelectric conversion element being connected to the second electrode of the split transistor via a second transfer transistor; a floating diffusion region that accumulates photocharges generated by the first photoelectric conversion element or the second photoelectric conversion element; a capacitor for adjusting the capacitance of the floating diffusion region; a DCG (Dual Conversion Gain) transistor connected between the capacitor and the floating diffusion region to control capacitance of the floating diffusion region; 12. An imaging device comprising:

2. generating the pixel data based on photocharges generated by the first photoelectric conversion element when the split transistor is turned off; The imaging device of claim 1 , wherein when the split transistor is turned on, the pixel data is generated based on photocharges generated by the second photoelectric conversion element.

3. the floating diffusion region is connected to the first electrode; The imaging device of claim 1 , wherein the first pixel and the one or more second pixels share the split transistor, the floating diffusion region, the capacitor, and the DCG transistor.

4. the first pixel includes a light blocking structure that blocks at least a portion of incident light; The imaging device of claim 1 , wherein the light blocking structure includes a half shield structure, a neutral-density (ND) filter, or a gray filter.

5. The imaging device of claim 1 , further comprising a reset transistor coupled to the DCG transistor to reset a voltage level of the floating diffusion region.

6. The imaging device of claim 1 , further comprising a drain transistor connected to the second electrode and configured to drain overflow charges of the second photoelectric conversion element.

7. a signal control unit that generates a control signal; The imaging device of claim 6 , wherein at least one of the split transistor, the DCG transistor, and the drain transistor is turned on or off based on the control signal.

8. 2. The imaging device of claim 1, further comprising a read control unit including a source follower transistor that amplifies a change in the electrical potential of the floating diffusion region, and a selection transistor that outputs an electrical signal transmitted from the source follower transistor as a pixel signal.

9. The imaging device of claim 1 , wherein the first pixel and the one or more second pixels correspond to color filters of the same color and share a first microlens.

10. comparing a first pixel signal generated based on the first pixel with a ramp signal, and generating first image data according to the comparison result; 2. The imaging device of claim 1, further comprising a first ADC (Analog-Digital Converter) that compares second pixel signals generated based on the one or more second pixels with the ramp signal and generates second image data according to a comparison result.

11. further comprising a third pixel and one or more fourth pixels; comparing a third pixel signal generated based on the third pixel with the ramp signal, and generating third image data according to the comparison result; 11. The imaging device of claim 10, further comprising a second ADC that compares a fourth pixel signal generated based on each of the one or more fourth pixels with the ramp signal and generates fourth image data according to a comparison result.

12. 12. The imaging device of claim 11, further comprising an image signal processor that generates a phase difference image using the first image data generated based on the first pixels and the third image data generated based on the third pixels.

13. The imaging device of claim 10 , further comprising an image signal processor that generates a phase difference image using the second image data generated based on each of the one or more second pixels.

14. a multi-pixel including: a split transistor for separating a first time point at which first pixel data of a first pixel is generated from a second time point at which second pixel data of one or more second pixels is generated; a first photoelectric conversion element included in the first pixel and connected to a first electrode of the split transistor via a first transfer transistor; a second photoelectric conversion element included in the second pixel and connected to a second electrode of the split transistor via a second transfer transistor; a floating diffusion region for accumulating photocharges generated by the first photoelectric conversion element or the second photoelectric conversion element; a capacitor for adjusting capacitance of the floating diffusion region; and a DCG transistor connected between the capacitor and the floating diffusion region and for controlling capacitance of the floating diffusion region; a signal control unit that generates a control signal to control each of the split transistor and the DCG transistor; an image synthesis unit that synthesizes first image data generated based on the first pixels and second image data generated based on the one or more second pixels to generate a High Dynamic Range (HDR) image; 12. An imaging device comprising:

15. 15. The imaging device of claim 14, wherein the first photoelectric conversion element corresponds to a lower light transmittance than the second photoelectric conversion element.

16. 15. The imaging device of claim 14, wherein the signal control unit causes the split transistor to be turned off in a first illumination environment and to be turned on in a second illumination environment corresponding to an illumination intensity lower than the first illumination environment.

17. 15. The imaging device of claim 14, wherein the signal control unit turns on the DCG transistor so that the capacitance is greater than a reference capacitance, and turns off the DCG transistor so that the capacitance is smaller than the reference capacitance.

18. an overflow detection unit that generates a detection signal when the photocharge generated by the second photoelectric conversion element is equal to or greater than a threshold; a drain transistor connected to the second electrode and configured to drain the photocharges generated by the second photoelectric conversion element that are equal to or greater than the threshold, The imaging device of claim 14 , wherein the signal control unit controls the drain transistor to be turned on based on the detection signal generated by the overflow detection unit.

19. generating first pixel data based on first photocharges generated by the first photoelectric conversion element when a split transistor separating the first photoelectric conversion element from one or more second photoelectric conversion elements is turned off and a DCG transistor is turned on; adjusting a capacitance of a floating diffusion region that accumulates second photocharges generated by the one or more second photoelectric conversion elements to a first capacitance by turning on the split transistor and the DCG transistor; generating second pixel data corresponding to a first conversion gain (Low Conversion Gain) based on the second photocharges generated by the one or more second photoelectric conversion elements; adjusting the capacitance to a second capacitance by turning on the split transistor and turning off the DCG transistor; generating third pixel data corresponding to a second conversion gain based on the second photocharges generated by the one or more second photoelectric conversion elements; An image sensing method comprising:

20. The image sensing method of claim 19, further comprising generating an HDR image based on the first to third pixel data.

Images