Method and apparatus for facilitating pipelined read-modify-write support in a cache

Abstract

An apparatus, method, and system for facilitating fully pipelined read-modify-write support in a level one data cache using a store queue and data forwarding.SOLUTION: The level one data cache (110) includes a first storage (214), a second storage (218), and a store queue (212, 216) coupled to the first storage and the second storage. The store queue receives a first memory operation identifying a first set of data, processes the first memory operation to store the first set of data in at least one of the first storage and the second storage, receives a second memory operation, and feeds back the first set of data for use in the second memory operation prior to storing the first set of data in at least one of the first storage and the second storage.SELECTED DRAWING: Figure 2

Description

[Technical Field]

[0001] This description relates generally to computer architecture, and more particularly to a method and apparatus for facilitating fully pipelined read-modify-write support in a level 1 data cache using store queues and data forwarding. [Background technology]

[0002] A computing system includes one or more processing cores for executing instructions by accessing data stored in memory. However, the amount of time it takes for a processing core to access data from memory can be significant. Therefore, most computing systems include a cache that stores a significant amount of data from memory (e.g., often smaller than the total amount of data in memory) that is likely to be accessed by the processing core in the future. Thus, when the processing core calls for data, the cache can provide the data to the processing core faster than the processing core can retrieve it from memory, thereby improving the speed and efficiency of the computing system. [Brief explanation of the drawings]

[0003] [Figure 1] 1 is an exemplary computing system described in connection with the examples described herein.

[0004] [Figure 2] FIG. 2 is a block diagram of an example level 1 cache of the example computing system of FIG. 1.

[0005] [Figure 3A] 2 illustrates an example circuit implementation of a level 1 cache of the example computing system of FIG. 1. [Figure 3B] 2 illustrates an example circuit implementation of a level 1 cache of the example computing system of FIG. 1. [Figure 3C] 2 illustrates an example circuit implementation of a level 1 cache of the example computing system of FIG. 1. [Figure 3D] 2 illustrates an example circuit implementation of a level 1 cache of the example computing system of FIG. 1.

[0006] [Figure 4A] 3A-3D is an exemplary circuit implementation of the main cache store queue.

[0007] [Figure 4B] 3A-4A illustrate an example circuit implementation of example data transfer logic implemented in connection with the main cache store queue of FIGS.

[0008] [Figure 4C] 10 is an additional exemplary circuit implementation of a main cache store queue and / or a victim cache store queue.

[0009] [Figure 4D] 4B is an example hardware implementation of the merging circuit of FIG. 4A.

[0010] [Figure 5] 3A-3D illustrate an example victim cache-based section of the level 1 cache of FIGS.

[0011] [Figure 6] 10 illustrates an example first table and an example second table for implementing the example replacement policy components of FIGS. 3A-3D and 5.

[0012] [Figure 7A] 1 illustrates an example encapsulated data cache system including a victim cache store queue and victim storage.

[0013] [Figure 7B]1 illustrates another example encapsulated data cache system including a main cache store queue and main storage.

[0014] [Figure 7C] 1 illustrates an exemplary victim cache bank structure.

[0015] [Figure 7D] 1 illustrates an exemplary main cache bank structure.

[0016] [Figure 7E] 1 illustrates an exemplary unified cache bank structure.

[0017] [Figure 8A] 1 illustrates a schematic diagram of an exemplary implementation of a victim cache tag random access memory.

[0018] [Figure 8B] 8B illustrates another schematic diagram of an example implementation of the example victim cache tag random access memory of FIG. 8A.

[0019] [Figure 9A] 1 illustrates an example command processing workflow. [Figure 9B] 1 illustrates an example command processing workflow.

[0020] [Figure 10A-1] 1 illustrates an exemplary data cache system. [Figure 10A-2] 1 illustrates an exemplary data cache system.

[0021] [Figure 10B-1] 1 illustrates a second exemplary data cache system. [Figure 10B-2] 1 illustrates a second exemplary data cache system.

[0022] [Figure 11A]3A-3D is an exemplary circuit implementation of the victim cache store queue of FIG.

[0023] [Figure 11B-1] 1 is an example circuit implementation of an example unified cache store queue. [Figure 11B-2] 1 is an example circuit implementation of an example unified cache store queue.

[0024] [Figure 12] 1-3D; 2-4 are flow charts depicting machine-readable instructions that may be executed to implement the level 1 cache of FIGS. [Figure 13] 1-3D; 2-4 are flow charts depicting machine-readable instructions that may be executed to implement the level 1 cache of FIGS. [Figure 14] 1-3D; 2-4 are flow charts depicting machine-readable instructions that may be executed to implement the level 1 cache of FIGS. [Figure 15] 1-3D; 2-4 are flow charts depicting machine-readable instructions that may be executed to implement the level 1 cache of FIGS. [Figure 16] 1-3D; 2-4 are flow charts depicting machine-readable instructions that may be executed to implement the level 1 cache of FIGS. [Figure 17] 1-3D; 2-4 are flow charts depicting machine-readable instructions that may be executed to implement the level 1 cache of FIGS. [Figure 18A] 1-3D; 2-4 are flow charts depicting machine-readable instructions that may be executed to implement the level 1 cache of FIGS. [Figure 18B] 1-3D; 2-4 are flow charts depicting machine-readable instructions that may be executed to implement the level 1 cache of FIGS. [Figure 19] 1-3D; 2-4 are flow charts depicting machine-readable instructions that may be executed to implement the level 1 cache of FIGS. [Figure 20] 1-3D; 2-4 are flow charts depicting machine-readable instructions that may be executed to implement the level 1 cache of FIGS. [Figure 21] 1-3D; 2-4 are flow charts depicting machine-readable instructions that may be executed to implement the level 1 cache of FIGS. [Figure 22] 1-3D; 2-4 are flow charts depicting machine-readable instructions that may be executed to implement the level 1 cache of FIGS. [Figure 23] 1-3D; 2-4 are flow charts depicting machine-readable instructions that may be executed to implement the level 1 cache of FIGS. [Figure 24] 1-3D; 2-4 are flow charts depicting machine-readable instructions that may be executed to implement the level 1 cache of FIGS. [Figure 25] 1-3D; 2-4 are flow charts depicting machine-readable instructions that may be executed to implement the level 1 cache of FIGS. [Figure 26] 1-3D; 2-4 are flow charts depicting machine-readable instructions that may be executed to implement the level 1 cache of FIGS. [Figure 27] 1-3D; 2-4 are flow charts depicting machine-readable instructions that may be executed to implement the level 1 cache of FIGS. [Figure 28] 1-3D; 2-4 are flow charts depicting machine-readable instructions that may be executed to implement the level 1 cache of FIGS. [Figure 29A] 1-3D; 2-4 are flow charts depicting machine-readable instructions that may be executed to implement the level 1 cache of FIGS. [Figure 29B-1] 1-3D; 2-4 are flow charts depicting machine-readable instructions that may be executed to implement the level 1 cache of FIGS. [Figure 29B-2] 1-3D; 2-4 are flow charts depicting machine-readable instructions that may be executed to implement the level 1 cache of FIGS. [Figure 30] 1-3D; 2-4 are flow charts depicting machine-readable instructions that may be executed to implement the level 1 cache of FIGS. [Figure 31] 1-3D; 2-4 are flow charts depicting machine-readable instructions that may be executed to implement the level 1 cache of FIGS. [Figure 32]1-3D; 2-4 are flow charts depicting machine-readable instructions that may be executed to implement the level 1 cache of FIGS. [Figure 33] 1-3D; 2-4 are flow charts depicting machine-readable instructions that may be executed to implement the level 1 cache of FIGS.

[0025] [Figure 34] FIG. 3B is a block diagram of an example processing platform configured to execute the instructions of FIGS. 3A-3D to implement the level 1 cache of FIGS. 1-3D. DETAILED DESCRIPTION OF THE INVENTION

[0026] The drawings are not to scale. Instead, the thickness of layers or regions in the drawings may be exaggerated. Generally, the same reference numbers are used to refer to the same or similar parts throughout the drawings and accompanying description. As used in this patent, describing any part (e.g., a layer, film, area, region, or plate) as being on another part in any manner (e.g., disposed on, located on, or formed on another part, etc.) indicates that the referenced part is in contact with the other part, or that the referenced part is above the other part with one or more intermediate parts disposed therebetween. Connection references (e.g., attached, coupled, connected, and joined) should be interpreted broadly and may include intermediate members between and relative movement between a group of elements, unless otherwise indicated. Thus, connection references do not necessarily imply that two elements are directly connected and in a fixed relationship to each other. Describing any part as "in contact" with another part means that there are no intermediate parts between the two parts. Although the figures show layers and regions with clear lines and boundaries, some or all of these lines and / or boundaries may be idealized. In reality, boundaries and / or lines may be non-observable, blended, and / or irregular.

[0027] Various forms of the term "couple" are used throughout this specification. These terms may encompass connection, communication, or a signal path that enables a functional relationship consistent with the description herein. For example, if device A generates a signal to control device B to perform an action, in a first example device, A is coupled to device B by a direct connection, or in a second example device, A is coupled to device B through an intervening component C such that device B is controlled by device A via a control signal generated by device A, where intervening component C does not change the functional relationship between device A and device B.

[0028] Consistent with this description, the term "configured to" describes the structural and functional characteristics of one or more tangible, non-transitory components. For example, a device "configured to" perform a certain function means that the device has a particular configuration designed or dedicated to performing the function. A device is "configured to" perform a particular function if such device includes tangible, non-transitory components that can be enabled, activated, or powered to perform the function. While the term "configured to" can encompass configurability, the term is not limited to such a narrow definition. Thus, when used to describe a device, the term "configured to" does not require that the described device be configurable at any given time.

[0029] Also, the term "example" is used herein to mean serving as an example, illustration, or the like, and is not necessarily advantageous. Furthermore, while the present description has been shown and described with respect to one or more implementations, equivalent modifications and variations will become apparent based on this description and the accompanying drawings. All such modifications and variations are fully supported by this description and are limited only by the scope of the following claims. In particular, with respect to various functions performed by the above-described components (e.g., elements, resources, etc.), the terms used to describe such components correspond, unless otherwise indicated, to any component that performs the specified function of the described component (e.g., is functionally equivalent), even if it is not structurally equivalent to the described structure. Furthermore, while certain features of the description are described with respect to only one of several implementations, such features can be combined with one or more other features of other implementations, as may be desirable and advantageous for any given or particular application.

[0030] While this specification contains many details, these should not be construed as limitations on the scope of what may be claimed, but rather as descriptions of features that may be unique to particular embodiments. Some features that are described herein in the context of a separate embodiment may also be implemented in combination in a single embodiment. Conversely, various features that are described in the context of a single embodiment may also be implemented in multiple embodiments separately or in any suitable subcombination. Also, while features may be described above as acting in a certain combination and may initially be claimed as such, one or more features from a claimed combination may, in some cases, be omitted from the combination, and a claimed combination may be directed to a subcombination or variations of the subcombination.

[0031] Similarly, although operations are shown in the figures in a particular order of illustration, this does not require that such operations be performed in the particular order of illustration or sequential order shown, or that all of the operations shown be performed, to achieve desirable results, unless such order is recited in one or more claims. In some situations, multitasking and parallel processing may be advantageous. Also, the separation of various system components in the above-described embodiments does not require such separation in all embodiments.

[0032] Descriptors such as "first," "second," and "third" are used herein to distinguish between multiple elements or components that may be referenced separately. Unless otherwise specified or understood based on the context of use, such descriptors do not imply any sense of priority, physical order or placement within a list, or temporal ordering, but are merely used as labels to refer to multiple elements or components separately to aid in understanding the examples being described. In some instances, the descriptor "first" may be used to refer to an element in the detailed description, while the same element may be referred to in the claims using a different descriptor, such as "second" or "third." In such cases, such descriptors are used merely to facilitate reference to the multiple elements or components.

[0033] A central processing unit (CPU) is an electronic circuit that executes instructions that make up a program or workload. A CPU may include one or more processor cores to execute instructions by accessing data from main memory (e.g., expanded memory). Because it takes time to access data from main memory, the one or more processor cores may retrieve data from memory and store it locally in a local memory (e.g., a data cache). The local memory is smaller and faster than the main memory. In this way, the processor cores can use and / or manipulate data locally rather than interfacing with the main memory. Storing data from expanded memory in a cache improves the speed and efficiency of a computing system because the latency for reading and / or writing data (e.g., the amount of time required to read and / or write data to / from memory) is lower when accessing the cache.

[0034] Some local memory devices (e.g., caches) include one or more victim caches. A victim cache is additional storage included in or connected to a cache. A victim cache improves (e.g., reduces) cache miss rates, particularly conflict misses, by storing data recently evicted from the corresponding cache. The addition of a victim cache can have a similar impact on cache performance. The benefits are most pronounced when a victim cache is added to a direct mapped cache, since direct mapped caches have a relatively high conflict miss rate.

[0035] Some examples described herein include improved data cache and victim cache architectures that reduce overall cache latency. In some alternative cache designs, the victim cache is at the end of the cache controller. When a line is evicted from the cache controller (e.g., removed to make room for additional data), rather than removing the data line and sending the evicted data line up to the next level cache (e.g., L2) to be stored, the victim cache holds the evicted data line (e.g., victim data) until there is a reason for it to be evicted due to capacity or other reasons. In such a system, when a subsequent miss occurs in the corresponding cache (e.g., L1 cache), the victim cache can service the miss and return the line to the corresponding cache and thereby to the requesting processor core, resulting in reduced latency for read misses. However, because some example systems include a victim cache in series with the main cache, the victim cache must wait for the main cache to determine that it does not have data corresponding to a memory operation (also referred to herein as a memory instruction, memory request, and / or memory transaction) from a CPU (e.g., a read operation, instruction, request, and / or transaction, a write operation, instruction, request, and / or transaction, a read-modify-write operation, instruction, request, and / or transaction, an atomic operation, instruction, and / or transaction, a histogram operation, instruction, request, and / or transaction, etc.) before the victim cache can determine if the memory address is stored in the victim cache. Examples described herein include cache systems that reduce latency (e.g., increase speed), reduce the number of cycles to perform write operations, atomic operations (e.g., manipulating data stored in a location to increment, decrement, swap with other data, etc.), and / or histogram operations (e.g., determining the total number of each value in a cache line), and / or increase the efficiency of a computing system that includes the cache.

[0036] 1 illustrates an exemplary computer system 100. The exemplary computing system 100 includes an exemplary CPU 102, exemplary processing cores 104a-104n, an exemplary expanded memory 106, and an exemplary data cache 108. The exemplary data cache 108 includes an exemplary level 1 (L1) cache 110, an exemplary level 2 (L2) cache 112, and an exemplary level 3 (L3) cache 114. Although the exemplary computing system 100 of FIG. 1 includes N processing cores and three levels of cache, the exemplary computing system 100 may include any number of processing cores and / or levels of cache. Additionally, one or more of the exemplary components of computing system 100 may be implemented on the same die and / or different dies within the same chip and / or different chips.

[0037] The example CPU 102 of FIG. 1 includes example processing cores 104a-104n. The processing cores 104a-104n may be integrated on the same die or on separate dies (e.g., connected via one or more interfaces). The CPU 102 connects to the example data cache 108 via one or more interfaces. For example, the example core 104a of the example CPU 102 may connect to the data cache 108 via a scalar interface (e.g., a 64-bit wide bidirectional interface and / or a unidirectional interface) and / or a vector interface (e.g., a 512-bit wide interface). The use of the scalar and vector interfaces may be based on interface utilization, data size, and / or other considerations. For example, a scalar read operation may be transmitted via the scalar data, while data corresponding to the scalar read may be transmitted via the vector interface. Also, if the other interface is busy, either the scalar interface, the vector interface, or both may be used. In some examples, CPU 102 may be connected to data cache 108 using a different number and / or different types of interfaces.

[0038] 1 access data from the example expanded memory 106 and / or the example data cache 108 to execute instructions stored in the example expanded memory 106 and / or the example data cache 108. The example cores 104a-104n may execute different processes simultaneously to expedite the execution of tasks (e.g., instructions) of the computing system 100. For example, the cores 104a-104n may execute instructions from an application workload by writing data to and / or reading data from the expanded memory 106 and / or the data cache 108. Because the data cache 108 contains several copies of the data stored in the example expanded memory 106, when one of the example cores 104a needs to access (e.g., read and / or write) data from the expanded memory 106, the example core 104a sends read and / or write instructions to the example data cache 108. As described below, if data cache 108 contains data corresponding to the instruction from core 104a (e.g., corresponding to a cache hit), data cache 108 fulfills the request and / or instruction from processing core 104a. If data cache 108 does not contain data corresponding to the instruction from core 104a (e.g., corresponding to a cache miss), data cache 108 interfaces with expanded memory 106 to fulfill the transaction from core 104a.

[0039] 1 is connected to the example data cache 108 via an interface (e.g., a 1024-bit wide extended memory interface). However, a different number and / or type of interfaces may additionally or alternatively be used. The example extended memory 106 stores all data that may be accessed for the computing system 100. The example extended memory 106 may be incorporated within the computing system 100 and / or may be memory that is external to the computing system 100 (e.g., off-chip memory). In some examples, the extended memory 108 interacts with a controller of a top-level cache (e.g., the example L3 cache 114), which interacts with a next-top-level cache (e.g., the example L2 cache 112), and so on. In such an example, CPU 102 sends a memory operation to exemplary L1 cache 110, and if the memory operation cannot be processed by L1 cache 110, L1 cache 110 sends the memory operation to L2 cache 112, and so on. In the example of Figure 1, if L3 cache 114 (e.g., the highest level cache) cannot perform the read or write transaction (e.g., because the memory address is not located in the local storage of L3 cache 114), L3 cache 114 interacts with expanded memory 106 to read or write the corresponding data to the memory address. Expanded memory 106 may be on-chip or off-chip memory (e.g., DDR), and the interface to the expanded memory may be 2N bits, where N depends on the type of expanded memory used. In some examples, there may be a prefetcher and / or preload mechanism in any of the data caches that can pull data from the exemplary expanded memory 106 prior to execution of an instruction that should be stored locally in the cache before the CPU 102 executes any instruction, and the memory 106 provides a copy of the data stored in the memory to the exemplary data cache 108.The data cache 108 may request additional information and / or instruct the expanded memory 106 to adjust the data stored in the expanded memory 106 based on instructions from the CPU 102, periodically, aperiodically, and / or based on a trigger.

[0040] The example data cache 108 of FIG. 1 stores blocks of data from the example expanded memory 106 (e.g., a cached subset of data stored in the expanded memory 106) to reduce the time required for the example CPU 102 to access the cached subset, thereby improving system performance. To achieve best performance, an attempt is made to ensure that the data in the data cache 108 corresponds to data that is most likely to be used by the CPU 102. The data cache 108 provides access to cached data when called by the CPU 102 during a cache hit (e.g., when the requested data is stored in the data cache 108). If the CPU 102 requests data that is not contained in the data cache 108 (e.g., a cache miss), the data cache 108 retrieves the corresponding data from the expanded memory 106. For example, if the CPU 102 sends a read operation corresponding to a particular address in the expanded memory 106, the data cache 108 determines whether the data corresponding to the particular address in the expanded memory 106 is cached in the data cache 108. If the data cache 108 determines that the data is cached, the data cache 108 provides the data to be read to the CPU 102. If the data cache 108 determines that the data is not cached, the data cache 108 obtains the data from the extended memory 106 and returns the data to the CPU 102. The example data cache 108 can also update the cached data based on a cache miss (e.g., to mitigate future cache misses). In the case of a write transaction from the CPU 102, the example data cache 108 can temporarily store the corresponding data before providing it to update the old data stored in the extended memory 106.

[0041] The example data cache 108 includes an example L1 cache 110, an example L2 cache 112, and an example L3 cache 114. The levels of cache may be based on speed and / or size. For example, the example L1 cache 110 is the fastest cache and smallest, followed by the L2 112 (e.g., slower but larger than the L1 110) and the L3 114 (e.g., slower but larger than the L2 112). Often, the most commonly used data is stored in the L1 110, followed by the L2 112 and the L3 114. Thus, when the CPU 102 calls an address to write or read, the instruction from the CPU 102 is sent first to the L1 cache 110, and if the corresponding data is not stored in the L1 cache 110, the instruction is sent to the L2 cache 112. If the corresponding data is not stored in the L2 cache 112, the instruction is sent to the L3 cache 114. If the corresponding data is not stored in the L3 cache 114 , the example data cache 108 accesses the data from the expanded memory 106 .

[0042] As explained further below, the example L1 cache 110 of FIG. 1 includes a main cache and a victim cache in parallel for executing instructions from the CPU 102. The victim cache stores victim data (e.g., data evicted from the main cache to make room for new data corresponding to other address locations in the expanded memory 106). Thus, when there is a cache miss at the L1 level, the main L1 cache evicts a first set of data (e.g., victim data) to make room for a second set of data corresponding to the transaction that caused the cache miss. The victim cache then stores the first set of data removed from the main cache to make room for the second set of data in the main cache.

[0043] Figure 2 is an example block diagram of the example L1 cache 110 of Figure 1. The example L1 cache 110 includes an example CPU interface 202, example tag RAM (random access memory) accesses 204, 206, example tag RAMs 208, 210, an example main cache store queue 212, example main storage 214 (also referred to as main cache storage or main cache), an example victim cache store queue 216, example victim storage 218 (also referred to as victim cache storage or victim cache), an example cache controller 220, an example main cache controller 222, an example victim cache controller 224, and an example L2 interface 228.

[0044] CPU interface 202 connects CPU 102 (e.g., cores 104a-104n of CPU 102) to components of L1 cache 110. CPU interface 202 is connected to tag RAM accesses 204, 206 and a cache controller 220. The example CPU interface 202 receives instructions from example cores 104a-104n of example CPU 102. The instructions may include read instructions, write instructions, read-modify-write instructions, atomic instructions, etc. When CPU interface 202 retrieves an instruction corresponding to particular data stored at a particular address, CPU interface 202 interfaces with cache controller 220 and main tag RAM access 204 to determine whether the corresponding data is stored in main storage 214 and / or victim storage 218 to perform the transaction. Additionally, for certain types of transactions (e.g., read transactions), the example CPU interface 202 returns the corresponding data to example CPU 102. Additionally, when CPU interface 202 retrieves an instruction corresponding to data at a particular address, main components (e.g., example main tag RAM access 204, example tag RAM 208, example main cache store queue 212, example main storage 214, and example main cache controller 222) and victim components (e.g., example tag RAM access 206, example tag RAM 210, example victim cache store queue 216, example victim storage 218, and example victim cache controller 224) operate in parallel (e.g., simultaneously) to determine whether data from the corresponding address is to be stored in main storage 214 and / or victim storage 218.

[0045] 1 is coupled to tag RAM 208 and cache controller 220. Victim tag RAM access 206 is coupled to tag RAM 210 and cache controller 220. Main tag RAM access 204 accesses tag RAM 208 to determine whether data from a memory address corresponding to an instruction from CPU 102 is present in main storage 214. Example victim tag RAM access 206 accesses tag RAM 210 to determine whether data from a memory address corresponding to an instruction from CPU 102 is present in victim storage 218 in parallel with main tag RAM access 204. In some examples, main tag RAM access 204 is implemented in tag RAM 208 and victim tag RAM access 206 is implemented in tag RAM 210. If the main tag RAM access 204 and / or the victim tag RAM access 206 determine that an address corresponding to an instruction from the CPU 102 is present in the respective tag RAMs 208, 210, the main tag RAM access 204 and / or the victim tag RAM access 206 transmits the result (e.g., the determination and / or any corresponding data) to the example cache controller 220.

[0046] In some instances, main storage is direct mapped. Thus, in such instances, a particular CPU memory address can only be stored in a particular location in main storage 214. Thus, the example tag RAM 208 can potentially have fixed memory addresses for CPU instructions. In a direct-mapped cache, a given address is stored in a particular location in tag RAM 208.

[0047] 2 is coupled to the example cache controller 220 and the example main storage 214. The example tag RAM 208 stores a table that records entries in the example main storage 214 that correspond to memory addresses in the expanded memory 106. In this manner, the example main tag RAM access 204 can review the table to determine whether data corresponding to an instruction from the CPU 102 is available in the main storage 214. The example tag RAM 210 is coupled to the example cache controller 220 and the example victim storage 218. The example tag RAM 210 stores a table that records entries in the example victim storage 218. In this manner, the example victim tag RAM access 206 can review the table to determine whether data corresponding to an instruction from the CPU 102 is available in the victim storage 218. When data in the main storage 214 is updated, the example tag RAM 208 can update the table to reflect any changes to the entries. For example, if main storage 214 removes a first set of data corresponding to a first memory address in expanded memory 106 and replaces it with a second set of data corresponding to a second memory address in expanded memory 106, the example tag RAM 208 may update the table so that the first set of data at the first memory address is no longer stored in main storage 214 and the second set of data at the second memory address is now stored in main storage 214. Similarly, if data from a first address location in victim storage 218 is changed to data from a second address location, the example tag RAM 210 may update the table to reflect any changes to the entries.

[0048] The example victim tag RAM 210 may be content-addressable memory. In some examples, the victim storage 218 is fully associative (e.g., any location in the victim storage 218 can be used to store data from any CPU address). Thus, when the example CPU 102 provides a memory address to the example L1 cache 110, the example victim tag RAM 210 compares the provided memory address with all entries in the tag RAM 210. If there is a match between the provided address and an entry stored in the tag RAM 210, the address of the corresponding location in the victim storage 218 is output by the tag RAM 210. This address is used to retrieve the data corresponding to the CPU instruction from the victim storage 218.

[0049] The example main cache store queue 212 of FIG. 2 is coupled to the example main storage 214 and the example cache controller 220. The example main cache store queue 212 is used when the CPU 104 issues store operations (e.g., write operations, atomic compare and swap, atomic operations, etc.). The example main cache store queue 212 can implement a read-modify-write function. The read-modify-write function includes storing data in local storage, which requires first reading an old version of the data being written that already exists in the main storage 214 for reasons including updating error correction code data. In this way, new bits included in the write portion of a read-modify-write transaction from the CPU 102 are buffered in the main cache store queue 212 while a read operation is performed to obtain a copy of the old data from the main storage 214. When the old data is available, only the new bits that the CPU 102 is overwriting are updated in the store queue buffer, and the updated (e.g., merged) data is written back to the main storage 214. For example, new bits that CPU 102 is overwriting (e.g., from CPU 102) from the write portion of a read-modify-write transaction that includes the corresponding memory address are buffered in main cache store queue 212 until the old data of the corresponding write (e.g., store) instruction is read from main storage 214. Once the new bits included in the write portion of the read-modify-write transaction are merged with the old data from main storage 214, the updated (e.g., merged) data is written back to main storage 214. The additional pipelining for store instructions provided by main cache store queue 212 allows continued execution of instructions from CPU 104 while a preceding store instruction is waiting for load data from main storage 214 to become available. In some examples, main storage 214 includes SRAM, as described further below in connection with Sections 5 and 16.An example main cache store queue 212 is further described below in connection with FIGS. 3A, 3B, and 4.

[0050] 2 is coupled to the example victim storage 218 and the example cache controller 220. The example victim cache store queue 216 buffers data to be stored in the example victim storage 218. For example, a victim value (e.g., from the cache controller 220) from a store instruction including a corresponding memory address and / or store data is buffered in the victim cache store queue 216 until the previous or old value of the corresponding store instruction is read from the victim storage 218. Once the stored bytes are merged with the previous / old data from the victim storage 218, the value is written back to the victim storage 218. Victim cache store queue 216 may process read, modify, and / or write operations from cache controller 220 sent in response to a retirement point being met (e.g., when one or more cache lines are removed from L1 cache 110 to L2 cache 112), although in other examples described herein, victim cache store queue 216 may process read, modify, and / or write operations from cache controller 220 sent directly from CPU 102. An example victim cache store queue 216 is described further below.

[0051] 2 is coupled to the example tag RAM 208, the example main cache store queue 212, and the example cache controller 220. The example main storage 214 stores data (e.g., entries) corresponding to data in memory address locations in the expanded memory 106. The main storage 214 stores data that is likely to be accessed by the example CPU 102. The stored data may be updated, for example, when the CPU 102 attempts to access (e.g., read, write, etc.) data that is not cached in the example main storage 214. The example main storage 214 may be or include static RAM (SRAM) and / or any other type of storage that provides single-cycle access to stored data.

[0052] 2 is coupled to the example tag RAM 210, the example victim cache store queue 216, and the example cache controller 220. The example victim storage 218 stores data (e.g., entries) corresponding to memory address locations that have been removed from the example main storage 214 to make room for data from other address locations that have been more recently accessed or are more likely to be accessed by the CPU 102. The example victim storage 218 may be or include a register file, static RAM (SRAM), and / or any other type of storage.

[0053] In operation, the example main storage 214 first stores data from different addresses in the example expanded memory 106 based on likelihood of use. When the example CPU 102 sends an instruction corresponding to a memory address stored in the main storage 214, the example cache controller 220 controls the components that perform the transaction. For example, the cache controller 220 may send the instruction to the main cache store queue 212 for subsequent processing and storage in the main storage 214. When the example CPU 102 sends an instruction corresponding to a memory address not stored in the main storage (e.g., stored in the victim storage 218), the example main storage 214 may store the data at the corresponding memory address after the data is retrieved from another storage. To make room for the data, the main storage 214 removes some data corresponding to one or more memory address locations. The removed data and the corresponding memory address locations are referred to as victims or evicted lines. The selection of which data to sacrifice is based on various parameters according to a replacement policy. After being removed from main storage 214, the victim is stored in exemplary victim storage 218. If victim storage 218 is full, victim storage 218 removes data (e.g., a second victim) to make room for storing the victim from main storage 214. After the second victim is removed from victim storage 218, the second victim is sent to L2 cache 112 for storage.

[0054] 1 includes one main cache store queue 212 with corresponding main storage 214 and one example victim cache store queue 216 with corresponding victim storage 218, the example main cache store queue 212 and / or the example victim cache store queue 216 may include multiple store queues corresponding to multiple storages. For example, the main storage 214 and / or the victim storage 218 may be divided into multiple independently addressable banks (e.g., any number of storages having any number of line widths, rows, etc.), and each bank may have its own corresponding store queue. For example, the main storage 214, which is organized into 256 rows with each row having a line width of 1024 bits, may be divided into 16 main storages (e.g., banks) with 64 bits per row in a particular bank, and each bank may have its own main store queue. In such an example, if the vector data for a read and / or write request hitting L1 cache 110 is 512 bits wide, cache controller 220 may process the request as eight parallel writes and / or reads to eight banks. In such a multi-bank setup, read and / or write operations may be sent to the banks in parallel, and the banks arbitrate their own processes in response to the read and / or write operations. By operating independently, the multi-bank approach operates more efficiently than a single main storage (e.g., because an entire cache line is not locked up when a request is received, but only the portion of the cache line assigned to the bank that received such a request) at the expense of complexity and / or parts.

[0055] 2 couples to the L1 components to control how data is read and / or written to the example storages 214, 216 and / or how data is updated in the example storages 214, 218. For example, when a read request, a write request, an atomic request, a read-modify-write request, etc. is received at the example CPU interface 202, the cache controller 220 retrieves the request and directs other components accordingly. For example, during a read request for data at a particular location in expanded memory 106, the example cache controller 220 directs the main tag RAM access 204 to access the tag RAM 208 to determine whether main storage 214 stores data corresponding to the location in expanded memory 106 from the read request. If the main tag RAM access 204 determines that the entry is located in main storage 214 (e.g., a cache hit), the cache controller 220 determines the location of the particular entry based on the data in the tag RAM 208, interfaces with the main cache store queue 212 to read the value from the example main storage 214, and returns the value to the CPU 102 via the CPU interface 202. The example cache controller 220 includes a main cache controller 222 for controlling the main cache components (e.g., the main tag RAM access 204, the example tag RAM 208, the example main cache store queue 212, and the example main storage 214) and an example victim cache controller 224 for controlling the victim cache components (e.g., the example victim tag RAM access 206, the example tag RAM 210, the example victim cache store queue 216, and the example victim storage 218) in parallel with the main cache controller 222 control of the main cache components. In some examples, cache controllers 222, 224 may be separate controllers and / or may be combined to operate as a single controller.

[0056] 2 interfaces with the example L2 interface 228 to obtain data to be stored in the example main storage 214 (e.g., first, after a cache miss, etc.). The example cache controller 220 may also send updates to the data in the main storage 214 and / or victim storage 218 to the L2 cache 112 when new data is written (e.g., when old data is overwritten), so that read instructions from the CPU 102 are propagated to the L2 cache 112 via the L2 interface 228. The example cache controller 220 interfaces with the example L2 interface 228 to send and / or receive data from the L2 cache 112 and / or the L3 cache 114 (e.g., directly or via the L2 cache 112). For example, if main storage 214 and victim storage 218 do not contain a memory address location for data corresponding to an instruction from CPU 102 (e.g., corresponding to a cache miss), the example cache controller 220 sends the instruction to the example L2 cache 112 via L2 interface 228. The cache controller 220 may receive corresponding data from L2 cache 112 via L2 interface 228 if the data is stored in L2 cache 112 or L3 cache 114. In such an example, the cache controller 220 may store the corresponding information from L2 cache 112 in main storage 214. In some examples, when victim storage 218 must remove data for a particular location (e.g., an old victim) to make room for a new victim from main storage 214, the example cache controller 220 may send the old victim to L2 cache 112 via L2 interface 228 to be stored in the L2 cache.

[0057] Figures 3A-3D illustrate an example circuit implementation of the L1 cache 110 of the example computing system 100 of Figure 1. The example implementation of Figures 3A-3D includes the example CPU interface 202, example tag RAMs 208, 210, example main cache store queue 212, example main storage 214, example victim cache store queue 216, example victim storage 218, and example cache controller 220 of Figure 2. The example implementation of FIGS. 3A-3D further includes an example modified exclusive shared invalid (MESI) RAM 300, example address processing components 302a-c, example bank processing logic 303, example hit / miss comparison logic 304, 306, an example replacement policy component 308, an example flash engine 309, example error correction code (ECC) logic 310, 312, example data multiplexer (MUX) circuits 314, 316, example MUXes 318, 320, and an example latch 322.

[0058] In the example implementation of Figures 3A-3D, the example CPU interface 202 includes two interfaces (e.g., one scalar interface and one vector interface, each having two parts: one for input data from CPU 102 and one for output data to CPU 102). The input CPU interface 202 of Figures 3A-3D includes a multiplexer to select between buffered data from the elastic buffer when there are pending CPU instructions in the elastic buffer and instructions sent from CPU 102 when the elastic buffer queue is empty, and splits the input instruction into a corresponding address, operation (e.g., read, write, etc.), and write data (e.g., if the instruction corresponds to a write operation). The output CPU interface 202 of Figures 3A-3D sends data back to CPU 102.

[0059] The example main cache store queue 212 of Figures 3A-3D includes blocks corresponding to the operations of the main cache store queue 212. For example, the main cache store queue 212 includes blocks for implementing a read-modify-write operation, a write merge, a write data transfer, a write operation, a complete parity block write data, a weighted histogram calculation, a load and increment operation, and a compare and swap operation. The example main cache store queue 212 is further described below in conjunction with Figure 4A. The example main cache store queue 212 operates in conjunction with example main storage 214. In the example of Figures 3A-3D, the main storage 214 is data RAM (DRAM).

[0060] The example victim cache store queue 216 of Figures 3A-3D includes blocks corresponding to the operations of the victim cache store queue 216. For example, the victim cache store queue 216 includes blocks for implementing a read-modify-write operation, a write merge, a write data transfer, a write operation, a complete parity block write data, a load and increment operation, and a compare and swap operation. The example victim cache store queue 216 is further described below in conjunction with Figure 5. The example victim cache store queue 216 operates in conjunction with an example victim storage 218. In the example of Figures 3A-3D, the main storage 214 is a register file.

[0061] The example MESI RAM 300 of FIGS. 3A-3D is connected to the example CPU interface 202 and the command line of the example DRAM 214. The example MESI RAM 300 tracks the state of data in the example main storage 214 based on commands from the CPU 102. For example, the MESI RAM 300 tracks the state of cache lines by marking them as modified, exclusive, shared, or invalid. Modified or dirty corresponds to when a cache line contains data that is not stored in other similar level caches and that data has changed from the value in main memory (e.g., so that reading the data in expanded memory 106 is flagged or allowed because it is not up-to-date or valid). Exclusive refers to when a cache line contains data that is not stored in other similar level caches and that data is clean (e.g., matches the data in expanded memory 106). Shared indicates that the cache line contains data that may be stored in other caches and is clean (e.g., the line may be discarded because it exists in another cache). Invalid indicates that the cache line is invalid or unused. MESI RAM 300 may be invoked upon updates to main storage 214 and / or expanded memory 106. The example MESI RAM 300 for victim caching is implemented in conjunction with the example tag RAM 210.

[0062] The example MESI RAM 300 of FIGS. 3A-3D provides coherency to the system through tracking, labeling, marking, etc. The state of a memory address may prevent data writes at certain times to prevent data inconsistencies in different levels of cache. The state tracked by the MESI RAM 300 may be sent along with a cache miss so that higher-level caches understand what the data at that memory address is used for. For example, if the L1 cache sends a cache miss for a read operation, the cache miss includes a shared state, informing the higher-level cache that the data will be read but not manipulated. If the L1 cache 110 sends a cache miss for a write operation, the cache miss includes an exclusive state to inform the higher-level cache that the data will be modified. When the example main storage 214 and / or victim storage 218 evict a victim, they can use the state from the example MESI RAM 300 to know how to evict it. For example, if the data is shared, main storage 214 and / or victim storage 218 can simply discard (e.g., because the data at the memory address is already located in a higher cache). If the data is exclusive or to be modified, cache controller 220 instructs interface 228 to send a victim to a higher level cache (e.g., because the data for the memory address is not located in a higher level cache, or is located in a higher level cache but is outdated).

[0063] 3A-3D are coupled to CPU interface 202, example main storage 214, example main cache store queue 212 (e.g., via MUX 318), example victim storage 218 (e.g., via MUX 320), and to each other. Example address processing components 302a-c include example first address processing component 302a, second address processing component 302b, and third address processing component 302c. First address processing component 302a performs address translation, second address processing component 302b performs data rotation, and third address processing component 302c facilitates bank organization. Alternatively, one or more of first address processing component 302a, second address processing component 302b, and third address processing component 302c can be included in the same hardware, logic circuit, integrated chip, etc. The example address processing components 302a-c organize data to be written to the example main storage 214 and victim storage 218 according to a particular storage protocol to ensure that the data is stored correctly. For example, in a multi-bank example (e.g., where the main cache store queue 212, main storage 214, victim cache store queue 216, and victim storage 218 are split into multiple banks), the address processing components 302a-c can use memory addresses from a CPU operation to determine which banks of the main cache store queue 212, main storage 214, victim cache store queue 216, and victim storage 218 are split into multiple banks required for a given CPU operation.

[0064] The example bank processing logic 303 is coupled to the CPU interface 202, the example main storage 214, the example main cache store queue 212 (e.g., via MUX 318), and the example victim storage 218 (e.g., via MUX 320). In operation, the bank processing logic 303 is configured to analyze read, modify, and / or write instructions from the CPU interface 202. In this manner, the bank processing logic 303 is configured to determine the nature of the read, modify, and / or write instructions to facilitate efficient partial bank read, modify, and / or write instructions. In the example described herein, the bank processing logic 303 detects whether an incoming write instruction indicates a full bank write or a partial bank write. In this manner, the bank processing logic 303 can indicate whether to operate a read-modify-write operation while disabling transmission of a read instruction. An example description of the operation of the bank processing logic 303 is provided below.

[0065] 3A-3D is coupled (e.g., via a data transfer latch) to input CPU interface 202, tag RAM 208, main storage 214, main cache store queue 212, cache controller 220, and / or example MUX circuit 314. Hit / miss comparison logic 304 takes an address from tag RAM 208 and an address of an instruction from CPU 102 and compares the two (e.g., using exclusive or (XNOR) logic) to determine whether the address from the instruction was a hit or a miss (e.g., whether data corresponding to the address is stored in example DRAM 214). Example hit / miss comparison logic 304 includes TAG comparison logic for outputting the result of the comparison to example main cache store queue 212, example cache controller 220, and / or example MUX circuit 314.

[0066] 3A-3D are coupled to input CPU interface 202, tag RAM 210, victim cache store queue 216, and / or example replacement policy component 308. Hit / miss comparison logic 306 obtains the victim cache entry number (e.g., location) from tag RAM 210 and the address from the instruction from CPU interface 202 and compares the two to determine whether the access (e.g., instruction from CPU interface 202) is a hit or a miss (e.g., whether data corresponding to the address is stored in example victim storage 218). The example hit / miss comparison logic 306 outputs the result to replacement policy component 308, address encoder 326, multiplexer 330, and / or victim cache store queue 216.

[0067] 3A-3D is coupled to the tag RAM 210 and the multiplexer 330 (via the hit / miss compare logic 306). The address encoder 326 encodes the address of the tag RAM 210 into a format that can be interpreted by the victim storage 218. For example, the tag RAM 210 may store a 16-bit memory address, while the victim storage 218 stores a 4-bit memory address that corresponds to the 16-bit memory address. As such, the address encoder 326 can convert the 16-bit memory address into a 4-bit memory address to locate and / or enter the corresponding memory address in the victim storage 218. Additionally and / or alternatively, the address encoder 326 encodes the memory address into an arbitrary bit value. The address encoder 326 is coupled to the exemplary multiplexer 330 such that the address encoder 326 provides the encoded address to the multiplexer 330.

[0068] The example replacement policy component 308 of FIGS. 3A-3D is coupled to the hit / miss comparison logic 306 and the replacement address encoder 328. In some examples, the replacement policy component 308 is coupled to the tag RAM 210. The example replacement policy component 308 controls the replacement policy for data stored in the example victim storage 218 (e.g., which data to move from the victim cache when a new victim is to be stored in the victim storage 218). In some examples, there may be a replacement policy component for the example main storage 214. However, a replacement policy is not required for a direct-mapped cache (e.g., if the example main storage 214 is direct-mapped because a particular address only goes to one location). An example flush engine (e.g., a flush engine component) 309 is coupled to the replacement policy 308. In some examples, the flush engine 309 is used to flush out write misses stored in the victim storage 218 at a predetermined periodicity and / or is otherwise invoked.

[0069] 3A-3D is coupled to multiplexer 330 such that replacement address encoder 328 provides an encoded replacement address to multiplexer 330. Replacement address encoder 328 encodes the address selected by replacement policy component 308. For example, replacement policy component 308 outputs a 16-bit replacement memory address to replacement address encoder 328, which converts the 16-bit replacement memory address to a 4-bit replacement memory address. Additionally and / or alternatively, replacement address encoder 328 encodes the replacement memory address into an arbitrary bit value.

[0070] 3A-3D are connected to the hit / miss compare logic 306, the address encoder 326, the replacement address encoder 328, and the address read 332. The multiplexer 330 selects an encoded address based on the result of the hit / miss compare logic 306 (e.g., based on whether the access was a hit or a miss). The multiplexer 330 provides the selected memory address to the address read 332 to be read into the victim storage 218. For example, the multiplexer 330 outputs a location in the victim storage 218 that the CPU instruction can use to read data from or store data from in the case of a write instruction.

[0071] The example error correction code (ECC) logic 310 of Figures 3A-3D is connected to the example main storage 214 via a latch 322 and to a multiplexer 314. If the example L1 cache 110 supports ECC memory, the example main storage 214 stores data in blocks along with a set of ECC syndrome bits corresponding to the blocks. When a read operation is received, the example main storage 214 may provide the stored data block and corresponding ECC syndrome bits to the ECC logic 310. The example ECC logic 310 may regenerate the ECC syndrome bits based on the data block read from the main storage 214 and compare the regenerated ECC syndrome bits with the previously stored bits. The example ECC logic 310 may determine that the data block was not read correctly when there is a discrepancy and correct the error in the data block.

[0072] 3A-3D is coupled to the example victim storage 218 via a latch 324 and to a multiplexer 316. The example ECC logic 312 performs ECC correction logic in a manner similar to the example ECC logic 310. However, the example ECC logic 312 performs ECC syndrome bit comparisons with respect to the example victim storage 218.

[0073] 3A-3D is connected to main cache store queue 212, ECC logic 310, the output of hit / miss compare logic 304 (e.g., via a latch), the example output CPU interface 202 (e.g., via example latch 322), the example victim data MUX 316, and the example cache controller 220. The example main data MUX circuit 314 has the inverse operation of the example address processing components 302a-c to translate data in data addresses to be sent to the example CPU 102. The MUXes in the example MUX circuit 314 are controlled by cache controller 220 via their respective select inputs.

[0074] 3A-3D is connected to victim cache store queue 216, ECC logic 312, example main data MUX circuit 314, L2 cache 112 (e.g., via latches), and example cache controller 220. Example main data MUX circuit 314 has the inverse operation of example address processing components 302a-c to translate data in data addresses to be sent to example CPU 102. The MUXes in example MUX circuit 316 are controlled by cache controller 220 via their respective select inputs.

[0075] 3A-3D are connected to the L2 cache 112, to the example CPU interface 202 via a latch, to address processing components 302a-c, the main cache store queue 212, the main storage 214, and the cache controller 220. The example cache controller 220 controls the MUX 318 to control all manner in which data may be written to or read from the example main storage 214 (e.g., via direct memory access (DMA), snoop transactions (e.g., when the L2 cache 112 wants data from the L1 cache 110), the main cache store queue 212, a read hit buffer, etc.). The example MUX 320 is connected to the example main storage 214 (e.g., via eviction lines for storing victims), address processing components 302a-c (e.g., via write streams and / or CPU loads), the example L2 cache 112 (e.g., via L2W and / or snoop lines), the victim storage 218, and / or the cache controller 220. The example cache controller 220 controls the MUX 320 to control all manner in which data is written to and read from the example victim storage 218 (e.g., via direct memory access (DMA), snoop transactions, victim cache store queue 216, eviction from the example main storage 214, etc., via the L2 cache 112). The example MUXes 318, 320 are controlled by the example cache controller 220 via their respective select inputs.

[0076] 3A and 3B are arranged to represent a transaction processing flow. The time elements are represented by stages E1 through E5. Each stage represents a distinct period of time, and in some examples, each stage represents a clock cycle or an integer number of clock cycles.

[0077] Write miss in L1 data cache

[0078] In operation, the example CPU 102 sends instructions (e.g., returning data based on a read operation and writing data to a particular memory location). When the example CPU 102 first requests data at a particular memory address, if the data for the memory address is not stored in main storage 214, the tag RAM 208 outputs a read miss, and the L1 cache sends the read miss information (e.g., to the L2 cache 112, the L3 cache 114, and / or the extended memory 106) to be processed (e.g., returning data corresponding to the address of the request from the CPU 102). Next, the L1 cache 110 may perform a read allocate. A read allocate is when the L1 cache 110 stores data in main storage 214 and updates the tag RAM 208, etc., to identify that the data for the address is currently stored in main data storage. The L1 cache 110 may return the data to the CPU 102 and / or wait for the CPU 102 to issue a subsequent read request to the same address. If CPU 102 issues a subsequent read request to the same address, tag RAM 208 identifies that the data for the address currently resides in main storage 214, thereby resulting in a read hit. If CPU 102 writes to the same address, tag RAM 208 identifies a write hit because the address is stored in main storage 214. In the case of a write hit, CPU 102 supplies the data to be written, and L1 cache 110 writes the data to main storage 214 corresponding to that address.

[0079] If an initial action from CPU 102 (or a subsequent action from CPU 102) results in a write miss (e.g., the memory address to which CPU 102 is attempting to write is not stored in exemplary main storage), L1 cache 110 may implement the write miss. During a write miss, L1 cache 110 sends the write miss to a higher level cache (e.g., L2 cache 112, L3 cache 114, etc.) and / or expanded memory 106, retrieves the data from the memory address, stores the data in main storage 214, and then writes the data from CPU 102 in main storage 214 at the location corresponding to the memory address.

[0080] However, when the CPU 102 performs a write operation, it often does not need the information it wrote immediately. Therefore, some exemplary cache systems have included a write buffer to store write instructions from the CPU to prevent the CPU from stalling (e.g., by attempting to load a memory address from a higher cache before writing the data). In this way, the CPU can continue to send instructions while the L1 cache interfaces with the higher level cache to obtain data in the memory address corresponding to the write instruction in the buffer, store the data in main storage, and write the data (e.g., stored in the write buffer) in parallel with subsequent instructions from the CPU. However, the CPU can only write a few bytes per write instruction, and the interface between the L1 cache and the higher level cache and / or extended memory is capable of sending a larger number of bytes (e.g., 64-byte bandwidth). Therefore, sending a few bytes per cycle over a large byte interface is inefficient.

[0081] In the system of FIGS. 3A-3D , instead of implementing a write buffer, a section of victim storage 218 is dedicated to write miss information. Thus, the exemplary victim storage 218 is a victim cache and a write miss buffer. The section of victim storage is referred to as a write miss cache. In some examples, the write miss cache may additionally or alternatively be implemented in main storage 214. In some examples, the write miss cache is a 128-byte cache line. The write miss cache stores all write miss data until the write miss cache is full and / or exceeds a first threshold number of bytes that can be sent to a higher level cache and / or expanded memory. Once the write miss cache is full or the first threshold amount of write miss data is added to the write miss cache, victim storage 218 combines a second threshold amount of write miss data in the write miss cache into a signal sent to the higher level cache (e.g., L2 cache 112) and / or expanded memory 106 (e.g., via the exemplary L2 interface 228) to be written to an address stored therein. In this way, most or all of the interface's bandwidth may be utilized in a particular cycle. The second threshold may be the same as or different from the first threshold. Also, write data is stored locally in main storage 214 or victim storage 218. Thus, if an additional read or write operation is sent from CPU 102 before the write operation is passed to a higher level cache (e.g., L2 cache 112, illustrative L3 cache 114, etc.) and / or expanded memory 106, cache controller 220 may read and / or write the data to the corresponding address in the write miss cache before sending it to the higher level cache and / or expanded memory 106.

[0082] In some examples, the structure of the write miss cache in the victim storage 218 includes a byte enable register file that represents value bytes of write miss information (e.g., bytes to be written). For example, if a write miss corresponding to write data in the first and third bytes of a memory address is stored in the write miss cache, the victim storage 218 stores the write miss data for the first and third bytes in association with the memory address and populates the corresponding entry of the byte enable register file with a first value (e.g., “1”) for the elements of the entry that correspond to the first and third bytes and a second value (e.g., “0”) for the remaining elements of the entry. In this way, when the write miss data is sent to a higher level cache, the byte enable bits of the entry are included in the transmission, allowing the higher level cache to know which data is valid (e.g., which bytes should be written) and which data is invalid (e.g., which bytes should not be written).

[0083] In some cases, if a write or read request is a hit in main storage 214, the result of victim storage 218 may be ignored. When main storage 214 is configured as a one-way associative cache, cache request conflicts with multiple data paths are straightforward. A data path is one or more logic circuits that, when executed and / or otherwise invoked, effect the transmission or delivery of data (e.g., logic signals, bit vectors, etc.) from a source to an address. Cache request conflicts from multiple data paths can be a problem for victim storage 218, which is fully associative and can store write miss entries as well as cache entries. Cache request conflicts for two data paths can be handled as described in the examples below. In the examples below, cache operations are described in the context of specific data paths. However, these examples are directed to specific cache operation combinations, regardless of which data path a particular cache operation is implemented on.

[0084] In a first example, there is a cache read miss for the first data path and a cache write hit for the second data path, with two different memory addresses. If the victim storage 218 is fully associative, the cache request can go to any location in the victim storage 218. Referring to FIGS. 3A-3D , address generation for a location in the victim storage 218 occurs in the E2 pipe stage in conjunction with an address lookup table in the victim cache tag RAM 210; therefore, address generation for a location in the victim cache occurs before it is known whether the address of the cache request is a hit or a miss. After the controller 220 determines there is a read miss on the main storage 214, a request is issued to a higher level cache or memory to obtain the memory address of the read request. If the main storage 214 is one-way associative, the memory address of the read request for the first data path maps to a single location in the main storage 214. If there is already cached data in the single location, the already cached data is evicted from the main storage 214 to the victim storage 218, to a pre-created location in the victim storage 218. If this pre-generated location is the same location that the second data path cache write hits, a conflict occurs. This conflict can be detected by cache controller 220. As described above, address generation for a location in victim storage 218 occurs before it is known whether the address of the cache request is a hit or a miss, and therefore there is an address generated for a second location in victim storage 218 for the second data path cache write before determining that the cache write is a hit. Based on the detection of the conflict, this second location in the victim cache can be used to store the data evicted from main storage 214 due to the read miss.

[0085] In another example, similar to the first example, there may be a cache read miss for the first data path and a cache write hit for the second data path. In this example, the read miss causes a request to be issued to a higher level cache or memory to obtain the memory address of the write request, and the already cached data is evicted from victim storage 214 to victim storage 218 to a pre-created location in victim storage 218, here location A. In this example, the cache write of the second data path also hits location A in victim storage 218, resulting in a set conflict. One possible solution to such a conflict is to load the requested read miss directly from the higher level cache or memory to a victim cache in a separate location. Another solution to the conflict is for cache controller 220 to stall the read miss so that the already cached data is not evicted to victim storage 218 until the cache write to location A of the second data path is completed and location A is evicted to the higher level cache or memory. In some cases, a stall may occur while waiting for the higher level cache or memory to return the read miss data.

[0086] As another example, a first cache write is received on a first data path for the victim storage 218, and a second cache write is also received on a second data path for the victim storage 218. If the first cache write and the second cache write are addressed to different memory addresses, both cache writes may proceed in parallel to the victim storage 218. If both the first cache write and the second cache write are addressed to the same memory address and are both cache misses, the victim cache controller 224 allocates a single location in the allocated victim cache write miss memory and merges the first cache write and the second cache write in the victim cache store queue 216. The merged data may be written to the victim cache write miss memory along with merged byte enable, priority, and color tag information. If both the first cache write and the second cache write are addressed to the same memory address and are both cache hits, both the first cache write and the second cache write are merged into the cache at the hit location.

[0087] As another example, a cache read may be received on a first data path for the victim storage 218, and a cache write may be received on a second data path for the victim storage 218. If the cache read is a hit and the cache write is a hit to a different location in the victim storage 218, the cache read and the cache write proceed in parallel without contention. If the cache read is a hit and the cache write is a miss to a different location in the victim storage 218, the cache read and the cache write also proceed in parallel without contention. If the cache read is a miss and the cache write is a hit to a different location in the victim storage 218, the cache read may use an address generated for the location in the victim storage 218 for the cache write, as described above. If the cache read is a miss and the cache write is a miss to a different location in the victim storage 218, both the cache read and the cache write use addresses generated for locations in the victim storage 218.

[0088] In another example, a cache read may be received on a first data path for the victim storage 218 and a cache write may be received on a second data path for the victim storage 218. In one case, the cache read may be a hit to a first address in a set of addresses stored in the victim storage 218. The cache write may be a hit to a second address in the same set of addresses stored in the victim storage 218. In such a case, the cache read and the cache write may proceed in parallel without contention. In another case, the cache read may be a hit to a first address in the set of addresses stored in the victim storage 218. The cache write may be a miss to a second address in the same set of addresses stored in the victim storage 218. In such a case, the cache read and the cache write may proceed in parallel without contention. In another case, the cache read may be a miss to a first address in the set of addresses stored in the victim storage 218. The cache write may be a hit to a second address in the same set of addresses stored in the victim storage 218. In such a case, similar to that described above, the cache read may be stalled until the second data path cache write to a location in victim storage 218 completes and is evicted to a higher level cache or memory. The cache read then proceeds to read the set of addresses from the higher level cache or memory to victim storage 218. In another case, the cache read may be a miss to a first address in the set of addresses stored in victim storage 218. The cache write may be a miss to a second address in the same set of addresses stored in victim storage 218. In such a case, the cache read and cache write may proceed in parallel without conflict.

[0089] In another example, a cache read may be received on a first data path for the victim storage 218, and a cache write may be received on a second data path for the victim storage 218. In some cases, the cache read may be a hit to an address stored in the victim storage 218. The cache write may be a hit to the same address stored in the victim storage 218. In such cases, the cache read may proceed first and may be stalled until the cache read completes. Alternatively, the order of the cache write and cache read may be based on the data path on which the cache write and cache read are received, and a cache operation arriving on a lower (or higher) numbered data path may complete before the other cache operation. In some cases, the cache read may be a miss to an address stored in the victim storage 218. The cache write may be a miss to the same address stored in the victim storage 218. In such cases, the cache write operation may be forwarded to a higher level cache or memory, and the cache read may retrieve data from the higher level cache or memory after the cache write operation for storage to the victim storage 218 completes.

[0090] In another example, a first cache read may be received on a first data path for the victim storage 218, and a second cache read may be received on a second data path for the victim storage 218. If the first cache read and the second cache read are for different memory addresses, no conflict occurs for either a hit or a miss. In some cases, the first cache read may be a miss for a first address in a set of addresses. The second cache read may be a miss for a second address in the same set of addresses. If the first cache read and the second cache read are at different priority levels, a higher level cache or memory is accessed based on the higher of the different priority levels. Otherwise, a higher level cache or memory is accessed, and the resulting set of memory addresses is accessed for storage in the victim storage 218. The same process applies if the first cache read and the second cache read are for the same address.

[0091]

[0009] Exemplary methods, apparatus, systems, and products for facilitating write miss caching in an L1 data cache are described herein, and some examples and combinations thereof include the following. Example 1 includes an apparatus including a first cache storage, a second cache storage, and a cache controller. The second cache storage includes a first portion operable to store a first set of data evicted from the first cache storage and a second portion. The cache controller is coupled to the first cache storage and the second cache storage and is operable to receive a write operation, determine that the write operation generates a miss in the first cache storage, and, in response to the miss in the first cache storage, provide write miss information associated with the write operation to the second cache storage for storage in the second portion.

[0092] Example 2 includes the apparatus of Example 1, wherein the cache controller is operable to compare a second portion of the second cache storage to a threshold and, based on the second portion exceeding the threshold, cause the write miss information to be sent to the second cache.

[0093] Example 3 includes the apparatus of example 2, where the threshold corresponds to a bandwidth of the interface.

[0094] Example 4 includes the apparatus of example 2, wherein the threshold corresponds to a size of the second portion.

[0095] Example 5 includes the apparatus of example 1, wherein the write miss information is first write miss information, and the cache controller operable with the second cache storage is for not providing the first write miss information from the first cache storage to the second cache storage when the second cache storage includes second write miss information for a memory address corresponding to the first write miss information.

[0096] Example 6 includes the apparatus of example 1, wherein the first cache storage and the second cache storage are connected in parallel to the central processing unit.

[0097] Example 7 includes the apparatus of Example 1, wherein the write miss information is first write miss information, and the cache controller is operable to merge the first write miss information with the second write miss information when a first memory address of the first write miss information from the first cache storage matches a second memory address of second write miss information stored in the second portion.

[0098] Example 8 includes the apparatus of example 7, wherein the cache controller is to merge the first write miss information with the second write miss information by at least one of (a) maintaining the first write information of the first write miss information, or (b) discarding the second write information of the second write miss information when the second write information corresponds to the same one or more bytes as the first write miss information.

[0099] Example 9 includes the apparatus of example 1, wherein the second portion includes a byte enable register, and the cache controller is to store a value in the byte enable register based on the write miss information.

[0100] Example 10 includes the apparatus of example 9, wherein the value corresponds to an element of the write miss information to be written.

[0101] Example 11 includes a system including a central processing unit for outputting a write command corresponding to a memory address, a first cache storage for outputting write miss information from the first storage to a second storage when the first cache storage does not store data for the memory address, and a second cache storage, the second cache storage including a first portion and a second portion operable to store a first set of data evicted from the first cache storage, the second cache storage for storing the write miss information in a dedicated section of the second storage, the dedicated section being dedicated to the write miss information.

[0102] Example 12 includes the system of example 11, wherein the second cache storage is to output the write miss information to the second cache when the dedicated section has more than a threshold amount of write miss information.

[0103] Example 13 includes the system of example 12, wherein the threshold corresponds to a bandwidth of an interface to the second cache.

[0104] Example 14 includes the system of example 12, wherein the threshold corresponds to a size of the second portion.

[0105] Example 15 includes the system of example 11, wherein the second cache storage is to not store the write miss information from the first storage in the second portion when the second cache storage includes a second write instruction corresponding to the same memory address as the write miss information from the central processing unit.

[0106] Example 16 includes the system of example 11, wherein the first cache storage and the second cache storage are connected in parallel to the central processing unit.

[0107] Example 17 includes the system of Example 11, wherein the write miss information is first write miss information, and the system further includes a controller for merging the first write miss information with the second write miss information when a first memory address of the first write miss information from the first cache storage matches a second memory address of the second write miss information stored in the second portion.

[0108] Example 18 includes the system of Example 17, wherein the cache controller is to merge the first write miss information with the second write miss information by at least one of (a) maintaining the first write information of the first write miss information, or (b) discarding the second write information of the second write miss information when the second write information corresponds to the same one or more bytes as the first write miss information.

[0109] Example 19 includes a method, including receiving a write operation; determining that the write operation generates a miss in a first cache storage; and, in response to the miss in the first cache storage, providing write miss information associated with the write operation to a second cache storage element having a first portion and a second portion for storing in the second portion, the first portion storing a first set of data evicted from the first cache storage.

[0110] Example 20 includes the method of example 19, further including comparing the second portion of the second cache storage to a threshold value and outputting write miss information to the second cache based on the second portion exceeding the threshold value.

[0111] FIG. 4A is an example circuit implementation of the example main cache store queue 212 of FIG. 2 and / or FIG. 3. In FIG. 4A, the main cache store queue 212 includes example latches 402a, 402b, 402c, 402d, and 402e, example merge circuits 403a-c, an example arithmetic component 404, an example atomic compare component 406, an example read-modify-write-merge component 408, an example selection multiplexer 410, and an example ECC generator 412, an example arbitration manager 414, an example pending store address data store 416, an example priority multiplexer 418, an example read port 424, and an example write port 426. The example merge circuits 403a-d include an example comparator 420 and an example switch 422. The example of FIG. 4A illustrates a single pipeline of the main cache store queue 212. However, main storage element 214 may be configured to support two or more independent replicas of the pipeline for different banks, as indicated by dashed box 400. Thus, the pipeline of FIG. 4A may be replicated multiple times for different banks, as described further below.

[0112] 4A , example latches 402a, 402b, 402c, 402d, and 402e are electronic devices configured to store information (e.g., bytes, bits, etc.) obtained by main cache store queue 212. Example latches 402a-c pass write data and information corresponding to whether the write data needs to be combined with read and corrected data from arithmetic unit 404, atomic unit 406, and / or ECC logic 310 within RMW merge component 408. In the example of FIG. 4A , latch 402a is communicatively coupled to cache controller 220 to receive read, write, and / or modify instructions. Such read, modify, and / or write instructions may originate from CPU 102 and be transferred to latch 402a via cache controller 220. Latch 402a is coupled to latch 402b, tag RAM 208, arbitration manager 414, and pending store address data store 416 to transmit such read, modify, and / or write instructions to latch 402b, tag RAM 208, arbitration manager 414, and pending store address data store 416 in response to a subsequent clock cycle of cache controller 220.

[0113] 4A, latch 402b is coupled to latch 402a, pending store address data store 416, latch 402c, priority multiplexer 418, and comparator 420 to transmit the resulting read, modify, and / or write instructions in response to subsequent clock cycles of cache controller 220. In this manner, values ​​(e.g., byte values, bit values, etc.) resulting from the read, modify, and / or write instructions propagate through main cache store queue 212.

[0114] An example of latch 402c is coupled to latch 402b, priority multiplexer 418, compute component 404, atomic compare component 406, and read-modify-write-merge component 408. This coupling allows latch 402c to transmit values ​​(e.g., byte values, bit values, etc.) resulting from read, modify, and / or write instructions to compute component 404, atomic compare component 406, and / or read-modify-write-merge component 408 in response to subsequent clock cycles of cache controller 220. In some examples described herein, latch 402c may transmit values ​​(e.g., byte values, bit values, etc.) resulting from read, modify, and / or write instructions to one or more of compute component 404, atomic compare component 406, and / or read-modify-write-merge component 408. For example, if cache controller 220 sends an instruction to write a bit to a currently stored word, latch 402c may read, modify, and / or send the value resulting from the instruction (e.g., byte value, bit value, etc.) to read-modify-write-merge component 408. In other examples described herein, cache controller 220 may send an instruction to write a bit to a currently stored word, but latch 402c may send the value resulting from the read, modify, and / or write instruction (e.g., byte value, bit value, etc.) to operation component 404, atomic comparison component 406, and / or read-modify-write-merge component 408.

[0115] Example latch 402d is coupled to first multiplexer 410, ECC generator 412, and latch 402e. This coupling allows latch 402d to transfer the value obtained from first multiplexer 410 to ECC generator 412 and / or merge circuit 403a in response to a subsequent clock cycle of cache controller clock 220.

[0116] The example latch 402e is coupled to the priority multiplexer 418 and to the MUX circuit 314 of Figures 3 and / or 4. This coupling allows the latch 402e to forward the value obtained from the priority multiplexer 418 to the MUX circuit 314 in response to a subsequent clock cycle of the cache controller 220. For example, in a read operation by the CPU 102 to an address that hits in the main storage element 214, a previous write to the same address may still be inflight (e.g., not completely written to the main storage element 214). In such an example, the latch 402e collects the unwritten data byte and provides it to the MUX 314, which ultimately sends it back to the CPU 102.

[0117] Example merge circuit 403a is coupled to latch 402d, merge circuit 403b, arithmetic component 404, atomic compare component 406, and read-modify-write-merge component 408. Example merge circuit 403b is coupled to merge circuit 403a, priority multiplexer 418, and merge circuit 403c. Example merge circuit 403c is coupled to merge circuit 403b and latch 402b. Example merge circuits 403a-c facilitate comparison of read operations in different sections of main cache store queue 212 and potentially reroute write operations that are merged with write operations corresponding to the same memory address location, as described further below. While the example of FIG. 4A includes three merge circuits 403a-c, there can be additional merge circuits (e.g., a merge circuit coupling the output of latch 402d to the output of latch 402b and / or latch 402a) to merge write operations from other sections of main cache store queue 212. In some examples, the merged circuits 403a-c are combined into a single circuit that compares write operations from different latches 402b-d and redirects based on matching memory addresses in any two or more different latches 402b-d.

[0118] In the example shown in FIG. 4A , a computing component 404 is coupled to the latch 402 c, the first multiplexer 410, and the ECC logic 310 to perform arithmetic operations (e.g., increment, decrement, etc.) on data from the main storage 214. The computing component 404 also performs histogram operations on data stored in the main storage 214. The example computing component 404 in the illustrated example of FIG. 4A is implemented by a logic circuit, such as a hardware processor. However, any other type of circuit may additionally or alternatively be used, such as, for example, one or more analog or digital circuits, logic circuits, programmable processors, application specific integrated circuits (ASICs), programmable logic devices (PLDs), field programmable logic devices (FPLDs), digital signal processors (DSPs), etc. The operation of the example computing component 404 is further described below.

[0119] 4A, the atomic comparison component 406 is coupled to the latch 402c, the first multiplexer 410, and the ECC logic 310 to compare the data at the memory address with a key and replace the data if the data at the memory address matches the key. The example atomic comparison component 406 in the illustrated example of FIG. 4A is implemented by a logic circuit, such as a hardware processor. However, any other type of circuit may additionally or alternatively be used, such as one or more analog or digital circuits, logic circuits, programmable processors, application specific integrated circuits (ASICs), programmable logic devices (PLDs), field programmable logic devices (FPLDs), digital signal processors (DSPs), etc. The operation of the example atomic comparison component 406 is further described below.

[0120] In the example shown in FIG. 4A , the read-modify-write-merge component 408 is coupled to the latch 402 c, the first multiplexer 410, and the ECC logic 310 to facilitate read, modify, and / or write instructions sent by the cache controller 220. For example, the read-modify-write-merge component 408 is coupled to the ECC logic 310 to retrieve the currently stored word affected by the read, modify, and / or write instruction. In an example write operation, the read-modify-write-merge component 408 is configured to update the currently stored word retrieved from the ECC logic 310 with the new bit, byte, etc. retrieved from the latch 402 c. Additional description of the read-modify-write-merge component 408 is provided below. The example read-modify-write-merge component 408 of the illustrated example of FIG. 4A is implemented by logic such as, for example, a hardware processor. However, any other type of circuitry may additionally or alternatively be used, such as, for example, one or more analog or digital circuits, logic circuits, programmable processors, application specific integrated circuits (ASICs), programmable logic devices (PLDs), field programmable logic devices (FPLDs), digital signal processors (DSPs), etc.

[0121] The example first multiplexer 410 is coupled to the arithmetic component 404, the atomic comparison component 406, and the read-modify-write-merge component 408 to send the output of either the arithmetic component 404, the atomic comparison component 406, or the read-modify-write-merge component 408 to latch 402d based on an indication from the cache controller 220. For example, when the cache controller 220 indicates to perform a write function (e.g., when the cache control sends a write request to latch 402b), an indication is sent by the cache controller 220 to the first multiplexer 410 to select the input connected to the read-modify-write-merge component 408 to be sent to latch 402d. The example first multiplexer 410 in the illustrated example of FIG. 4A is implemented by a logic circuit, such as, for example, a hardware processor. However, any other type of circuitry may additionally or alternatively be used, such as, for example, one or more analog or digital circuits, logic circuits, programmable processors, application specific integrated circuits (ASICs), programmable logic devices (PLDs), field programmable logic devices (FPLDs), digital signal processors (DSPs), etc.

[0122] In the example illustrated in FIG. 4A , an ECC generator 412 is coupled to the latch 402d and the merge circuit 403 to facilitate detection and correction of errors in values ​​(e.g., bytes, bits, etc.) stored in the latch 402d. For example, the ECC generator 412 is configured to regenerate an ECC value (e.g., generate an error detection code), which is stored along with the data (e.g., a merged word from the read-modify-write-merge component 1108). The ECC value is used by the error detection and correction circuitry, as described above, to determine whether an error occurred during a read and / or write operation. The exemplary ECC generator 412 in the example illustrated in FIG. 4A is implemented by logic, such as, for example, a hardware processor. However, any other type of circuitry may additionally or alternatively be used, such as, for example, one or more analog or digital circuits, logic circuits, programmable processors, application-specific integrated circuits (ASICs), programmable logic devices (PLDs), field-programmable logic devices (FPLDs), digital signal processors (DSPs), etc.

[0123] 4A , an example arbitration manager 414 is coupled to latch 402a, latch 402b, pending store address data store 416, and main storage 214 to facilitate read, modify, and / or write instructions received from cache controller 220. For example, when a write instruction is received from cache controller 220, arbitration manager 414 is configured to send a read instruction for the corresponding currently stored word to main storage 214. Arbitration manager 414 is also coupled to main storage 214 to arbitrate between conflicting accesses of main storage 214. When multiple operations attempt to access main storage 214 in the same cycle, arbitration manager 414 may select which operation is permitted to access main storage 214 according to a priority scheme. While a suitable priority scheme is described in more detail below, in one example, arbitration prioritizes read operations over write operations because write data residing in main cache store queue 212 is available for use by subsequent operations even before it is written to main storage 214. Thus, there is minimal performance impact in allowing write data to wait in the main cache store queue 212. However, if the main cache store queue 214 fills with write data that has not yet been written back, the priority of the write operation may increase until it takes precedence over competing read operations.

[0124] 4A is implemented by logic circuitry such as a hardware processor, however, any other type of circuitry may additionally or alternatively be used, such as one or more analog or digital circuits, logic circuits, programmable processors, application specific integrated circuits (ASICs), programmable logic devices (PLDs), field programmable logic devices (FPLDs), digital signal processors (DSPs), etc.

[0125] 4A , pending store address data store 416 is configured to store addresses of read, modify, and / or write instructions obtained from cache controller 220. In this manner, pending store address data store 416 maintains a log of addresses associated with each value stored in any of latches 402a, 402b, 402c, 402d, 402e, and / or merge circuits 403a, 403b, and / or 403c. The example pending store address data store 416 in the illustrated example of FIG. 4A may be implemented by any device for storing data, such as, for example, flash memory, magnetic media, optical media, etc. Additionally, the data stored in pending store address data store 416 may be in any data format, such as binary data, comma-separated data, tab-separated data, structured query language (SQL) structures, etc.

[0126] Example priority multiplexer 418 is coupled to latch 402b, latch 402c, latch 402d, and merge circuit 403a to facilitate a read operation when any of latch 402b, latch 402c, latch 402d, or merge circuit 403a stores a value corresponding to a write instruction. For example, the cache controller may initiate the following four write instructions for a 4-byte word having addresses A3, A2, A1, and A0: write byte 0x11 to address A0, write byte 0x22 to address A1, write byte 0x23 to address A3, and write byte 0x44 to address A0. In such an example, if cache controller 220 initiates a read instruction to read an entire four-byte word, priority multiplexer 418 is configured to retrieve the byte value 0x11 stored in merge circuit 403a, the byte value 0x22 stored in latch 402d, the byte value 0x23 stored in latch 402c, and the byte value 0x22 stored in latch 402b. Pending store address data store 416 also sends an instruction to priority multiplexer 418 indicating which address values ​​are associated with the byte values ​​stored in latch 402b, latch 402c, latch 402d, and merge circuit 403a. In such an example, because the byte value stored in latch 402b is associated with address A0 and the byte value stored in merge circuit 403a is also associated with address A0, priority multiplexer 418 is configured to send a packet to latch 402e indicating that address A0 is 0x44 (e.g., the most recent write instruction associated with address A0), address A1 is 0x22, and address A3 is 0x23.

[0127] In this manner, MUX circuit 314 is configured to update the value of the currently stored word with the byte value obtained from priority multiplexer 418. Such operation ensures that a read instruction sent by main cache store queue 212 potentially points to the correct word, even if a write instruction has not completely propagated through main cache store queue 212.

[0128] An illustrative read path (e.g., a read input to tag RAM 208) may execute in parallel with main cache store queue 212. Because a read operation (e.g., a read instruction) may reference data in a write operation (e.g., a write instruction) that may not yet be completed, main cache store queue 212 may include a write forwarding function that allows the read path to obtain data from main cache store queue 212 that has not yet been written back to main storage 214. In one example, main cache store queue 212 includes a pending store address data store 416 that records the addresses of operations in each stage of main cache store queue 212, a priority multiplexer 418 that selects data from one of the stages (e.g., latches) of main cache store queue 212 for forwarding, and a MUX circuit 314 that selects between the output of main storage 214 and main cache store queue 212 data forwarded from data priority multiplexer 418 (via error detection and correction circuit 310).

[0129] Alternatively, because a read operation (e.g., a read command, etc.) may refer to sacrificing (evicting) data for a write operation (e.g., a write command, etc.) that may not yet have completed, the main cache store queue 212 includes a read invalidation function that transfers in-flight data (e.g., data in the store queue 212 that has not yet been stored in the main storage element 214) to the victim storage element 214 and / or the L2 cache 212 and invalidates the in-flight data remaining in the store queue 212.

[0130] An exemplary read port 424 is coupled to the read path and to the data store 416. The read port 424 may be implemented by an interface that interfaces with the main cache controller 222 whenever a read miss occurs. For example, the read port 424 is utilized to receive a victim address and a read invalidation command from the main cache controller 222. The read port 424 is for sending the victim address to the data store 416 to be compared with the pending address stored in the data store 416.

[0131] An exemplary write port 426 is coupled to the write path and latch 402a. The write port 426 may be implemented by an interface that interfaces with the main cache controller 222 (e.g., cache controller 220) to receive write instructions. For example, the write port 426 is used to receive an address and value from the cache controller 220 for writing.

[0132] The elements of Figure 4A are arranged in a manner that represents a transaction processing flow. The time elements are represented by stages E1 through E5. Each stage represents a distinct period of time, and in some examples, each stage represents a clock cycle or an integer number of clock cycles.

[0133] An example flow of a read operation through main cache store queue 212 will now be described. In the first cycle, corresponding to stage El, L1 data cache 110 retrieves a record associated with the address of the read operation from tag RAM 208 to determine whether the data is stored in main storage 214. In a direct-mapped example, L1 data cache 110 does not need to wait for the tag RAM 208 comparison before requesting the data from main storage 214; therefore, tag RAM 208's comparison of the address of the read operation with its cached address record may extend into a second or third clock cycle.

[0134] In the second cycle, corresponding to stage E2, L1 data cache 110 may request data and ECC syndrome bits from main storage 214, if arbitration manager 414 grants. In this cycle, L1 data cache 110 may also determine whether newer data is available in main cache store queue 212 by comparing the read address with pending store address data store 416. If so, priority multiplexer 418 is set to forward the appropriate data from main cache store queue 212.

[0135] The data and ECC may be provided by main cache storage 214 in the third cycle, corresponding to stage E3. However, this data may or may not correspond to the memory address specified by the read operation, as L1 data cache 110 may assign multiple extended memory addresses to the same entry in main storage 214 of the cache. Thus, in the third cycle, L1 data cache 110 determines whether the data and ECC provided from main storage 214 correspond to the memory address in the read operation (e.g., a cache hit) based on a comparison of tag RAM 208 records. If there is a cache hit, the data and ECC bits are received by error detection and correction circuitry 310, which corrects the error in the data in the fourth cycle, corresponding to stage E4.

[0136] As mentioned above, new data that has not yet been written to main storage 214 may be present in main cache store queue 212 and may be forwarded from main cache store queue 212 by priority multiplexer 418. If so, MUX circuit 314 selects the forwarded data over the corrected data from main storage 214.

[0137] Either the corrected data from main storage 214 or the forwarded data from main cache store queue 212 is provided to L1 data cache 110 in the fifth cycle, corresponding to stage E5. In this manner, controller 220 can provide fully ECC checked and corrected data in the event of a cache hit in approximately five cycles.

[0138] If the data and ECC bits are not present in main storage 214 (e.g., a cache miss), the main cache store queue 212 may stall until the data is retrieved from either expanded memory 106 and / or victim storage 218, at which point the data may be written to main storage and the tag RAM 208 may be updated.

[0139] Method and apparatus for facilitating fully pipelined read-modify-write support in a level 1 data cache using store queues and data forwarding

[0140] In the example described herein, there are two cache systems (e.g., main storage 214 and victim cache storage 218) operating in tandem. In the example described herein, main storage 214 is a direct-mapped cache element, and victim cache storage 218 is a fully associative cache storage. Both the direct-mapped main storage 214 and the fully associative victim cache storage 218 are protected by error correcting codes (ECC). In this case, an example application involves reading a line from and / or moving a line from main storage 214. Accordingly, ECC logic corrects the cache line, regenerates the ECC syndrome, and then writes the line to victim cache storage 218. Such an application may utilize two additional clock cycles of the CPU (e.g., one clock cycle for error correction by the ECC logic and another clock cycle for ECC syndrome regeneration). To reduce this latency, examples described herein include utilizing the same parity block size between main storage 214 and victim cache storage 218. Thus, both main storage 214 and victim cache storage 218 calculate and / or otherwise determine parity on 32-bit boundaries. In this manner, L1 cache 110 may move cache lines directly from main storage 214 to victim cache storage 218 with low latency.

[0141] In the example described herein, L1 data cache 110 supports a number of operations that read data from the cache and modify the data before rewriting it. For example, L1 data cache 110 may support read-modify-write operations. A read-modify-write operation reads existing data and overwrites at least a portion of that data. In ECC implementations, a read-modify-write operation may be performed when writing less than the full bank width (e.g., when writing less than a 32-bit, 4-byte word). The read function of read-modify-write is used because some of the data in the bank that is not overwritten still contributes to the ECC syndrome bits.

[0142] Read-modify-write operations may be split into write operations and read operations, and the main cache store queue 212 may be structured such that read operations in the read path remain synchronized with write operations in the main cache store queue 212. The read and write operations remain synchronized until the read-modify-write merge component 408 overwrites at least a portion of the read data with the write data to generate merged data. The merged data may be provided to an ECC generator 412, which generates new ECC syndrome bits for the merged data, and the merged data and ECC syndrome bits may then be provided to the arbitration manager 414 for storage in the main storage 214.

[0143] In an exemplary read-modify-write operation, cache controller 220 of FIG. 2 and / or FIG. 3 transmits a write request indicating a subset of bytes of a word to be written, or an entire word (e.g., a first set of data). In such an example, the write request transmitted by cache controller 220 includes address values ​​of the bytes to be written and the data to write to the indicated bytes. For example, main storage 214 of FIG. 2 and / or FIG. 3 may include the 4-byte word 0x12345678 associated with addresses A3, A2, A1, and A0. In such an example, address A3 corresponds to byte 0x12, address A2 corresponds to byte 0x34, address A1 corresponds to byte 0x56, and address A0 corresponds to byte 0x78 of the stored word. In such an example operation, cache controller 220 may send write requests to replace address A3 with byte 0x33, replace address A1 with byte 0x22, and replace address A0 with byte 0x11 of currently stored word 12345678. Also in such an example, a first write request to replace stored word address A3 with byte 0x33 makes the stored word 0x33345678, a second write request to replace stored word address A1 with byte 0x22 makes the stored word 0x33342278, and a third write request to replace stored word address A0 with byte 0x11 makes the stored word 0x33342211.

[0144] To process such a request, L1 data cache 110 compares the address of the read operation with the record in tag RAM 208, and the L1 data cache requests data and ECC syndrome bits from main storage 214 and / or main cache store queue 212. Because read-modify-write operations modify data, in an example that tracks the MESI (Modify, Exclusive, Shared, and Invalid) state of entries in main storage 214, a cache hit that is not in either the Modified or Exclusive state may be considered a cache miss. Once the data is retrieved in the appropriate state and any errors corrected, it is provided to read-modify-write-merge component 408. In this same cycle, read-modify-write-merge component 408 may overwrite at least a portion of the corrected data with the write data to generate merged data. ECC generator 412 generates new ECC syndrome bits for the merged data.

[0145] In the example described herein, ECC generator 412 operates at word granularity. Thus, ECC generator 412 calculates ECC syndromes for blocks of data. In the example described herein, the blocks of data may be 4 bytes (e.g., words). While main cache store queue 212 processes a write instruction in the first example cycle (e.g., to compete with the first write request to replace address A3 with byte 0x33) because ECC generator 412 operates at word granularity (e.g., 4 bytes or 32-bit words), cache controller 220 initiates a read request for the currently stored byte at address A3 of the currently stored word. In this example, the byte and address of the first write request (e.g., 0x33 and A3) are stored in latch 402b. Cache controller 220 also sends a read request for the entire currently stored word to main storage 214. Thus, at the end of the first cycle, a read request for the entire currently stored word is sent to main storage 214 and byte 0x33 is stored in the first latch 402b.

[0146] In the illustrated second cycle (e.g., to complete a second write request to replace address A1 with byte 0x22), the byte from the first write request is sent to latch 402c, the entire currently stored word is sent from main storage 214 to ECC logic 310, and a second write request (e.g., to replace address A1 with byte 0x22) is sent by cache controller 220 and stored in latch 402b. During the second cycle, read-modify-write-merge component 408 obtains the byte stored in latch 402c and the entire currently stored word sent by ECC logic 310. In this manner, read-modify-write-merge component 408 identifies the address of the byte within the currently stored word to be updated. Once the read-modify-write-merge component 408 identifies and / or otherwise obtains (a) the value (e.g., byte value, bit value, etc.) of the currently stored word portion to be updated from the latch 402c and (b) the currently stored word from the ECC logic 310, the read-modify-write-merge component 408 writes (e.g., replaces, merges, etc.) the currently stored word portion with the value of the currently stored word portion obtained from the latch 402c. For example, the read-modify-write-merge component 408 writes the word portion value to an address value corresponding to the word portion within the word. Such an example written portion output by the read-modify-write-merge component 408 may be referred to herein as a merged word. In some examples described herein, such a merged word is provided by the read-modify-write-merge component 1108 for writing to the victim storage 218.

[0147] In response, to initiate the write portion of the exemplary read-modify-write operation, select multiplexer 410 sends the merged word from read-modify-write merge component 408 to be stored in latch 402d. In a subsequent clock cycle, ECC generator 412 takes the merged word from latch 402d and generates corresponding ECC syndrome bits. Either in the same clock cycle or a subsequent clock cycle, ECC generator 412 sends the merged word through merge circuits 403a, 403b, and 403c, which are processed by arbitration manager 414 and stored in main storage 214.

[0148] However, in the example described above, because three consecutive write instructions were sent by cache controller 220 corresponding to the same word stored in main storage 214, read-modify-write-merge component 408 may merge these three write instructions into one transaction when writing the three values ​​of the three write instructions to the currently stored word. For example, before storing the merged word from the first write instruction in main storage 212, main store queue 212 feeds back (e.g., transmits) the merged word for use by a subsequent second write instruction.

[0149] Figure 4B is an example circuit implementation of example data transfer logic 460 implemented in association with main cache store queue 212 of Figures 3A-4A. Although Figure 4B is described as example data transfer logic 460 implemented in association with main cache store queue 212, in other examples described herein, any of the examples described in Figure 4B may be implemented in association with victim cache store queue 216.

[0150] In the example of FIG. 4B, example address lines 462 (RD_ADDR) are coupled to cache controller 220 to obtain an example read instruction from CPU 102. In the example of FIG. 4B, such example address lines 462 obtain a read instruction for main cache store queue 212. In this manner, main cache store queue 212 may forward any data from an in-flight write transaction when executing a CPU 102 read instruction. In main cache store queue 212, instructions from CPU 102 (e.g., read instructions and / or other transactions, and / or write instructions and / or other transactions) include an address, a byte enable (byten), and associated data. The topology of FIG. 4B includes an example address store 464a (e.g., pending store address data store 416 of FIG. 4), an example byten store 464b (e.g., a byte enable store), and an example data store 464c (e.g., any of latches 402a, 402b, 402c, etc.). In FIG. 4B, addr0 of address store 464a corresponds to the oldest read and / or write instruction in main cache store queue 212, and addr3 of address store 464a corresponds to the most recent read and / or write instruction in main cache store queue 212.

[0151] An incoming address (e.g., a read instruction) via address lines 462 is compared by example compare logic 466 with all addresses (e.g., addr0, addr1, addr2, and addr3) in address store 464a. In the example described herein, compare logic 466 may compare the address of the read instruction with any number of entries, since addresses addr0, addr1, addr2, and addr3 may be fully or partially equivalent (e.g., the same). Thus, the example output of compare logic 466 is a 4-bit signal. Such a 4-bit signal is generated based on the corresponding byte enable signals in byten store 464b. Such a 4-bit signal may have any value (e.g., all 0s, all 1s, partial 0s, partial 1s, etc.).

[0152] In an example operation, the four addresses in address store 464a may contain one or more valid bytes (e.g., bytes that are logic high). In the example described herein, main cache store queue 212 is 64-bit (e.g., 8 bytes), and therefore main cache store queue 212 may perform writes to any number of bytes, such as 1 to 8.

[0153] In response to the compare logic 466 identifying addresses in the address store 464a to be included based on the byte enables in the byten store 464b, the example output lines 468 transmit an 8-bit result for each address in the address store 464a. In the example described herein, there are four output lines 468 (e.g., dram_hit_DP0[0][7:0]), dram_hit_dp0[1][7:0], dram_hit_dp0[2][7:0], and dram_hit_dp0[3][7:0]). In operation, a bit set to a logic high (e.g., 1) in any of the output lines 468 indicates that the corresponding byte at the corresponding address in the address store 464a has valid data to be transferred. For example, if the first output line of the output lines 468 includes dram_hit_dp0[0], the byte value for the corresponding read instruction can be obtained from any of the addresses in the address store 464a.

[0154] The example of FIG. 4B includes example select logic 470 and example select line 472. In the example described herein, select line 472 includes eight 2-byte outputs. Thus, there is one select signal for each corresponding byte enable of byte store 464c. In example operation, if a read instruction indicates to read multiple addresses having multiple valid bytes, example select logic 720 selects the most recent data. Such outputs of select logic 470 (e.g., select line 472) respectively control example multiplexers 474a-474h (multiplexers 474e-h are not shown). In the example of FIG. 4B, multiplexers 474a-h include eight 1-byte input terminals. In operation, multiplexers 474a-h receive respective select signals from select lines 472 indicating which byte of each of data stores 464c to transfer. In this manner, the main cache store queue 212 may forward data from different in-flight stores (e.g., either of the data stores 464c) based on the address comparison (e.g., the comparison performed by the comparator 466), the corresponding byte enables of the byten store 464b, and the order in which the main cache store queue 212 was issued (e.g., the comparison performed by the selection logic 470).

[0155] In the examples described herein, any of address line 462, address store 464a, byten store 464b, data store 464c, compare logic 466, output line 468, select logic 470, select line 472, and / or multiplexers 474a-h may be implemented in victim cache store queue 216. In FIG. 4B, the output terminals of multiplexers 474a-h are coupled to an example cache multiplexer 476. In the example of FIG. 4B, cache multiplexer 476 is also coupled to a similar multiplexer thus implemented in association with victim cache store queue 216. In operation, cache multiplexer 476 receives a select signal from the cache controller (e.g., main cache controller 222 or victim cache controller 224) that sent the read instruction. In this manner, cache multiplexer 476 facilitates data transfer to CPU 102.

[0156] 4B may correspond to example write data transfer components of the main cache store queue 212, the victim cache store queue 216, and the MUX circuits 314, 316. In such examples, the cache multiplexer 476 may be implemented by example MUX circuits 314, 316. Also, in such examples, any of address line 462, address store 464a, byten store 464b, data store 464c, comparison logic 466, output line 468, selection logic 470, select line 472, and / or multiplexers 474a-h may be implemented by example write data transfer components of main cache store queue 212, and address line 462, address store 464a, byten store 464b, data store 464c, comparison logic 466, output line 468, selection logic 470, select line 472, and / or multiplexers 474a-h may be implemented by example write data transfer components of victim cache store queue 216 as implemented in association with victim storage 216.

[0157] 4B may correspond to pending store address data store 418 and example priority multiplexer 418. For example, address store 464a, byten store 464b, and / or data store 464c may be implemented by example pending store address data store 416. In further examples, any of address line 462, comparison logic 466, output line 468, selection logic 470, selection line 472, and / or multiplexers 474a-h may be implemented by example priority multiplexer 418.

[0158] In the example described herein, the topology of Figure 4B is utilized for each bank of main storage 214 and victim storage 218. For example, if main storage 214 has eight banks, then the topology of Figure 4B is replicated eight times, once for each bank.

[0159] Described herein are exemplary methods, apparatus, systems, and articles of manufacture for facilitating fully pipelined read-modify-write support in a level 1 data cache using store queues and data forwarding. Further examples and combinations thereof include the following:

[0160] Example 1 includes a first storage, a second storage, and a store queue coupled to the first storage and the second storage, wherein the store queue is operable to receive a first memory operation identifying a first set of data, process the first memory operation to store the first set of data in at least one of the first storage and the second storage, receive a second memory operation, and feed back the first set of data for use in the second memory operation before storing the first set of data in at least one of the first storage and the second storage.

[0161] Example 2 includes the apparatus of example 1, wherein the second memory operation is a read-modify-write operation and identifies a second set of data, and the store queue is operable to merge the first set of data and the second set of data to generate a third set of data before storing the first set of data in at least one of the first storage and the second storage, and provide the third set of data for storing in at least one of the first storage and the second storage.

[0162] Example 3 includes the apparatus of example 2, further including receiving a third memory operation indicating reading a third set of data.

[0163] Example 4 includes the apparatus of example 1, wherein the second storage is configured as a victim storage for the first storage.

[0164] Example 5 includes the apparatus of example 1, wherein the store queue further includes a data store configured to store the first address value of the first set of data.

[0165] Example 6 includes the apparatus of example 1, wherein the store queue further includes an error code correction generator for generating an error detecting code.

[0166] Example 7 includes the apparatus of example 6, wherein the error code correction generator is for generating an error detection code in response to processing the first memory operation.

[0167] Example 8 includes a method, including receiving a first memory operation identifying a first set of data; processing the first memory operation to store the first set of data in at least one of a first storage and a second storage; receiving a second memory operation; and transmitting the first set of data for use in the second memory operation before storing the first set of data in at least one of the first storage and the second storage.

[0168] Example 9 includes the method of example 8, wherein the second memory operation is a read-modify-write operation and identifies a second set of data, and the method further includes merging the first set of data and the second set of data to generate a third set of data before storing the first set of data in at least one of the first storage and the second storage, and providing the third set of data for storing in at least one of the first storage and the second storage.

[0169] Example 10 includes the method of example 9, further including receiving a third memory operation indicating reading a third set of data.

[0170] Example 11 includes the method of example 8, wherein the second storage is configured as a victim storage for the first storage.

[0171] Example 12 includes the method of example 8, further including storing the first address value of the first set of data.

[0172] Example 13 includes the method of example 8, further including generating an error detecting code.

[0173] Example 14 includes the method of example 13, further including generating an error detection code in response to processing the first memory operation.

[0174] Example 15 includes a system including a central processing unit configured to transmit a first memory operation and a second memory operation, a first storage coupled to the central processing unit, a second storage coupled to the central processing unit, and a store queue coupled to the first storage, the second storage, and the central processing unit, wherein the store queue is operable to receive the first memory operation to identify a first set of data, process the first memory operation to store the first set of data in at least one of the first storage and the second storage, receive the second memory operation, and feed back the first set of data for use in the store second memory operation before storing the first set of data in at least one of the first storage and the second storage.

[0175] Example 16 includes the system of Example 15, wherein the second memory operation is a read-modify-write operation and identifies a second set of data, and the store queue is operable to merge the first set of data and the second set of data to generate a third set of data before storing the first set of data in at least one of the first storage and the second storage, and provide the third set of data for storing in at least one of the first storage and the second storage.

[0176] Example 17 includes the system of example 16, further including receiving a third memory operation indicating reading a third set of data.

[0177] Example 18 includes the system of example 15, wherein the second storage is configured as a victim storage for the first storage.

[0178] Example 19 includes the system of example 15, wherein the store queue further includes a data store configured to store the first address value of the first set of data.

[0179] Example 20 includes the apparatus of example 15, wherein the store queue further includes an error code correction generator for generating an error detection code in response to processing the first memory operation.

[0180] Method and apparatus for reducing read-modify-write cycles for misaligned writes - Patents.com

[0181] When issuing a write instruction to a multi-bank storage system, such a write instruction may be sent along with a corresponding read instruction, regardless of the size of the write instruction, in order to perform a complete read-modify-write cycle of such a write instruction. For example, in such an application, a write instruction may be obtained by a CPU indicating a 128-bit write across two 64-bit memory banks, beginning at address A0 of the first memory bank. In such an example, both example memory banks are written in their entirety, but such an application maintains a read instruction to read the data currently stored in the two example memory banks. However, such an approach is inefficient because it uses twice the processing power (e.g., for the write and read instructions). Also, such an approach does not provide control logic and / or processing circuitry for analyzing the write instruction.

[0182] 4A , main storage 214 and / or victim storage 218 may be multi-bank storage. For example, main storage 214 may include 16 memory banks (e.g., 16 sub-RAMs), each 64 bits wide. In such an example, if cache controller 220 sends a write instruction to write all 64 bits of a first bank of main storage 214 (e.g., to write a 64-bit word starting at a first address in the first bank), the write instruction may be performed without initiating a read instruction. For example, bank processing logic 303 may detect that such a write of the entire bank is to be performed and, therefore, may indicate to cache controller 220 to disable sending the read instruction and initiate a read-modify-write operation.

[0183] Similarly, if cache controller 220 sends a write instruction to write port 426 to write the entire 128 bits of a first bank and a second bank of main storage 214 (e.g., a write instruction indicating to write a 128-bit word beginning at a first address in the first bank and ending at the last address in the second bank), the write instruction may be implemented without initiating a read instruction. For example, bank processing logic 303 may detect that such a write of multiple entire banks is to be performed and therefore may indicate to cache controller 220 to initiate a read-modify-write operation and may disable sending of the read instruction.

[0184] However, in some examples described herein, cache controller 220 may send a write instruction to write 130 bits of data (or any write instruction indicating a write to a subset of memory banks). Of the 130 bits of data, 64 bits of data may be written to a first bank, 64 bits of data may be written to a second bank, and 2 bits of data may be written to a third bank of main storage (e.g., a write instruction indicating a 130-bit word may begin at a first address in the first bank and end at a second address in the third bank). In such an example, bank processing logic 303 may detect that all addresses in the first and second banks of main storage 214 should be completely written and therefore indicate to the cache controller to initiate a read-modify-write operation for the first and second banks of main storage and disable sending of the read instruction. In such an example, the bank processing logic 303 may detect (e.g., determine) that a subset of the memory banks of main storage 214 (e.g., the third bank of memory storage) should be partially written (e.g., two addresses out of 64 addresses should be written) and therefore indicate to cache controller 220 to initiate a full read-modify-write operation for the third bank of main storage 214. In the example described herein, the bank processing logic 303 determines whether to perform a read operation in response to a write operation (e.g., whether to initiate a full read-modify-write operation) based on whether some addresses in the subset of memory banks being written meet a threshold. In the example described herein, if the number of addresses in the subset of memory banks is greater than zero and / or less than the number of addresses in the memory bank, the threshold is not met. In this example, the bank processing logic 303 generates an instruction to CPU 102 to execute the write instruction as a full read-modify-write transaction.In the example described herein, the threshold is met when the number of addresses in the subset of the plurality of memory banks equals the number of addresses in the memory bank, which in this example is n, and the bank processing logic 303 generates an instruction to the CPU 102 to execute the write instruction as a partial read-modify-write transaction (e.g., void read). An example description of a read-modify-write operation is provided above.

[0185] Described herein are exemplary methods, apparatus, systems, and articles of manufacture for reducing read-modify-write cycles for non-consistent writes. Further examples and combinations thereof include:

[0186] Example 1 includes an apparatus, the apparatus including the memory including a plurality of memory banks, an interface configured to be coupled to a central processing unit for receiving a write operation from the central processing unit, the write operation being to write a subset of the plurality of memory banks, and bank processing logic coupled to the interface and the memory, the bank processing logic for determining a subset of the plurality of memory banks to write to based on the write operation, and for determining whether to cause a read operation to be performed in response to the write operation based on whether some addresses in the subset of the plurality of memory banks to write to satisfy a threshold.

[0187] Example 2 includes the apparatus of example 1, wherein the threshold is met when all addresses of at least one memory bank of the plurality of memory banks are included in the write operation.

[0188] Example 3 includes the apparatus of Example 1, wherein the bank processing logic is to generate a second instruction to the central processing unit to perform a write operation to at least one of the plurality of memory banks by issuing a read operation when a number of addresses of at least one of the plurality of memory banks to write to does not meet a threshold.

[0189] Example 4 includes the apparatus of example 1, wherein the bank processing logic determines the number of the plurality of memory banks to write to based on the write operation by determining a total number of addresses included in the write operation and determining the number of the plurality of memory banks based on having an address included in the total number of addresses.

[0190] Example 5 includes the device of example 1, wherein the write operation indicates a number of memory banks to rewrite.

[0191] Example 6 includes the apparatus of example 1, wherein the plurality of memory banks is 16 memory banks.

[0192] Example 7 includes the apparatus of example 1, wherein the memory is the sacrificial storage.

[0193] Example 8 includes a system, the system including: a central processing unit configured to generate a write operation indicating writing to a subset of a plurality of memory banks; a victim storage including a plurality of memory banks; and bank processing logic coupled to the central processing unit and the victim storage, the bank processing logic for determining the subset of the plurality of memory banks to write to based on the write operation, and for determining whether to cause a read operation to be performed in response to the write operation based on whether some addresses in the subset of the plurality of memory banks to write to satisfy a threshold.

[0194] Example 9 includes the system of example 8, wherein the threshold is met when all addresses of at least one memory bank of the plurality of memory banks are included in the write operation.

[0195] Example 10 includes the system of Example 8, wherein the bank processing logic is for generating a second instruction to the central processing unit to perform a write operation to at least one of the plurality of memory banks by issuing a read operation when a number of addresses of at least one of the plurality of memory banks to write to does not meet a threshold.

[0196] Example 11 includes the operations of example 10, wherein the central processing operations are further for generating, in response to the second instruction, a read-modify-write operation to be performed by at least one of the plurality of memory banks.

[0197] Example 12 includes the system of example 8, wherein the bank processing logic determines the number of the plurality of memory banks to write to based on the write operation by determining a total number of addresses included in the write operation and determining the number of the plurality of memory banks based on having an address included in the total number of addresses.

[0198] Example 13 includes a method that includes determining, based on a write operation, a subset of a plurality of memory banks of a memory to write to; and determining, based on whether a plurality of addresses in the subset of the plurality of memory banks to write to satisfy a threshold, whether to cause a read operation to be performed in response to the write operation.

[0199] Example 14 includes the method of example 13, further including sending an indication to the central processing unit in response to the threshold being met.

[0200] Example 15 includes the method of example 13, wherein the threshold is met when all of the addresses of at least one memory bank of the plurality of memory banks are included in the write operation.

[0201] Example 16 includes the method of Example 13, further including generating a second instruction to perform a write operation to at least one of the plurality of memory banks by issuing a read operation when a number of addresses of the at least one memory bank of the plurality of memory banks to write does not meet a threshold.

[0202] Example 17 includes the method of example 13, determining the number of memory banks to write to by determining a total number of addresses included in the write operation and determining the number of memory banks based on having an address included in the total number of addresses.

[0203] Example 18 includes the method of example 13, wherein the write operation indicates a number of the plurality of memory banks to be rewritten.

[0204] Example 19 includes the method of example 14, further including receiving a write operation from the central processing unit, the write operation indicating a number of the plurality of memory banks to write to.

[0205] Example 20 includes the method of example 14, wherein the memory is sacrificial storage.

[0206] Aggressive write merging to reduce bank pressure

[0207] 4A, the example main cache store queue 212 stores several write operations in different sections (e.g., example latches 402a-e) of the main cache store queue 212. For example, if the CPU 102 sends three separate write operations in a row, the first write operation provided by the CPU 102 is stored in the first latch 402b and moved to the second latch 402c when the second operation is received at the first latch 402b. Thus, after the three write operations are received, the first latch 402b may store and / or output the last write operation in time (e.g., the one last stored in main storage 214), the second latch 402c may contain the second write operation (e.g., the one second stored in main storage 214), and the third latch 402d may contain the first write operation (e.g., the one first stored in main storage 214). Whenever data in main cache store queue 212 is next to be stored to main storage 214, the example arbitration manager 414 reserves a cycle for the data to be written to the example main storage 214. Thus, during the reserved cycle, main storage 214 may not be available to perform a read operation. However, if data operations stored in two or more of latches 402b, 402c, 402d correspond to the same memory address, the data may be merged to write the data to the memory address in main storage 214 in one go, rather than two or three goes. For example, if a write operation stored in latch 402d corresponds to writing a byte at a memory address and a write operation stored in latch 402c corresponds to writing the same byte to the memory address, the second write may overwrite the first write.

[0208] Instead of reserving a cycle to write the first byte to be overwritten in a subsequent cycle to main storage 214, main cache store queue 212 merges the two writes into one write so that only one cycle is used to write the second transaction (e.g., no cycle is reserved for the first write). Such aggressive merging reduces the number of cycles reserved for write operations. In this way, main storage 214 has extra cycles to perform read operations, thereby reducing overall system latency.

[0209] To enable proactive merging of write operations to the same memory address, the outputs of example latches 402b-402d are coupled to example merge circuits 403a-403c. For example, the output of the third latch 402d may be coupled to merge circuit 403a, the output of the second latch 402c may be coupled to merge circuit 403b, and the output of the first latch 402b may be coupled to merge circuit 403c. The output of merge circuit 403a may additionally be coupled to the outputs of the second latch 402c and merge circuit 403b, which may be coupled to merge circuit 403c, which may be coupled to the input of the first latch 402b. Additionally or alternatively, there may be additional comparator circuits that compare the outputs of different sets of latches (e.g., a comparator circuit that compares the output of latch 402b with the output of latch 402d). Example merge circuits 403a-c include an example comparator 420 and an example switch 422.

[0210] Comparator 420 compares the memory address locations of each write operation stored in each latch 402b-402d to determine whether any of the write operations in the example store queue correspond to the same memory address. The example comparator 420 may be a single comparator for comparing all of the write operations in latches 402b-402d, or may be separate comparators 420 that compare two of latches 402b-d (e.g., a first comparator between the memory address of latch 402b and the memory address of latch 402c, a second comparator between the memory address of 402b and the memory address of latch 402d, etc.). Comparator 420 outputs the results of the comparisons (e.g., in one or more signals corresponding to the one or more comparisons) to example switch 422 and / or arbitration manager 414. If the example arbitration manager 414 receives a signal indicating a match, the arbitration manager 414 does not reserve cycles for the first write operation, and the first write operation is merged with the second write operation to the same memory location (e.g., to free up cycles for other cache operations).

[0211] The example switch 422 redirects the write operation in the example latches 402b-402d based on the comparison. For example, if the memory address of the write operation stored in the example latch 402d is the same as the memory address stored in the latch 402c, the example switch 422 enables and / or disables the output of the latch 402d to be redirected to the latch 402c instead of being routed to the example arbitration manager 414. In this manner, the two write operations are combined and written to the main storage 214 in a subsequent cycle as a single write operation instead of two write operations. The switch 422 may be an electrical switch, a transistor (e.g., a MOSFET), a demultiplexer, and / or any other component capable of redirecting a signal in a circuit.

[0212] When a MUX in one of merge circuits 403a-c receives a rerouted write operation, the MUX implements a merging protocol for the one or more rerouted write operations that prioritizes the most recent write operation. For example, if comparator 420 determines that the write operation stored in example latch 402c corresponds to the same memory address as the write operation stored in example latch 402d, the MUX in comparator 420 merges the data (as further described in connection with FIG. 4D ), and switch 422 reroutes the merged write operation stored in example latch 402d to latch 402c. In this example, if the write operation in example latch 402c corresponds to writing data to bytes 0 and 2 of a memory address and the write operation from latch 404d corresponds to writing data to bytes 0 and 1, example merge circuit 403a will retain the write data stored in latch 402c (e.g., writes to byte 0 and byte 2) and merge these two write operations to include the non-overlapping write data from latch 402d (e.g., byte 2). In this example, merge circuit 403a discards the write data for byte 0 from latch 404d as part of the merge operation because the data to be written in byte 0 from latch 404d would be overwritten by the write instruction for latch 402c. Thus, in the above example, the merged data corresponds to the write data for byte 0 from latch 402c, the write data for byte 1 from latch 404d, and the write data for byte 2 from latch 402c. When a subsequent write operation is added to the main cache store queue 212, the merged write data from latch 402c may be manipulated (e.g., via one of example blocks 404, 406, 408) and / or pushed to the next latch 402d to be stored in example main storage 214 during a subsequent cycle. An example hardware implementation of the merge protocol is further described below in connection with FIG. 4D.

[0213] FIG. 4D illustrates a hardware implementation of merge circuit 402c of FIG. 4A and / or 1102c of FIG. 11A (e.g., for merging data from latch 402d to latch 402c). A similar hardware setup can be implemented to merge data between any two latches. The example of FIG. 4D includes example latches (e.g., stores) 402b-402d and hardware components for comparator 420 and switch 422 of FIG. 4A. Example comparator circuit 420 includes comparators and / or logic gates 480a-480f, and switch circuit 422 includes OR gate 482 and MUX 484. Although described in connection with FIG. 4A, latches 1102a-d, example comparator 1120, and example switch 322 of FIG. 11A could be used when described in connection with victim cache store queue 216 of FIG. 11A.

[0214] In the example of FIG. 4D, example latch 402d outputs stored data to example storage (e.g., main storage 214 or victim storage 218 via arbitration manager 414, 1114), which locks the bank for the first cycle. FIG. 4D illustrates a write merge that locks old data in a bank of storage when another store / latch containing new write data to the same address precedes the old data. While the example of FIG. 4C illustrates a merge between example latch 402d and example latch 402c, a similar structure can be used to merge data between any of latches 402a-402d. For example, if the address of the data in latch 402d matches the address of the data in latch 402b, latch 402 can merge its data with the data in latch 402b. Also, if the data in three or more latches corresponds to the same address, the data in the three or more latches can be merged into a single latch. As described above, when the data in a particular latch is merged with the data and the preceding latch, the data in the particular latch is invalid (e.g., by setting a bit corresponding to an invalidated value) or is discarded, so that no arbitration is performed for that data to be locked into a bank in storage.

[0215] In operation, example comparator 480b compares the address of the data in latch 402d with the address of the data in latch 403c. The output of comparator 480b is valid only if both latches 402c and 402d contain bits set to valid. Therefore, example comparator 480a compares the valid bits from latches 402c and 402d to ensure that both bits are valid. In this manner, example comparator 480d outputs a value (e.g., "1") only if the address in latch 402c and the address in latch 402d are the same and the valid bits of both latches 402c and 402d are valid. Otherwise, example comparator 480d outputs a second value ("0"). The output of comparator 480d is input to the select line of MUX 484 of switch 422. Therefore, if the addresses of latches 402c and 402d have the same value, comparator 480d controls MUX 484 of switch 422 to output the merged data (eg, from OR gate 482 of switch 422).

[0216] The example ADD gate 480c performs a logical AND function (e.g., using a NOT gate) with the byten of latch 402d but not with the byten of latch 402c. The output of the example ADD gate 480c ensures that if there is a byte being written by both latches 402c and 402d, latch 402c is held and latch 402d is ignored because latch 402c has the most recent store issued by CPU 102. Therefore, the example comparator 480f outputs only the most recent store issued by CPU 102 for addresses in the store queue. The output of comparator 480f corresponds to dram_mrg_data_sel[7:0], which is the signal used to select the final merged data between logic gate 402d and logic gate 402c on a byte-by-byte basis. Similar merging logic exists when merging the byten of latch 402c and latch 402d. As above, the signal marked (1) is used to select between store_byten or (store3_byten merged with store_4_byten).

[0217]

[0009] Example methods, apparatus, systems, and articles of manufacture for facilitating aggressive write merging to reduce bank pressure are described herein. Further examples and combinations thereof include the following. Example 1 includes an apparatus, the apparatus including: a first cache storage; a second cache storage; and a store queue coupled to at least one of the first cache storage and the second cache storage, the store queue operable to receive a first memory operation, process the first memory operation to store a first set of data in at least one of the first cache storage and the second cache storage, receive a second memory operation, and merge the first memory operation with the second memory operation before storing the first set of data in at least one of the first cache storage and the second cache storage.

[0218] Example 2 includes the apparatus of Example 1, wherein the first memory operation identifies a first set of data, the second memory operation identifies a second set of data, and the store queue is operable to merge the first set of data and the second set of data to generate a third set of data before storing the first set of data in at least one of the first cache storage and the second cache storage, and provide the third set of data for storing in at least one of the first cache storage and the second cache storage.

[0219] Example 3 includes the apparatus of example 2, wherein the store queue is for storing the third set of data in at least one of the first cache storage or the second cache storage in one cycle.

[0220] Example 4 includes the apparatus of example 1, wherein the store queue is operable to merge the first memory operation with the second memory operation by canceling a portion of the first memory operation.

[0221] Example 5 includes the apparatus of example 4, wherein the portion of the first memory operation is a byte that the second memory operation writes.

[0222] Example 6 includes the apparatus of example 4, wherein the portion is a first portion, and the store queue is operable to merge the first memory operation and the second memory operation by maintaining a second portion of the first memory operation.

[0223] Example 7 includes the apparatus of example 6, wherein the second portion of the first memory operation is a byte that the second memory operation does not write.

[0224] Example 8 includes the apparatus of example 1, wherein the first cache storage is a main cache storage and the second cache storage is a victim cache storage.

[0225] Example 9 includes a system including: a central processing unit coupled in parallel to a first cache storage and a second cache storage; and a store queue coupled to at least one of the first cache storage and the second cache storage, the store queue for processing a first memory operation from the central processing unit, the first memory operation being to store a first set of data in at least one of the first cache storage and the second cache storage, and for merging the first memory operation with a second memory operation corresponding to the same memory address before storing the first set of data in at least one of the first cache storage and the second cache storage.

[0226] Example 10 includes the system of Example 9, wherein the first memory operation identifies a first set of data, the second memory operation identifies a second set of data, and the store queue is operable to merge the first set of data and the second set of data to generate a third set of data before storing the first set of data in at least one of the first cache storage and the second cache storage, to provide the third set of data for storing in at least one of the first cache storage and the second cache storage.

[0227] Example 11 includes the apparatus of example 10, further including a store queue configured to store the third set of data in at least one of the first cache storage or the second cache storage in one cycle.

[0228] Example 12 includes the system of example 9, wherein the store queue is operable to merge the first memory operation with the second memory operation by canceling a portion of the first memory operation.

[0229] Example 13 includes the system of example 12, wherein the portion of the first memory operation is a byte that the second memory operation writes.

[0230] Example 14 includes the system of example 12, wherein the portion is a first portion, and the store queue is operable to merge the first memory operation and the second memory operation by maintaining a second portion of the first memory operation.

[0231] Example 15 includes the system of example 14, wherein the second portion of the first memory operation is a byte that the second memory operation does not write.

[0232] Example 16 includes the system of example 9, wherein the first cache storage is a main cache storage and the second cache storage is a victim cache storage.

[0233] Example 17 includes a method, the method including: obtaining a first memory operation; processing the first memory operation by executing instructions with a processor to store a first set of data in at least one of a first cache storage and a second cache storage; obtaining a second memory operation; and merging the first memory operation and the second memory operation by executing instructions with the processor before storing the first set of data in at least one of the first cache storage and the second cache storage.

[0234] Example 18 includes the method of Example 17, wherein the first memory operation corresponds to the first set of data and the second memory operation corresponds to the second set of data, the method further including, before storing the first set of data in at least one of the first cache storage and the second cache storage, merging the first set of data and the second set of data to generate a third set of data, and providing the third set of data for storing in at least one of the first cache storage and the second cache storage.

[0235] Example 19 includes the method of example 18, further including storing the third set of data in at least one of the first cache storage or the second cache storage in one cycle.

[0236] Example 20 includes the method of example 17, further including merging the first memory operation and the second memory operation by canceling a portion of the first memory operation.

[0237] Optimized atomic operations and histogram calculation support in L1 cache

[0238] An atomic operation is a further example of a multi-part memory operation. For example, an atomic compare and swap operation manipulates a value stored in a memory location based on the result of a comparison of an existing value stored at that memory location. For example, CPU 102 may want to replace data stored in L1 cache 110 with a new value if the existing value stored in L1 cache 110 matches a particular value.

[0239] In some example systems, when a CPU wanted to perform an atomic operation, the CPU would send a read operation to a memory address, perform the operation on the read data, and then perform a write operation to the same memory address to store the manipulated data. Also, in such example systems, the L1 cache would suspend, reject, block, and / or stall transactions from other devices (e.g., other cores of the CPU, higher-level caches, extended memory, etc.) until the atomic operation was complete (e.g., to avoid manipulating the memory address corresponding to the atomic operation during the atomic operation). Thus, such example approaches required a lot of effort on behalf of the CPU and many reserved cycles that increased latency.

[0240] 4A , the example main cache store queue 212 handles atomic operations in conjunction with a read-modify-write structure. In this manner, the example CPU 102 can send a single atomic operation to the L1 cache 110, and the main cache store queue 212 processes the atomic data manipulation and write operation. Thus, the CPU 102 can utilize a single cycle to perform the atomic operation and use other cycles (e.g., as used in some example atomic protocols) to perform other functions, thereby reducing the overall latency of the computing system 100.

[0241] In operation, for example, when CPU 102 sends an atomic operation and / or an atomic compare and swap operation to increment and / or swap data at a memory address, for example, by a value of one, tag RAM 208, where the atomic instruction is received by latch 402a, verifies whether the memory address is stored in example main storage 214. If the memory address is stored in example main storage 214, tag RAM 208 instructs example main storage 214 to output the data at the memory address, while the atomic instruction is passed to example latch 402b. Example latch 402b outputs the atomic operation to latch 402c, while main storage 214 outputs the data to latch 402a. At this point, ECC logic 310 implements an error detection and / or correction protocol as described above, and the data from the memory address location is forwarded to example compute component 404 (e.g., for an atomic operation) or atomic compare component 406 (e.g., for an atomic compare and swap operation). The computation component 404 may obtain the atomic operation (e.g., including data for identifying how to operate on the data) and / or the atomic compare and swap 406 may obtain the atomic compare and swap operation (e.g., including a key and data to write if the key matches the outgoing data) from the latch 402c and obtain the data from the corresponding memory address from the output of the ECC logic 310. The computation component 404 may perform the operation on the data (e.g., increment the data by 1) and / or the atomic compare component 406 may perform the swap (e.g., replace the data if the read data matches the key) and output the incremented and / or swapped-in data for the corresponding memory address (e.g., the atomic result) to the example latch 402d via the example MUX 410 (e.g., this may be enabled via the cache controller 220).Latch 402d outputs the new data corresponding to the memory address to ECC generator 412 for generating ECC bits, and arbitration manager 414 writes the new data (e.g., the atomic result and / or the atomic compare and swap result) to the memory address along with the ECC bits in exemplary main storage 214. Additionally or alternatively, the corrected value from EDD logic 412 is returned to CPU 102. Thus, the atomic operation is performed with only one instruction from CPU 102.

[0242] The atomic comparison component 406 and / or the computation component 404 have several inputs. For example, the atomic component 406 receives (e.g., obtains) the type of atomic operation to perform (e.g., atomic compare and swap or atomic swap), the ECC-corrected data read from the cache 310, and the size of the data to be operated on during the atomic operation (e.g., 32 bits or 64 bits). In the example circuit implementation 450 of FIG. 4B, the atomic comparison component 406 receives the atomic compare and swap operation, and the computation component 404 receives the atomic operation. The atomic comparison component 406 compares a comparison value (e.g., a key) provided by the CPU 102 with the ECC data 310. If there is a match, the new data is swapped in place of the old data (e.g., ECC data 310) and output to the MUX 410. The size of the new data to be swapped in is determined by the cas_acc_sz input (e.g., 32 bits or 64 bits). In the example circuit implementation 450 of FIG. 4C , the atomic comparison component 406 may also receive an atomic swap operation. The atomic comparison component 406 swaps in new data to replace the ECC data 310 regardless of the comparison result, outputs the new value to mux 410, and the old data from the address is read from main storage 214 and returned to CPU 102. The size of the new data swapped in is determined by the cas_acc_sz input (e.g., 32 bits or 64 bits). In the example circuit implementation 450 of FIG. 4C , the computation component 404 may receive an atomic operation. The computation component 404 manipulates the ECC data 310 and stores the manipulated data in the main storage element 214. The size of the new data swapped in is determined by the cas_acc_sz input (e.g., 32 bits or 64 bits). Although the example circuit 450 of FIG. 4C is described above in relation to a main store queue, the circuit 450 can also be described in relation to a victim store queue, as described further below in relation to FIG. 11A.

[0243] Figure 4C illustrates an example circuit diagram of a portion of the main cache store queue 212 of Figure 4A and / or a portion of the victim cache store queue 216 of Figure 11 A. Figure 4C illustrates a detailed circuit diagram of an arithmetic unit 404, 1104.

[0244] The arithmetic unit 404 may be used for other types of memory transactions, such as histogram operations. A histogram operation takes values ​​stored in memory that may represent bins of a histogram, and modifies the values ​​before storing them back at the same memory address or an alternate address. In one example, a first data set includes values ​​[0, 0, 2, 0, 0, 3], and a second set of data includes bins representing the number of occurrences of each value in the first data set. In some exemplary systems without the arithmetic unit 404, to perform the histogram function, the CPU reads each value in the first data set and increments the second set of data for each value. For example, to determine the number of zeros stored in a 10-byte data set, the CPU may perform 10 reads. Then, to determine the number of ones in the same data set, the CPU may perform another 10 reads. Thus, to perform a histogram operation, such a system may need to perform (N)(M) reads, where N is the size of the section of memory being read (e.g., 10 bytes) and M is the number of values ​​that may be stored in each byte. Similar to an atomic operation, the L1 SRAM may have to block, pause, stop, or discard all other read and / or write operations until the histogram operation is complete, whereas the computation unit 404 may be used to perform the same operation in a single transaction from the CPU.

[0245] The computation unit 404, 1104 has several inputs including histogram type (e.g., weighted or incremental, signed or unsigned), histogram size (e.g., byte, halfword, or word), histogram weight (e.g., signed weight added for each selected bin of a weighted histogram, weight equal to 1 in normal histograms), histogram sign (e.g., existing big signed or unsigned), and histogram saturation enable.

[0246] Component 451 in FIG. 4C selects the bins read from ECC component 310 for the bank shown in FIG. 4C. Component 452 selects the weights to be added to the bins from a vector of weights provided by CPU 102. Cnt_value is the sum of the bin value from component 451 and the weight provided by CPU 102. Components 453, 454, and 458 are used as part of the saturation circuitry. Component 453 receives the histogram size (byte, halfword, or word) and the count value (the sum of the outputs of components 451 and 452) and determines whether signed bins will saturate. Component 454 receives the histogram size (byte, halfword, or word) and the count value (the sum of the outputs of components 451 and 452) and determines whether unsigned bins will saturate. The outputs of components 453 and 454 are sent to a MUX that selects whether to use signed or unsigned saturation values ​​based on the type of bin selected (e.g., signed or unsigned). Component 458 receives the output of the MUX, the histogram saturation enable, the histogram type (e.g., signed or unsigned), the bin sign bit, and the weight sign bit, and outputs an updated Cnt_value adjusted for the selected saturation type (e.g., based on Table 1 above). Components 455, 456, and 457 are used to position the resulting cnt_value and the byte enables in the correct bit positions to write the new data bank to the correct bins.

[0247] 4A, the CPU 102 commands the main storage 214 to perform a histogram operation, which changes the number of cycles the CPU 102 must reserve for an operation from (N)×(M) to 1. Also, because the atomic operation protocol is already implemented in the store queue, the histogram operation can be performed using the operation component 404 by performing N reads for N sizes of memory and incrementing a count for each value in the example main cache store queue 212, thereby reducing the number of read operations from (N)×(M) operations to N operations.

[0248] In operation, when CPU 102 sends a histogram calculation corresponding to a section (e.g., an SRAM line) of main storage 214, the histogram calculation is stored in example latch 402a while tag RAM 208 verifies whether the memory address corresponding to the histogram calculation is available in main storage 214. Example cache controller 220 facilitates a read operation for each byte of the section identified in the histogram calculation (e.g., histogram bins are accessed in parallel by reading up to 128 bytes at a time). If available, tag RAM 208 instructs main storage 214 to output the data in the first byte of the section of main storage 214 while the histogram calculation is output by example latch 402a to example latch 402b. When example main storage 214 outputs the data read from the memory address to example latch 402a, latch 402b outputs the histogram calculation to example latch 402c. After the ECC logic 310 performs error detection and correction functions, the data read in bytes is sent to the exemplary computation component 404 .

[0249] After receiving the read value from ECC logic 310 and the histogram command from latch 402c, the computation component 404 initiates data representing the histogram. For example, the computation component 404 may initiate a vector (e.g., representing the histogram) with an initial value (e.g., zero) for each possible value that can be stored in a byte of main storage. The computation component 404 increments the value of the vector based on the output (e.g., read byte) by the ECC logic 310. For example, if the read value of the byte is 0, the computation component 404 increments the value corresponding to 0 in the vector.

[0250] As each vector is incremented in parallel, the resulting vector corresponds to a histogram of values ​​read in parallel in the corresponding section of SRAM. As a histogram value is incremented for each bit, the resulting vector is a histogram of values ​​stored in the section of memory identified in the histogram operation from CPU 102. In some examples, the calculation component 404 may increment in parallel by some weighted value (e.g., 1.5). Upon completion, the example histogram is input to the example MUX 418 (e.g., controlled by the example pending store address table 416) for input to MUX 314 via example latch 402e. Upon completion of the operation, the example cache controller 220 controls MUX 314 to output the final histogram vector to the example CPU interface 202 via example latch 322b, thereby completing the histogram operation.

[0251] In some examples, the L1 cache 110 supports functionality that allows histogram bins to saturate after they exceed a threshold limit for bin size (e.g., byte, halfword, word, etc.). Table 1 below shows example saturation values. With this functionality, histogram bin values ​​do not roll over once they reach their maximum value. TIFF2026012814000002.tif59136

[0252]

[0013] Exemplary methods, apparatus, systems, and articles of manufacture for facilitating optimized atomic operations and histogram operations are described herein. Further examples and combinations thereof include the following. Example 1 includes a system, the system including a cache storage coupled to a computing component; and a cache controller coupled to the cache storage, the cache controller operable to receive a memory operation identifying a set of data, retrieve the set of data from the cache storage, utilize the computing component to determine a set of counts of each value in the set of data, generate a vector representing the set of counts, and provide the vector.

[0253] Example 2 includes the system of example 1, wherein the cache controller is operable to provide the vector for storage in the cache storage.

[0254] Example 3 includes the system of example 1, wherein the cache controller is operable to provide the vector to the processor.

[0255] Example 4 includes the system of example 1, further including a store queue coupled to the cache controller, the store queue including an arithmetic component.

[0256] Example 5 includes the system of example 1, wherein the cache storage is at least one of a main cache storage or a victim cache storage.

[0257] Example 6 includes the system of Example 1, wherein the computing component is for (a) retrieving a set of data from cache storage via error detection and correction circuitry and (b) retrieving a memory operation from the central processing unit via a latch.

[0258] Example 7 includes the system of example 1, wherein the cache controller is operable to provide the vector to the central processing unit based on a single instruction from the central processing unit in a single cycle.

[0259] Example 8 includes a system, the system including cache storage; and a cache controller coupled to the cache storage and the computing component, the cache controller operable to receive a memory operation identifying a first set of data and an operational operation, retrieve the first set of data from the cache storage, perform the operational operation on the first set of data utilizing the computing component to generate a second set of data, and provide the second set of data.

[0260] Example 9 includes the system of example 8, wherein the cache controller is operable to provide a second set of data for storage in the cache storage.

[0261] Example 10 includes the system of example 8, wherein the cache controller is operable to provide the second set of data to the processor.

[0262] Example 11 includes the system of example 8, further including a store queue coupled to the cache controller, the store queue including an arithmetic component.

[0263] Example 12 includes the system of example 8, wherein the cache storage is at least one of a main cache storage or a victim cache storage.

[0264] Example 13 includes the system of Example 8, wherein the computing component is for (a) retrieving the first set of data from the cache storage via the error detection and correction circuitry, and (b) retrieving the memory operation from the central processing unit via the latch.

[0265] Example 14 includes the system of example 8, wherein the cache controller is operable to provide the second set of data to the central processing unit based on a single instruction from the central processing unit in a single cycle.

[0266] Example 15 includes a method, the method including obtaining a memory operation identifying a set of data, obtaining the set of data from cache storage, determining a set of counts of each value in the set of data, generating a vector representing the set of counts, and providing the vector.

[0267] Example 16 includes the method of example 15, wherein the vector is provided to cache storage.

[0268] Example 17 includes the method of example 15, wherein the vector is provided to a processor.

[0269] Example 18 includes the method of example 15, wherein the cache storage is at least one of a main cache storage or a victim cache storage.

[0270] Example 19 includes the method of example 15, further including (a) retrieving the set of data from the cache storage via the error detection and correction circuitry; and (b) retrieving the memory operation from the central processing unit via the latch.

[0271] Example 20 includes the method of example 15, wherein providing the vector to the central processing unit is based on a single instruction from the central processing unit in a single cycle.

[0272] Atomic compare and swap support in L1 caches for coherent systems

[0273] When data from an address is stored in the L1 cache 110, data for the same address may also be cached in other caches (e.g., the L2 cache 112 and / or the L3 cache 114). Therefore, memory addresses need to be tracked and / or monitored to ensure that any changes to data in one cache are identified, tracked, and / or reflected in the other caches (e.g., the L2 cache 112 and the L3 cache 114). As described above in connection with FIGS. 3A-3D , the example MESI RAM 300 may track the state of data stored in the main storage 214 to avoid problems with inconsistent data in different caches corresponding to the same memory address. For example, if the CPU 102 sends a read operation, the example MESI RAM 300 changes the state of the memory address to shared because the data in the memory address is not manipulated. If the CPU 102 sends a write operation, the example MESI RAM 300 changes the state of the memory address to exclusive because the data in the memory address is manipulated and the main storage 214 requires write permission for the address. After the data in the memory address is written to main storage 214, MESI RAM 300 updates the status of the memory address to modified (eg, indicating that the memory address has been modified).

[0274] As described above, during the atomic and / or histogram protocols, data from a memory address is read from main storage 214, provided to main cache store queue 212, updated (e.g., incremented), and written back to main storage 214. However, if MESI RAM 300 identifies the state of the corresponding memory address as a shared state, the write operation of the atomic protocol may cause problems for other levels of cache (e.g., because the write causes data inconsistencies in different caches).

[0275] To avoid such data inconsistencies during atomic operations (e.g., including atomic compare and swap), the example cache controller 220 marks a cache hit corresponding to a shared state as a cache miss. In this manner, the cache controller 220 may instruct the L2 interface 228 to send the cache miss to the higher level cache with an exclusive state request. In this manner, the higher level cache may grant the exclusive state to the L1 cache 110, which may perform read and write operations as part of the atomic operation in response to receiving the granted exclusive state.

[0276] After a cache miss with an exclusive request is sent to a higher level cache and the higher level cache responds with the write data and an exclusive response, the example atomic operation logic 406 directs the MESI RAM 300 to tag the data as modified. The data received from the L2 cache 112 is sent to the main cache store queue 212 and stored in main storage 214. Because the operation was an atomic operation (e.g., a regular atomic operation or an atomic compare and swap) or histogram protocol, the data from the higher level cache is manipulated by the example computation component 404 and / or the example atomic comparison component 406 for manipulation and stored in the example main storage 215 via the example ECC generator 412 and the example arbitration manager 414.

[0277]

[0013] Example methods, apparatus, systems, and articles of manufacture for facilitating atomic compare and swap are described herein. Further examples and combinations thereof include the following. Example 1 includes a system, the system including a cache storage and a cache controller coupled to the cache storage, the cache controller operable to: receive a memory operation identifying a key, a memory address, and a first set of data; retrieve a second set of data corresponding to the memory address; compare the second set of data with the key; cause the first set of data to be stored at the memory address based on the second set of data corresponding to the key; and complete the memory operation without storing the first set of data at the memory address based on the second set of data not corresponding to the key.

[0278] Example 2 includes the system of Example 1, further including a store queue for the cache storage, the store queue including a latch interfacing with a tag random access memory (RAM) to retrieve the second set of data from the cache storage; an atomic comparison component, wherein a cache controller causes the atomic comparison component to compare the second set of data with a key and, if the key does not match the second set of data, discard the first set of data; and an arbitration manager, wherein, if the key matches the second set of data, the arbitration manager stores the first set of data at the memory address in the cache storage.

[0279] Example 3 includes the system of example 1, wherein the cache storage is at least one of a main cache storage or a victim cache storage.

[0280] Example 4 includes the system of example 2, wherein the latch is a first latch, and the atomic compare component is for (a) retrieving a second set of data from the cache storage via the error detection and correction circuitry, and (b) retrieving the atomic compare and swap command from the first latch via the second latch.

[0281] Example 5 includes the system of example 1, wherein the cache controller is operable to complete a memory operation based on a single instruction from the central processing unit in a single cycle.

[0282] Example 6 includes the system of example 1, further including a modify-exclusive-shared-invalid (MESI) component for determining a state of a memory address of the memory operation, wherein the cache controller is operable to provide a miss instruction to another cache if the memory address of the memory operation corresponds to the shared state, the miss instruction including an exclusive state request.

[0283] Example 7 includes the system of example 6, wherein the cache controller is to cause the arbitration manager to store the first set of data at the memory address in the cache storage after the exclusive state request is granted from the other cache if the first data matches the key.

[0284] Example 8 includes the system of example 6, wherein the cache controller causes the tag RAM to retrieve the second set of data from the cache storage from the memory address after the exclusive status request is granted from the other cache.

[0285] Example 9 includes a storage queue for cache storage, the storage queue including a key, a memory address, a first set of data, a latch for retrieving the memory address and retrieving a second set of data corresponding to the memory address, and an atomic comparison component for comparing the second set of data with the key and, based on the second set of data corresponding to the key, causing the first set of data to be stored at the memory address, and, based on the second set of data not corresponding to the key, completing the memory operation without storing the first set of data at the memory address.

[0286] Example 10 includes the storage queue of example 9, wherein the cache storage is at least one of a main cache storage or a victim cache storage.

[0287] Example 11 includes the storage queue of example 9, wherein the latch is a first latch, and the atomic compare component is for (a) retrieving a second set of data from the cache storage via the error detection and correction circuitry, and (b) retrieving the atomic compare and swap command from the first latch via the second latch.

[0288] Example 12 includes the storage queue of example 9, wherein if the first data matches the key, the storage queue performs the atomic compare and swap command in a single cycle based on a single instruction from the central processing unit.

[0289] Example 13 includes the storage queue of example 9, further including a modify-exclusive-shared-invalid (MESI) component to determine a state of a memory address of the memory operation, and an interface to provide a miss instruction to another cache if the memory address of the memory operation corresponds to the shared state, wherein the miss instruction includes an exclusive state request.

[0290] Example 14 includes the storage queue of example 13, and further includes an arbitration manager that stores the first set of data at the memory address after the exclusive state request is granted from the other cache if the first data matches the key.

[0291] Example 15 includes the storage queue of example 13, wherein the latch is for interfacing with the tag RAM to read the second set of data after an exclusive state request has been granted from another cache.

[0292] Example 16 includes a method, including receiving a memory operation identifying a key, a memory address, and a first set of data; retrieving a second set of data corresponding to the memory address; comparing the second set of data to the key; causing the first set of data to be stored at the memory address based on the second set of data corresponding to the key; and completing the memory operation without storing the first set of data at the memory address based on the second set of data not corresponding to the key.

[0293] Example 17 includes the method of Example 16, further including interfacing with a tag random access memory (RAM) to retrieve the second set of data from cache storage, comparing the second set of data to a key, discarding the first set of data if the key does not match the second set of data, and storing the first set of data at the memory address in cache storage if the key matches the second set of data.

[0294] Example 18 includes the method of example 17, further including: (a) passing a second set of data through the error detection and correction circuitry; and (b) a memory operation from the central processing unit.

[0295] Example 19 includes the method of example 16, wherein completion of the memory operation is based on a single instruction from the central processing unit in a single cycle.

[0296] Example 20 includes the method of example 16, further including determining a state of a memory address of the memory operation and providing a miss instruction to another cache if the memory address of the memory operation corresponds to a shared state, the miss instruction including an exclusive state request.

[0297] Method and apparatus for in-flight data transfer and invalidation of pending writes in a store queue - Patents.com

[0298] In the examples described herein, when CPU 102 issues a read operation, tag RAM accesses 204, 206 determine whether the read operation hits or misses main storage element 214 and / or victim storage element 218. In examples where tag RAM accesses 204, 206 determine that the read command misses both main storage element 214 and victim storage element 218, cache controller 220 sends an operation to main storage element 214 to create a victim (e.g., to determine which line in main storage element 214 to evict). In some examples, a problem may occur when main storage element 214 evicts a line corresponding to an outstanding write. For example, a line in main storage element 214 to which data is being written by store queue 212 may have an outstanding write located in one of latches 402a-d. In some examples, an error may occur when a new address replaces a line in main storage element 214 that was evicted and store queue 212 attempts to write data to the same line from a previous write operation.

[0299] Examples described herein include a read invalidate operation issued to store queue 212 when cache controller 220 determines that a read operation is a read miss. Cache controller 220 sends a read invalidate operation to store queue 212 when main storage element 214 creates a victim. The read invalidate operation signals store queue 212 to compare the victim's address with all addresses stored in latches 402a-d. If any of the addresses in latches 402a-d match the victim's address, priority multiplexer 418 sends the data in the matching address to latch 402e, which sends the data to MUX circuit 314. Such an operation may be referred to as a data transfer of in-flight data. For example, priority multiplexer 418 sends the data corresponding to the victim through latch 402e to MUX circuit 314, which then transfers the victim's data to victim storage element 218 and / or L2 cache 112. Additionally, a read invalidate operation invalidates data stored in latches 402a-d when the latches 402a-d contain an address corresponding to the victim. For example, each of latches 402a-d contains a valid tag. The valid tag indicates to latch 402a-d whether data should be stored in main storage element 214. When a read invalidate operation invalidates the valid tag, latches 402a-d stop writing invalid data to main storage element 214.

[0300] In exemplary operation, CPU 102 issues a write operation. In some examples, the write operation corresponds to address A. For example,

[0301] Write operation = Write (address A): Data 1 ∥ Write data 1 to the cache line corresponding to address A

[0302] Store queue 212 receives the write operation and begins the process of writing the data to address A in main storage element 214. In some examples, address A corresponds to cache line 1 in main storage element 214. CPU 102 then issues a read operation. In some examples, the read operation corresponds to address B. For example, as follows:

[0303] Read operation = Read (address B) ∥ Read data 2 from the cache line corresponding to address B

[0304] Example tag RAM accesses 204, 206 check the addresses in tag RAM 208 and tag RAM 210 and determine that neither tag RAM 208, 210 contains address B. Cache controller 220 obtains the read miss results from tag RAM accesses 204, 206 and issues an allocate operation to determine the victim in main storage element 214 for eviction to victim storage element 218 and / or L2 cache 112. Once cache controller 220 obtains the response corresponding to the victim, cache controller 220 issues a read invalidate operation to store queue 212.

[0305] A read port 424 of store queue 212 receives a read invalidate operation and receives a victim address. Read port 424 sends the victim address to data store 416, which is compared to all of the addresses stored in latches 402a-d. If data store 416 determines that any of the addresses stored in latches 402a-d matches the victim address, data store 416 outputs an operation to priority multiplexer 418 to send the data corresponding to the victim address to latch 402e. Latch 402e forwards the data to MUX circuit 314 for sending to victim storage element 218 and / or L2 cache 112.

[0306] Additionally, in response to the address stored in latches 402a-d matching the victim address, latches 402a-d invalidate the data corresponding to the victim address. For example, the valid tags in latches 402a-d are updated to indicate that the data in the latch corresponding to the victim address is invalid. In this example, store queue 212 does not attempt to write the data to the cache line corresponding to the previous address that was evicted.

[0307] Exemplary methods, apparatus, systems, and articles of manufacture for in-flight data transfer and invalidation are described herein. Further examples and combinations thereof include the following:

[0308] Example 1 includes an apparatus including cache storage and a cache controller coupled to the cache storage, the cache controller operable to receive a first memory operation, determine that the first memory operation corresponds to a read miss in the cache storage, determine a victim address in the cache storage to be evicted in response to the read miss, issue a read invalidation command identifying the victim address, compare the victim address to a set of addresses associated with a set of memory operations being processed by the cache controller, and provide data associated with the second memory operation in response to the victim address matching a first address in the set of addresses corresponding to a second memory operation in the set of memory operations.

[0309] Example 2 includes the apparatus of example 1, wherein the cache controller is to issue a read invalidate command when a tag random access memory access issues a read miss.

[0310] Example 3 includes the apparatus of example 1, wherein the cache controller is to determine a victim address to evict from cache storage to make room for data of a third memory operation.

[0311] Example 4 includes the apparatus of example 1, wherein the cache controller is operable to abort writing of data associated with the second memory operation in the cache storage.

[0312] Example 5 includes the device of example 1, further including a first latch, a second latch, a third latch, and a fourth latch, wherein the first latch, the second latch, the third latch, or the fourth latch is for storing data for the victim address.

[0313] Example 6 includes the apparatus of example 5, wherein the first latch, the second latch, the third latch, and the fourth latch include a valid tag that is updated to invalid when any of the first latch, the second latch, the third latch, or the fourth latch stores data for the victim address.

[0314] Example 7 includes the apparatus of example 1, further including a read port that, when the read port receives a read invalidate command and a victim address, initiates a comparison between the victim address and a set of addresses associated with a set of memory operations being processed by the cache controller.

[0315] Example 8 includes a method for invalidating a write operation, the method including receiving a first memory operation; determining that the first memory operation corresponds to a read miss in cache storage; determining a victim address in the cache storage to be evicted in response to the read miss; issuing a read invalidation command identifying the victim address; comparing the victim address with a set of addresses associated with a set of memory operations being processed by the cache controller; and providing data associated with the second memory operation in response to the victim address matching a first address in the set of addresses corresponding to a second memory operation in the set of memory operations.

[0316] Example 9 includes the method of example 8, further including issuing a read invalidate command when the tag random access memory access issues a read miss.

[0317] Example 10 includes the method of example 8, further including determining a victim address to evict from cache storage to make room for the data of the third memory operation.

[0318] Example 11 includes the method of example 8, including aborting writing of data associated with the second memory operation in the cache storage.

[0319] Example 12 includes the method of example 8, further including storing data related to the victim address in at least one of the first latch, the second latch, the third latch, and the fourth latch.

[0320] Example 13 includes the method of example 12, further including updating a valid tag of the first latch, the second latch, the third latch, or the first latch to invalid when any of the first latch, the second latch, the third latch, and the fourth latch stores data of the victim address.

[0321] Example 14 includes the method of example 8, further including, when the read port receives the read invalidate command and the victim address, initiating a comparison between the victim address and a set of addresses associated with the set of memory operations being processed by the cache controller.

[0322] Example 15 includes a system including a central processing unit that outputs a first memory operation; a cache coupled to the central processing unit and including cache storage; and a cache controller coupled to the cache storage, wherein the cache controller is operable to receive the first memory operation, determine that the first memory operation corresponds to a read miss in the cache storage, determine in response to the read miss that a victim address in the cache storage should be evicted, issue a read invalidation command identifying the victim address, compare the victim address with a set of addresses associated with a set of memory operations being processed by the cache controller, and, in response to the victim address matching a first address in the set of addresses corresponding to a second memory operation in the set of memory operations, provide data associated with the second memory operation and invalidate the second memory operation.

[0323] Example 16 includes the system of Example 15, wherein the cache is a first cache, and the first cache is operable to retrieve data associated with the first memory operation from the second cache in response to the cache storage not containing data associated with the first memory operation.

[0324] Example 17 includes the system of example 15, wherein the cache includes a store queue for storing write data of the second memory operation to the cache storage over a plurality of clock cycles, each clock cycle writing at least one portion of data associated with the second memory operation to the cache storage.

[0325] Example 18 includes the system of example 17, wherein the cache is a first cache, and the cache controller is operable to provide the portion of the data remaining in the store queue to the second cache for storing when the second memory operation is invalidated.

[0326] Example 19 includes the system of example 15, wherein the cache includes a store queue for storing the outstanding write, and wherein the second memory operation corresponds to the outstanding write.

[0327] Example 20 includes the system of Example 15, wherein the central processing unit outputs the first memory operation following the output of the second memory operation. Figure 5 illustrates an example victim cache-based section of the level 1 (L1) cache 110 of Figures 1 and 3. Figure 5 includes the tag RAM 210, the victim storage 218, the MESI RAM 300, example hit / miss comparison logic 306a, 306b, 306c, example replacement policy 308 (e.g., replacement policy component 308), example address encoders 326a, 326b, 326c, example multiplexers (MUX) 330a, 330b, 330c, example address reads 332a, 332b, 332c, an example scalar interface 502, an example vector interface 504, an example snoop address component 506, and an example response multiplexer 508. Figure 5 illustrates a victim cache system supporting dual data paths and a coherency pipeline.

[0328] In FIG. 5, the example scalar interface 502 is an interface coupling the L1 cache 110 of the data cache 108 of FIG. 1 to the example processing core 104a. In some examples, the scalar interface 502 is an interface corresponding to a first data path (DP0) in a dual data path victim cache system. In some examples, the scalar interface 502 is an interface corresponding to a second data path (DP1) in a dual data path cache system. The example scalar interface 502 is a 64-bit wide bidirectional and / or unidirectional interface. Alternatively, the example scalar interface 502 may support a different amount of bits (e.g., 32 bits, 128 bits, etc.). In some examples, the scalar interface 502 receives and / or retrieves data from the core 104a. In some examples, the scalar interface 502 sends data from the victim storage 218 to the core 104a. The example scalar interface 502 is coupled to the example tag RAM 210 and the compare logic 306 to compare addresses from the CPU 102 with addresses in the tag RAM 210 .

[0329] 5, the example vector interface 504 is an interface coupling the L1 cache 110 of the data cache 108 of FIG. 1 to the example processing core 104a. In some examples, the vector interface 504 is an interface corresponding to the second data path (DP1) in a dual data path cache system. In some examples, the vector interface 504 is an interface corresponding to the first data path (DP0) in a dual data path cache system. The example vector interface 504 is a 512-bit wide interface. Alternatively, the example vector interface 504 may support a different amount of bits (e.g., 256 bits, 1024 bits, etc.). In some examples, the vector interface 504 receives and / or retrieves data from the core 104a. In some examples, the vector interface 504 sends data from the victim storage 218 to the core 104a. The example vector interface 504 is coupled to the example tag RAM 210, snoop address component 506, and compare logic 306b to compare addresses from the CPU 102 with addresses from the tag RAM 210. In some embodiments, the scalar interface 502 and the vector interface 504 are implemented by the CPU interface 202 (FIG. 2). For example, the scalar interface 502 and the vector interface 504 can be included in the CPU interface 202.

[0330] In FIG. 5, the example tag RAM 210 is connected to the example interfaces 502, 504. However, in some examples, the tag RAM 210 may be coupled to the interfaces 502, 504 via the example victim tag RAM access 206 (FIG. 2). The example tag RAM 210 is a dual-ported, fully associative tag RAM, supporting dual paths (e.g., a scalar path and a vector path). As used herein, a fully associative tag RAM 210 allows data from main storage 214 (FIG. 2) to be stored in any cache block, rather than forcing each memory address to one specific block. In some examples, because the tag RAM 210 is fully associative, the victim storage 218 is also fully associative.

[0331] 5, comparison logic 306a is coupled to scalar interface 502, tag RAM 210, address encoder 326a, and replacement policy component 308. Comparison logic 306b is coupled to vector interface 504, tag RAM 210, address encoder 326b, and replacement policy component 308. Comparison logic 306a, 306b support both scalar and vector data paths. For example, comparison logic 306 may compare scalar data to data in tag RAM 210 and / or compare vector data to data in tag RAM 210. Comparison logic 306 provides a hit or miss output to replacement policy component 308 and address encoders 326a, 326b. In some examples, comparison logic 306 provides a hit or miss output to multiplexers 330a, 330b.

[0332] In Figure 5, the example replacement policy component 308 is coupled to the comparison logic 306a, 306b. The example replacement policy component 308 is control / decision-making logic. The example replacement policy component 308 dictates entries (e.g., data) in the example victim storage 218 based on multiple inputs. For example, the replacement policy component 308 may determine whether the cache controller 220 (Figure 2) should remove and / or insert an entry to / from the victim storage 218. The control logic of the replacement policy component 308 is configured to resolve address conflicts between two addresses (e.g., a scalar and a vector) in a manner such that data consistency is maintained. Figure 6 shows the control logic of the example replacement policy component 308.

[0333] 5, example address encoders 326a, 326b encode memory addresses into a format interpretable by victim storage 218. For example, address encoders 326a, 326b may operate similarly to address encoder 326 of FIGS. 3A-3D. Example address encoders 326a, 326b output the encoded addresses to multiplexers 330a, 330b. For example, address encoder 326a may output the encoded memory address to multiplexer 330a, and address encoder 326b may output the encoded memory address to multiplexer 330b.

[0334] 5, multiplexers 330a, 330b select an address in response to execution of comparison logic 306a, 306b. For example, multiplexer 330a can receive an input from comparison logic 306a corresponding to a hit and, therefore, select the encoded address from address encoder 326a. Additionally and / or alternatively, multiplexer 330a can receive an input from comparison logic 306a corresponding to a miss and, therefore, select the memory address chosen by replacement policy component 308. The example multiplexers 330a, 330b are coupled to address reads 332a, 332b.

[0335] 5, the example address reads 332a, 332b read an address value selected by a multiplexer into the victim storage 218. For example, the address reads 332a, 332b can identify addresses to be stored and / or removed from the victim storage 218.

[0336] 5, the example victim storage 218 is a fully associative cache. For example, the fully associative victim storage 218 may place data in any unused block of the cache when data is fetched (e.g., victimized) from main storage 214. The placement of data in the victim storage 218 is based on the replacement policy component 308. For example, the replacement policy component 308 may determine when and where a line of data from main storage 214 should be placed in the victim storage 218. In some examples, when an address read 332a, 332b reads data into the victim storage 218, the victim storage 218 outputs a response. In some examples, the victim storage 218 generates a DP0 response, a DP1 response, and a snoop response to be sent to the L2 data cache 112. In some examples, the response includes the data requested by the CPU 102. For example, the victim storage 218 may output data from a memory address location if the CPU 102 requested such data based on the address read 332a, 332b. Additionally and / or alternatively, if the replacement policy component 308 is replacing data in the victim storage 218 based on the address read 332a, 332b, the victim storage 218 may output the evicted data to the L2 cache 112.

[0337] 5, an example snoop address component 506 is implemented by a snoop data path and / or other interfaces. In addition to two CPU data paths (e.g., DP0 and DP1), L1 cache 110 includes a snoop data path for providing coherency to L1 cache 110. The example snoop address component 506 is coupled to tag RAM 210 and comparison logic 306c. In some examples, snoop address component 506 obtains an example snoop request address issued by a higher-level data cache (e.g., L2 data cache 112), which issues the read address to tag RAM 210. For example, snoop address component 506 attempts to read a memory address from tag RAM 210. The snoop address component 506 also provides the read address to comparison logic 306c. The snoop address component 506, or more generally the coherency pipeline, is used to store the MESI state of every cache line in victim storage 218 in MESI RAM 300. By storing the MESI state of every cache line in MESI RAM 300, the victim cache system supports coherency.

[0338] 5, example memory RAM 300 is connected to comparison logic 306c. Example MESI RAM 300 tracks the state of cache lines in main storage 214 and victim storage 218 by marking the cache lines as modified, exclusive, shared, or invalid based on comparison logic 306c. For example, when snoop address component 506 issues a read to tag RAM 210, tag RAM 210 either returns the correct memory address or does not. Thus, comparison logic 306c compares the memory address of the issued snoop read with the results of tag RAM 210 to determine the state of the cache line.

[0339] 5, response multiplexer 508 is coupled to victim storage 218 and victim cache store queue 216. In this manner, response multiplexer 508 is configured to select between data retrieved by victim storage 214 and / or data retrieved by victim cache store queue 216 and send the most recent data to the system. An exemplary operational description of priority multiplexer 508 is described below.

[0340] Method and apparatus for a multi-bank victim cache with dual data paths

[0341] Some victim caches do not support a multi-bank architecture. For example, a victim cache may be a monolithic storage device that does not support multiple accesses by a processor (e.g., a CPU) during the same clock cycle. For example, a request to access data in a single victim cache may lock up the entire victim cache. In such examples, there is a single register file that can support one complete victim cache line access per clock cycle. In some such examples, a single register file is assigned to the victim storage data bank that receives such a request, so that the entire victim cache line associated with the single victim storage may be locked in order to process the request.

[0342] Examples described herein include a multi-bank victim cache with dual data paths. In some described examples, victim storage 218 of FIG. 2 has multiple banks and is therefore multi-banked or has a multi-bank data or memory structure. Advantageously, the multi-bank structure of victim storage 218 may achieve support for two or more accesses (e.g., CPU accesses) per clock cycle. Advantageously, the multi-bank structure of victim storage 218 allows two or more accesses to be processed and / or accomplished without performance overhead.

[0343] In some described examples, the victim storage 218 comprises a two-ported, fully associative tag RAM (e.g., tag RAM 210 of FIG. 2). In some examples, hit / miss comparison is supported for both scalar and vector addresses. In such described examples, the victim storage 218 is locked based on a hit / miss determination for each of the data paths (e.g., scalar data path, vector data path, etc.). In examples where an access to the victim storage 218 is a hit, the location of the hit entry is selected. In one example, if an access to the victim storage 218 is a miss, an allocation policy is checked for a particular set of victim storage 218.

[0344] In some described examples, in a subsequent pipe stage, the selected set of victim storage 218 for both addresses is read and a response is returned to the CPU. In some described examples, the set selection logic resolves address conflicts between two addresses (e.g., a scalar address and a vector address) such that data consistency is maintained. In some described examples, the control logic also resolves address conflicts.

[0345] In some described examples, bank arbitration logic calculates and / or otherwise determines the bank required for each of the addresses and selects a read on each of the banks. In some described examples, control logic resolves bank conflicts between the two addresses to enable serialization of the two memory operations. In some described examples where both data paths access the same address, the control logic may prevent issuing multiple allocate requests for the same address. Once data is read from victim storage 218, example data multiplexing logic may fold the data onto the correct data lane before returning the data to the CPU as a read response.

[0346] FIG. 7A is a schematic diagram of a first example encapsulated data cache system 700. The first encapsulated data cache system 700 may be an example circuit implementation of the L1 cache 110 of FIG. 1 or a portion thereof, and / or more generally, the data cache 108 of FIG. 1 or a portion thereof. The first encapsulated data cache system 700 is encapsulated to provide a unified storage view to an external system (e.g., one or more CPUs, one or more processors, external hardware, etc.). For example, the first encapsulated data cache system 700 may be encapsulated using firmware, software, hardware logic, etc., and / or a combination thereof, and may encapsulate and / or otherwise generalize all complexities associated with read-after-write (RAW) hazards, write-after-write (WAW) hazards, data transfers, etc. Advantageously, the merge architecture shown in the example of FIG. 7A may provide a separate port to an external device (e.g., the central processing unit 102) to simplify obtaining access to the latest version of the data of interest.

[0347] In the example of FIG. 7A , a first encapsulated data cache system 700 includes the victim cache store queue 216 of FIG. 2 and the victim storage 218 of FIG. 2 . In FIG. 7A , the victim cache store queue 216 includes a plurality of first example independently addressable banks (e.g., data banks, store banks, data store banks, etc.) 702. For example, the first independently addressable banks 702 may be bank queues, bank sub-queues, etc. In such examples, the bank queues, bank sub-queues, etc. may include multiple storage elements, as described below in FIG. 7C and / or FIG. 7E . The first independently addressable banks 702 are victim cache store queue banks (e.g., victim cache store queue data banks, victim cache bank queues, victim cache bank sub-queues, etc.). In FIG. 7A , the victim cache store queue 216 includes 16 victim cache store queue banks 702. Alternatively, there may be more or fewer than 16 instances of the victim cache store queue banks 702.

[0348] 7A , the victim storage 218 includes a plurality of second exemplary independently addressable banks (e.g., data banks, store banks, data store banks, etc.) 704. The second independently addressable banks 704 are victim storage banks (e.g., victim storage data banks). In FIG. 7A , the victim storage 218 includes 16 victim storage banks 704. Alternatively, the number of victim storage banks 704 may be less than or greater than 16. For example, the victim cache store queue 216 may include a plurality of bank queues or bank subqueues including a first bank queue or a first bank subqueue (e.g., victim cache store queue: BANK1), and the victim storage 218 may include a plurality of data banks including the first data bank (e.g., victim storage: BANK1).

[0349] In some examples, victim cache store queue 216 and victim storage 218 each have 256 rows, each row having a line width of 1024 bits, but are divided into 16 banks with 64 bits per row within a given bank, as shown in FIG. 7A. In some examples, victim cache store queue 216 and victim storage 218 each have 384 rows, each row having a line width of 1024 bits, but are divided into 16 banks with 64 bits per row within a given bank, as shown in FIG. 7A. Of course, the cache sizes described in the above examples are merely two examples, and this description is not limited to any particular cache line width, number of banks, or rows. As shown in FIG. 7A, each of first banks 702 corresponds to one of second banks 704. For example, the first bank (BANK1) of victim cache store queue 216 is in circuit with, and therefore corresponds to, the first bank (BANK1) of victim storage 218.

[0350] Advantageously, victim cache store queue 216, victim storage 218, and / or more generally, the multi-bank structure of first encapsulated data cache system 700 may process read and write operations sent to the banks in parallel. In some examples, each bank arbitrates its own process in response to read and / or write operations. By allowing each bank of first encapsulated data cache system 700 to operate independently, operation of first encapsulated data cache system 700 becomes more efficient because an entire cache line is not locked up when a request is received. Instead, only the portion of the cache line assigned to the bank receiving such a request is locked.

[0351] 7C illustrates an example victim cache multi-bank structure 720. In some examples, L1 cache 110, L2 cache 112, and / or L3 cache 114 of FIG. 1 may have victim cache bank structure 720. In some examples, victim cache store queue 216 of FIG. 2 and / or victim storage 218 of FIG. 2 may have victim cache multi-bank structure 720. For example, victim cache multi-bank structure 720 may be an example implementation of victim cache store queue 216 and / or victim storage 218.

[0352] The victim cache multi-bank structure 720 is a data or memory structure that includes 16 exemplary banks (banks 0-15) 722, each of which has a data width of 64 bytes (e.g., bytes 0-7). Each of the banks 722 includes 16 exemplary rows (rows 0-15) 724, each of which has a data width of 128 bytes (e.g., 128 bytes = 8 bytes / bank x 16 banks). In FIG. 7C, each of the banks 722 can store 128 bytes (e.g., 128 bytes = 8 bytes / row x 16 rows). In FIG. 7C, the victim cache multi-bank structure 720 can store 2048 bytes (e.g., 2048 bytes = 128 bytes / bank x 16 banks). The victim cache multi-bank structure 720 is independently addressable by bank. For example, the first row of rows 724 has a starting row address of 0 and an ending row address of 127, and the second row of rows 724 has a starting row address of 128 and an ending row address of 255.

[0353] In some examples, a cache line may be 128 bytes of data that fits within the width of a memory (e.g., DRAM) or storage unit (e.g., main storage 214, victim storage 218, etc.). In the example of FIG. 7C, a cache line may consume an entire row of the victim cache bank structure 720. For example, the cache line may use one of 16 banks of the row 724, each bank being 8 bytes wide. Advantageously, the victim cache bank structure 720 may enable 16 different cache lines to access data stored therein.

[0354] 8A shows a schematic diagram of an example victim cache tag (VCT) random access memory (RAM) 800. VCT RAM 800 may be an example implementation of tag RAM 210 of FIG. 2. For example, VCT RAM 800 may store addresses of data stored in victim cache store queue 216, victim storage 218, etc. of FIG. 2. VCT RAM 800 is a multi-bank VCT RAM. For example, VCT RAM 800 may include multiple banks (e.g., data banks, memory banks, etc.), such as 16 banks, although VCT RAM 800 may have a different number of banks.

[0355] The VCT RAM 800 includes example allocation ports 802, 804, 806, including a first example allocation port (AP0) 802, a second example allocation port (AP1) 804, and a third example allocation port (AP2) 806. The VCT RAM 800 includes example read ports 808, 810, 812, including a first example read port (RP0) 808, a second example read port (RP1) 810, and a third example read port (RP2) 812. The VCT RAM 800 includes an example LRU read port 814. VCT RAM 800 includes example output ports 816, 818, 820, 822, including a first example output port (OP0) 816, a second example output port (OP1) 818, a third example output port (OP2) 820, and a fourth example output port (OP3) 822. Alternatively, VCT RAM 800 may have fewer or more allocation ports, read ports, LRU read ports, and / or output ports than those shown in FIG.

[0356] The VCT RAM 800 includes allocation ports 802, 804, and 806 for filling the victim storage 218. For example, the allocation ports 802, 804, and 806 may be configured to receive requests from external hardware (e.g., the CPU 102, the main storage 214, etc.) to store data in the victim storage 218. The first allocation port 802 is configured to receive a first example data 824. For example, the first allocation port 802 may receive the first data 824 from a write state machine associated with the scalar data path (DP0). The first data 824 includes WRM_TAG_UPDATE0 data, which may represent a control signal (e.g., the scalar data path (DP0)) generated from the CPU interface 202 of FIG. 2 . The control signal may be generated to inform the VCT RAM 800 that the CPU interface 202 has a cache line to be moved from the CPU interface 202 to the victim storage 218 and therefore the CPU interface 202 has an address to be moved from the CPU interface 202 to the tag RAM 210. The first data 824 includes VTAG_WR_TAG0 data, which may represent an address in the VCT RAM 800 (e.g., a tag address) that may correspond to the address of the data to be stored in the victim cache 218. The first data 824 includes VTAG_WR_SET0 data, which may represent an address in the victim cache 218 of where to store the data (e.g., a victim cache tag for DP0).

[0357] The second allocation port 804 is configured to receive second example data 826. For example, the second allocation port 804 may receive the second data 826 from a write state machine associated with the vector data path (DP1). The second data 826 includes WRM_TAG_UPDATE1 data, which may represent a control signal (e.g., vector data path (DP1)) generated from the CPU interface 202 of FIG. 2 . The control signal may be generated to inform the VCT RAM 800 that the CPU interface 202 has a cache line to be moved from the CPU interface 202 to the victim storage 218 and, therefore, the CPU interface 202 has an address to be moved from the CPU interface 202 to the tag RAM 210. The second data 826 includes VTAG_WR_TAG1 data, which may represent an address (e.g., a tag address) in the VCT RAM 800 that may correspond to the address of the data to be stored in the victim cache 218. The second data 826 includes VTAG_WR_SET1 data, which may represent an address in the victim cache 218 of where to store the data (eg, a victim cache tag for DP1).

[0358] The third allocation port 806 is configured to receive third example data 828. The third data 828 includes ARB_EVT_TAG_UPDATE data, which may represent a control signal generated from main storage 214. The control signal is an arbitration (ARB) eviction (EVT) tag update control signal, which may be generated to inform VCT RAM 800 that main storage 214 has a cache line to be moved from main storage 214 to victim storage 218 and therefore has an address to be moved from tag RAM 208 to tag RAM 210. The third data 828 includes ADP_EVT_WR_TAG data, which may represent an address in VCT RAM 800 (e.g., a tag address) that may correspond to the address of data to be stored in victim cache 218. The third data 828 includes ADP_EVT_WR_SET data, which may represent an address in victim cache 218 of where to store the data (e.g., a victim cache tag of a line moved from main cache to victim cache). For example, the ADP_EVT_WR_TAG and ADP_EVT_WR_SET data may be referred to as Address Data Path (ADP) data. The first data 824, the second data 826, and / or the third data 828 may be one or more data packets, one or more signals based on a communication protocol (e.g., an Inter-Integrated Circuit (I2C) protocol), etc.

[0359] The VCT RAM 800 includes read ports 808, 810, and 812, which provide an interface through which external hardware (e.g., the CPU 102) can request to read and / or otherwise access data stored in the victim storage 218. The first read port 808 is configured to receive fourth example data 830. For example, the first read port 808 may receive the fourth data 830 from the scalar interface 502 of the CPU 102. The fourth data 830 may include ADP_ADDR_E2_DP0 data, which may represent an address in the victim storage 218 to which the scalar interface 502 requests access.

[0360] The second read port 810 is configured to receive fifth example data 832. For example, the second read port 810 may receive the fifth data 832 from the vector interface 504 of the CPU 102. The fifth data 832 includes ADP_ADDR_E2_DP1 data that may represent an address of the victim storage 218 to which the vector interface 504 requests access.

[0361] The third read port 812 is configured to receive sixth example data 834 . For example, the third read port 812 may receive sixth data 834 from the snoop address component 506 (e.g., snoop interface) of Figure 5. The sixth data 834 may include SNP_ADDR_E2_DP0 data, which may represent the address of the victim storage 218 to which the snoop address component 506 requests access.

[0362] The LRU read port 814 is configured to receive seventh example data 836. For example, the LRU read port 814 may receive the seventh data 836 from the replacement policy component 308 of Figures 3A-3D. The seventh data 836 may include LRU_SET_DP0 and LRU_SET_DP1, which may represent respective addresses associated with least recently used (LRU) cache lines in the victim storage 218. For example, the LRU read port 814 may be a victim LRU (VLRU) read port configured to receive the LRU data from the replacement policy component 308.

[0363] The VCT RAM 800 includes output ports 816, 818, 820, 822 for sending output to external hardware (e.g., the CPU 102, the main storage 214, etc.) in response to a read or write request (e.g., an allocation request) related to the victim storage 218. The first output port 816 is configured to send first example output data 838. For example, the first output port 816 may send the first output data 838 to the scalar interface 502. The first output data 838 includes VTAG_HIT_DP0 data, which may indicate that the data requested by the scalar interface 502 is stored in the victim storage 218. The first output data 838 includes VTAG_MISS_DP0 data, which may indicate that the data requested by the scalar interface 502 is not stored in the victim storage 218. The first output data 838 includes VTAG_SET_DP0 data, which may represent an address within the victim storage 218 where the data requested by the scalar interface 502 is stored.

[0364] The second output port 818 is configured to transmit second example output data 840. For example, the second output port 818 may transmit the second output data 840 to the vector interface 504. The second output data 840 includes VTAG_HIT_DP1 data, which may indicate that the data requested by the vector interface 504 is stored in the victim storage 218. The second output data 840 includes VTAG_MISS_DP1 data, which may indicate that the data requested by the vector interface 504 is not stored in the victim storage 218. The second output data 840 includes VTAG_SET_DP1 data, which may represent an address within the victim storage 218 where the data requested by the vector interface 504 is stored.

[0365] The third output port 820 is configured to transmit third example output data 842. For example, the third output port 820 may transmit the third output data 842 to the replacement policy component 308. The third output data 842 includes VTAG_ADDR_DP0 data, which may represent an address of the victim storage 218 associated with the request LRU_SET_DP0 by the replacement policy component 308 received at the LRU read port 814.

[0366] The fourth output port 822 is configured to transmit fourth example output data 844. For example, the fourth output port 822 may transmit the fourth output data 844 to the replacement policy component 308. The fourth output data 844 may include VTAG_ADDR_DP1 data, which may represent an address of the victim storage 218 associated with the request LRU_SET_DP1 by the replacement policy component 308 received at the LRU read port 814.

[0367] 8B illustrates another schematic diagram of an example implementation of the VCT RAM 800 of FIG. 8A. For example, FIG. 8B may correspond to a victim cache-based section or portion of the L1 cache 110 of FIG.

[0368] Figure 8B shows another example implementation of the VCT RAM 800 of Figure 8A. In Figure 8B, the VCT RAM 800 includes 16 example sets 846. For example, the sets 846 include a first set VCT_ADDR[0], a second set VCT_ADDR[1], etc. Alternatively, the VCT RAM 800 may include fewer or more than 16 sets 846.

[0369] The VCT RAM 800 is a victim cache tag storage configured to store addresses (e.g., tag addresses) corresponding to the sets 846. Each of the sets 846 is coupled to a respective one of the first example comparators 850 and a respective one of the second example comparators 852. The first comparators 850 may be the example implementation of the comparison logic 306a of FIGS. 3 and / or 5. The second comparators 852 may be the example implementation of the comparison logic 306b of FIGS. 3 and / or 5. The first set VCT_ADDR[0] is coupled to a first one of the first comparators 850 and a first one of the second comparators 852, and the second set VCT_ADDR[1] is coupled to a second one of the first comparators 850 and a second one of the second comparators 852.

[0370] The first comparator 850 and the second comparator 852 are coupled to respective example address encoder logic circuits 854, 856, which include a first example address encoder logic circuit 854 and a second example address encoder logic circuit 856. The first comparator 850 is coupled to the first address encoder logic circuit 854. The second comparator 852 is coupled to the second address encoder logic circuit 856.

[0371] The address encoder logic 854, 856 may be an example implementation of the address encoders 326a, 326b of Figure 3 and / or Figure 5. For example, the first address encoder logic 854 may be an example implementation of the address encoder 326a. In another example, the second address encoder logic 856 may be an example implementation of the address encoder 326b.

[0372] The first example multiplexer 858A is coupled to the first address encoder logic circuit 854. The first address encoder logic circuit 854 includes a first example decoder 860A, a first example inverter (e.g., a logic gate, an inverting logic gate, etc.) 862A, a first example AND gate (e.g., a logic gate, an AND logic gate, etc.) 864A, a first example OR gate (e.g., a logic gate, an OR logic gate, etc.) 866A, a first example encoder 868A, a third example comparator 870A, and a fourth example comparator 872A.

[0373] 8B shows only one instance each of the first AND gate 864A, the first OR gate 866A, the third comparator 870A, and the fourth comparator 872A for clarity. However, each of the first AND gate 864A, the first OR gate 866A, the third comparator 870A, and the fourth comparator 872A can represent 16 instances of these components. For example, the first AND gate 864A can represent 16 instances of the first AND gate 864A and / or can be implemented in other ways, and the first OR gate 866A can represent 16 instances of the first OR gate 866A and / or can be implemented in other ways.

[0374] The first multiplexer 858A has a first input for receiving ADP_ADDR_E2_DP0, which represents the address requested by the DP0 interface from the E2 arbitration stage of Figures 3A-3D. The first multiplexer 858A has a second input for receiving SNP_ADDR_E2_DP0, which represents the snoop address requested by the snoop interface from the E2 arbitration stage of Figures 3A-3D. The first multiplexer 858A has a select input for receiving SNP_ADDR_EN_DP0, which represents an enable signal from the snoop interface that, when asserted, may invoke the first multiplexer 858A to select the second input. The output of the first multiplexer 858A is coupled to the input of the first comparator 850. For example, each of the first comparators 850 may compare an address from the output of the first multiplexer 858A with a corresponding one of the sets in the VCT RAM 800. In such an example, a first one of the first comparators 850 may compare the address included in ADP_ADDR_E2_DP0 with the address stored in VCT_ADDR[0]. In some such examples, the first one of the first comparators 850 may output and / or otherwise generate a logic one in response to the address from the first multiplexer 858A matching the address stored in VCT_ADDR[0].

[0375] The output of the first multiplexer 858A is coupled to a first input of a third comparator 870A. An output of an example DP0 read finite state machine (FSM) (READ_FSM_DP0) 873 and / or an output of an example DP0 write finite state machine (WRITE_FSM_DP0) 874 is coupled to a second input of the third comparator 870A. The DP0 read finite state machine 873 and the DP0 write finite state machine 874 are hardware-implemented finite state machines that perform logic on data from the scalar interface 502 of FIG. 5. For example, the DP0 read finite state machine 873 and / or the DP0 write finite state machine 874 may send one or more of WRM_TAG_UPDATE0, VTAG_WR_TAG0, and VTAG_WR_SET0 to the third comparator 870A and / or the fourth comparator 872A. The DP0 read finite state machine 873 and / or the DP0 write finite state machine 874 may send VTAG_WR_TAG0 to the sixth example comparator 872B included in the second address encoder logic 856. WRM_TAG_UPDATE0, VTAG_WR_TAG0, and VTAG_WR_SET0 are described above in connection with FIG. 8A.

[0376] The first decoder 860A is a 4x16 decoder. The first decoder 860A has an input for receiving VTAG_WR_SET0 data, which may represent an in-flight address from the scalar interface 502 to the victim storage 218. The first decoder 860A has an output coupled to an input of a first inverter 862A. The first decoder 860A may convert the in-flight address into a bit vector, with each bit being inverted by one of 16 instances of the first inverter 862A. The output of the first inverter 862A is coupled to a first input of a first AND gate 864A. A second input of the first AND gate 864A is coupled to the tag comparison result bit from the first comparator 850 having set 0 (e.g., VCT_ADDR[0]) and the output of the first multiplexer 858A. For example, the second input of the first AND gate 864A may be configured to receive HIT_DP0 data, which may represent a 16-bit vector, with each bit corresponding to whether the ADP_ADDR_E2_DP0 data is a hit (e.g., a bit value of 1) or a miss (e.g., a bit value of 0) within the victim storage 218.

[0377] The output of the first AND gate 864A is coupled to a first input of the first OR gate 866A. The output of the third comparator 870A is coupled to a second input of the first OR gate 866A. The output of the fourth comparator 872A is coupled to a third input of the first OR gate 866A. The output of the first OR gate 866A is coupled to an input of the first encoder 868A. The first encoder 868A is a 16x4 encoder. For example, the first encoder 868A may generate HIT_ADDR0 data that may represent VTAG_SET_DP0 in FIG. 8A . In such an example, HIT_ADDR0 may correspond to the first output data 838 in FIG. 8A .

[0378] The second address encoder logic circuit 856 includes a second example decoder 860B, a second example inverter (e.g., a logic gate, an inverting logic gate, etc.) 862B, a second example AND gate (e.g., a logic gate, an AND logic gate, etc.) 864B, a second example OR gate (e.g., a logic gate, an OR logic gate, etc.) 866B, a second example encoder 868B, a fifth example comparator 870B, and a sixth example comparator 872B.

[0379] 8B shows only one instance each of the second AND gate 864B, the second OR gate 866B, the fifth comparator 870B, and the sixth comparator 872B for clarity. However, each of the second AND gate 864B, the second OR gate 866B, the fifth comparator 870B, and the sixth comparator 872B may represent 16 instances of these components. For example, the second AND gate 864B may represent 16 instances of the second AND gate 864B and / or may be implemented in other ways, the second OR gate 866B may represent 16 instances of the second OR gate 866B and / or may be implemented in other ways, etc.

[0380] The second address encoder logic 856 has a first input that receives ADP_ADDR_E2_DP1, which represents the address requested by the DP1 interface from the E2 arbitration stage of FIGS. 3A-3D. ADP_ADDR_E2_DP1 is coupled to an input of the second comparators 852. For example, each of the second comparators 852 may compare the address included in ADP_ADDR_E2_DP1 with a corresponding one of the sets in the VCT RAM 800. In such an example, a first one of the second comparators 852 may compare the address included in ADP_ADDR_E2_DP1 with the address stored in VCT_ADDR[0]. In some such examples, the first comparator of the second comparator 852 may output and / or generate a logical 1 in response to the address included in ADP_ADDR_E2_DP1 matching the address stored in VCT_ADDR[0].

[0381] ADP_ADDR_E2_DP1 is coupled to a first input of a fifth comparator 870B. An output of an example DP1 read finite state machine (READ_FSM_DP1) 875 and / or an output of an example DP1 write finite state machine (WRITE_FSM_DP1) 876 is coupled to a second input of the fifth comparator 870B. The DP1 read finite state machine 875 and the DP1 write finite state machine 876 are hardware-implemented finite state machines that perform logic on data from the vector interface 504 of FIG. 5. For example, the DP1 read finite state machine 875 and / or the DP1 write finite state machine 876 may send one or more of WRM_TAG_UPDATE1, VTAG_WR_TAG1, and VTAG_WR_SET1 to the fifth comparator 870B and / or the sixth comparator 872B. The DP1 read finite state machine 875 and / or the DP1 write finite state machine 876 may send VTAG_WR_TAG1 to a fourth comparator 872A included in the first address encoder logic circuit 854. WRM_TAG_UPDATE1, VTAG_WR_TAG1, and VTAG_WR_SET1 are described above in connection with FIG. 8A.

[0382] The second decoder 860B is a 4x16 decoder. The second decoder 860B has an input for receiving VTAG_WR_SET1 data, which may represent an in-flight address from the vector interface 504 to the victim storage 218. The second decoder 860B has an output coupled to an input of a second inverter 862B. The second decoder 860B may convert the in-flight address into a bit vector, with each bit inverted by one of 16 instances of the second inverter 862B. The output of the second inverter 862B is coupled to a first input of a second AND gate 864B. A second input of the second AND gate 864B is coupled to the tag comparison result bits from the second comparator 852 having set 0 (e.g., VCT_ADDR[0]) and ADP_ADDR_E2_DP1. For example, the second input of the second AND gate 864B may be configured to receive HIT_DP1 data, which may represent a 16-bit vector, with each bit corresponding to whether the ADP_ADDR_E2_DP1 data is a hit (e.g., a bit value of 1) or a miss (e.g., a bit value of 0) within the victim storage 218.

[0383] The output of the second AND gate 864B is coupled to a first input of the second OR gate 866B. The output of the fifth comparator 870B is coupled to a second input of the second OR gate 866B. The output of the sixth comparator 872B is coupled to a third input of the second OR gate 866B. The output of the second OR gate 866B is coupled to an input of the second encoder 868B. The second encoder 868B is a 16x4 encoder. For example, the second encoder 868B may generate HIT_ADDR1 data that may represent VTAG_SET_DP1 of FIG. 8A. In such an example, HIT_ADDR1 may correspond to the second output data 840 of FIG. 8A.

[0384] In an example operating condition, the first address encoder logic circuit 854 may receive a first read address (e.g., ADP_ADDR_E2_DP0) for a store instruction requested by the CPU 102 of FIG. 1, where the first read address is received from the E2 pipeline stage (ARBITRATION) of FIG. 3A-3D. In response to the first multiplexer 858A selecting the first input, the first multiplexer 858A may send the first read address to the first comparator 850. The first comparator 850 may compare the read address with a respective one of the sets 846. If the first one of the first comparators 850 determines that the read address matches an address stored in a corresponding one of the sets 846, the first one of the first comparators 850 may assert and / or otherwise output a logic one; otherwise, the first one of the first comparators 850 may output a logic zero. Thus, in response to the comparison, the first comparator 850 may generate HIT_DP0 as a 16-bit vector on the 16-bit data bus. For example, the 16-bit vector may be an implementation of a train of signals (e.g., a pulse train) representing the bit vector. The first comparator 850 may send HIT_DP0 to the first AND gate 864A.

[0385] Part of the first address encoder logic 854 and / or the second address encoder logic 856 is cache hit / miss translation logic. For example, the first AND gate 864A, the third comparator 870A, and / or the fourth comparator 872A may be example implementations of cache hit / miss translation logic. In such an example, the second AND gate 864B, the fifth comparator 870B, and / or the sixth comparator 872B may be example implementations of cache hit / miss translation logic.

[0386] The first AND gate 864A is configured to determine whether to convert a hit (e.g., a cache hit) to a miss (e.g., a cache miss). For example, a new address (VTAG_WR_SET0) may be written to the victim storage 218 during the E3 pipeline stage of FIGS. 3A-3D while the first read address is being processed during the E2 pipeline stage. In such an example, the first decoder 860A may convert the new address to a 16-bit value, which may be inverted by the first inverter 862A. The first inverter 862A may send the inverted 16-bit value to a first input of the first AND gate 864A. The first AND gate 864A may assert a logic 1 in response to VTAG_WR_SET0 not matching the address in HIT_DP0, thereby not converting the cache hit to a cache miss. In another example, the first AND gate 864A may output a logic zero in response to VTAG_WR_SET0 matching the address in HIT_DP0, thereby converting a cache hit to a cache miss because the address requested in ADP_ADDR_E2_DP0 has been overwritten and is no longer available at that address.

[0387] In an example operating condition, the third comparator 870A and the fifth comparator 870B may be configured to convert a cache miss to a cache hit. For example, the third comparator 870A may determine that a first read address (ADP_ADDR_E2_DP0) in the VCT RAM 800 requested during the E2 pipeline stage is written to the E3 pipeline stage represented by VTAG_WR_TAG0. In such an example, the third comparator 870A may assert a logic 1 in response to ADP_ADDR_E2_DP0 matching VTAG_WR_TAG0, thereby converting the cache miss to a cache hit, and HIT_ADDR0 may be updated with VTAG_WR_SET0 because data is available when the ADP_ADDR_E2_DP0 address is read during the E3 pipeline stage.

[0388] In an example operating condition, the fourth comparator 872A and the sixth comparator 872B may be configured to convert a cache miss to a cache hit. For example, the fourth comparator 872A may determine that a first read address (ADP_ADDR_E2_DP0) in the VCT RAM 800 requested during the E2 pipeline stage is being written to the E3 pipeline stage by the vector interface 504 represented by VTAG_WR_TAG1. In such an example, the fourth comparator 872A may assert a logic 1 in response to ADP_ADDR_E2_DP0 matching VTAG_WR_TAG1, thereby converting the cache miss to a cache hit, and HIT_ADDR0 may be updated with VTAG_WR_SET1 because data is available when the ADP_ADDR_E2_DP0 address is read during the E3 pipeline stage.

[0389] In an example operating condition, the first OR gate 866A and the second OR gate 866B may be configured to generate an output to a corresponding one of the first encoder 868A or the second encoder 868B. For example, the first OR gate 866B may transmit a 16-bit vector representing a cache miss (e.g., a 16-bit value of 0) or a cache hit (e.g., a 16-bit value of the address of the cache hit). In such an example, the first encoder 868A may encode the 16-bit value from the first OR gate 866A as a 4-bit address and thus generate HIT_ADDR0. Such example operations are applicable to the second OR gate 866B, the second encoder 868B, and / or the second address encoder logic 856 more generally.

[0390]

[0013] Exemplary methods, apparatus, systems, and articles of manufacture for a multi-bank victim cache with dual data paths are described herein. Further examples and combinations thereof include the following:

[0391] Example 1 includes a cache system, the cache system including a storage element including a bank operable to store data and a port operable to receive memory operations in parallel, each of the memory operations having a respective address, and a plurality of comparators coupled to a respective one of the ports and a respective one of the banks, such that each of the comparators is coupled to a respective one of the ports and to a respective one of the banks and is operable to determine whether a respective address of a respective memory operation received by the respective port corresponds to data stored in the respective bank.

[0392] Example 2 includes the cache system of example 1, further including a victim cache containing victim cache data, the data being tag data corresponding to the victim cache data.

[0393] Example 3 includes the cache system of Example 1, wherein the memory operation includes a first memory operation further including a cache including cache data, the data being tag data corresponding to the cache data, and wherein a first comparator of the plurality of comparators generates a signal in response to detecting a cache hit based on first data associated with the first memory operation corresponding to the data in the storage element.

[0394] Example 4 includes the cache system of Example 1, wherein the plurality of comparators are a plurality of first comparators. The cache system further includes: an address encoder logic circuit including a decoder having a decoder input and a decoder output, the decoder input coupled to a first finite state machine associated with a scalar interface of the central processing unit; a plurality of inverters having respective inverter inputs and respective inverter outputs, the inverter inputs coupled to the decoder outputs; a plurality of AND logic gates having respective first inputs and respective second inputs, each of the first inputs coupled to a respective one of the inverter outputs and each of the second inputs coupled to one of the respective outputs of the plurality of first comparators; a plurality of second comparators coupled to each of the outputs of the plurality of first comparators and to the first finite state machine; and a plurality of third comparators coupled to each of the outputs of the plurality of first comparators and to a second finite state machine associated with the vector interface of the central processing unit.

[0395] Example 5 includes the cache system of Example 4, wherein a first AND logic gate of the plurality of AND logic gates outputs a logic line signal in response to a first address associated with the scalar interface matching a second address associated with the cache hit to convert the cache hit to a cache miss.

[0396] Example 6 includes the cache system of Example 4, wherein a first comparator of the plurality of second comparators outputs a logic high signal in response to a first address associated with the scalar interface matching a second address associated with the cache miss to convert the cache miss to a cache hit.

[0397] Example 7 includes the cache system of Example 4, wherein a first comparator of the plurality of third comparators outputs a logic high signal in response to a first address associated with the vector interface matching a second address associated with the cache miss to convert the cache miss to a cache hit.

[0398] Example 8 includes the cache system of Example 4, wherein the address encoder logic circuit includes a plurality of OR logic gates having respective third inputs, respective fourth inputs, and respective fifth inputs, the third inputs coupled to respective ones of the outputs of the plurality of AND logic gates, the fourth inputs coupled to respective ones of the outputs of the plurality of second comparators, and the fifth inputs coupled to respective ones of the outputs of the plurality of third comparators; and an encoder having an encoder input and an encoder output, the encoder input coupled to the outputs of the plurality of OR logic gates, and the encoder output coupled to the input of the multiplexer.

[0399] Example 9 includes the cache system of Example 1, wherein the plurality of comparators are a plurality of first comparators. The cache system further includes a decoder logic circuit having a decoder input and a decoder output, the decoder input coupled to a first finite state machine associated with a vector interface of the central processing unit, a plurality of inverters having respective inverter inputs and respective inverter outputs, the inverter inputs coupled to the decoder outputs, a plurality of AND logic gates having respective first inputs and respective second inputs, each one of the first inputs coupled to a respective one of the inverter outputs and each one of the second inputs coupled to a respective one of the outputs of the plurality of first comparators, a plurality of second comparators coupled to each of the outputs of the plurality of first comparators and to the first finite state machine, and a plurality of third comparators coupled to each output of the plurality of first comparators and to a second finite state machine associated with the vector interface of the central processing unit.

[0400] Example 10 includes a victim cache system, the victim cache system including a victim cache store queue including a first data bank, and victim storage coupled to the victim cache store queue, the victim storage including a second data bank different from the first data bank.

[0401] Example 11 includes the victim cache system of example 10, wherein at least one of the first data bank or the second data bank includes 16 data banks.

[0402] Example 12 includes the victim cache system of example 10, wherein the first data bank includes a first data bank having eight addresses each having a data width of 1 byte, and the first data bank is configured to store 64 bits.

[0403] Example 13 includes the victim cache system of example 10, wherein the second data bank includes a second data bank having eight addresses each having a data width of 1 byte, and the second data bank is configured to store 64 bits.

[0404] Example 14 includes the victim cache system of example 10, wherein each one of the first data banks is coupled to each one of the second data banks.

[0405] Example 15 includes a method for identifying a cache hit in a victim cache, the method including receiving a first read address from a first interface of a processor; receiving a second read address from a second interface of the processor; comparing the first read address and the second read address with data banks of a multi-bank victim cache tag memory; identifying a cache hit in response to mapping at least one of the first read address or the second read address to a first data bank of the data banks; and outputting a cache hit address representing a victim cache address of cache data stored in the victim cache.

[0406] Example 16 includes the method of example 15, wherein the first interface is a scalar interface and the second interface is a vector interface.

[0407] Example 17 includes the method of Example 15, further including, in response to identifying the cache hit address, comparing the cache hit address with a first address received from a finite state machine associated with the first interface, the first address representing an address written to the victim cache in a previous pipeline stage; and, in response to the cache hit address matching the first address, converting the cache hit to a cache miss.

[0408] Example 18 includes the method of example 15, further including, in response to identifying the cache hit, comparing the cache hit address with a first address received from a finite state machine associated with the second interface, the first address representing an address written to the victim cache in a previous pipeline stage; and, in response to the cache hit address matching the first address, converting the cache hit to a cache miss.

[0409] Example 19 includes the method of Example 15, further including: identifying a cache miss in response to at least one of the first read address or the second read address not mapping to any of the data banks; comparing the first read address with a first address received from a finite state machine associated with the first interface, the first address representing an address to be written to the victim cache in a subsequent pipeline stage; and converting the cache miss to a cache hit in response to the first read address matching the first address.

[0410] Example 20 includes the method of example 15, further including: identifying a cache miss in response to at least one of the first read address or the second read address not mapping to any of the data banks; comparing the second read address with a first address received from a finite state machine associated with the second interface, the first address representing an address to be written to the victim cache in a subsequent pipeline stage; and converting the cache miss to a cache hit in response to the second read address matching the first address.

[0411] Example 21 includes the method of example 15, wherein comparing the first read address and the second read address to the data banks of the multi-bank victim cache tag memory is performed substantially in parallel.

[0412] Method and apparatus for allocation in a victim cache system

[0413] A data cache architecture including a victim cache system allows the main cache (e.g., main storage 214) to allocate data to a victim cache (e.g., victim storage 218) when the main cache needs to create a victim. For example, when an incoming instruction is a read miss, the main cache needs to make room for the read miss data. The main cache may be a direct-mapped cache so that the read miss can be stored in only one location indicated by the read miss address. The main cache may allocate data of a read miss location to be moved to the victim cache when the data is dirty, and may evict data of a read miss location to be sent to a higher-level memory location when the data in that location is clean. For example, the main cache controller may select modified (e.g., dirty) lines in main storage to be victimized and unmodified (e.g., clean) lines in main storage to be evicted. Dirty and / or modified data lines are data updated by the CPU 102. For example, if a cache line in main storage 214 exists only in a current state and has changed from the value in main memory (e.g., such that a read of data in expanded memory 106 is flagged or disallowed because it is not up-to-date or valid), the cache line is dirty and / or changed, and therefore becomes a candidate for allocation (e.g., victimized). The example MESI RAM 300 stores and / or tracks cache line states (e.g., clean, dirty, shared, exclusive, etc.), and therefore enables and / or allows identification of dirty lines in main storage 214.

[0414] A main storage allocation policy may instruct the main cache controller to choose to sacrifice a modified line because the data for the memory address is not located in a higher level cache and, instead, is located in a higher level cache but is outdated. Such an allocation policy may instruct the main cache controller not to allocate / sacrifice a clean line and / or a shared line in main storage because that line contains data for that memory address that is already located in a higher level cache (e.g., L2 cache, L3 cache, extended memory, etc.).

[0415] However, such an allocation policy creates latency (e.g., an increase in the time it takes the CPU to retrieve requested data) when only allocating dirty and / or modified lines in the L1 cache 110. This latency is a result of using extra clock cycles to retrieve data from higher levels of memory. For example, due to the parallel connection between main storage 214 and victim storage 218, retrieving data from higher levels of storage takes more time than retrieving data from victim storage 218.

[0416] In the examples described herein, the allocation policy reduces the latency of allocating cache lines from the main cache (e.g., main storage 214) to the victim cache (e.g., victim storage 218). For example, due to the architecture of the L1 cache 110 (e.g., the parallel connection between the main storage 214 and the victim storage 218), the allocation policy allows the main cache controller 222 to allocate any cache line (e.g., clean and / or dirty) in the main storage 214 to the victim storage 218. By configuring the main storage 214 and the victim storage 218 in parallel, the victim storage 218 can act as an extension of the main storage 214. Thus, in addition to providing a location for storing victim lines, the victim storage 218 can also provide additional associativity to the main storage 214 by moving any cache line (e.g., clean and / or dirty) from the main storage 214 to the victim storage 214. For example, because victim storage 218 and main storage 214 are accessed in parallel (e.g., simultaneously) by CPU 102, if a clean line is to be accessed and it is allocated to victim storage 218, the latency to access a clean line of data is not affected.

[0417] In exemplary operation, the main cache controller 222 obtains an instruction (e.g., a memory operation) from the CPU interface 202 (e.g., the scalar interface 502 and / or the vector interface 504). The main cache controller 222 obtains a result from the main tag RAM access 204 corresponding to the instruction. For example, the main tag RAM access 204 determines whether an address in the instruction matches an address in the tag RAM 208 and provides the result to the main cache controller 222. In some examples, the main cache controller 222 determines, based on the instruction and the result from the main tag RAM access 204, whether the main storage 214 should victimize data and / or allocate data to the victim storage 218. For example, the main cache controller 222 determines whether the instruction is a read operation and whether the read operation is a miss (e.g., determined based on the result of the main tag RAM access 204). If the read operation is a miss, the main cache controller 222 determines that the main storage 214 needs to allocate a line, way, block, slot, etc. of data for allocation in the victim storage 218.

[0418] In some examples, the main cache controller 222 allocates a line corresponding to the address of the read miss operation. For example, if a read operation wants to read data from address A, but main storage 214 stores different data for that address location (e.g., address A'), the main cache controller 222 must remove the data at address A' because the data at address A can only be stored in one location (e.g., address A) in main storage 214. The main cache controller 222 identifies a location in the direct-mapped cache (e.g., main storage 214) that maps to address A' and allocates the data at address A' to the victim storage 218. Thus, the read operation can store the data at address A in main storage 214.

[0419] Exemplary methods, apparatus, systems, and articles of manufacture for allocating data are described herein. Further examples and combinations thereof include the following:

[0420] Example 1 includes an apparatus including a first cache storage, a second cache storage, and a cache controller coupled to the first cache storage and the second cache storage, the cache controller operable to receive a memory operation identifying an address, determine based on the address that the memory operation should evict a first set of data from the first cache storage, determine that the first set of data is unchanged relative to the expanded memory, and cause the first set of data to be stored in the second cache storage.

[0421] Example 2 includes the apparatus of example 1, wherein the cache controller is for identifying a portion within the first cache storage that corresponds to the direct-mapped location of the address.

[0422] Example 3 includes the apparatus of example 1, wherein the cache controller is to allocate the first set of data to the second cache storage to make space for data of the second memory operation.

[0423] Example 4 includes the apparatus of example 1, wherein the cache controller receives a second memory operation identifying a second address; determines, based on the second address, that the second memory operation should evict a second set of data from the first cache storage; determines that the second set of data has been modified relative to the expanded memory; and causes the second set of data to be stored in the second cache storage.

[0424] Example 5 includes the apparatus of example 1, wherein the cache controller enforces outstanding transactions in the store queue on the first set of data during eviction.

[0425] Example 6 includes the apparatus of example 1, wherein the second cache storage is for providing associativity to the first cache storage when the second cache storage stores the first set of data.

[0426] Example 7 includes the apparatus of example 1, wherein the second cache storage is a victim cache storage.

[0427] Example 8 includes a method, including receiving a memory operation that identifies an address; determining, based on the address, that the memory operation should evict a first set of data from a first cache storage; determining that the first set of data is unchanged from the expanded memory; and causing the first set of data to be stored in a second cache storage.

[0428] Example 9 includes the method of example 8, further including identifying a portion within the first cache storage that corresponds to the direct-mapped location of the address.

[0429] Example 10 includes the method of example 8, further including allocating the first set of data to a second cache storage to make space for data of a second memory operation.

[0430] Example 11 includes the method of Example 8, further including receiving a second memory operation identifying a second address; determining, based on the second address, that the second memory operation should evict a second set of data from the first cache storage; determining that the second set of data has been modified to the expanded memory; and storing the second set of data in the second cache storage.

[0431] Example 12 includes the method of example 8, further including enforcing outstanding transactions in the store queue on the first set of data during eviction.

[0432] Example 13 includes the method of example 8, wherein storing the first set of allocated data from the first cache storage includes providing associativity to the first cache storage.

[0433] Example 14 includes the method of example 8, wherein the second cache storage is a victim cache storage.

[0434] Example 15 includes a system including a central processing unit that outputs a memory operation that identifies an address; a cache coupled to the central processing unit, the cache operable to obtain the memory operation from the central processing unit; and a first cache storage; a second cache storage; and a cache controller that determines, based on the address of the memory operation, that the memory operation should evict a first set of data from the first cache storage; determines that the first set of data is unchanged from the expanded memory; and causes the first set of data to be stored in the second cache storage.

[0435] Example 16 includes the system of example 15, wherein the cache further includes a first tag random access memory coupled to the central processing unit, the first cache storage, and the cache controller, and a second tag random access memory coupled to the central processing unit, the second cache storage, and the cache controller.

[0436] Example 17 includes the system of example 15, wherein the cache controller determines, based on a second address of the second memory operation, that the second memory operation should evict a second set of data from the first cache storage, determines that the second set of data has been modified to the expanded memory, and causes the second set of data to be stored in the second cache storage.

[0437] Example 18 includes the system of example 15, wherein the cache controller is to enforce outstanding transactions in the store queue on the first set of data during eviction.

[0438] Example 19 includes the system of example 15, wherein the first cache storage and the second cache storage are connected in parallel to the central processing unit.

[0439] Example 20 includes the system of example 15, wherein the first cache storage is a direct-mapped cache and the second cache storage is a fully associative cache, and wherein the direct-mapped cache and the fully associative cache are coupled in parallel to the central processing unit.

[0440] Method and apparatus for facilitating read-modify-write support in a coherent victim cache with parallel data paths

[0441] To facilitate a memory system that operates coherently with memory, i.e., where corresponding memory locations for each processing element contain the same stored data, some example systems avoid including victim storage. The examples described herein overcome this challenge by facilitating a fully coherent memory system in which victim storage (e.g., victim storage 218) can operate with memory coherence operations within the system.

[0442] To provide coherency on data cache 108, an example scalar interface 502 (e.g., a 64-bit wide interface) and an example vector interface 504 (e.g., a 512-bit wide interface) are included in victim storage 218 of L1 cache 110. In this manner, victim storage 218 of L1 cache 110 may handle two data paths from CPU 102.

[0443] In some examples described herein, snoop address component 506 is used to store the MESI state of all cache lines in victim storage 218 in MESI RAM 300. By storing the MESI state of each cache line in MESI RAM 300, the victim cache system supports coherency.

[0444] The example snoop address component 506 also obtains example snoop requests from a higher level memory cache memory (e.g., L2 data cache 112) and transmits such snoop requests to tag RAM 210 and comparison logic 306c. In some examples, the snoop address component 506 triggers an address read instruction to tag RAM 210. For example, if L2 data cache 112 cannot identify the requested data in a read request from CPU 102, L2 data cache 112 transmits snoop address component 506 to lower level L1 data cache 110 to attempt to fulfill the read request of the memory address in tag RAM 210. The snoop address component 506 also provides the read address to comparison logic 306c. If a miss is identified (e.g., if a read issued to tag RAM 210 returns a miss), an appropriate snoop response indicating that the read failed is generated and sent to the higher level data cache (e.g., L2 data cache 112) that generated snoop address component 506.

[0445] Alternatively, if a hit is identified (e.g., a read issued to tag RAM 210 returns a hit), the state of the corresponding line in MESI RAM 300 is read, and the example address encoder 326c generates an address value for victim storage 218 to use in retrieving the data. An appropriate response indicating that the read request was successful is then generated and returned as a snoop response to the higher level data cache that generated snoop address component 506 (e.g., L2 data cache 112). In the example described herein, the snoop response includes the data in victim storage 218 that corresponds to the address in tag RAM 210.

[0446] In exemplary operation, the corresponding store queue (e.g., victim cache store queue 216) may be processing a write instruction to an address being read via the snoop address. Thus, while victim storage 218 is processing the snoop request (e.g., while a snoop request is being processed in response to snoop address component 506 obtaining the snoop request), victim cache store queue 216 forwards data from victim cache store queue 216 (e.g., data stored in latch 402e) to response multiplexer 508. In this manner, any state changes obtained by vector interface 504 due to the snoop address and any recently updated addresses obtained from victim cache store queue 216 are forwarded to a higher level data cache (e.g., L2 data cache 112).

[0447] In the topology illustrated in FIG. 5, the coherency pipeline is longer than the victim cache pipeline to provide sufficient time for the victim cache controller 224 to properly order possible snoop responses and / or subsequent CPU 102 operations when such snoop responses and / or subsequent CPU 102 operations are issued to a higher-level memory controller.

[0448] In the examples described herein, victim storage 218 of L1 data cache 110 may issue tag updates to a higher-level cache controller when cache line tracking is required. In this way, victim storage 218 may facilitate cache line tracking and distinguish between exclusive and modified cache elements.

[0449] In the example described herein, the victim storage 218 of the L1 data cache 110 supports global coherence operations by iterating over the tag RAM 208 on a set-by-set basis, allowing global coherence operations to be processed on a fully associative cache.

[0450] Although the above operations are described with reference to L1 data cache 110, any of the above operations and / or elements may be implemented on any of L2 data cache 112, L3 data cache 114, and / or any additional level data cache within data cache 108.

[0451]

[0009] Exemplary methods, apparatus, systems, and articles of manufacture for facilitating read-modify-write support in a coherent victim cache with parallel data paths are described herein. Further examples and combinations thereof include the following:

[0452] Example 1 includes an apparatus, the apparatus including: a random access memory configured to be coupled to a central processing unit via a first interface and a second interface, the random access memory configured to receive a read request indicating a first address for reading via the snoop interface; an address encoder coupled to the random access memory, the address encoder generating a second address corresponding to a victim cache based on the first address when the random access memory indicates a hit for the read request; and a multiplexer coupled to the victim cache for sending a response including data retrieved from the second address of the victim cache.

[0453] Example 2 includes the device of example 1, where the read request is sent by the level 2 data cache.

[0454] Example 3 includes the apparatus of example 1, wherein the multiplexer is configured to be coupled to the victim cache storage queue, the multiplexer obtaining input data from the victim cache storage queue indicating a value to be written to the second address.

[0455] Example 4 includes the apparatus of example 3, wherein the multiplexer is configured to send a response that includes the input data from the victim cache storage queue.

[0456] Example 5 includes the apparatus of example 1, wherein the random access memory is a tag random access memory.

[0457] Example 6 includes the apparatus of example 1, wherein the victim cache is a multi-bank memory.

[0458] Example 7 includes the apparatus of example 1, wherein the first interface is a scalar interface and the second interface is a vector interface.

[0459] Example 8 includes the apparatus of example 7, wherein the scalar interface is a 64-bit wide interface and the vector interface is a 512-bit wide interface.

[0460] Example 9 includes a system including a controller, a first memory, and a second memory configured to retrieve a snoop request from the first memory, the second memory configured to execute a random access memory read request in response to the snoop request, generate an address corresponding to a victim cache for use in the victim cache read when the random access memory indicates a hit for the read request, and send a response to the second memory including data retrieved from the address in the victim cache.

[0461] Example 10 includes the system of example 9, wherein the first memory is a level 2 cache memory and the second memory is a level 1 cache memory.

[0462] Example 11 includes the system of Example 9, wherein the second memory includes a multiplexer configured to be coupled to the victim cache storage queue, the multiplexer to obtain input data from the victim cache storage queue indicating a value to be written to an address of the victim cache in the second memory.

[0463] Example 12 includes the system of example 11, wherein the multiplexer is configured to send a response that includes the input data from the victim cache storage queue.

[0464] Example 13 includes the system of example 9, wherein the second memory is coupled to the controller via the scalar interface and the vector interface, and the second memory is coupled to the first memory via the snoop interface.

[0465] Example 14 includes the system of Example 13, where the scalar interface is a 64-bit wide interface and the vector interface is a 512-bit wide interface.

[0466] Example 15 includes the system of example 13, wherein the controller is a central processing unit.

[0467] Example 16 includes a method, the method including: obtaining a read request indicating a first address to read via a snoop interface; and, when the read request is a hit, generating a second address corresponding to a victim cache based on the first address; and generating a response including data obtained from the second address in the victim cache.

[0468] Example 17 includes the method of example 16, further including sending the read request from the level 2 data cache.

[0469] Example 18 includes the method of example 16, further including obtaining input data from the victim cache storage queue indicating a value to be written to the second address.

[0470] Example 19 includes the method of example 18, further including sending a response including the input data from the victim cache storage queue.

[0471] Example 20 includes the method of example 16, wherein the victim cache is a multi-bank memory.

[0472] Method and apparatus for eviction in a dual data path victim cache system

[0473] In a victim cache system, a main cache (e.g., main storage 214) sacrifices (e.g., allocates) a cache line to a victim cache (e.g., victim storage 218) when the main cache needs to store new data. When the main cache creates a victim, a replacement policy (e.g., replacement policy component 308) determines where in the victim cache (e.g., victim storage 218) the victim can be stored. In some instances, the victim cache is full, and therefore data needs to be evicted to a higher level cache memory (e.g., L2 cache 112, L3 cache 114, extended memory 106). The victim cache (e.g., victim storage 218) also evicts data to the higher level cache memory when a write miss occurs. For example, the victim storage 218 includes a write miss buffer that buffers write miss data. The replacement policy may use a fixed scheme to determine which data to evict from the victim cache. For example, the eviction scheme may be a first in first out (FIFO), a random scheme, or a least recently used (LRU) scheme. However, such eviction schemes are not designed to efficiently manage the eviction of data from victim caches when there are two or more data paths.

[0474] For example, the FIFO approach evicts the block of data that has been in the victim cache the longest (e.g., data in slot 0 if the eviction occurs for the first time). In a dual data path victim cache system (e.g., the victim cache section shown in FIG. 5), the FIFO approach does not work when two incoming CPU accesses (e.g., instructions) are both misses and / or both allocating instructions. In such an instance, an additional stall is created if the two sets from the victim cache are not speculatively locked and read.

[0475] In another example, main storage 214 stores address A, and victim storage 218 stores address B. CPU 102 sends two requests: CPU 102 requests to read data at address A' using DP0, and CPU 102 requests to read data from address B using DP1. The data at address A' is mapped to the same location in main storage 214 as address A. Therefore, a first data path DP0 must allocate the data at address A to victim storage 218 (e.g., allocate the data at address A' to main storage 214). In a typical FIFO scheme, address A would be allocated to slot 0 of victim storage 218. However, slot 0 is occupied by address B, and CPU 102 is requesting to access address B in parallel with the request to allocate data for the read instruction to address A'. Thus, when data path DP0 evicts address B from slot 0, a stall (e.g., the cycle or number of cycles that CPU 102 is stalled waiting for a memory access) is created in order to later retrieve the evicted data from a higher level cache.

[0476] Examples described herein include an eviction scheme that efficiently evicts data from victim storage 218 in a dual data path victim cache system. The example eviction scheme is implemented by replacement policy component 308 of FIGS. 3 and 5 . For example, replacement policy component 308 includes logic that analyzes input and generates output. For example, replacement policy component 308 takes input from hit-miss comparison logic 306 a and 306 b and determines which locations in victim storage 218 should be replaced with data from main storage 214 and / or should be replaced with data from a write miss instruction. In examples described herein, replacement policy component 308 reserves entries (e.g., ways, sets, cache lines, etc.) in victim storage 218 that correspond to the eviction locations. For example, replacement policy component 308 speculatively locks (e.g., reserves) the first and second victim cache lines (e.g., sets) specifically for eviction. The first and second victim cache lines may be locked to a particular data path (e.g., the first victim cache line locked to DP0 and the second victim cache line locked to DP1). The eviction logic implemented by the replacement policy component 308 is described in further detail below in connection with FIG. 6.

[0477] Referring to FIG. 6 , an example first table 602 and an example second table 604 are shown. The example first and second tables 602, 604 illustrate the logic of the example replacement policy component 308. The example replacement policy component 308 utilizes an LRU value. As used herein, an LRU value corresponds to a least recently used portion of the victim storage 218. In some examples, an LRU value corresponds to a location in the victim storage element 218 that has not been recently accessed by the first or second data path. In a fully associative cache (e.g., the victim storage 218), an address can map to any “way” in the cache. Thus, a way is a block in the cache that stores data and includes a tag. In some LRU schemes, when a victim cache needs to evict data, the data in the location indicated by the LRU value (e.g., data in the portion of the victim storage 218 that has not been recently accessed) is evicted. For example, in a 3-way cache, address A, address B, and address C occupy all three ways (e.g., blocks, slots, etc.). In this example, address A was most recently accessed by CPU 102, address B was accessed immediately before address A access, and address C was accessed before address B. Therefore, address C is the least recently used address, and the portion mapped to address C has a location equal to the LRU value.

[0478] The example first table 602 of FIG. 6 includes a first data path scenario 606, a second data path scenario 608, and a third data path scenario 610. The example data path scenarios 606, 608, and 610 correspond to the validity of transactions (e.g., accesses) on DP0 and DP1 of FIG. 5. The validity of a transaction corresponds to whether the CPU 102 sends a valid instruction to the L1 cache 110. A valid instruction on the first data path DP0 and an invalid instruction on the second data path DP1 corresponds to when a processing core sends an instruction on the first data path DP0 and leaves the second data path DP1 idle. In some examples, during a particular clock cycle, the first data path DP0 contains an invalid instruction. In some examples, during a particular clock cycle, the second data path DP1 contains an invalid instruction. Additionally and / or alternatively, both data paths DP0 and DP1 may contain valid instructions and / or invalid instructions.

[0479] In the first example table 602, a first data path scenario 606 corresponds to the case where both data paths (DP0, DP1) in Figure 5 contain valid transactions (DP0_valid=1, DP1_valid=1) in the same clock cycle. In some examples, the replacement policy component 308 obtains results and / or instructions from both data paths DP0, DP1.

[0480] In the example of the first table 602, a second data path scenario 608 corresponds to a first data path (DP0) that includes a valid transaction (DP0 valid = 1) and a second data path (DP1) that includes an invalid transaction (DP1 valid = 0). In such an example, the replacement policy component 308 determines that the transaction of DP1 includes an invalid instruction.

[0481] In the example of the first table 602, a third data path scenario 610 corresponds to a first data path (DP0) that includes an invalid transaction (DP0 valid = 0) and a second data path (DP1) that includes a valid transaction (DP1 valid = 1). In some examples, the replacement policy component 308 determines that the transaction of DP0 includes an invalid instruction.

[0482] The example first data path scenario 606 in the example first table 602 includes an example hit-hit action 612, an example miss-hit action 614, an example hit-miss action 616, and an example miss-miss action 618. The example hit-hit action 612 indicates that the address on DP0 and the address on DP1 hit (e.g., match) an address in either of the tag RAMs 208, 210. In other words, the example hit-hit action 612 indicates that the address on DP0 and the address on DP1 hit an address in the main storage 214, the victim storage 218, and / or the write miss cache (discussed above in connection with FIGS. 3A-3D ). The example miss-hit action 614 indicates that the address on DP0 does not match an address in the main storage 214, the victim storage 218, and / or the write miss cache, and the address on DP1 hits an address in the main storage 214, the victim storage 218, and / or the write miss cache. In some examples, the miss portion of the miss-hit action 614 indicates that DP0 is to allocate a cache line from main storage 214 to victim storage 218, thereby evicting data from victim storage 218 to make room for the cache line in main storage 214. The example hit-miss action 616 indicates that the address on DP0 hits an address in the victim storage 218 and / or the write miss cache, and that the address on DP1 does not match an address in the victim storage 218 and / or the write miss cache. In some examples, the miss portion of the hit-miss action 616 indicates that DP1 is to allocate a cache line from main storage 214 to victim storage 218, thereby evicting data from victim storage 218 to make room for the cache line in main storage 214. The example miss-miss action 618 indicates that the addresses of both DP0 and DP1 do not have a match in the victim storage 218 and / or the write miss cache.In some examples, the miss-miss action 618 indicates that both data paths DP0 and DP1 are for allocating data from main storage 214 to victim storage 218. Additionally and / or alternatively, the miss indicates that a write miss is for writing data to a write miss buffer in victim storage 218.

[0483] The example second data path scenario 608 in the example first table 602 includes an example DP0 hit action 620 and an example DP0 miss action 622. In the second path scenario 608, the first data path DP0 includes a valid transaction and the second data path DP1 includes an invalid transaction. In some examples, the replacement policy component 308 ignores the second data path DP1 because the second data path DP1 does not include an instruction.

[0484] The example third data path scenario 610 in the example first table 602 includes an example DP1 hit action 624 and an example DP1 miss action 626. The example DP1 hit action 624 corresponds to an action taken by the replacement policy component 308 when an address on the second data path DP1 matches an address in the victim storage 218 and / or the write miss cache. The example DP1 miss action 624 corresponds to an action taken by the replacement policy component 308 when an address on the second data path DP1 does not match an address in the victim storage 218 and / or the write miss cache. Similar to the example DP0 hit action 620 and DP0 miss action 622 under the example second data path scenario 608, the example replacement policy component 308 ignores the transaction on the first data path DP0 in the example third data path scenario 610 because the transaction is invalid.

[0485] In the first example table 602, DP0 Hit Way indicates the portion of victim storage 218 and / or write miss cache that should be accessed by the first data path DP0 when the instruction hits (e.g., read, evict, write, etc.). In the first example table 602, DP1 Hit Way is the portion within victim storage 218 and / or write miss cache that should be accessed by the second data path DP1 when the instruction hits.

[0486] In the example first table 602, the variable "Y" indicates the location of the current way selected as LRU and is a variable that indicates the location from which the first data path DP0 should remove data. In some examples, Y is assigned to the DP0 pointer. For example, when DP0 needs to evict a portion of the victim storage 218, the DP0 pointer points to location Y (e.g., the LRU way) for eviction. In some examples, the replacement policy component 308 is for storing an indicator of the LRU way of the victim storage 218 that should be replaced by DP0. For example, the replacement policy component 308 may be accessed by the cache controller 220 to hold an indicator that a particular way that has not been accessed recently is available for eviction by the first data path DP0. As used herein, the terms "pointer" and "indicator" may be used interchangeably.

[0487] In the example first table 602, the variable "Y+U" indicates the location of the next LRU way from which the second data path DP1 should remove data. In some instances, "Y+1" is assigned to the DP1 pointer. For example, if the second data path DP1 needs to evict a portion of the victim storage 218, the DP1 pointer points to location Y+1 (e.g., the next LRU way) for eviction. In some examples, the replacement policy component 308 is for storing an indicator of the LRU way of the victim storage 218 that should be replaced by DP1. For example, the replacement policy component 308 may be accessed by the cache controller 220 to hold an indicator that a particular way that has not been accessed recently is available for eviction by the first data path DP0.

[0488] In a first example operation of the replacement policy component 308, both data paths (DP0 and DP1) contain valid transactions (e.g., as shown in first data path scenario 606), and both data paths (DP0 and DP1) contain addresses that match addresses in the example victim storage element 218 (e.g., hit action 612). For example, comparison logic 306a and 306b compare the addresses of DP0 and DP1 with the addresses of the example tag RAM 210 and provide a hit result to the replacement policy component 308. Because both data paths are valid and both data paths are hits, the DP0 Hit Way points to the portion (e.g., way) in the victim storage 218 that contains the hit / matching data corresponding to data path DP0, and the DP1 Hit Way points to the way that contains the hit / matching data corresponding to data path DP1. The victim storage 218 responds with the requested data. The location of the LRU way is not incremented and remains at location Y.

[0489] In a second example operation of the replacement policy component 308, both data paths (DP0 and DP1) contain valid transactions (e.g., as shown in first data path scenario 606), the first data path DP0 is a miss, and the second data path DP1 is a hit to the victim storage 218 (e.g., miss-hit action 614). For example, the first comparison logic 306a returns a “miss” result to the replacement policy component 308, and the second comparison logic 306b returns a “hit” result to the replacement policy component 308. The DP1 Hit Way points to a portion (e.g., a way) within the victim storage 218 that contains the hit / matching data (e.g., Hit Way). In some examples, the first data path DP0 is for evicting data from a portion (e.g., a way) within the victim storage 218. Thus, the DP0 pointer points to location Y within the victim storage 218 to be evicted.

[0490] Before the eviction occurs, replacement policy component 308 determines whether DP1 Hit Way matches the address of the LRU way (e.g., location Y). If DP1 Hit Way does not have the same location as Y, then the DP0 pointer points to a way (e.g., the LRU way) that has a location equal to location Y. If DP1 Hit Way does not match the address of the LRU way, then the DP0 pointer points to the location of the DP1 pointer (Y+1), so DP0 can evict data without conflicting with the DP1 Hit Way.

[0491] In a second example scenario 614, the LRU value and the next LRU value are incremented based on which location was evicted. For example, if DP0 evicted data from location Y+1 (e.g., DP1 Hit Way matches the location of the DP0 pointer), the LRU value is incremented twice and the next LRU value is incremented twice. Alternatively, if DP0 evicted data from location Y (e.g., DP1 Hit Way did not match the location of the DP0 pointer), the LRU value is incremented once and the next LRU value is incremented once.

[0492] In a third example operation of the replacement policy component 308, both data paths (DP0 and DP1) contain valid transactions (e.g., as shown in first data path scenario 606), with the first data path DP0 being a hit and the second data path DP1 being a miss (e.g., hit-miss action 616). For example, the first comparison logic 306a returns a “hit” result to the replacement policy component 308, and the second comparison logic 306b returns a “miss” result to the replacement policy component 308. The DP0 Hit Way points to the way in the victim storage 218 that contains the hit / matching data. In some examples, the miss causes the second data path DP1 to evict a way to make space in the victim storage 218. Thus, the DP1 pointer points to location Y+1 in the victim storage 218 to be evicted.

[0493] Before the eviction occurs, the replacement policy component 308 determines whether the DP0 Hit Way matches the address of the next LRU way (e.g., location Y+1). If the replacement policy component 308 determines that the DP0 Hit Way matches the address of the next LRU way (e.g., Y+1), the DP1 pointer points to the location of the DP0 pointer (e.g., location Y) so that DP1 can evict the data without conflicting with the DP0 Hit Way. If the DP0 Hit Way does not match the address of the next LRU way, DP1 evicts the data from location Y+L.

[0494] In a third example scenario 616, the LRU value and next LRU value are incremented based on which location was evicted. For example, if DP1 evicts data from location Y (e.g., DP0 Hit Way matches the location of the DP1 pointer), the LRU value is incremented once and the next LRU value is incremented once. Otherwise, if DP1 evicts data from location Y+1 (e.g., DP0 Hit Way did not match the location of the DP1 pointer), the LRU value is incremented twice and the next LRU value is incremented twice.

[0495] In a fourth example operation of the replacement policy component 308, both data paths (DP0 and DP1) contain valid transactions (e.g., as shown in the first data path scenario 606) and both data paths are flagged as misses (e.g., column 618). For example, the comparison logic 306a and 306b return a "miss" result to the replacement policy component 308 if both addresses in data paths DP0 and DP1 are not found and / or do not match the addresses in the tag RAMs 208, 210. In the fourth operation, both data paths DP0 and DP1 are for evicting ways in the victim storage 218. Thus, the DP0 pointer points to location Y and the DP1 pointer points to location Y+L.

[0496] When both eviction operations are complete, the LRU value is incremented by 2 (e.g., Y+2) and the next LRU value is incremented by 2 (e.g., (Y+1)+2). On subsequent operations, if DP0 and DP1 miss, the DP0 way points to the new LRU value (e.g., Y+2) and the DP1 way points to the next LRU value (e.g., (Y+1)+2).

[0497] In a fifth example operation of the replacement policy component 308, the first data path DP0 is a valid transaction and the second data path DP1 is an invalid transaction (e.g., as shown in second data path scenario 608). In the fifth example operation, the first data path DP0 is a hit (e.g., as shown in DP0 hit action 620). For example, the comparison logic 306a returns a "hit" result to the replacement policy component 308. The DP0 Hit Way points to the way in the victim storage 218 that contains matching data. The LRU value (Y) remains the same because there is no data to be evicted in the clock cycle.

[0498] In a sixth example operation of the replacement policy component 308, the first data path DP0 is a valid transaction and the second data path DP1 is an invalid transaction (e.g., as shown by second data path scenario 608). In the sixth example operation, the first data path DP0 is a miss (e.g., as shown by DP0 miss action 622). For example, the comparison logic 306a returns a "miss" result to the replacement policy component 308. In this example, the first data path DP0 is for evicting data from the victim storage 218. The example DP0 pointer points to location Y (e.g., the LRU way). After the eviction, the LRU value is incremented (e.g., Y+1).

[0499] In a seventh example operation of the replacement policy component 308, the first data path DP0 is an invalid transaction and the second data path DP1 is a valid transaction (e.g., as shown in the third data path scenario 610). In the seventh example operation, the second data path DP1 is a hit (e.g., as shown in the DP1 hit action 624). For example, the comparison logic 306b returns a "hit" result to the replacement policy component 308. The DP1 Hit Way points to the way in the victim storage 218 that contains matching data. The LRU value (Y) remains the same because there is no data to be evicted in the clock cycle.

[0500] In an eighth example operation of the replacement policy component 308, the first data path DP0 is an invalid transaction and the second data path DP1 is a valid transaction (e.g., as shown in third data path scenario 610). In the eighth example operation, the second data path DP1 is a miss (e.g., as shown in DP1 miss action 626). For example, the comparison logic 306b returns a “miss” result to the replacement policy component 308. In this example, the second data path DP1 is for evicting data from the victim storage 218. The DP1 pointer points to location Y (e.g., the LRU way). The DP1 pointer does not point to location Y+1 because of the invalid transaction of DP0. Otherwise, when both transactions are valid, DP1 always points to Y+1 (e.g., unless switched when the DP0 Hit Way matches Y+1). After the second data path DP1 evicts the data from location Y, the LRU value is incremented (e.g., to Y+1).

[0501] Referring to second table 604, second table 604 illustrates the increment of the LRU value when first data path DP0 and / or second data path DP1 are allocating data to victim storage 218. For example, when a read miss occurs, main storage 214 utilizes one of the data paths to allocate a data line to victim storage 218. Second table 604 includes a first valid column 626, a second valid column 628, a first allocation column 630, a second allocation column 632, a first LRU interference 634, a second LRU interference 636, and an LRU increment column 638.

[0502] In the second table 604, an example first valid column 626 corresponds to the validity of the second data path transaction. For example, a zero indicates that the DP1 transaction is invalid and a one indicates that the DP1 transaction is valid. An example second valid column corresponds to the validity of the first data path transaction. For example, a zero indicates that the DP0 transaction is invalid and a one indicates that the DP0 transaction is valid.

[0503] In the second table 604, an example first allocation column 630 indicates the allocation status of the second data path DP1. The allocation status corresponds to the allocation of data from the main storage 214 to the victim storage 218 in a clock cycle. For example, a zero indicates that the second data path DP1 has not allocated data to the victim storage 218, and a one indicates that the second data path DP1 has allocated data to the victim storage 218. An example second allocation column 632 indicates the allocation status of the first data path DP0. For example, a zero indicates that the first data path DP0 has not allocated data to the victim storage 218, and a one indicates that the first data path DP0 has allocated data to the victim storage 218. When a data path allocates data to the victim storage 218, the data path evicts ways (e.g., slots, blocks, etc.) to make space for the allocated data. In some examples, data is allocated to the victim storage 218 when a read miss occurs in the main storage 214.

[0504] In the second table 604, the first LRU interference column 634 indicates whether the first data path DP0 hits the same location in the victim storage 218 as the location of the second data path allocation pointer. For example, the address of the first data path DP0 is located at the least recently used location in the victim storage 218. The first LRU interference column 634 contains a 1 to indicate that the first data path DP1 hit location is equal to the location of the second data path DP1 allocation pointer.

[0505] The second LRU interference column 636 indicates whether the second data path DP1 hits a location in the victim storage 218 that is the same as the location of the second data path allocation pointer. For example, the address of the second data path DP1 is located at the least recently used location in the victim storage 218. The second LRU interference column 636 contains a 1 to indicate that the second data path DP1 hit location is equal to the location of the first data path allocation pointer. As used herein, the first data path allocation pointer points to location Y (the LRU value) when DP0 is allocated, and the second data path allocation pointer points to location Y+1 (the next LRU value) when DP1 is allocated. In some examples, the pointers inform the cache controller 220 to evict a portion of the victim storage 218 to a higher level cache (e.g., L2 112, L3 114, extended memory 106). The example replacement policy component 308 may initialize a first path allocation pointer to point to location Y (the LRU portion) and a second path allocation pointer to point to Y+1 (the next LRU portion).

[0506] In the second table 604, the LRU increment column 628 indicates the increment of the LRU value Y, for example, the replacement policy component 308 increments the LRU value by 1 (e.g., Y+1), by 2 (e.g., Y+2), or not at all (e.g., Y). In some examples, the increment of the LRU value depends on the status of data paths DP0 and DP1.

[0507] In an exemplary operation, both the first data path DP0 and the second data path DP1 contain valid transactions. The exemplary replacement policy component 308 determines whether either data path is allocated. For example, the cache controller 220 sends information to the replacement policy component 308 when the main storage 214 needs to allocate data.

[0508] If the first data path DP0 is allocating data (e.g., moving data from main storage 214 to victim storage 218), the first data path DP0 evicts the data (e.g., as indicated by the first data path allocation pointer) from the victim storage 214. To evict the data, the replacement policy component 308 determines whether the second data path DP1 was a hit and where the hit location is. For example, the replacement policy component 308 analyzes the location of the address of the second data path DP1 and determines whether the location matches the location of the first path allocation pointer.

[0509] If the second path hit location is equal to the location of the first path allocation pointer (e.g., DP1 hit location = Y), the replacement policy component 308 updates the first path allocation pointer to point to the next LRU value (Y+1) (e.g., notifies the cache controller 220 to evict the data of the next LRU value). In this way, the second data path DP1 reads / writes from the hit location Y, and the first data path DP0 evicts the data of the LRU location Y+L. This action prevents the first data path DP0 from evicting DP1's read / write data. After the eviction occurs (e.g., eviction of data from Y+1 in the victim storage 218), the replacement policy component 308 increments the first path allocation pointer by 2 and increments the second path allocation pointer by 2. For example, replacement policy component 308 increments the LRU value (Y) by 2 and the next LRU value (Y+1) by 2 because DP0 just evicted location Y+1, so the new LRU value is Y+2. This operation is illustrated in line 640.

[0510] If the second data path hit location is not equal to the location of the first data path allocation pointer (e.g., DP1 hit location is not equal to Y), the replacement policy component 308 notifies the cache controller 220 that location Y is being evicted. In this manner, the cache controller 220 evicts the data from location Y in the victim storage 218. After the eviction occurs (e.g., the eviction of the data from Y in the victim storage 218), the replacement policy component 308 increments the first path allocation pointer by 1 and increments the second path allocation pointer by 1. For example, the replacement policy component 308 increments the LRU value (Y) by 1 and the next LRU value (Y+1) by 1 because DP0 just evicted location Y, so the new LRU value is Y+L. This operation is illustrated in line 642.

[0511] In another operation, the second data path DP1 is allocating data (e.g., moving data from main storage 214 to victim storage), and the second data path DP1 evicts the data (e.g., as indicated by the second data path allocation pointer) from the victim storage 214. To evict the data, the replacement policy component 308 determines whether the first data path DP0 was a hit and where the hit location is. For example, the replacement policy component 308 analyzes the location of the address of the first data path DP0 and determines whether the location matches the location of the second path allocation pointer.

[0512] If the first path hit location is equal to the location of the second path allocation pointer (e.g., DP0 hit location = Y+1), the replacement policy component 308 updates the second path allocation pointer to point to the LRU value (Y) (e.g., notifies the cache controller 220 to evict the data at the LRU value). Thus, the first data path DP0 reads / writes from the hit location Y+1, and the second data path DP1 evicts the data at the LRU location Y. This action causes the second data path DP1 to not evict the read / write data of DP0. After the eviction occurs (e.g., the eviction of data from Y in the victim storage 218), the replacement policy component 308 increments the first path allocation pointer by 1 and increments the second path allocation pointer by 1. For example, replacement policy component 308 increments the LRU value (Y) by 1 and increments the next LRU value (Y+1) by 1 because DP1 just evicted location Y, so the new LRU value is Y+L. This operation is illustrated in line 644.

[0513] If the first data path hit location is not equal to the location of the second data path allocation pointer (e.g., DP0 hit location is not equal to Y+1), the replacement policy component 308 notifies the cache controller 220 that location Y+1 is to be evicted. In this manner, the cache controller 220 evicts data from location Y+1 in the victim storage 218. After the eviction occurs (e.g., eviction of data from Y+1 in the victim storage 218), the replacement policy component 308 increments the first path allocation pointer by 2 and increments the second path allocation pointer by 2. For example, the replacement policy component 308 increments the LRU value (Y) by 2 and the next LRU value (Y+1) by 2 because DP1 just evicted location Y+1, so the new LRU value is Y+2. This operation is illustrated in line 646.

[0514] Exemplary methods, apparatus, systems, and articles of manufacture for egress in sacrificial storage are described herein. Further examples and combinations thereof includ...

Claims

1. 1. An apparatus comprising: a first storage; A second storage; a store queue coupled to the first storage and the second storage; Including, The store queue: receiving a first memory operation identifying a first set of data; processing the first memory operation to store the first set of data in at least one of the first storage and the second storage; receiving a second memory operation; and feeding back the first set of data for use in the second memory operation before storing the first set of data in at least one of the first storage and the second storage; The apparatus is operable to:

2. 10. The apparatus of claim 1, the second memory operation is a read-modify-write operation and identifies a second set of data; The store queue: merging the first set of data and the second set of data to generate a third set of data before storing the first set of data in at least one of the first storage and the second storage; and providing a third set of the data for storage in at least one of the first storage and the second storage; The apparatus is operable to:

3. 3. The apparatus of claim 2, The apparatus further includes receiving a third memory operation indicating to read a third set of the data.

4. 10. The apparatus of claim 1, The apparatus, wherein the second storage is configured as a sacrificial storage for the first storage.

5. 10. The apparatus of claim 1, The apparatus, wherein the store queue further includes a data store configured to store first address values ​​of the first set of data.

6. 10. The apparatus of claim 1, The apparatus, wherein the store queue further comprises an error code correction generator for generating an error detection code.

7. 7. The apparatus of claim 6, The apparatus, wherein the error code correction generator is for generating the error detection code in response to processing the first memory operation.

8. 1. A method comprising: receiving a first memory operation specifying a first set of data; processing the first memory operation to store the first set of data in at least one of a first storage and a second storage; receiving a second memory operation; transmitting the first set of data for use in the second memory operation before storing the first set of data in at least one of the first storage and the second storage; A method comprising:

9. 9. The method of claim 8, the second memory operation is a read-modify-write operation and identifies a second set of data; The method comprises: merging the first set of data and the second set of data to generate a third set of data before storing the first set of data in at least one of the first storage and the second storage; providing the third set of data for storage in at least one of the first storage and the second storage; The method further comprises:

10. 10. The method of claim 9, The method further comprising receiving a third memory operation indicating to read a third set of the data.

11. 9. The method of claim 8, The method, wherein the second storage is configured as a victim storage for the first storage.

12. 9. The method of claim 8, The method further comprising storing a first address value of the first set of data.

13. 9. The method of claim 8, The method further comprising generating an error detecting code.

14. 14. The method of claim 13, The method further comprising generating the error detection code in response to processing the first memory operation.

15. 1. A system comprising: a central processing unit configured to transmit the first memory operation and the second memory operation; a first storage coupled to the central processing unit; a second storage coupled to the central processing unit; and a store queue coupled to the first storage, the second storage, and the central processing unit; Including, The store queue: receiving the first memory operation identifying a first set of data; processing a first memory operation to store the first set of data in at least one of the first storage and the second storage; receiving the second memory operation; feeding back the first set of data for use in the second memory operation before storing the first set of data in at least one of the first storage and the second storage; A system capable of operating as follows.

16. 16. The system of claim 15, the second memory operation is a read-modify-write operation and identifies a second set of data; The store queue: merging the first set of data and the second set of data to generate a third set of data before storing the first set of data in at least one of the first storage and the second storage; providing a third set of data for storage in at least one of the first storage and the second storage; A system capable of operating as follows.

17. 17. The system of claim 16, The system further includes receiving a third memory operation indicating to read a third set of the data.

18. 16. The system of claim 15, The system, wherein the second storage is configured as a victim storage for the first storage.

19. 16. The system of claim 15, The system, wherein the store queue further includes a data store configured to store first address values ​​of the first set of data.

20. 16. The system of claim 15, The apparatus, wherein the store queue further includes an error code correction generator that generates an error detection code in response to processing the first memory operation.

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