Image pickup device

Abstract

To provide an imaging element for expanding a dynamic range.SOLUTION: The image sensor includes a first substrate (7) including a photodiode (31) and a transfer unit (FD), the photodiode (31) being a photoelectric conversion unit configured to generate a charge in an amount corresponding to a light amount of incident light, the transfer unit (FD) being configured to transfer the charge converted by the photoelectric conversion unit, and a second substrate stacked on the first substrate and including a transfer signal supplying unit (307a) configured to supply a transfer signal for controlling the transfer unit to the transfer unit.SELECTED DRAWING: Figure 5

Description

[Technical Field]

[0001] The present invention relates to an imaging device. [Background technology]

[0002] Conventionally, there has been known an imaging element in which a chip on which pixels are formed and a chip on which a pixel drive circuit for driving the pixels are formed are stacked (for example, Patent Document 1). In order to control the exposure amount for each pixel in a conventional imaging element, there was a problem in that two power supplies for transfer pulses had to be provided for each pixel. [Prior art documents] [Patent documents]

[0003] [Patent Document 1] Japanese Patent Publication No. 2010-225927 Summary of the Invention

[0004] According to a first aspect, an imaging element includes a first semiconductor substrate having a first photoelectric conversion unit that converts light into electric charges, a second photoelectric conversion unit that converts light into electric charges and is arranged alongside the first photoelectric conversion unit in the row direction, a first transfer unit that transfers the electric charges converted by the first photoelectric conversion unit, and a second transfer unit that transfers the electric charges converted by the second photoelectric conversion unit, and a second semiconductor substrate stacked on the first semiconductor substrate, having a first transfer signal supply unit that supplies a transfer signal to the first transfer unit for controlling the first transfer unit, and a second transfer signal supply unit that supplies a transfer signal to the second transfer unit for controlling the second transfer unit. [Brief explanation of the drawings]

[0005] [Figure 1] 1 is a cross-sectional view schematically illustrating a configuration of an imaging device; [Figure 2] Cross-section of the image sensor [Figure 3] Block diagram showing the pixel configuration [Figure 4]Circuit diagram of analog circuit section and pixel driving section [Figure 5] 1 is a diagram schematically illustrating well structures of a first semiconductor substrate and a second semiconductor substrate; [Figure 6] Timing chart showing an imaging sequence using an imaging element [Figure 7] FIG. 2 is a diagram schematically illustrating well structures of a first semiconductor substrate, a second semiconductor substrate, and a third semiconductor substrate; [Figure 8] 1 is a diagram schematically illustrating well structures of a first semiconductor substrate and a second semiconductor substrate; [Figure 9] 1 is a diagram schematically illustrating well structures of a first semiconductor substrate and a second semiconductor substrate; [Figure 10] 1 is a diagram schematically illustrating well structures of a first semiconductor substrate and a second semiconductor substrate; [Figure 11] 1 is a diagram schematically illustrating well structures of a first semiconductor substrate and a second semiconductor substrate; DETAILED DESCRIPTION OF THE INVENTION

[0006] (First embodiment) 1 is a cross-sectional view schematically illustrating the configuration of an imaging device using an imaging element according to Embodiment 1. The imaging device 1 includes an imaging optical system 2, an imaging element 3, a control unit 4, a lens driving unit 5, and a display unit 6.

[0007] The imaging optical system 2 forms a subject image on the imaging surface of the imaging element 3. The imaging optical system 2 is made up of a lens 2a, a focusing lens 2b, and a lens 2c. The focusing lens 2b is a lens for adjusting the focus of the imaging optical system 2. The focusing lens 2b is configured to be drivable in the direction of the optical axis O.

[0008] The lens driving unit 5 has an actuator (not shown). The lens driving unit 5 uses this actuator to drive the focusing lens 2b by a desired amount in the direction of the optical axis O. The imaging element 3 captures an image of a subject and outputs the image. The control unit 4 controls each unit, including the imaging element 3. The control unit 4 performs image processing and the like on the image signal output by the imaging element 3, and records the image on a recording medium (not shown) or displays the image on the display unit 6. The display unit 6 is a display device having a display member such as a liquid crystal panel.

[0009] FIG. 2 is a cross-sectional view of the image sensor 3. Note that FIG. 2 shows only a partial cross-section of the entire image sensor 3. The image sensor 3 is a so-called back-illuminated image sensor. The image sensor 3 photoelectrically converts incident light from above the paper surface. The image sensor 3 includes a first semiconductor substrate 7 and a second semiconductor substrate 8.

[0010] The first semiconductor substrate 7 includes at least a PD layer 71 and a wiring layer 72. The PD layer 71 is disposed on the back side of the wiring layer 72. A plurality of photodiodes 31, which are embedded photodiodes, are two-dimensionally disposed in the PD layer 71. Therefore, the surface of the PD layer 71 facing the wiring layer 72 (i.e., the surface opposite to the incident side of incident light) has the opposite conductivity type to that of the PD layer 71. For example, if the PD layer 71 is an N-type semiconductor layer, a P-type semiconductor layer with a high concentration and a thin thickness is disposed on the surface facing the wiring layer 72. A ground voltage (GND) is applied to the first semiconductor substrate 7 as a substrate voltage. Various circuits for reading out signals from at least the photodiodes 31 are disposed on the second semiconductor substrate 8. Specifically, part of a pixel drive unit 307 (a transfer signal supply unit 307a and a second reset signal supply unit 307c that handle negative voltages) is disposed on the second semiconductor substrate 8. A voltage VTxL (described later) is applied to the second semiconductor substrate 8 as a substrate voltage.

[0011] A plurality of color filters 73 corresponding to the plurality of photodiodes 31 are provided on the incident side of the PD layer 71 where incident light is incident. There are a plurality of types of color filters 73 that transmit wavelength regions corresponding to red (R), green (G), and blue (B), respectively. For example, three types of color filters 73 corresponding to red (R), green (G), and blue (B) are arranged in a Bayer array.

[0012] A plurality of microlenses 74 corresponding to each of the plurality of color filters 73 are provided on the incident light side of the color filters 73. The microlenses 74 focus the incident light toward the corresponding photodiode 31. The incident light that passes through the microlenses 74 has only a partial wavelength range filtered by the color filters 73 and is then incident on the photodiode 31. The photodiode 31 performs photoelectric conversion on the incident light to generate an electric charge.

[0013] A plurality of bumps 75 are arranged on the surface of the wiring layer 72. A plurality of bumps 76 corresponding to the plurality of bumps 75 are arranged on the surface of the second semiconductor substrate 8 facing the wiring layer 72. The plurality of bumps 75 and the plurality of bumps 76 are bonded to each other. The first semiconductor substrate 7 and the second semiconductor substrate 8 are electrically connected via the plurality of bumps 75 and the plurality of bumps 76.

[0014] As will be described in detail later, the imaging element 3 has a plurality of pixels 30. One pixel 30 includes a first pixel 30x provided on the first semiconductor substrate 7 and a second pixel 30y provided on the second semiconductor substrate 8. One first pixel 30x includes one microlens 74, one color filter 73, one photodiode 31, etc. In addition to these, the first pixel 30x also includes various circuits (described later) provided on the first semiconductor substrate 7. The second pixel 30y also includes various circuits (described later) provided on the second semiconductor substrate 8.

[0015] 3 is a block diagram schematically illustrating the configuration of a pixel 30. The pixel 30 includes an analog circuit unit 301, an A / D conversion unit 302, a sampling unit 303, a pixel value holding unit 304, a pixel driving unit 307, an individual pixel control unit 306, and a calculation unit 305.

[0016] The analog circuit unit 301 outputs the result of photoelectric conversion of the incident light as an analog signal to the A / D conversion unit 302. The A / D conversion unit 302 samples the analog signal output by the analog circuit unit 301 and outputs a digital signal multiplied by a predetermined gain. The A / D conversion unit 302 repeatedly samples the pixel reset signal and the pixel signal, and outputs the sampling results of the pixel reset signal and the sampling results of the pixel signal separately as digital signals.

[0017] The sampling unit 303 calculates and stores the integral of the sampling results of the pixel reset signal and the pixel signal. The sampling unit 303 includes a first adder 308 and a first memory 309 for the pixel reset signal, and a second adder 310 and a second memory 311 for the pixel signal.

[0018] The sampling unit 303 adds the sampling result of the pixel reset signal output by the A / D conversion unit 302 to the integrated value of the past sampling results held in the first memory 309 using the first adder 308. The sampling unit 303 stores this addition result in the first memory 309. The sampling unit 303 updates the value stored in the first memory 309 every time the A / D conversion unit 302 outputs a sampling result of the pixel reset signal.

[0019] The sampling unit 303 adds the sampling result of the pixel signal output by the A / D conversion unit 302 to the integrated value of the past sampling result held in the second memory 311 using the second adder 310. The sampling unit 303 stores this addition result in the second memory 311. The sampling unit 303 updates the value stored in the second memory 311 every time the A / D conversion unit 302 outputs the sampling result of the pixel signal.

[0020] As described above, the A / D conversion unit 302 and the sampling unit 303 repeatedly sample the pixel reset signal and the pixel signal and integrate the sampling results. This processing is so-called correlated multiple sampling processing.

[0021] When the individual pixel control unit 306 has completed a predetermined number of samplings, the sampling unit 303 outputs a digital value based on the values ​​stored in the first memory 309 and the values ​​stored in the second memory 311 to the pixel value holding unit 304. The pixel value holding unit 304 stores this digital value as the result of photoelectric conversion by the pixel 30. The pixel value holding unit 304 is connected to a signal line 340. The digital value stored in the pixel value holding unit 304 can be read out from outside via the signal line 340.

[0022] The calculation unit 305 calculates the number of repetitions, exposure time, gain, etc. in the correlated multiple sampling process based on an externally instructed exposure time and the previous photoelectric conversion result stored in the pixel value storage unit 304. The individual pixel control unit 306 outputs the number of repetitions and gain calculated by the calculation unit 305 to the A / D conversion unit 302. The individual pixel control unit 306 outputs the exposure time and gain calculated by the calculation unit 305 to the pixel drive unit 307. The pixel drive unit 307 outputs various signals (described later) that drive each unit of the analog circuit unit 301 to the analog circuit unit 301.

[0023] Fig. 4 is a circuit diagram of the analog circuit unit 301, individual pixel control unit 306, and pixel driving unit 307. For convenience, Fig. 4 only shows a portion of the individual pixel control unit 306 and pixel driving unit 307. Portions of the individual pixel control unit 306 are given reference numerals such as 306a and 306b, and portions of the pixel driving unit 307 are given reference numerals such as 307a and 307b.

[0024] The analog circuit unit 301 has a photodiode 31, a transfer transistor Tx, a floating diffusion FD, a first reset transistor RST1, a second reset transistor RST2, an amplification transistor AMI, a selection transistor SEL, a capacitance expansion transistor FDS, and a capacitor C1.

[0025] The photodiode 31 is a photoelectric conversion unit that photoelectrically converts incident light and generates an amount of charge corresponding to the amount of incident light. The transfer transistor Tx is a transfer unit that transfers the charge generated by the photodiode 31 to the floating diffusion FD based on a transfer signal supplied from a transfer signal supply unit 307a (described later). The floating diffusion FD is a storage unit that accumulates the charge transferred by the transfer transistor Tx. The amplification transistor AMI outputs a signal corresponding to the amount of charge accumulated in the floating diffusion FD. When the selection transistor SEL is turned on, the signal output by the amplification transistor AMI is input to the A / D conversion unit 302.

[0026] The analog circuit unit 301 has two reset transistors: a first reset transistor RST1 and a second reset transistor RST2. When resetting the floating diffusion FD, the first reset transistor RST1 receives a first reset signal from a first reset signal supply unit 307b (described later). The first reset signal supply unit 307b (described later) supplies a signal of voltage VDD as the first reset signal. The first reset transistor RST1 resets the floating diffusion FD based on this first reset signal. When resetting the photodiode 31, the second reset transistor RST2 receives a second reset signal from a second reset signal supply unit 307c (described later). The second reset signal supply unit 307c (described later) supplies a signal of voltage VDD as the second reset signal. The second reset transistor RST2 resets the photodiode 31 based on this second reset signal.

[0027] The capacitance expansion transistor FDS switches the connection between the floating diffusion FD and the capacitor C1 based on a capacitance expansion signal supplied from a capacitance expansion signal supply unit 307d (described later). For example, if the amount of light incident on the photodiode 31 is large and the floating diffusion FD becomes saturated, the capacitance expansion transistor FDS is turned on to connect the floating diffusion FD and the capacitor C1. This effectively increases the capacitance of the floating diffusion FD by the amount of the capacitor C1, allowing it to accommodate a larger amount of light.

[0028] The first reset signal supply unit 307b is a CMOS circuit consisting of a pMOS transistor Tr7 and an nMOS transistor Tr8. The first reset signal supply unit 307b supplies either VDD or GND voltage as a first reset signal to the gate of the first reset transistor RST1 based on the output signal of the first reset control unit 306b. As described above, the first reset control unit 306b is part of the individual pixel control unit 306, and the first reset signal supply unit 307b is part of the pixel drive unit 307. When performing overdrive, the first reset control unit 306b can supply a voltage VRST1H, which is higher than the voltage VDD, to the gate of the first reset transistor RST1 instead of the voltage VDD.

[0029] The capacitance expansion signal supply unit 307d is a CMOS circuit consisting of a pMOS transistor Tr11 and an nMOS transistor Tr12. Based on the output signal of the capacitance expansion control unit 306d, the capacitance expansion signal supply unit 307d supplies either VDD or GND voltage as a capacitance expansion signal to the gate of the capacitance expansion transistor FDS. As described above, the capacitance expansion control unit 306d is part of the individual pixel control unit 306, and the capacitance expansion signal supply unit 307d is part of the pixel drive unit 307. When performing overdrive, the capacitance expansion signal supply unit 307d can supply a voltage VFDSH higher than the voltage VDD to the gate of the capacitance expansion transistor FDS instead of the voltage VDD.

[0030] The transfer signal supply unit 307a has an nMOS transistor Tr1, an nMOS transistor Tr2, a pMOS transistor Tr3, an nMOS transistor Tr4, an nMOS transistor Tr5, and a pMOS transistor Tr6.

[0031] The nMOS transistor Tr2 and the pMOS transistor Tr3 constitute a CMOS circuit. A voltage VTxH is applied to the source of the pMOS transistor Tr3 from a predetermined power supply. A transfer control signal is supplied to the gates of the nMOS transistor Tr2 and the pMOS transistor Tr3 by the transfer control unit 306a. The source of the nMOS transistor Tr2 is connected to the drain of the nMOS transistor Tr1. A voltage VTxL is applied to the source of the nMOS transistor Tr1 from a predetermined power supply. The voltage VTxH is a voltage higher than the ground voltage, which is the substrate voltage of the first semiconductor substrate 7 (i.e., a positive voltage), and the voltage VTxL is a voltage lower than the ground voltage, which is the substrate voltage of the first semiconductor substrate 7 (i.e., a negative voltage).

[0032] The nMOS transistor Tr5 and the pMOS transistor Tr6 constitute a CMOS circuit. A voltage VTxH is applied to the source of the pMOS transistor Tr6 from a predetermined power supply. A signal obtained by inverting the high level and low level of the transfer control signal is supplied to the gates of the nMOS transistor Tr5 and the pMOS transistor Tr6 by the transfer control unit 306a. The source of the nMOS transistor Tr5 is connected to the drain of the nMOS transistor Tr4. A voltage VTxL is applied to the source of the nMOS transistor Tr4 from a predetermined power supply.

[0033] The gate of nMOS transistor Tr4 is connected to the drains of nMOS transistor Tr2 and pMOS transistor Tr3. The gate of nMOS transistor Tr1 is connected to the drains of nMOS transistor Tr5 and pMOS transistor Tr6. The voltages from the drains of nMOS transistor Tr5 and pMOS transistor Tr6 are supplied to transfer transistor Tx as transfer signals.

[0034] That is, the pMOS transistor Tr6 functions as a first power supply unit that supplies a voltage VTxH that is higher than the substrate voltage of the first semiconductor substrate 7 to the gate of the transfer transistor Tx. Furthermore, the nMOS transistors Tr4 and Tr5 function as a second power supply unit that supplies a voltage VTxL that is lower than the substrate voltage of the first semiconductor substrate 7 to the gate of the transfer transistor Tx.

[0035] The transfer signal supply unit 307a includes not only an nMOS transistor Tr5 and a pMOS transistor Tr6 that constitute a CMOS, but also an nMOS transistor Tr1, an nMOS transistor Tr2, a pMOS transistor Tr3, and an nMOS transistor Tr4. The reason for this will be explained below. The inverted transfer control signal supplied by the transfer control unit 306a has a high level corresponding to voltage VDD and a low level corresponding to ground voltage (GND). The nMOS transistor Tr5 must be turned off when a low level signal, i.e., ground voltage, is applied to its gate. Let's consider a circuit in which nMOS transistor Tr4 is omitted and voltage VTxL is applied to the source of nMOS transistor Tr5. nMOS transistor Tr5 is turned off when the gate-source voltage VGS is lower than the gate threshold voltage Vth. When a low-level signal, i.e., ground voltage, is applied to the gate of nMOS transistor Tr5, the gate-source voltage VGS becomes greater than zero by VTxL (VGS = 0 - VTxL). For this reason, if the gate threshold voltage Vth is lower than -VTxL, the above circuit will not turn nMOS transistor Tr5 completely off even if a low-level signal is supplied to the gate of nMOS transistor Tr5, making it an unstable circuit. In the circuit used in this embodiment, even if the nMOS transistor Tr5 is not completely turned off, the nMOS transistor Tr4 cuts off the supply of the voltage VTxL to the source of the nMOS transistor Tr5, so the above-mentioned problem regarding the gate threshold voltage Vth does not occur. The nMOS transistor Tr1, the nMOS transistor Tr2, the pMOS transistor Tr3, and the nMOS transistor Tr4 may be omitted if the gate threshold voltage Vth of the nMOS transistor Tr5 can be made sufficiently large.

[0036] The transfer signal supply unit 307a configured as described above supplies either a voltage VTxH or VTxL as a transfer signal to the gate of the transfer transistor Tx based on the output signal of the transfer control unit 306a. As described above, the transfer control unit 306a is part of the individual pixel control unit 306, and the transfer signal supply unit 307a is part of the pixel drive unit 307. Note that the reason why a voltage VTxL lower than the substrate voltage of the first semiconductor substrate 7 is applied to the gate of the transfer transistor Tx is to prevent charge from being transferred from the photodiode 31 to the floating diffusion FD when the transfer transistor Tx is off.

[0037] The second reset signal supply unit 307c has nMOS transistor Tr21, nMOS transistor Tr22, pMOS transistor Tr23, nMOS transistor Tr24, nMOS transistor Tr25, and pMOS transistor Tr26. Based on the output signal of the second reset control unit 306c, the second reset signal supply unit 307c supplies either a voltage VTxH or VTxL as a second reset signal to the gate of the second reset transistor RST2. The configuration of the second reset signal supply unit 307c is similar to that of the transfer signal supply unit 307a, and therefore a description thereof will be omitted. As described above, the second reset control unit 306c is part of the individual pixel control unit 306, and the second reset signal supply unit 307c is part of the pixel drive unit 307.

[0038] FIG. 5 is a diagram schematically showing the well structures of the first semiconductor substrate 7 and the second semiconductor substrate 8. Incident light is incident on the first semiconductor substrate 7 from above on the paper. The first semiconductor substrate 7 is a P-type semiconductor substrate. The substrate voltage of the first semiconductor substrate 7 is set to a ground voltage (GND). The second semiconductor substrate 8 is a P-type semiconductor substrate. The substrate voltage of the second semiconductor substrate 8 is set to a voltage corresponding to VTxL.

[0039] 4, the analog circuit unit 301, the transfer control unit 306a, the first reset control unit 306b, and the first reset signal supply unit 307b are arranged on the first semiconductor substrate 7. Of the units shown in Fig. 4, the transfer signal supply unit 307a is arranged on the second semiconductor substrate 8. Although not shown in Fig. 5, the other units are arranged on the first semiconductor substrate 7.

[0040] Fig. 6 is a timing chart showing an imaging sequence using the image sensor 3. The image sensor 3 can selectively perform multiple exposure and correlated multiple sampling. First, multiple exposure control will be described with reference to Fig. 6(a).

[0041] FIG. 6(a) is a timing chart for performing multiple exposure for each pixel 30. The horizontal axis of FIG. 6(a) represents time, with time progressing to the right. The squares labeled "Dark" in FIG. 6(a) indicate the timing at which the A / D conversion unit 302 samples the pixel reset signal. The squares labeled "Sig" in FIG. 6(a) indicate the timing at which the A / D conversion unit 302 samples the pixel signal. The squares labeled "Out" in FIG. 6(a) indicate the timing at which the digital value (photoelectric conversion result) stored in the pixel value holding unit 304 is output to the peripheral circuit via the signal line 340. In FIG. 6(a), multiple exposure is performed by classifying the pixels 30 into four groups, pixels 30a to 30d, based on the amount of incident light.

[0042] The operation of resetting the photodiode 31 and floating diffusion FD at time t0, the start of the exposure period T1, is the same for all pixels 30. Thereafter, for pixel 30a, which receives an extremely small amount of incident light, the floating diffusion FD is reset at time t3, and the pixel reset signal is sampled. Time t3 is the time obtained by subtracting the time required for resetting the floating diffusion FD and sampling the pixel reset signal from time t4, the end of the exposure period T1. At time t4, the end of the exposure period T1, the charge generated from time t0 to t4 and accumulated in the photodiode 31 is transferred to the floating diffusion FD, and the pixel signal is sampled. Thereafter, at time t5, the photoelectric conversion result is stored in the pixel value holding unit 304.

[0043] For pixel 30b, which receives a slightly smaller amount of incident light, the externally specified exposure period T1 is divided equally into two periods, period T2 and period T3, and the above-described operation is performed twice. Specifically, at time t1 and time t3, the floating diffusion FD is reset and the pixel reset signal is sampled. Time t1 is the time obtained by subtracting the time required for resetting the floating diffusion FD and sampling the pixel reset signal from time t2, the end of period T2. Thereafter, at time t2, the charge accumulated in the photodiode 31 is transferred to the floating diffusion FD and the pixel signal is sampled. The operation from times 3 to t5 is the same as that for pixel 30a.

[0044] For pixel 30c, which receives a slightly higher amount of incident light, the externally specified exposure period T1 is divided into four equal parts, and the above-described operation is performed four times.For pixel 30d, which receives an extremely higher amount of incident light, the externally specified exposure period T1 is divided into eight equal parts, and the above-described operation is performed eight times.

[0045] As described above, multiple exposure control enables imaging by individually changing the exposure time for pixels 30 with a large amount of incident light and pixels 30 with a small amount of incident light. Even when the amount of incident light is so large that the floating diffusion FD is saturated in normal imaging, the dynamic range can be expanded by dividing the exposure time into small intervals and repeatedly imaging.

[0046] Next, correlated multiple sampling control will be described using FIG. 6(b). FIG. 6(b) is a timing chart when correlated multiple sampling control is performed for each pixel 30. The horizontal axis of FIG. 6(b) represents time, with time progressing to the right. The squares labeled "Dark" in FIG. 6(b) indicate the timing at which the A / D conversion unit 302 samples the pixel reset signal. The squares labeled "Sig" in FIG. 6(b) indicate the timing at which the A / D conversion unit 302 samples the pixel signal. The squares labeled "Out" in FIG. 6(b) indicate the timing at which the A / D conversion unit 302 outputs the sampling result to the sampling unit 303. In FIG. 6(b), correlated multiple sampling is performed by classifying the pixels 30 into four groups, pixels 30a to 30d, based on the amount of incident light.

[0047] Pixel 30a has the longest exposure time, and pixel 30d has the shortest exposure time. Under correlated multiple sampling control, the longer the exposure time of a pixel 30, the earlier the floating diffusion FD is reset. The longer the exposure time of a pixel 30, the longer the time between resetting the floating diffusion FD and sampling the pixel signal. During that period, the pixel reset signal is repeatedly sampled.

[0048] For example, in Figure 6(b), pixel 30a has the longest exposure time. The floating diffusion FD is reset at time t7, which is a period T5 before the end of exposure time T6 of pixel 30a's exposure time T4. As a result, the pixel reset signal is sampled four times by time t6. After exposure time T4 ends, the pixel signal is repeatedly sampled until the end of the next exposure time T6.

[0049] A long exposure time means that the amount of incident light is small, and the pixel signal is more susceptible to noise from the amplification transistor AMI, the selection transistor SEL, and the A / D conversion unit 302. In other words, the more susceptible a pixel 30 is to the noise mentioned above, the more times the pixel reset signal and pixel signal are sampled, enabling imaging with higher sensitivity.

[0050] The image sensor 3 performs the above operations in parallel for each pixel 30. That is, each pixel 30 performs operations in parallel, from photoelectric conversion by the photodiode 31 to storing a digital value in the pixel value holding unit 304. The image capture results are read out from the pixel value holding unit 304 sequentially for each pixel 30.

[0051] As described above, the image sensor 3 of this embodiment can control the exposure time for each pixel. To control the exposure time for each pixel, the on / off timing of the transfer transistor Tx must be controlled for each pixel. That is, the voltages supplied to the gates of the transfer transistors Tx (voltages VTxH and VTxL in this embodiment) must be controlled for each pixel. That is, a first power supply unit that supplies voltage VTxH and a second power supply unit that supplies voltage VTxL must be provided for each pixel. Because the voltages handled by the first semiconductor substrate 7 are different from voltages VTxH and VTxL, providing the first and second power supply units within the pixel 30 would occupy a large area. In particular, the first power supply unit handles voltage VTxL, which is lower than the substrate voltage, and therefore requires a triple-well structure to prevent forward bias with respect to the substrate. Therefore, the first power supply unit requires a particularly large area. As a result, the area occupied by the photodiode 31 in the pixel 30 is significantly reduced. This significantly reduces the aperture ratio of the photodiode 31, making it difficult to miniaturize the image sensor. In this embodiment, by providing the first power supply unit and the second power supply unit on the second semiconductor substrate 8, it is possible to control the exposure time for each pixel without providing the first power supply unit and the second power supply unit near the photodiode 31 on the first semiconductor substrate 7 (without reducing the aperture ratio of the photodiode 31).

[0052] According to the above-described embodiment, the following effects can be obtained. (1) The first semiconductor substrate 7 is provided with a photodiode 31 that photoelectrically converts incident light and a transfer transistor Tx that transfers the charge generated by the photodiode 31 to the floating diffusion FD based on a transfer signal. However, the transfer signal supply unit 307a that supplies the transfer signal to the gate electrode of the transfer transistor TX is not disposed on the first semiconductor substrate 7. The second semiconductor substrate 8 is provided with a transfer signal supply unit 307a that supplies either a voltage VTxL lower than the ground voltage or a voltage VTxH higher than the ground voltage as a transfer signal to the gate of the transfer transistor Tx. This ensures that the transfer transistor Tx is turned off, preventing an increase in dark current. Furthermore, because the first semiconductor substrate 7 does not include a circuit for handling a negative power supply, there is no need to provide a diffusion layer or the like for handling a negative power supply on the first semiconductor substrate 7, thereby improving the aperture ratio of the photodiode 31. The same effect can be achieved with the second reset transistor RST2.

[0053] (2) The first semiconductor substrate 7 includes a plurality of photodiodes 31, floating diffusions FD, and transfer transistors Tx. The second semiconductor substrate 8 includes a plurality of transfer signal supply units 307a. Some of the plurality of transfer signal supply units 307a transfer the charge generated by the photodiodes 31 to the floating diffusion FD during a first period. Other transfer signal supply units 307a transfer the charge generated by the photodiodes 31 to the floating diffusion FD during a second period that is different in length from the first period. This allows the exposure time to be different for each pixel 30, thereby expanding the dynamic range of the image sensor 3.

[0054] (3) The imaging sequence is set so that the end time of the first period is the same as the end time of the second period, which makes it possible to easily control imaging.

[0055] (4) The substrate voltage of the first semiconductor substrate 7 is set to the ground voltage, while the substrate voltage of the second semiconductor substrate 8 is set to a voltage corresponding to a different voltage VTxL. This allows the signal voltage fluctuation range of the transfer signal supplied to the gate of the transfer transistor Tx to be set to a voltage different from that of other drive signals without increasing the diffusion layer. A similar effect can be achieved for the second reset transistor RST2.

[0056] (5) Of the voltages VTxL and VTxH of the transfer signal, the former is a voltage based on the substrate voltage of the second semiconductor substrate 8. This makes it possible to set the fluctuation range of the signal voltage of the transfer signal supplied to the gate of the transfer transistor Tx to a voltage different from that of other drive signals without increasing the diffusion layer. A similar effect can be obtained for the second reset transistor RST2.

[0057] (6) The first reset transistor RST1 is provided on the first semiconductor substrate 7 and resets the charge accumulated in the floating diffusion FD based on a first reset signal. The first reset signal supply unit 307b is provided on a first semiconductor substrate 7 different from the second semiconductor substrate 8 and supplies either ground voltage or a voltage VDD higher than the ground voltage to the first reset transistor RST1 as the first reset signal. As a result, the signal voltage fluctuation range of the transfer signal can include negative voltages, while the signal voltage fluctuation range of the first reset signal can be a normal range that does not include negative voltages.

[0058] (7) Of the voltages of the first reset signal, the ground voltage and the voltage VDD, the former is a voltage based on the substrate voltage of the first semiconductor substrate 7. This eliminates the need to provide an additional diffusion layer for providing the first reset signal supply unit 307b.

[0059] (8) The A / D converter 302 and the sampling unit 303 perform analog-to-digital conversion of the analog signal based on the amount of charge accumulated in the floating diffusion FD by correlated multiple sampling processing, thereby improving the S / N ratio of the imaging signal.

[0060] (9) A second reset transistor RST2 is provided to reset the charge accumulated in the photodiode 31. This allows the exposure time to be varied for each pixel 30.

[0061] (10) The image sensor 3 includes a plurality of pixels 30, each having a photodiode 31, a floating diffusion FD, a transfer transistor Tx, and a transfer signal supply unit 307a. The transfer signal supply units 307a of some of the pixels 30 supply a transfer signal that causes the charge generated by the photodiode 31 to be transferred to the floating diffusion FD during a first period. The transfer signal supply units 307a of the other pixels 30 supply a transfer signal that causes the charge generated by the photodiode 31 to be transferred to the floating diffusion FD during a second period that is different in length from the first period. This allows the exposure time to be different for each pixel 30, thereby expanding the dynamic range of the image sensor 3.

[0062] 5, the second semiconductor substrate 8 has both the pMOS transistor Tr6 (first power supply unit) that supplies the voltage VTxH corresponding to the high level of the transfer signal, and the nMOS transistors Tr4 and Tr5 (second power supply unit) that supply the voltage VTxL corresponding to the low level of the transfer signal. However, only one of these may be provided on the second semiconductor substrate 8, and the other on the first semiconductor substrate 7. In this case, it is preferable to provide the nMOS transistor Tr4 and nMOS transistor Tr5 (second power supply unit), which have larger areas, on the second semiconductor substrate 8, and the pMOS transistor Tr6 (first power supply unit), which has smaller area, on the first semiconductor substrate 7.

[0063] 10 is a diagram showing an example in which a pMOS transistor Tr6 (first power supply unit) is provided on the first semiconductor substrate 7. FIG. 10 shows an example in which not only the pMOS transistor Tr6 (first power supply unit) but also the pMOS transistor Tr3 is provided on the first semiconductor substrate 7. In the configuration shown in FIG. 10, the circuit configuration and operation are the same as those of the first embodiment described above.

[0064] (Second embodiment) The imaging element 3 according to the first embodiment has a first semiconductor substrate 7 and a second semiconductor substrate 8. The imaging element 3 according to the second embodiment further has a third semiconductor substrate 9. The following describes the imaging element 3 according to the second embodiment, focusing on the differences from the imaging element 3 according to the first embodiment. Note that the same components as those in the first embodiment are denoted by the same reference numerals as those in the first embodiment, and descriptions thereof will be omitted.

[0065] 7 is a diagram schematically showing the well structures of the first semiconductor substrate 7, the second semiconductor substrate 8, and the third semiconductor substrate 9. In this embodiment, the first semiconductor substrate 7 is not provided with the first reset control unit 306b and the first reset signal supply unit 307b. Instead, the third semiconductor substrate 9 is provided with the first reset control unit 306b and the first reset signal supply unit 307b. The third semiconductor substrate 9 is a P-type semiconductor substrate whose substrate voltage is set to the ground voltage.

[0066] According to the above-described embodiment, in addition to the effects described in the first embodiment, the following effects can be obtained. (11) The image sensor 3 further includes a third semiconductor substrate 9 to which the same substrate voltage (ground voltage) as that of the first semiconductor substrate 7 is set. The first reset signal supply unit 307b is provided on the third semiconductor substrate 9. This reduces the amount of circuitry occupying the first semiconductor substrate 7 compared to the first embodiment, allowing the aperture of the photodiode 31 to be made larger. In other words, the light utilization efficiency of the photodiode 31 is further improved.

[0067] 7, the second semiconductor substrate 8 has both the nMOS transistor Tr6 (first power supply unit) that supplies the voltage VTxH corresponding to the high level of the transfer signal, and the pMOS transistors Tr4 and Tr5 (second power supply unit) that supply the voltage VTxL corresponding to the low level of the transfer signal. However, only one of these may be provided on the second semiconductor substrate 8, and the other on the first semiconductor substrate 7. In this case, it is preferable to provide the pMOS transistor Tr4 and pMOS transistor Tr5 (second power supply unit) that have larger areas on the second semiconductor substrate 8, and the nMOS transistor Tr6 (first power supply unit) that has smaller areas on the first semiconductor substrate 7.

[0068] 7, the pMOS transistor Tr1, pMOS transistor Tr2, nMOS transistor Tr3, pMOS transistor Tr4, pMOS transistor Tr5, and nMOS transistor Tr6 included in the transfer signal supply unit 307a are all provided on the second semiconductor substrate 8. However, some of these transistors may be provided on the first semiconductor substrate 7 or the third semiconductor substrate 9.

[0069] (Third embodiment) In the image sensor 3 according to the first embodiment, the second semiconductor substrate 8 is configured as a P-type semiconductor substrate. In the image sensor 3 according to the third embodiment, the second semiconductor substrate 8 is configured as an N-type semiconductor substrate. The image sensor 3 according to the third embodiment will be described below, focusing on the differences from the image sensor 3 according to the first embodiment. Note that the same parts as in the first embodiment are assigned the same reference numerals as in the first embodiment, and description thereof will be omitted.

[0070] FIG. 8 is a diagram schematically illustrating the well structures of the first semiconductor substrate 7 and the second semiconductor substrate 8. The second semiconductor substrate 8 is an N-type semiconductor substrate, and the substrate voltage is set to a voltage corresponding to the voltage VDD. In this embodiment, the first semiconductor substrate 7 is not provided with the transfer control unit 306a, the first reset control unit 306b, the transfer signal supply unit 307a, and the first reset signal supply unit 307b. Instead, the second semiconductor substrate 8 is provided with the transfer control unit 306a, the first reset control unit 306b, the transfer signal supply unit 307a, and the first reset signal supply unit 307b. Although not shown in FIG. 8, it is desirable to also arrange the remaining parts of the individual pixel control unit 306 and the pixel driving unit 307 on the second semiconductor substrate 8.

[0071] The transfer control unit 306a, first reset control unit 306b, transfer signal supply unit 307a, and first reset signal supply unit 307b have the same configurations as those in the first embodiment, but the polarity of the diffusion layers is different from that in the first embodiment. This is because the second semiconductor substrate 8 is an N-type semiconductor substrate. Therefore, the nMOS transistors in the first embodiment that make up each unit have been replaced with pMOS transistors, and the pMOS transistors in the first embodiment have been replaced with nMOS transistors.

[0072] The transfer signal supply unit 307a of this embodiment supplies either the voltage VDD or the voltage VTxL as a transfer signal to the gate of the transfer transistor Tx based on the output signal of the transfer control unit 306a. Since the substrate voltage of the second semiconductor substrate 8 corresponds to the voltage VDD, by using the voltage VDD instead of the voltage VTxH, it is possible to avoid an increase in the circuit size (such as adding an additional diffusion layer).

[0073] According to the above-described embodiment, in addition to the effects described in the first embodiment, the following effects can be obtained. (12) The second semiconductor substrate 8 is configured as an N-type semiconductor substrate, and the individual pixel control unit 306 and the pixel driving unit 307 are provided on the second semiconductor substrate 8. This configuration reduces the amount of circuitry occupying the first semiconductor substrate 7 compared to the first and second embodiments, allowing the aperture of the photodiode 31 to be larger. In other words, the light utilization efficiency of the photodiode 31 is further improved. Furthermore, unlike the second embodiment, there is no need to add an additional semiconductor substrate, which reduces material costs and prevents the thickness of the image sensor 3 from increasing.

[0074] 8, the second semiconductor substrate 8 has both the nMOS transistor Tr6 (first power supply unit) that supplies the voltage VTxH corresponding to the high level of the transfer signal, and the pMOS transistors Tr4 and Tr5 (second power supply unit) that supply the voltage VTxL corresponding to the low level of the transfer signal. However, only one of these may be provided on the second semiconductor substrate 8, and the other on the first semiconductor substrate 7. In this case, it is preferable to provide the pMOS transistor Tr4 and pMOS transistor Tr5 (second power supply unit) that have large areas on the second semiconductor substrate 8, and the nMOS transistor Tr6 (first power supply unit) that has a small area on the first semiconductor substrate 7.

[0075] (Fourth embodiment) As with the image sensor 3 according to the third embodiment, the image sensor 3 according to the fourth embodiment has an individual pixel control unit 306 and a pixel driving unit 307 provided on a second semiconductor substrate 8. However, it differs from the third embodiment in that the second semiconductor substrate 8 is configured as a P-type semiconductor substrate. The following description of the image sensor 3 according to the third embodiment will focus on the differences from the image sensor 3 according to the first embodiment. Note that the same components as those in the first embodiment are denoted by the same reference numerals as those in the first embodiment, and description thereof will be omitted.

[0076] 9 is a diagram schematically showing the well structures of the first semiconductor substrate 7 and the second semiconductor substrate 8. The second semiconductor substrate 8 is a P-type semiconductor substrate like the first semiconductor substrate 7, and the substrate voltage is set to the ground voltage like the first semiconductor substrate 7.

[0077] In order to provide the transfer signal supply unit 307a that handles the voltages VTxH and VTxL on the second semiconductor substrate 8, in this embodiment, N-type diffusion layers 81 and 82 are provided on the second semiconductor substrate 8. As in the third embodiment, the transfer signal supply unit 307a is arranged in the diffusion layers 81 and 82, in which the nMOS transistors in the first embodiment are replaced with pMOS transistors, and the pMOS transistors in the first embodiment are replaced with nMOS transistors. Since the N-type diffusion layers 81 and 82 electrically isolate the transfer signal supply unit 307a from the P-type substrate, the transfer signal supply unit 307a can handle the voltages VTxH and VTxL.

[0078] According to the above-described embodiment, the following effects can be obtained. (13) The photodiode 31 photoelectrically converts incident light. The transfer transistor Tx transfers the charge photoelectrically converted by the photodiode 31 to the floating diffusion FD based on a transfer signal. The transfer signal supply unit 307a supplies the transfer signal to the gate of the transfer transistor Tx. The first reset transistor RST1 resets the charge accumulated in the floating diffusion FD based on a first reset signal. The first reset signal supply unit 307b supplies a reset signal to the first reset transistor RST1. The photodiode 31 and the transfer transistor Tx are provided on a first semiconductor substrate 7. The second semiconductor substrate 8 is provided with a first reset signal supply unit 307b arranged in an N-type diffusion layer and a transfer signal supply unit 307a arranged in a P-type diffusion layer. This configuration reduces the amount of circuitry occupying the first semiconductor substrate 7 compared to the first and second embodiments, and allows the aperture of the photodiode 31 to be larger, as in the third embodiment. That is, the light utilization efficiency of the photodiode 31 is further improved. Furthermore, unlike the second embodiment, there is no need to add an additional semiconductor substrate, which reduces material costs and prevents the thickness of the imaging element 3 from increasing.

[0079] 9, the second semiconductor substrate 8 has both the nMOS transistor Tr6 (first power supply unit) that supplies the voltage VTxH corresponding to the high level of the transfer signal, and the pMOS transistors Tr4 and Tr5 (second power supply unit) that supply the voltage VTxL corresponding to the low level of the transfer signal. However, only one of these may be provided on the second semiconductor substrate 8, and the other on the first semiconductor substrate 7. In this case, it is preferable to provide the pMOS transistor Tr4 and pMOS transistor Tr5 (second power supply unit) that have large areas on the second semiconductor substrate 8, and the nMOS transistor Tr6 (first power supply unit) that has a small area on the first semiconductor substrate 7.

[0080] 11 is a diagram showing an example in which pMOS transistor Tr4 and pMOS transistor Tr5 (second power supply unit) are provided on the first semiconductor substrate 7. FIG. 11 shows an example in which not only pMOS transistor Tr4 and pMOS transistor Tr5 (second power supply unit), but also pMOS transistor Tr1 and pMOS transistor Tr2 are provided on the first semiconductor substrate 7. In the configuration shown in FIG. 11, the circuit configuration and operation are the same as those of the fourth embodiment described above.

[0081] The following modifications are also within the scope of the present invention, and one or more of the modifications may be combined with the above-described embodiment. (Variation 1) Circuits different from those described in the above-described embodiments may be provided on the second semiconductor substrate 8 or the third semiconductor substrate 9. For example, by providing the circuits mounted on the first semiconductor substrate 7 in the above-described embodiments on the second semiconductor substrate 8 or the third semiconductor substrate 9, a larger space can be secured for the photodiode 31, enabling light to be captured more efficiently.

[0082] Although various embodiments and modifications have been described above, the present invention is not limited to these. Other embodiments that are conceivable within the scope of the technical idea of ​​the present invention are also included within the scope of the present invention. The above-described embodiment and modifications also include the following imaging apparatus and electronic camera. (1) An imaging element comprising: a first semiconductor substrate on which a plurality of pixels are provided, each pixel having a photoelectric conversion unit that photoelectrically converts incident light; a storage unit to which the charge photoelectrically converted by the photoelectric conversion unit is transferred and stored; and a transfer unit that transfers the charge generated by the photoelectric conversion unit to the storage unit; and a second semiconductor substrate on which a supply unit is provided for each pixel that supplies a transfer signal to the transfer unit for transferring the charge from the photoelectric conversion unit to the storage unit. (2) In the imaging element as described in (1), the first substrate voltage applied to the first semiconductor substrate is different from the second substrate voltage applied to the second semiconductor substrate. (3) In the imaging device as described in (2), the supply section includes a first power supply section and a second power supply section, and at least one of the first power supply section and the second power supply section is provided on the second semiconductor substrate. (4) In an imaging element such as (3), the first power supply unit supplies a first voltage higher than the first substrate voltage, and the second power supply unit supplies a second voltage lower than the first substrate voltage. (5) In an imaging element such as (4), the transfer unit electrically connects the photoelectric conversion unit and the storage unit to transfer the charges generated by the photoelectric conversion unit to the storage unit, and the supply unit supplies the transfer signal to the transfer unit to electrically connect or disconnect the photoelectric conversion unit and the storage unit. (6) In an imaging element such as (5), when the first voltage is supplied as the transfer signal, the transfer unit electrically connects the photoelectric conversion unit and the storage unit, and when the second voltage is supplied as the transfer signal, the transfer unit electrically disconnects the photoelectric conversion unit and the storage unit. (7) In an imaging element such as those described in (4) to (6), some of the supply units transfer the charges generated by the photoelectric conversion unit to the storage unit during a first period, and other supply units transfer the charges generated by the photoelectric conversion unit to the storage unit during a second period that is different in length from the first period. In the imaging device as in (8) and (7), the end time of the first period is the same as the end time of the second period. (9) In the imaging device as described in (4) to (8), one of the first voltage and the second voltage is the second substrate voltage. (10) In an imaging element such as (4) or (5), the imaging element further comprises a first reset unit provided on the first semiconductor substrate, which resets the charge stored in the storage unit based on a reset signal, and a reset signal supply unit provided on a semiconductor substrate different from the second semiconductor substrate, which supplies either a third voltage equal to or higher than the first substrate or a fourth voltage higher than the third voltage to the first reset unit as the reset signal. (11) In the imaging device as in (10), one of the third voltage and the fourth voltage is the first substrate voltage. (12) The imaging device as in (10) further comprises a third semiconductor substrate to which the first substrate voltage is applied, and the reset signal supply unit is provided on the third semiconductor substrate. (13) In an imaging element such as those described in (1) to (6), the supply unit possessed by some of the pixels supplies the transfer signal that causes the charges generated by the photoelectric conversion unit to be transferred to the storage unit during a first period, and the supply unit possessed by some other of the pixels supplies the transfer signal that causes the charges generated by the photoelectric conversion unit to be transferred to the storage unit during a second period that is different in length from the first period. (14) An imaging element comprising: a photoelectric conversion unit that photoelectrically converts incident light; a transfer unit that transfers charges photoelectrically converted by the photoelectric conversion unit to an accumulation unit based on a transfer signal; a transfer signal supply unit that supplies the transfer signal to the transfer unit; a first reset unit that resets the charges accumulated in the accumulation unit based on a reset signal; a reset signal supply unit that supplies the reset signal to the first reset unit; a first semiconductor substrate on which the photoelectric conversion unit, the transfer unit, and the first reset unit are provided; and a second semiconductor substrate on which the reset signal supply unit arranged in a first diffusion layer and the transfer signal supply unit arranged in a second diffusion layer having a polarity different from that of the first diffusion layer are provided. (15) The imaging device as described in (1) to (14) further comprises an A / D converter that performs analog-to-digital conversion of an analog signal based on the amount of charge stored in the storage unit by correlated multiple sampling processing. (16) The imaging device according to any one of (1) to (15) further comprises a second reset unit that resets the charges accumulated in the photoelectric conversion unit. (17) In the imaging device as described in (1) to (16), the photoelectric conversion section is a buried photodiode. (18) An electronic camera having an image sensor such as those described in (1) to (16).

[0083] The above-described embodiment and modifications also include the following imaging element. (1) An imaging element comprising: a first semiconductor substrate provided with a photoelectric conversion unit that photoelectrically converts incident light and a transfer unit that transfers charges generated by the photoelectric conversion unit to an accumulation unit based on a transfer signal; and a second semiconductor substrate provided with a transfer signal supply unit that supplies either a first voltage lower than ground voltage or a second voltage higher than ground voltage to the transfer unit as the transfer signal. (2) In an imaging element such as (1), the first semiconductor substrate includes a plurality of the photoelectric conversion units, the storage units, and the transfer units, and the second semiconductor substrate includes a plurality of the transfer signal supply units, some of which transfer the charges generated by the photoelectric conversion units during a first period to the storage units, and other of which transfer the charges generated by the photoelectric conversion units during a second period that is different in length from the first period to the storage units. (3) In the imaging device as in (2), the end time of the first period is the same as the end time of the second period. (4) In the imaging device as described in (1) to (3), the first substrate potential set in the first semiconductor substrate is different from the second substrate potential set in the second semiconductor substrate. (5) In the imaging device as described in (4), one of the first voltage and the second voltage is a voltage based on the second substrate potential. (6) In an imaging element such as (4) or (5), the imaging element further comprises: a first reset unit provided on the first semiconductor substrate, which resets the charge stored in the storage unit based on a reset signal; and a reset signal supply unit provided on a semiconductor substrate different from the second semiconductor substrate, which supplies either a third voltage equal to or higher than the ground voltage or a fourth voltage higher than the third voltage to the first reset unit as the reset signal. (7) In the imaging device as described in (6), one of the third voltage and the fourth voltage is a voltage based on the first substrate potential. (8) The imaging device as described in (6) further comprises a third semiconductor substrate to which the first substrate potential is set, and the reset signal supply unit is provided on the third semiconductor substrate. (9) In an imaging element such as (1), the imaging element includes a plurality of pixels each having the photoelectric conversion unit, the storage unit, the transfer unit, and the transfer signal supply unit, and the transfer signal supply unit of some of the pixels supplies the transfer signal that causes the charge generated by the photoelectric conversion unit to be transferred to the storage unit during a first period, and the transfer signal supply unit of another portion of the pixels supplies the transfer signal that causes the charge generated by the photoelectric conversion unit to be transferred to the storage unit during a second period that is different in length from the first period. (10) An imaging element comprising: a photoelectric conversion unit that photoelectrically converts incident light; a transfer unit that transfers charges photoelectrically converted by the photoelectric conversion unit to an accumulation unit based on a transfer signal; a transfer signal supply unit that supplies the transfer signal to the transfer unit; a first reset unit that resets the charges accumulated in the accumulation unit based on a reset signal; a reset signal supply unit that supplies the reset signal to the first reset unit; a first semiconductor substrate on which the photoelectric conversion unit, the transfer unit, and the first reset unit are provided; and a second semiconductor substrate on which the reset signal supply unit arranged in a first diffusion layer and the transfer signal supply unit arranged in a second diffusion layer having a polarity different from that of the first diffusion layer are provided. (11) The imaging device as described in (1) to (10) further comprises an A / D conversion unit that performs analog-to-digital conversion of an analog signal based on the amount of charge stored in the storage unit by correlated multiple sampling processing. (12) The imaging device according to any one of (1) to (11) further comprises a second reset unit that resets the charge accumulated in the photoelectric conversion unit. (13) In the imaging device as described in (1) to (12), the photoelectric conversion section is a buried photodiode.

[0084] The disclosures of the following priority applications are incorporated herein by reference: Japanese Patent Application No. 2015-195280 (filed September 30, 2015) [Explanation of symbols]

[0085] 3...imaging element, 7...first semiconductor substrate, 8...second semiconductor substrate, 30...pixel, 31...photodiode, 301...analog circuit section, 302...A / D conversion section, 303...sampling section, 306...individual pixel control section, 307...pixel driving section

Claims

[Claim 1] a first semiconductor substrate having a first photoelectric conversion unit that converts light into electric charges, a second photoelectric conversion unit that converts light into electric charges and is arranged alongside the first photoelectric conversion unit in the row direction, a first transfer unit that transfers the electric charges converted by the first photoelectric conversion unit, and a second transfer unit that transfers the electric charges converted by the second photoelectric conversion unit; a second semiconductor substrate stacked on the first semiconductor substrate, the second semiconductor substrate having a first transfer signal supply unit that supplies a transfer signal for controlling the first transfer unit to the first transfer unit, and a second transfer signal supply unit that supplies a transfer signal for controlling the second transfer unit to the second transfer unit; An imaging element comprising:

Images