Modular multilevel cascaded converter and method of controlling the same

Abstract

To equally balance a primary side DC voltage and a voltage of a DC system even when a difference occurs in a load of the DC system.SOLUTION: M (m: an integer of 2 or more) cells each including an AC-DC converter ACDC, a primary-side DC capacitor C1, an insulated DC-DC converter DCDC, and a secondary-side DC capacitor C2 are provided per phase. X (x: an integer of 2 or more) DC systems in which a plurality of secondary side DC capacitors C2 are connected in parallel are provided, and voltages of the plurality of DC systems are supplied to a load or a power source. The control unit of the AC / DC converter ACDC adjusts the output voltage on the AC system side of the cell based on a value obtained by dividing the power detection value of each DC system by the power average value of the DC system.SELECTED DRAWING: Figure 1

Description

[Technical Field]

[0001] The present invention relates to a modular multilevel cascade converter (MMCC) of single star bridge cells (SSBC) connected to a three-phase AC system, in which a bidirectional isolated DC / DC converter (isolated DC / DC converter) or the like is connected to the DC side of the full bridge cells (AC / DC converter) that make up the converter, enabling multiple DC systems to be output. [Background technology]

[0002] A prime example of this configuration is the solid-state transformer (SST). Figure 1 shows an SST consisting of m = 4 cells per phase, which combines an MMCC-SSBC configured by cascading AC-DC converters ACDC and an isolated DC-DC converter DCDC using the dual active bridge (DAB) method. A cell consists of an AC-DC converter ACDC, an isolated DC-DC converter DCDC, and capacitors C1 and C2.

[0003] High-voltage AC power is converted into DC power using series-connected cells, and the DC power is converted into high-frequency AC power, which is then insulated and rectified using a transformer to convert back into DC power. Reverse power interchange is also possible. Because SST uses a high-frequency transformer, it can be made smaller than conventional commercial frequency transformers.

[0004] Isolated DC / DC converter DCDC: By connecting the output terminals of 3m / x = 6 units in parallel, it is possible to output x = 2 isolated DC systems with the same capacity. By connecting multiple DC systems in series, it is also possible to obtain a high DC voltage.

[0005] In cases where high reliability is required, such as when important loads are connected to the DC grid, it is necessary to realize a fault tolerance function that allows operation to continue even if some of the cells that make up the SST fail.

[0006] If a fault occurs inside a cell, such as an open or short circuit due to a broken conductor, or an open or short circuit in a switching device, the fault is detected by detecting that the voltage (primary DC voltage) of the DC capacitor connected to the AC system side of the high-frequency transformer is outside of a specified range, by detecting an overcurrent in the high-frequency transformer current, or by using the short-circuit detection function built into the gate driver for the switching device.After detection, the output terminal on the three-phase AC system side is short-circuited using the remaining healthy switching device or a separately provided mechanical switch, and the output terminal on the DC system side is opened, thereby preventing the effects of the fault from spreading to other cells.

[0007] However, problems then arise with the primary DC voltage of the remaining cells and the voltage of the DC system they output. If the voltage increases abnormally, it can cause problems such as the breakdown of components inside other cells, making it impossible to continue operating, or damaging other devices connected to the DC system. If the voltage in the DC system drops, there is also the risk that other devices will not be able to operate normally.

[0008] Patent Document 5 discloses a control method for maintaining uniformity in the cell primary side DC voltage and the voltage of the output DC system in the SST shown in FIG.

[0009] Patent documents 1, 2, and 3 disclose a method in which, when a cell constituting a converter fails, a switch connected to one of the input / output terminals of the cell is turned on to short-circuit the terminals, thereby preventing the effects of the failure from spreading to other cells and allowing operation to continue.

[0010] Furthermore, Patent Document 1 assumes that either AC or DC power is input and DC power is output, and is configured with the cells on the output side connected in series (the input side can be either parallel or series).If some of the cells fail, the DC capacitor voltage on the output side of the series-connected cells can be increased to obtain an output voltage from the converter with the same amplitude as before the failure.

[0011] Patent Document 2 describes a technology that applies to a configuration in which both the input and output terminals of cells are connected in series, assuming the mutual conversion of two types of AC power. If one of the cells fails, the switch on the failed side of the input and output terminals of the cell is short-circuited, and the other terminal is controlled to maintain the DC capacitor voltage of the cell constant, thereby enabling the converter to obtain an output voltage with the same amplitude as before the failure.

[0012] Furthermore, in Patent Document 2, the waveform before the failure is shown in Figure 5, and the waveform after the failure is shown in Figure 6. The pulse width of the AC output voltages (Vo2 to Vo4) of the non-failed cells increases. In other words, the AC output voltage of the converter is made equal before and after the failure by operating with the highest priority on increasing amplitude even if the distortion of the AC output voltage of the non-failed cells worsens, and by removing the distortion of the failed cell.

[0013] Patent Document 3 describes a technology that assumes the mutual conversion of two DC power sources, and applies it to a configuration in which one cell is connected in parallel and the other in series within the unit that makes up the converter. If one of the cells fails, the voltage of the DC capacitor on the parallel-connected side of the cells is not changed, but the voltage of the DC capacitor on the series-connected side is increased. With Patent Document 3, the voltage of the DC system on the series-connected side does not change before and after the failure. Furthermore, the input and output power are equal, allowing for continued stable operation.

[0014] Patent Documents 6 and 7 disclose techniques for superimposing a zero-phase sequence voltage of the fundamental wave so that the amplitude of the AC voltage output by the SST can be maintained even when some cells fail.

[0015] In Non-Patent Document 1, Sections 3 and 4 introduce an SST that connects two DC systems in series to output high-voltage DC power. By adjusting the secondary DC voltage according to the number of cells connected to each DC system, equalization of the power load of each cell is achieved.

[0016] Patent Document 4 discloses the configuration of an SST in which two DC buses are connected in series using an inter-bus connection switch, thereby enabling similar output of high-voltage DC power. [Prior art documents] [Patent documents]

[0017] [Patent Document 1] Patent No. 6476318 [Patent Document 2] Patent No. 6725758 [Patent Document 3] Patent No. 6976426 [Patent Document 4] Japanese Patent Publication No. 2022-185478 [Patent Document 5] Patent application No. 2023-191251 [Patent Document 6] Patent application No. 2023-215645 [Patent Document 7] Patent application No. 2023-215646 [Non-patent literature]

[0018] [Non-Patent Document 1] Akihiko Kanada, Kimihisa Furukawa, Choudhury Abhijit, Yuichi Mabuchi, "Load Balancing of Cell Converters in Multi-Output EV Chargers Using SST," 2021 IEEJ Industrial Applications Conference, 1-21 Summary of the Invention [Problem to be solved by the invention]

[0019] The control method of Patent Document 5 may not be able to maintain the cell primary side DC voltage or the output voltage of the DC system uniformly. The reason for this will be explained below. The control method of Patent Document 5 is configured by the following feedback control.

[0020] (1) Primary side DC voltage average value control If the average value of the primary side DC voltage is lower than the command value, active power is input from the AC grid; if it is higher, the AC output current of the MMCC-SSBC is adjusted so that active power is output to the AC grid.

[0021] (2) Primary side DC voltage phase balance control The primary DC voltage of a cell connected to a phase of the AC system is compared with the average primary DC voltage of all cells connected to the same phase, and the AC output voltage of the AC / DC converter for that cell is adjusted. If the primary DC voltage of a cell is high and power is flowing in from the AC system, the AC voltage is reduced to suppress charging. If the power is flowing in the opposite direction to the AC system, the AC voltage is increased to encourage discharge.

[0022] (3) Individual balance control of primary side DC voltage The current of the isolated DC / DC converter is controlled so that the primary DC voltage of all cells connected to a DC system is equal. Cells with a high primary DC voltage increase the power transferred from the AC system to the DC system via the isolated DC / DC converter, while cells with a low primary DC voltage reduce the power transferred from the AC system to the DC system via the isolated DC / DC converter.

[0023] (4) Secondary DC voltage individual control The power transfer from the isolated DC / DC converters (DCDC) of all cells connected to the corresponding DC system is adjusted so that the voltage of the DC capacitor inside the cell that is closer to the DC system than the high-frequency transformer, i.e., the voltage of the DC system (secondary DC voltage), is equal to the command value.

[0024] Figure 2 shows a modular multilevel cascade converter (SST) when the load on the upper DC system 21 is twice that of the lower DC system 22. When the control method of Patent Document 5 is applied to this SST, first, the upper secondary DC voltage V DC21decreases, (4) individual control of secondary DC voltage operates, and the interchange power of the upper six cells connected to the DC grid 21 doubles. This power is supplied from a DC capacitor (primary-side DC capacitor) connected to the AC grid side rather than the high-frequency transformer inside the cell, so the primary DC voltage of the upper six cells drops. Then, (2) primary DC voltage intra-phase balance control begins to operate. The upper six cells need to receive twice as much power from the AC grid as the lower six cells. Because the AC current is common, the upper six cells increase the AC voltage of their AC-DC converters ACDC, and the lower six cells decrease the AC voltage of their AC-DC converters ACDC, doubling the difference and thereby balancing the secondary DC voltage and primary DC voltage.

[0025] The problem here is that the control method described in Patent Document 5 uses a feedback system, which means that the AC voltage of the AC / DC converter ACDC increases after the primary-side DC voltage drops, and it takes time for the AC voltage to increase. Because the maximum amplitude of the AC voltage that the cell's AC / DC converter ACDC can output is equal to the primary-side DC voltage, if the primary-side DC voltage drops too much, the cell's AC / DC converter ACDC will no longer be able to output the AC voltage with the amplitude required to maintain balance. In this case, the primary-side DC voltage of the six upper cells will continue to drop, making it impossible to receive power from the AC grid. As a result, the voltage of the upper DC grid 21 will also continue to drop, resulting in a loss of voltage balance.

[0026] When a regenerative load is connected to the DC system and power flows in the reverse direction, an increase in the regenerative power of the upper DC system 21 causes the primary DC voltage of the upper six cells to increase before the AC voltage of the AC-DC converter ACDC is increased. In this case, there is no limit to the amplitude of the AC voltage of the AC-DC converter ACDC. However, if the increase in the AC voltage of the AC-DC converter ACDC is delayed, the primary DC voltage of the cells will increase significantly, albeit temporarily. This can cause insulation breakdown in components inside the cells or damage to the switching devices due to excessive switching surges.

[0027] Figure 3 shows a case where one cell in the top row fails and shorts out the AC output terminal. In this case, the same problem occurs even if the control method described in Patent Document 5 is applied. The remaining five upper cells, V11 to W12, need to accommodate 1.2 times the power compared to the six lower cells, U21 to W22, and the AC voltage that the AC-DC converter ACDC should output also becomes 1.2 times higher. However, if the primary-side DC voltage drops too quickly, the voltage balance will be disrupted.

[0028] Possible countermeasures include setting the primary side DC voltage rating high enough so that the required AC voltage can be output even when the voltage drops, increasing the capacitor capacity to delay the voltage drop, or increasing the number of cells. However, these countermeasures not only affect cost and size, but also require changing to components with higher voltage resistance, which increases switching losses in the switching devices. Increasing the number of cells increases conduction losses in addition to cost and size.

[0029] In the primary DC voltage phase balance control in (2), it is possible to increase the gain to shorten the time from when the primary DC voltage drops until the cell AC voltage increases. However, increasing the gain also increases the risk of control instability.

[0030] In Patent Documents 1 and 3, if some cells fail, the primary DC voltage and secondary DC voltage of the cells are increased. This method also requires a cell voltage resistance design that takes into account the increase in DC capacitor voltage, and if a failure occurs, switching loss increases.

[0031] To apply the technology of Patent Document 2, it is necessary to keep the primary DC voltage of the cell constant using the full-bridge inverter of the failed cell. Therefore, if a failure occurs in the full-bridge inverter, the technology of Patent Document 2 cannot be applied.

[0032] Furthermore, in Patent Document 2, the AC output voltage of all cells that do not fail is increased (the pulse width is increased). Considering the case of Figure 3, in order to maintain equal power in DC system 21 and DC system 22, the AC output voltage of cells V11 to W12 should be increased, but the AC output voltage of cells U21 to W22 must not be increased. In this respect, too, the technology of Patent Document 2 cannot be applied as is.

[0033] Patent Documents 6 and 7 assume that all cells are connected in parallel on the DC system side, and do not mention maintaining voltage balance when connected in series.

[0034] Although Non-Patent Document 1 does not mention what to do if a cell fails, it is believed that adjusting the secondary DC voltage based on the number of cells connected to each DC system minus the number of failed cells would make it possible to equalize the power load of each cell. However, the secondary DC voltage, i.e., the voltage of each DC system, fluctuates depending on the number of failed cells and cannot be kept constant. This results in the same problems as Patent Documents 1 and 3. Furthermore, it is not possible to connect loads that do not anticipate voltage fluctuations.

[0035] In paragraph

[0032] of Patent Document 4, a method is shown for suppressing the difference in DC voltage by switching the cell connections so that the ratio of the power responsibilities of each DC system and the ratio of the cells connected to each DC system are roughly equal. However, realizing this method requires many changeover switches, which increases costs.

[0036] As shown above, even if there is a difference in the load on the DC system, the challenge is to balance the primary DC voltage and the voltage of the DC system evenly. [Means for solving the problem]

[0037] The present invention has been devised in view of the above-mentioned problems of the related art, and one aspect of the present invention is a modular multilevel cascade converter having m (m: an integer of 2 or more) cells per phase, each cell including an AC-DC converter connected to an AC system, a primary-side DC capacitor connected to the DC side of the AC-DC converter, an isolated DC-DC converter having one DC side connected to the primary-side DC capacitor, and a secondary-side DC capacitor connected to the other DC side of the isolated DC-DC converter, and having x (x: an integer of 2 or more) DC systems in which a plurality of the secondary-side DC capacitors are connected in parallel, and supplying voltages of a plurality of the DC systems to a load or a power source, wherein a control unit of the AC-DC converter adjusts an output voltage of the cell on the AC system side based on a value obtained by dividing a power detection value of each of the DC systems by an average power value of the DC systems.

[0038] In one aspect, the control unit of the AC-DC converter includes: a fourth multiplier that multiplies each phase voltage command value of the AC-DC converter by a value obtained by dividing the power detection value of the DC system by the average power value of the DC system; a primary DC voltage intra-phase balance control unit that outputs a primary DC voltage intra-phase balance control value based on the primary DC voltage intra-phase average value of each phase and the primary DC voltage of each cell; and a first subtractor that subtracts the primary DC voltage intra-phase balance control value from the output of the fourth multiplier to output each cell voltage command value, and generates a gate signal for the AC-DC converter based on each cell voltage command value.

[0039] In one embodiment, when one of the cells fails, the control unit of the AC-DC converter increases the output voltage on the AC system side of the cells connected to the same DC system as the failed cell, and decreases the output voltage on the AC system side of the cells connected to the other DC systems.

[0040] In one aspect, the control unit of the AC-DC converter includes a fifth multiplier that multiplies, when one of the cells fails, a value obtained by dividing the power detection value of the DC system by the average power value of the DC system, by 3m / (3m-x+1) for a cell connected to the same DC system as the failed cell, by (3m-x) / (3m-x-1) for a cell connected to a DC system different from the failed cell, and by 1 if there is no failed cell; The inverter circuit includes a fourth multiplier that multiplies each phase voltage command value by the output of the fifth multiplier, a primary DC voltage intra-phase balance control unit that outputs a primary DC voltage intra-phase balance control value based on the primary DC voltage intra-phase average value of each phase and the primary DC voltage of each cell, and a first subtractor that subtracts the primary DC voltage intra-phase balance control value from the output of the fourth multiplier to output each cell voltage command value, and generates a gate signal for the AC-DC converter based on each cell voltage command value.

[0041] In one aspect, the control unit of the AC-DC converter includes a dq inverse converter that converts a voltage command value on a rotating coordinate system into a voltage command value on a fixed coordinate system; a switch for each phase that outputs (3m-x+1) / (3m-x-2) as a coefficient for the phase to which the faulty cell is connected and 1 as a coefficient for the other phases; a sixth multiplier that multiplies the AC voltage of each phase by the output of the switch for each phase; a calculator that outputs a zero-phase voltage based on the output of the sixth multiplier and the coefficient; a third adder that adds the zero-phase voltage to the voltage command value on the fixed coordinate system; and a first multiplier that multiplies the output of the third adder by the reciprocal of the average value of the primary side DC voltages of all cells and outputs the result as the voltage command value for each phase. [Effects of the Invention]

[0042] According to the present invention, even when a difference occurs in the load of the DC system, it is possible to evenly balance the primary side DC voltage and the voltage of the DC system. [Brief explanation of the drawings]

[0043] [Figure 1]FIG. 2 is a diagram showing an example of a main circuit configuration of the modular multilevel cascade converter of the first embodiment. [Figure 2] This figure shows the main circuit configuration when two DC systems are connected in series and the load on the upper DC system is twice that of the lower DC system. [Figure 3] A diagram showing the main circuit configuration when a failure occurs in cell U11, causing the AC side to be short-circuited and the DC side to be open. [Figure 4] FIG. 2 is a block diagram showing a control unit of the AC-DC converter according to the first embodiment. [Figure 5] 2 is a phasor diagram showing the AC voltage of the AC-DC converter in FIG. 1; [Figure 6] 3 is a phasor diagram showing the AC voltage of the AC-DC converter when the first embodiment is applied in FIG. 2. [Figure 7] FIG. 10 is a block diagram showing a control unit of the AC-DC converter according to the second embodiment. [Figure 8] FIG. 4 is a phasor diagram showing the AC voltage of the AC-DC converter when the second embodiment is applied in FIG. 3. [Figure 9] FIG. 10 is a block diagram showing a voltage command value calculation unit according to a third embodiment. [Figure 10] FIG. 4 is a phasor diagram showing the AC voltage of the AC-DC converter when the third embodiment is applied in FIG. 3. DETAILED DESCRIPTION OF THE INVENTION

[0044] Hereinafter, first to third embodiments of the modular multilevel cascade converter of the present invention will be described in detail with reference to FIGS.

[0045] [Embodiment 1] Here, m (m: an integer of 2 or more) is the number of cells per phase, and x (x: an integer of 2 or more) is the number of DC systems to output. In Figure 1, m=4 and x=2.

[0046] Figure 1 shows the main circuit configuration of a modular multilevel cascade converter (SST) that generates multiple DC systems. As shown in Figure 1, the SST includes an AC-DC converter (ACDC) connected to a high-voltage AC system via reactors Lu, Lv, and Lw; a primary-side DC capacitor C1 connected to the DC side of the AC-DC converter (ACDC); an isolated DC-DC converter (DCDC) with one DC side connected to the primary-side DC capacitor C1; and a secondary-side DC capacitor C2 connected to the other DC side of the isolated DC-DC converter (DCDC). The AC-DC converter (ACDC) and the isolated DC-DC converter (DCDC) can be appropriately selected from conventionally known converters. Because the AC-DC converter (ACDC) and the isolated DC-DC converter (DCDC) are well known, detailed description thereof will be omitted here.

[0047] Here, the AC-DC converter ACDC, primary side DC capacitor C1, isolated DC-DC converter DCDC, and secondary side DC capacitor C2 constitute one cell. In FIG. 1, there are U-phase cells U11 to U22, V-phase cells V11 to V22, and W-phase cells W11 to W22. The AC sides of each cell are connected in series for each phase. The DC sides of cells U11 to W12 are connected in parallel to form DC system 21, and the DC sides of cells U21 to W22 are connected in parallel to form DC system 22. DC system 21 and DC system 22 are connected in series. V ACU11 ~V ACW22 indicates the AC output voltage of each cell, and V DC21 , V DC22 indicates the DC system voltage detection value, and I DC21 , I DC22 indicates the detected DC system current value.

[0048] In the first embodiment, the secondary side DC capacitors C2 are connected in parallel to form one DC system 21 or 22. In addition, the DC system voltage V dc21 , or DC system voltage V dc22 , or V dc21 +V dc22 is applied to the load or power supply. Each cell (AC-DC converter ACDC, isolated DC-DC converter DCDC) is equipped with a switching element. The voltage and current of each cell can be controlled by turning the switching element on and off.

[0049] In the first embodiment, the above-mentioned (1) primary-side DC voltage average value control, (3) primary-side DC voltage individual balance control, and (4) secondary-side DC voltage individual control are applied as they are, but a modification is made to the primary-side DC voltage intra-phase balance control of (2).

[0050] Here, (1) to (4) will be explained.

[0051] (1) Primary DC voltage average value control calculates the total primary DC voltage of all cells to be the total primary DC voltage of all cells, and calculates the primary DC voltage all-cell average value from the product of the total primary DC voltage all-cell value and the reciprocal of the total number of cells. The deviation between the primary DC voltage average value command value and the primary DC voltage all-cell average value is calculated and amplified, and the d-axis current command value i d_ref Output as

[0052] In addition, the AC system voltage V u ,V v ,V w The phase ωt is output based on the three-phase system current value i u , i v , i w and phase ωt, a d-q transformation is performed to obtain the d-axis current detection value i on the rotating coordinate system synchronized with the grid. d , q-axis current detection value i q Output.

[0053] The grid current control section calculates the d-axis current command value I d_ref to the d-axis current command value I d is subtracted and amplified to obtain the d-axis voltage command value V d_ref Also, the q-axis current command value I q_ref to q-axis current detection value I q is subtracted and amplified to obtain the q-axis voltage command value V q_ref Output as

[0054] (2) The primary DC voltage intra-phase balance control unit calculates the total value of the primary DC voltages in the phase as the primary DC voltage intra-phase total value, and calculates the primary DC voltage intra-phase average value for each phase from the product of the primary DC voltage intra-phase total value and the reciprocal of the number of cells in the phase. The control unit amplifies the deviation between the primary DC voltage intra-phase average value for each phase and the primary DC voltage of each cell in the phase, multiplies it by the sign of the system current value for each phase, and outputs the result as the primary DC voltage intra-phase balance control value. This value is used in embodiments 1 to 3 of the present invention, which will be described later.

[0055] (3) The primary DC voltage individual balance control unit calculates the total value of the primary DC voltages of the cells connected to each DC system, multiplies this by the reciprocal of the number of cells connected to each DC system, and calculates the DC system primary DC voltage average value for the cells connected to each DC system. It calculates the deviation between the DC system primary DC voltage average value and the primary DC voltage of each cell in the phase, removes the system frequency double component superimposed on the deviation as necessary, amplifies it with an amplifier, multiplies it by the turns ratio of the transformer of the AC-DC converter and the transformer of the isolated DC-DC converter, and outputs it as the primary DC voltage individual balance control value.

[0056] (4) The secondary DC voltage individual control unit amplifies the difference between the secondary DC voltage command value and the secondary DC voltage of each DC system, calculates the product by the reciprocal of the number of cells connected to the DC system, and outputs the result as the secondary DC voltage individual control value.The isolated DC / DC converter DCDC of each cell adds the corresponding primary DC voltage individual balance control value and secondary DC voltage individual control value to obtain a current command value, and performs power interchange based on this command.

[0057] FIG. 4 shows a block diagram of the control unit of the AC-DC converter ACDC according to the first embodiment. d_ref ,q-axis voltage command value V q_ref , and the phase ωt is the value calculated in (1).

[0058] The dq inverse converter 1 calculates the d-axis voltage command value V d_ref ,q-axis voltage command value V q_refand phase ωt, and converts the voltage command value on the rotating coordinate system synchronized with the grid into a voltage command value on the fixed coordinate system. The first multiplier 2 converts the output of the dq inverter 1 and the reciprocal 1 / V dc1_ave The output of the first multiplier 2 is multiplied by the voltage command value V u_ref , V v_ref , V w_ref Let's say.

[0059] In the first embodiment, the output voltage of the AC system side of the cell is adjusted based on the value obtained by dividing the power detection value of each DC system by the average power value of the DC system. Specifically, the voltage detection values ​​of multiple DC systems are input. In FIG. 4, application to FIG. 1 is assumed, and since there are x=2 DC systems, the DC system voltage detection value is V DC21 , V DC22 In addition, the current detection values ​​of multiple DC systems are input. As with voltage detection, the DC system current detection value I DC21 , I DC22 x=2.

[0060] The second multiplier 3 multiplies the DC system voltage detection value V DC21 , V DC22 and DC system current detection value I DC21 , I DC22 The power detection value P 21 , P 22 The first adder 4 calculates the power detection value P 21 , P 22 The third multiplier 5 calculates the sum of P 21 +P 22 Multiply by 1 / 2 to get the average power P 2ave The first divider 6 calculates the detected power value P 21 , P 22 The average power P 2ave Divide by.

[0061] The fourth multiplier 7 multiplies each phase voltage command value V u_ref , V v_ref , V w_ref The output P of the first divider 6 21 / P 2ave , P 22 / P 2aveThe number of fourth multipliers 7 is 3x, and when applied to FIG. 1, there are six. For example, when there are three DC systems, P23 / P 2ave and each phase voltage command value V u_ref , V v_ref , V w_ref Three fourth multipliers 7 are added to calculate the product of

[0062] The first subtractor 8 calculates each cell voltage command value by subtracting the primary side DC voltage intra-phase balance control value calculated in (2) from the output of the fourth multiplier 7. Based on each cell voltage command value, a gate signal for the AC / DC converter ACDC is generated by PWM modulation.

[0063] The reason why the control method in Patent Document 5 cannot maintain voltage balance is that the AC voltage of the AC-DC converter ACDC is adjusted after a load imbalance occurs and the primary-side DC voltage fluctuates, and if the primary-side DC voltage drops too quickly, the AC voltage of the AC-DC converter ACDC cannot be increased. Therefore, in this embodiment 1, feedforward control is added so that the AC voltage of the AC-DC converter ACDC is quickly adjusted when a load imbalance is detected.

[0064] The operation of the first embodiment when applied to the modular multilevel cascade converter (SST) shown in Fig. 2 will be described. 21 ) is the load of the DC system 22 (power detection value P 22 ) is detected, and the voltage command value V u_ref , V v_ref , V w_ref The voltage command value V of each phase of the cells connected to the DC system 21 u_ref , V v_ref , V w_ref has a coefficient P 21 / P 2ave = 4 / 3. The voltage command value V u_ref , V v_ref , V w_ref Coefficient P of 22 / P 2ave becomes 2 / 3.

[0065] As a result, the AC output voltage of the AC / DC converter ACDC for the upper cell is twice that of the lower cell. Because the AC current is common, the power the upper cell receives from the AC grid is twice that of the lower cell, and the secondary DC voltage and primary DC voltage are balanced. Because the AC output voltage of the AC / DC converter ACDC can be increased without waiting for the primary DC voltage to drop, it is possible to prevent the AC output voltage of the AC / DC converter ACDC from being limited by the primary DC voltage, preventing a collapse of the voltage balance. The response speed of the voltage balance control is also improved, and fluctuations in the secondary DC voltage can be suppressed.

[0066] Figure 5 shows the AC voltage V of the AC / DC converter ACDC in Figure 1. ACU11 ~V ACW22 The phasor diagram of the DC system 21 and the DC system 22 is shown. ACU11 ~V ACW22 The amplitudes of all the voltages are equal, and equal power is distributed to each DC system, maintaining voltage balance.

[0067] FIG. 6 shows the AC voltage V of the AC / DC converter ACDC when the first embodiment is applied to FIG. ACU11 ~V ACW22 1, the AC voltage V of the AC / DC converter ACDC of the cell connected to the DC grid 21 is ACU11 ~V ACW12 The amplitude of the AC voltage V of the AC / DC converter ACDC of the cell connected to the DC grid 22 is increased by 4 / 3. ACU21 ~V ACW22 The amplitude of the voltage (shown by the dashed line) changes to 2 / 3 times. As a result, the power received by the cell connected to the DC system 21 from the AC system becomes twice that of the cell connected to the DC system 22. Furthermore, since the total AC voltage of the AC-DC converters ACDC of each phase does not change before and after application of the first embodiment, there is no effect on the control of the AC current.

[0068] As described above, according to the first embodiment, it is possible to maintain balance between the DC systems and the DC voltages on the primary side of the cells in a modular multilevel cascade converter (SST) that can output multiple DC systems. The first embodiment can maintain voltage balance even when a larger load imbalance or sudden change occurs, and can suppress fluctuations in the DC voltage on the primary side of the cells. Furthermore, compared to Non-Patent Document 1, it is possible to suppress voltage fluctuations in the DC system, it is possible to connect loads that are affected by voltage fluctuations, and it is not necessary to design a voltage resistance that takes voltage fluctuations into consideration. Furthermore, unlike Patent Document 4, a changeover switch is not required.

[0069] In the first embodiment, even when the load difference between the DC systems is large or when a sudden change in the load occurs, a higher voltage balance stability can be achieved. However, for example, when the load on the DC system 21 becomes zero, the AC output voltage of the AC-DC converter ACDC of the cell connected to the DC system 21 must be set to zero. Only the cells connected to the DC system 22 must be connected to the AC system.

[0070] Therefore, it is necessary to increase the cell DC voltage and the number of cells. When the loads of the DC system 21 and the DC system 22 are opposite in direction but equal in magnitude, P 2ave = 0, the coefficient becomes infinite and balance cannot be maintained. The greater the load difference, the greater the tolerance required for the primary side DC voltage and number of cells.

[0071] [Embodiment 2] Figure 7 shows a block diagram of the control unit of the AC-DC converter ACDC of embodiment 2. In embodiment 2, when one cell fails, the output voltage on the AC system side of the cells connected to the same DC system as the failed cell is increased, and the output voltage on the AC system side of the cells connected to the other DC systems is decreased.

[0072] A specific difference from Figure 4 is that a fixed value of 3m / (3m+1-x) is input as the coefficient for increasing the output voltage. In Figure 1, m = 4 and x = 2, so 3m / (3m+1-x) = 12 / 11. Also, a fixed value of (3m-x) / (3m+1-x) is input as the coefficient for decreasing the output voltage. When applied to Figure 1 as well, (3m-x) / (3m+1-x) = 10 / 11.

[0073] The switch SW1 outputs 3m / (3m+1-x) if a cell connected to the DC system 21 fails, and outputs (3m-x) / (3m+1-x) otherwise.

[0074] The switch SW2 outputs (3m-x) / (3m+1-x) if a cell connected to the DC system 21 fails, and outputs 3m / (3m+1-x) otherwise.

[0075] The switch SW3 outputs the output of the switch SW1 if a faulty cell exists, and outputs 1 if not. The switch SW4 outputs the output of the switch SW2 if a faulty cell exists, and outputs 1 if not.

[0076] On the other hand, the fifth multiplier 9 inputs the output of the switch SW3, and outputs 1 if there is no faulty cell, 3m / (3m+1-x) if a cell connected to the DC system 21 fails, and (3m-x) / (3m+1-x) if a cell connected to the DC system 22 fails. 21 / P 2ave Put on.

[0077] The other fifth multiplier 9 inputs the output of the switch SW4, and outputs 1 if there is no faulty cell, (3m-x) / (3m+1-x) if a cell connected to the DC system 21 fails, and 3m / (3m+1-x) if a cell connected to the DC system 22 fails. 22 / P 2ave Put on.

[0078] The fourth multiplier 7 is P 21 / P 2ave , P 22 / P 2aveInstead of the output of the fifth multiplier 9 and the voltage command value V u_ref , V v_ref , V w_ref A first subtractor 8 subtracts the primary side DC voltage intra-phase balance control value from the output of the fourth multiplier 7.

[0079] In contrast to embodiment 1, embodiment 2 is designed to maintain voltage balance even if one cell fails. When all cells are normal, switches SW3 and SW4 are switched to the lower side, outputting 1, which is input to the fifth multiplier 9. Therefore, the operation is exactly the same as embodiment 1.

[0080] If one of the cells connected to the DC system 21 fails, switch SW1 outputs 3m / (3m+1-x) and switch SW2 outputs (3m-x) / (3m+1-x), which are input to the fifth multiplier 9. Using Figure 1 as an example, switch SW1 outputs 12 / 11 and switch SW2 outputs 10 / 11.

[0081] As a result, the output voltage of the AC / DC converter ACDC of the five cells connected to DC grid 21 changes by 12 / 11 times, and the output voltage of the ACDC of the six cells connected to DC grid 22 changes by 10 / 11 times. Because the AC current is common, the power transferred from the modular multilevel cascade converter (SST) to DC grid 21 is 5×12 / 11 ÷ 6 = 10 / 11, and the power transferred to DC grid 22 is 6×10 / 11 ÷ 6 = 10 / 11, which is equal, and voltage balance can be maintained.

[0082] The power supplied is reduced by 10 / 11 times, but this is because the voltage command value for each phase V u_ref , V v_ref , V w_ref By increasing the amplitude of the DC voltage or increasing the AC current by controlling the average value of the primary DC voltage (1) of Patent Document 5, the original interchange power can be maintained.

[0083] If one of the cells connected to DC system 22 fails, the output voltage of the AC / DC converter ACDC of the six cells connected to DC system 21 will change by 10 / 11 times, and the output voltage of the AC / DC converter ACDC of the five cells connected to DC system 22 will change by 12 / 11 times. In this case too, the power transferred from the SST to each system will be equal.

[0084] FIG. 8 shows the AC voltage V of the AC / DC converter ACDC when the second embodiment is applied to FIG. ACU11 ~V ACW22 The phasor diagram of V ACU11 becomes zero due to a fault, and the AC voltage V of the remaining AC-DC converter ACDC of the cells connected to the DC grid 21 ACU12 ~V ACW12 The amplitude of the AC voltage V of the AC / DC converter ACDC of the cell connected to the DC grid 22 is 12 / 11 times. ACU21 ~V ACW22 The amplitude of the voltage changes by 10 / 11 times. As a result, the total power received from the AC grid by the five cells connected to the DC grid 21 and the six cells connected to the DC grid 22 becomes equal, making it possible to maintain voltage balance.

[0085] Furthermore, the total AC voltage of the AC-DC converters ACDC for the V and W phases remains unchanged before and after the application of this embodiment 2. However, the total AC voltage of the AC-DC converter ACDC for the U phase decreases, resulting in a three-phase imbalance. This can be resolved by controlling the grid current, but this is feedback control, which takes time, and the AC voltage of the AC-DC converter ACDC for the U phase must be increased by a further factor of approximately 1.37. If the primary-side DC voltage is too low at this time, the AC voltage of the AC-DC converter ACDC for the U phase cannot be increased, which could lead to problems such as imbalance and distortion of the AC current. This problem can be addressed by the third embodiment.

[0086] As described above, according to the second embodiment, even if one cell fails, it is possible to continue operation while maintaining voltage balance. Unlike Patent Document 1 and Patent Document 3, there is no need to increase the primary-side DC voltage or secondary-side DC voltage of the cell, so there is no need to design the cell's withstand voltage taking this into consideration. Furthermore, unlike Patent Document 2, this embodiment can be applied to applications that perform AC / DC power conversion, and can also be applied to a configuration in which series-parallel connections are mixed on the DC side.

[0087] [Embodiment 3] FIG. 9 shows the phase voltage command value V u_ref , V v_ref , V w_ref The block diagram of the calculation unit of Fig. 9 is shown. Fig. 9 differs from Fig. 4 and Fig. 7 in the following points.

[0088] Enter the fixed value (3m-x+1) / (3m-x-2). Assuming application to Figure 1, the number of cells per phase is m=4, and the number of output DC systems is x=2, so (3m-x+1) / (3m-x-2)=11 / 8.

[0089] Switch SW5 outputs (3m-x+1) / (3m-x-2) if a cell connected to the U phase fails, and outputs 1 otherwise. u The switch SW6 outputs (3m-x+1) / (3m-x-2) if the cell connected to the V phase fails, and outputs 1 otherwise. v The switch SW7 outputs (3m-x+1) / (3m-x-2) if the cell connected to the W phase fails, and outputs 1 otherwise. w Let's say.

[0090] The numerator of the coefficient, N, is the number of cells in each phase, N=m. The notation of N conforms to Patent Documents 6 and 7. The denominator of the coefficient, n u , n v , n w is the number of cells in each phase that are operating without failure.

[0091] The sixth multiplier 11 multiplies the AC system voltage detection value V uand coefficient N / n u The product of this and the AC system voltage detection value V v and coefficient N / n v The product of this and the AC system voltage detection value V w and coefficient N / n w Find the product of

[0092] The computing unit 12 multiplies the output V of the sixth multiplier 11 by u N / n u , V v N / n v , V w N / n w , coefficient N / n u , N / n v , N / n w Based on Patent Document 6, the zero-phase voltage V 0q sinωt, V 0d Outputs cosωt.

[0093] Here, the method of calculating the zero-phase voltage of Patent Document 6, which is implemented inside the computing unit 12, will be described.

[0094] The correction voltage command value generator outputs a phase ωt synchronized with the AC voltage of the grid. The first dq converter converts the phase voltage detection signal or voltage command value, or the phase voltage detection signal or voltage command value, multiplied by a coefficient obtained by dividing the number of cells in each phase by the number of cells in each phase that are operating without failure, into a value on a rotating coordinate system synchronized with the grid frequency. The second dq converter converts the phase voltage detection signal or voltage command value, or the phase voltage detection signal or voltage command value, multiplied by a coefficient obtained by dividing the number of cells in each phase by the number of cells in each phase that are operating without failure, into a value on a rotating coordinate system that rotates in the direction opposite to the grid frequency. The calculator extracts a DC component from the output of the first dq converter and converts it into a positive-phase d-axis component V 1d , positive sequence q-axis component V 1q and the negative-phase d-axis component V extracted from the output of the second dq converter. 2d , reverse phase q-axis component V 2q Based on this, the zero-phase voltage d-axis component V that equalizes the AC output voltage of each cell is 0d , the zero-phase voltage q-axis component V 0q is calculated using one of the following equations (1) to (3). The zero-phase voltage d-axis component V 0dis multiplied by cosωt. The zero-phase voltage q-axis component V 0q Multiply by sinωt.

[0095]

number

[0096]

number

[0097]

number

[0098] Next, a method for calculating the zero-phase voltage when the method disclosed in Patent Document 7 is implemented in the computing unit 12 will be described.

[0099] The correction voltage command value generator calculates the amplitude of the correction voltage command value for each phase. The amplitude may be, for example, the effective value of the voltage command value, the value obtained by extracting the amplitude of the fundamental wave component of the voltage command value, or the peak value per cycle of the voltage command value. The calculated amplitude is multiplied by a coefficient based on the number of failed cells. The deviation between the three-phase average value of the amplitude of the multiplied correction voltage command value and the amplitude of the multiplied correction voltage command value is amplified and multiplied by a sine wave in phase with the voltage command value. The multiplied values ​​for the three phases are added together and output as the zero-phase sequence voltage.

[0100] The zero-phase voltage V output from the calculator 12 0q sinωt, V 0d cosωt is added by the second adder 13. The third adder 14 adds the zero-phase voltage V 0q sinωt+V 0d cosωt is added to the output of the dq inverse converter 1, and a corrected voltage command value for each phase is output.

[0101] The correction voltage command value of each phase is input to the first multiplier 2 and is also input again to the calculator 12, where it is again subjected to feedback control based on Patent Document 7 to calculate the zero-phase voltage V 0q sinωt, V 0dcosωt is calculated (when the calculation is performed based on Patent Document 6, the correction voltage command value for each phase does not need to be input to the calculator 12).

[0102] The first multiplier 2 adds the reciprocal 1 / V of the average DC voltage on the primary side of all cells to the output of the third adder 14. dc1_ave and each phase voltage command value V u_ref , V v_ref , V w_ref As such, the first and second embodiments are applied.

[0103] The third embodiment is an example of combining the first and second embodiments with patent documents 6 and 7. When all cells are normal, the combination can be performed without any particular problems. However, when there is a faulty cell, the combination cannot be applied as is.

[0104] In Patent Documents 6 and 7, the AC voltage of the phase including the failed cell is multiplied by a coefficient N / n u , N / n v , N / n w By multiplying this, the voltage amplitude appears larger according to the number of faulty cells, and a zero-phase sequence voltage is calculated and superimposed to equalize the voltage amplitude. However, this can only be applied if the amplitude of the AC output voltage of the AC / DC converter ACDC of each cell is equal.

[0105] In the first and second embodiments, a coefficient P 21 / P 2ave , P 22 / P 2ave Since the amplitudes of the AC output voltages of the AC / DC converters ACDC are different due to the factors 3m / (3m+1-x), (3m-x) / (3m+1-x), etc., the coefficients N / n u , N / n v , N / n w adjustments need to be made.

[0106] where P 21 =P 22 (The coefficient of the first embodiment is P 21 / P 2ave =P 22 / P2ave =1), the output voltage of the AC-DC converter ACDC of all cells before the cell failure is set to 1, and a case will be considered in which a cell connected to both the U phase and the DC system 21 fails. The remaining 3m / x-1 cells connected to the DC system 21 have an AC output voltage of 3m / (3m+1-x) based on embodiment 2. The cells connected to the other DC systems 22 to 2x have an AC output voltage of (3m-x) / (3m+1-x).

[0107] Looking at the U phase, there are m / x-1 cells whose AC output voltage of the AC-DC converter ACDC has become 3m / (3m+1-x), mm / x cells whose AC output voltage has become (3m-x) / (3m+1-x), and 1 cell that has failed and become 0. The total U phase of the AC output voltage of the AC-DC converter ACDC is m(3m-x-2) / (3m-x+1). Before the failure, there were m cells that output 1, so the total U phase of the AC output voltage of the AC-DC converter ACDC changes by a factor of (3m-x-2) / (3m-x+1).

[0108] For the V and W phases, the cells where the AC output voltage of the AC / DC converter ACDC has become 3m / (3m+1-x) due to the failure are in the m / x range, and the cells where it has become (3m-x) / (3m+1-x) are in the mm / x range, just like the U phase. The total AC output voltage of the AC / DC converter ACDC for the V and W phases is m, and does not change before or after the failure. Therefore, the coefficient N / n u may be set to (3m-x+1) / (3m-x-2), which is the reciprocal of the total amount of change in the U-phase AC output voltage of the AC-DC converter ACDC.

[0109] A case where a cell connected to both the U phase and the DC system 21 fails in the configuration of m=4 and x=2 in Fig. 2 will be described again. According to the second embodiment, the output voltage of the AC-DC converter ACDC with five cells connected to the DC system 21 is 12 / 11 times. The output voltage of the AC-DC converter ACDC with six cells connected to the DC system 22 is 10 / 11 times.

[0110] In the U phase, there is one cell that has increased to 12 / 11 times, and two cells that have increased to 10 / 11 times. The total output voltage changes from 4 to 32 / 11, decreasing to 8 / 11 times. The number of cells does not simply decrease from four to three, resulting in a 3 / 4 times increase; rather, the decrease in the total output voltage is greater because there are more cells whose AC / DC converter ACDC output voltage has decreased.

[0111] In the V and W phases, two cells have increased by 12 / 11 times, and two cells have increased by 10 / 11 times, so the total output voltage remains 4. From the above, it is sufficient to multiply vu by a coefficient of 11 / 8 to make the U-phase voltage amplitude appear larger. Based on the above, in the third embodiment, the AC voltage of the phase in which the faulty cell is located is multiplied by a coefficient of 11 / 8 to determine the zero-phase sequence voltage and superimpose it.

[0112] FIG. 10 shows the AC voltage V of the AC / DC converter ACDC when the third embodiment is applied to the configuration of FIG. ACU11 ~V ACW22 1 is a phasor diagram of the above. By adding the zero-phase sequence voltage, the line voltages are brought into three-phase balance. The amplitude of the AC voltage of the AC-DC converter ACDC needs to be increased not only for the U phase but also for the V and W phases, but the increase can be reduced from approximately 1.37 times in the second embodiment to approximately 1.09 times.

[0113] According to the third embodiment, when one cell fails, the AC output voltages of the AC-DC converters ACDC of cells connected to the same DC system can be equalized. This can prevent situations such as an excessive DC voltage being applied to other cells in the phase where the failed cell is located, causing a chain reaction of failures, or an insufficient AC output voltage in the phase where the failed cell is located, making it impossible to maintain grid connection and causing overcurrent, or voltage and current distortion. Furthermore, as in Patent Documents 6 and 7, the AC output voltages of the cells can be equalized when an imbalance occurs in the AC voltage or when an unbalanced AC voltage is intentionally output.

[0114] It should be noted that the first to third embodiments can also be applied to configurations other than m=4 and x=2.

[0115] Although the present invention has been described in detail above only with respect to the specific examples, it will be apparent to those skilled in the art that various modifications and variations are possible within the scope of the technical concept of the present invention, and it is natural that such modifications and variations fall within the scope of the claims. [Explanation of symbols]

[0116] 1...dq inverse converter, 2...first multiplier, 3...second multiplier, 4...first adder, 5...third multiplier, 6...first divider, 7...fourth multiplier, 8...first subtractor, 9...fifth multiplier, 11...sixth multiplier, 12...arithmetic unit, 13...second adder, 14...third adder, ACDC...AC-DC converter, DCDC...isolated DC-DC converter, C1...primary side DC capacitor, C2...secondary side DC capacitor

Claims

1. A modular multilevel cascade converter having m (m: an integer of 2 or more) cells per phase, each cell including an AC / DC converter connected to an AC system, a primary-side DC capacitor connected to the DC side of the AC / DC converter, an isolated DC / DC converter having one DC side connected to the primary-side DC capacitor, and a secondary-side DC capacitor connected to the other DC side of the isolated DC / DC converter, and having x (x: an integer of 2 or more) DC systems in which a plurality of the secondary-side DC capacitors are connected in parallel, and supplying voltages of a plurality of the DC systems to a load or a power source, The control unit of the AC / DC converter A modular multilevel cascade converter, characterized in that the output voltage of the AC system side of the cell is adjusted based on a value obtained by dividing a power detection value of each of the DC systems by an average power value of the DC system.

2. The control unit of the AC-DC converter a fourth multiplier that multiplies each phase voltage command value of the AC-DC converter by a value obtained by dividing the power detection value of the DC system by the average power value of the DC system; a primary DC voltage intra-phase balance control unit that outputs a primary DC voltage intra-phase balance control value based on the primary DC voltage intra-phase average value of each phase and the primary DC voltage of each cell; a first subtractor that subtracts the primary-side DC voltage intra-phase balance control value from the output of the fourth multiplier and outputs each cell voltage command value; 2. The modular multilevel cascade converter according to claim 1, further comprising: a gate signal for the AC-DC converter based on the voltage command value of each cell.

3. The control unit of the AC-DC converter 2. The modular multilevel cascade converter according to claim 1, wherein, when one of the cells fails, the output voltages on the AC system sides of the cells connected to the same DC system as the failed cell are increased, and the output voltages on the AC system sides of the other cells connected to the DC system are decreased.

4. The control unit of the AC-DC converter a fifth multiplier that multiplies, when one of the cells fails, a value obtained by dividing the power detection value of the DC system by the average power value of the DC system, by 3m / (3m-x+1) for cells connected to the same DC system as the failed cell, by (3m-x) / (3m-x-1) for cells connected to a DC system different from the failed cell when one of the cells fails, and by 1 when there is no failed cell; a fourth multiplier that multiplies each phase voltage command value of the AC-DC converter by an output of the fifth multiplier; a primary DC voltage intra-phase balance control unit that outputs a primary DC voltage intra-phase balance control value based on the primary DC voltage intra-phase average value of each phase and the primary DC voltage of each cell; a first subtractor that subtracts the primary-side DC voltage intra-phase balance control value from the output of the fourth multiplier and outputs each cell voltage command value; 2. The modular multilevel cascade converter according to claim 1, further comprising: a gate signal for the AC-DC converter based on the voltage command value of each cell.

5. The control unit of the AC-DC converter a dq inverse transformer for transforming a voltage command value on a rotating coordinate system into a voltage command value on a fixed coordinate system; A switch for each phase outputs (3m-x+1) / (3m-x-2) as a coefficient for the phase to which the faulty cell is connected, and outputs 1 as a coefficient for the other phases; a sixth multiplier that multiplies the AC voltage of each phase by the output of the switch of each phase; a computing unit that outputs a zero-phase voltage based on the output of the sixth multiplier and the coefficient; a third adder that adds the zero-phase sequence voltage to the fixed coordinate voltage command value; a first multiplier that multiplies the output of the third adder by the reciprocal of an average value of the primary side DC voltages of all the cells and outputs the result as the respective phase voltage command values; 5. The modular multilevel cascade converter according to claim 2, further comprising:

6. A control method for a modular multilevel cascade converter, the converter comprising: m (m: an integer of 2 or more) cells per phase, each cell including an AC-DC converter connected to an AC system; a primary-side DC capacitor connected to a DC side of the AC-DC converter; an isolated DC-DC converter having one DC side connected to the primary-side DC capacitor; and a secondary-side DC capacitor connected to the other DC side of the isolated DC-DC converter; x (x: an integer of 2 or more) DC systems in which a plurality of the secondary-side DC capacitors are connected in parallel; and the converter supplies voltages of a plurality of the DC systems to a load or a power source, The control unit of the AC / DC converter A control method for a modular multilevel cascade converter, comprising: adjusting an output voltage of the cell on the AC system side based on a value obtained by dividing a power detection value of each of the DC systems by an average power value of the DC system.

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