Slave device, processing system, processing method, and program

Abstract

To provide slave devices, a processing system, a processing method, and a program in which a plurality of slave devices having the same I2C address can exist in a system and which transmit in appropriate timing even when there is a read request from master devices.SOLUTION: In a processing system, a plurality of slave devices 20 performing communication by using an Inter-IntegratedCircuit communication system include reception means for receiving a read request from a master device, and output means for outputting data at timing corresponding to a set identifier when the reception means receives the read request.SELECTED DRAWING: Figure 10

Description

[Technical Field]

[0001] The present disclosure relates to a slave device, a processing system, a processing method, and a program. [Background technology]

[0002] Communication using the Inter-Integrated Circuit communication method (I2C communication) is used in a variety of fields. Patent Document 1 discloses a related technique for communication between devices in a master-slave relationship. [Prior art documents] [Patent documents]

[0003] [Patent Document 1] Special Publication No. 2017-500631 Summary of the Invention [Problem to be solved by the invention]

[0004] In the field of I2C communication related to Patent Document 1, there can be multiple slave devices with the same I2C address in a system, and there is a demand for technology that can transmit data at the appropriate time even when a read request is made by a master device.

[0005] One of the objectives of each aspect of the present disclosure is to provide a slave device, a processing system, a processing method, and a program that can solve the above-mentioned problems. [Means for solving the problem]

[0006] According to one aspect of the present disclosure, the slave device is a slave device that communicates using an Inter-Integrated Circuit communication method, and includes a receiving means that receives a read request from a master device, and an output means that, when the receiving means receives the read request, outputs data at a timing according to a set identifier.

[0007] According to another aspect of the present disclosure, a processing system includes the above-described slave device and a master device that sends a read request to the slave device.

[0008] According to another aspect of the present disclosure, a processing method is a processing method executed by a slave device that communicates using an Inter-Integrated Circuit communication method, and includes receiving a read request from a master device, and when the read request is received, outputting data at a timing according to a set identifier.

[0009] According to another aspect of the present disclosure, a program causes a computer of a slave device that communicates using an Inter-Integrated Circuit communication method to receive a read request from a master device, and, upon receiving the read request, output data at a timing according to a set identifier. [Effects of the Invention]

[0010] According to each aspect of the present disclosure, multiple slave devices having the same I2C address can exist in a system, and even if a read request is made by a master device, data can be transmitted at the appropriate time. [Brief explanation of the drawings]

[0011] [Figure 1] FIG. 1 illustrates an example of a configuration of a processing system according to some embodiments of the present disclosure. [Figure 2]FIG. 10 is a diagram illustrating a write process performed by a master device according to some embodiments of the present disclosure. [Figure 3] FIG. 1 illustrates an example of packaging for a slave device according to some embodiments of the present disclosure. [Figure 4] FIG. 10 is a diagram illustrating an example of setting an I2C address according to some embodiments of the present disclosure. [Figure 5] FIG. 10 is a diagram illustrating an example of ID setting according to some embodiments of the present disclosure. [Figure 6] FIG. 10 is a diagram illustrating a read process performed by a master device according to some embodiments of the present disclosure. [Figure 7] FIG. 1 illustrates an example of a configuration of a processing system according to some embodiments of the present disclosure. [Figure 8] FIG. 2 illustrates an example of timing in a write cycle of a processing system according to some embodiments of the present disclosure. [Figure 9] FIG. 10 illustrates an example of timing in a read cycle of a processing system according to some embodiments of the present disclosure. [Figure 10] FIG. 1 illustrates an example of a configuration of a slave device according to some embodiments of the present disclosure. [Figure 11] FIG. 10 illustrates an example of a processing flow of a slave device according to some embodiments of the present disclosure. [Figure 12] FIG. 1 is a schematic block diagram illustrating the configuration of a computer according to at least one embodiment. DETAILED DESCRIPTION OF THE INVENTION

[0012] Hereinafter, the embodiments will be described in detail with reference to the drawings. <Embodiment> A processing system 1 according to an embodiment of the present disclosure will be described with reference to the drawings. The processing system 1 is a system that enables simultaneous access to the same Inter-Integrated Circuit (hereinafter referred to as "I2C") address. Specifically, the processing system 1 keeps the I2C address of the I2C bus at 7 bits and has a device identifier (hereinafter referred to as "ID") separate from the I2C address, thereby increasing the number of devices that can be connected to the I2C bus and enabling simultaneous access. The processing system 1 will be described below to clarify this point.

[0013] (Processing system configuration) 1 is a diagram illustrating an example of a configuration of a processing system 1 according to some embodiments of the present disclosure. As shown in FIG. 1, the processing system 1 according to one embodiment of the present disclosure includes a master device 10, slave devices 20a1, 20a2, 20a3, 20a4, 20a5, 20a6, 20a7, 20a8, 20a9, 20a10, 20a11, 20a12, 20a13, 20a14, 20a15, and 20a16, and an I2C bus 30. The slave devices 20a1, 20a2, 20a3, 20a4, 20a5, 20a6, 20a7, 20a8, 20a9, 20a10, 20a11, 20a12, 20a13, 20a14, 20a15, and 20a16 may be collectively referred to as slave devices 20a.

[0014] The master device 10 simultaneously writes data to the slave devices 20a having the same I2C address. FIG. 2 is a diagram illustrating a write process performed by the master device 10 according to some embodiments of the present disclosure. FIG. 2 illustrates an example of a write cycle of the I2C bus in which the master device 10 simultaneously writes 16 bits (2 bytes) of data to the slave devices 20a5, 20a6, 20a7, and 20a8 at I2C address x1. As shown in FIG. 2, the master device 10 can execute the write shown in the write cycle to the slave device 20a having the same I2C address x1 without violating the I2C standard.

[0015] The master device 10 also reads data from the slave device 20a having the same I2C address. The master device 10 has previously registered the slave device 20a having the same I2C address, and thus knows the slave device 20a in advance. Alternatively, a higher-level control unit (not shown) of the master device 10 may have previously registered the slave device 20a, and the master device 10 may acquire information about the slave device 20a from the higher-level control unit, thereby learning about the slave device 20a in advance. Details of the processing performed by the master device 10 will be described later.

[0016] Slave devices 20a1, 20a2, 20a3, and 20a4 each have an address value x0 indicating the same I2C address. Slave devices 20a5, 20a6, 20a7, and 20a8 each have an address value x1 indicating the same I2C address. Slave devices 20a9, 20a10, 20a11, and 20a12 each have an address value x2 indicating the same I2C address. Slave devices 20a13, 20a14, 20a15, and 20a16 each have an address value x3 indicating the same I2C address.

[0017] Furthermore, slave devices 20a1, 20a5, 20a9, and 20a13 each have an ID value of ID0. Slave devices 20a2, 20a6, 20a10, and 20a14 each have an ID value of ID1. Slave devices 20a3, 20a7, 20a11, and 20a15 each have an ID value of ID2. Slave devices 20a4, 20a8, 20a12, and 20a16 each have an ID value of ID3.

[0018] FIG. 3 illustrates an example of packaging for a slave device 20a according to some embodiments of the present disclosure. For example, as illustrated in FIG. 3, each of the slave devices 20a includes terminals T1, T2, T3, T4, T5, T6, T7, and T8. For example, terminal T1 is a ground terminal. For example, terminal T2 is a terminal corresponding to the most significant bit of the two least significant bits in a seven-bit I2C address. For example, terminal T3 is a terminal corresponding to the least significant bit of the two least significant bits in a seven-bit I2C address. For example, terminal T4 is one of two terminals for setting an ID. For example, terminal T5 is a power supply terminal. For example, terminal T6 is the other of two terminals for setting an ID. For example, terminal T7 is a clock terminal. This clock terminal may be referred to as an SCL (Serial CLK) terminal. For example, terminal T8 is a data terminal. This data terminal may be referred to as an SDA (Serial DAta) terminal.

[0019] 4 is a diagram illustrating an example of setting an I2C address according to some embodiments of the present disclosure. For example, the upper five bits of a seven-bit I2C address are a device-specific value, and the lower two bits can set four different addresses. These lower two bits can be set depending on the states of terminals T2 and T3.

[0020] For example, as shown in FIG. 4, by connecting terminal T2 to a wiring having a high level potential (e.g., a wiring connected to a power supply terminal) via a pull-up resistor and connecting terminal T3 to a wiring having a high level potential via a pull-up resistor, the address value of slave device 20a can be set to x3. Alternatively, by connecting terminal T2 to a wiring having a high level potential via a pull-up resistor and terminal T3 to a wiring having a low level potential (e.g., a wiring connected to a ground terminal) via a pull-down resistor, the address value of slave device 20a can be set to x2. Alternatively, by connecting terminal T2 to a wiring having a low level potential via a pull-down resistor and terminal T3 to a wiring having a high level potential via a pull-up resistor, the address value of slave device 20a can be set to x1. Alternatively, by connecting terminal T2 to a wiring having a low level potential via a pull-down resistor and terminal T3 to a wiring having a low level potential via a pull-down resistor, the address value of slave device 20a can be set to x0.

[0021] FIG. 5 is a diagram illustrating an example of ID setting according to some embodiments of the present disclosure. For example, as shown in FIG. 5, the ID value of the slave device 20a can be set to ID3 by connecting terminal T4 to a wiring having a high potential via a pull-up resistor and connecting terminal T6 to a wiring having a high potential via a pull-up resistor. Alternatively, as shown in FIG. 5, the ID value of the slave device 20a can be set to ID2 by connecting terminal T4 to a wiring having a high potential via a pull-up resistor and connecting terminal T6 to a wiring having a low potential via a pull-down resistor. Alternatively, as shown in FIG. 5, the ID value of the slave device 20a can be set to ID1 by connecting terminal T4 to a wiring having a low potential via a pull-down resistor and connecting terminal T6 to a wiring having a high potential. Alternatively, as shown in FIG. 5, the ID value of the slave device 20a can be set to ID0 by connecting terminal T4 to a wiring having a low potential via a pull-down resistor and connecting terminal T6 to a wiring having a low potential via a pull-down resistor.

[0022] FIG. 6 is a diagram illustrating a read process performed by the master device 10 according to some embodiments of the present disclosure. FIG. 6 illustrates an example of an I2C read cycle in which the master device 10 reads a total of eight bytes of data, two bytes each, from the slave devices 20a9, 20a10, 20a11, and 20a12 at I2C address x2. As illustrated in FIG. 6, the master device 10 initiates a read cycle 170. In response to the read cycle 170 by the master device 10, the slave device 20a9, whose ID value is ID0, outputs a total of two bytes of data, data 171 and 172. Subsequently, in response to the read cycle 170 by the master device 10, the slave device 20a10, whose ID value is ID1, outputs a total of two bytes of data, data 173 and 174. Subsequently, in response to the read cycle 170 by the master device 10, the slave device 20a11, whose ID value is ID2, outputs a total of two bytes of data, data 175 and 176. Next, in response to read cycle 170 by master device 10, slave device 20a12, whose ID value is ID3, outputs a total of two bytes of data, data 177 and 178. In this way, slave device 20a having the same I2C address outputs data in a predetermined order of ID value (for example, ascending order) in response to the A (acknowledge) signal output by master device 10 (that is, outputs data at a timing according to its own ID value), thereby realizing the desired read. Details of the processing performed by slave device 20a will be described later.

[0023] The I2C bus connects the master device 10 and the slave device 20a, and transmits data in communication between the master device 10 and the slave device 20a.

[0024] The above-described processing performed by the processing system 1 according to the embodiment of the present disclosure is merely an example, and the processing system 1 is not limited to the above-described processing. For example, the processing system 1 may perform the processing described below.

[0025] (Processing performed by the processing system) The following describes processing performed by the processing system 1. FIG. 7 is a diagram illustrating an example of the configuration of the processing system 1 according to some embodiments of the present disclosure. As shown in FIG. 7, the processing system 1 described here includes a master device 10, slave devices 20a21, 20a22, 20a23, and 20a24, and pull-up resistors 180 and 181. The pull-up resistor 180 is a resistor that pulls up the SCL signal line. The pull-up resistor 181 is a resistor that pulls up the SDA signal line.

[0026] It is assumed that each of slave devices 20a21, 20a22, 20a23, and 20a24 is set to the same I2C address xN by using at least one of a pull-up resistor and a pull-down resistor to set the potential of terminals T2 and T3, where xN is any one of I2C addresses x0, x1, x2, and x3.

[0027] Furthermore, it is assumed that the ID value of slave device 20a21 is set to ID0 by using a pull-down resistor to set terminals T4 and T6 to low potential. Furthermore, it is assumed that the ID value of slave device 20a22 is set to ID1 by using a pull-down resistor to set terminal T4 to low potential and a pull-up resistor to set terminal T6 to high potential. Furthermore, it is assumed that the ID value of slave device 20a23 is set to ID2 by using a pull-up resistor to set terminal T4 to high potential and a pull-down resistor to set terminal T6 to low potential. Furthermore, it is assumed that the ID value of slave device 20a24 is set to ID3 by using a pull-up resistor to set terminals T4 and T6 to high potential.

[0028] The clock terminals of the master device 10 and the slave devices 20a21, 20a22, 20a23, and 20a24 are connected to the SCL signal line of the I2C bus. The data terminals of the master device 10 and the slave devices 20a21, 20a22, 20a23, and 20a24 are connected to the SDA signal line of the I2C bus. The clock terminals and data terminals of the master device 10 and the slave devices 20a21, 20a22, 20a23, and 20a24 are open-drain. That is, the clock terminals and data terminals of the master device 10 and the slave devices 20a21, 20a22, 20a23, and 20a24 output low-level signals only when the I2C bus is set to low. The high level of the I2C bus is realized by pulling up the SCL and SDA signal lines of the I2C bus to the power supply voltage VCC using pull-up resistors. Note that slave device 20a having an I2C address different from slave devices 20a21, 20a22, 20a23, and 20a24 may be connected to the SCL and SDA signal lines of the I2C bus.

[0029] (Write process) First, a write process performed by the processing system 1 will be described. FIG. 8 is a diagram illustrating an example of timing in a write cycle of the processing system 1 according to some embodiments of the present disclosure. FIG. 8 illustrates an example in which the master device 10 issues a write cycle command and writes 8 bits of data. Part (a) of FIG. 8 illustrates a clock signal propagating through the SCL signal line of the I2C bus. Part (b) of FIG. 8 illustrates a data signal propagating through the SDA signal line of the I2C bus. Part (c) of FIG. 8 illustrates a data signal output by the master device 10. Part (d) of FIG. 8 illustrates a data signal output by the slave device 20a21. Part (e) of FIG. 8 illustrates a data signal output by the slave device 20a22. Part (f) of FIG. 8 illustrates a data signal output by the slave device 20a23. Part (g) of FIG. 8 illustrates a data signal output by the slave device 20a24.

[0030] The data signal shown in part (b) of Fig. 8 is a combination of data signals output by all devices connected to the SDA signal line of the I2C bus (i.e., master device 10 and slave devices 20a21, 20a22, 20a23, and 20a24). The dotted lines in Fig. 8 indicate that the data signal outputs by master device 10 and slave devices 20a21, 20a22, 20a23, and 20a24 are off and are at a high level potential due to pull-up resistor 181 connected to the SDA signal line of the I2C bus.

[0031] The master device 10 outputs a low-level data signal 201 indicating a Start Condition, which is a signal to start a write cycle. Next, the master device 10 outputs a 7-bit I2C address 202. Then, the master device 10 outputs a low-level data signal 203 indicating a write access. Slave devices 20a21, 20a22, 20a23, and 20a24, which have the same I2C address, simultaneously output an A signal 204 indicating an acknowledgment.

[0032] In response to the A signal 204, the master device 10 outputs a write data signal 205, which is a data signal for writing 8 bits. Upon receiving the write data signal 205, each of the slave devices 20a21, 20a22, 20a23, and 20a24 simultaneously outputs an acknowledgement A signal 206. The master device 10 outputs a low-level data signal 207 indicating a stop condition, which is a signal to end the write cycle. In this manner, the write cycle ends.

[0033] (Read process) Next, a read process performed by the processing system 1 will be described. FIG. 9 is a diagram illustrating an example of timing in a read cycle of the processing system 1 according to some embodiments of the present disclosure. FIG. 9 illustrates an example in which the master device 10 issues a read cycle command and reads a total of 32 bits of data, 8 bits each, from each of the slave devices 20a21, 20a22, 20a23, and 20a24. Part (a) of FIG. 9 illustrates a clock signal propagating through the SCL signal line of the I2C bus. Part (b) of FIG. 9 illustrates a data signal propagating through the SDA signal line of the I2C bus. Part (c) of FIG. 9 illustrates a data signal output by the master device 10. Part (d) of FIG. 9 illustrates a data signal output by the slave device 20a21. Part (e) of FIG. 9 illustrates a data signal output by the slave device 20a22. Part (f) of FIG. 9 illustrates a data signal output by the slave device 20a23. Part (g) in FIG. 9 shows the data signal output by the slave device 20a24.

[0034] The master device 10 outputs a low-level data signal 301 indicating a start condition, which is a signal to start a read cycle. Next, the master device 10 outputs a 7-bit I2C address 302. Then, the master device 10 outputs a high-level data signal 303 indicating a read access.

[0035] Slave devices 20a21, 20a22, 20a23, and 20a24, which correspond to the information indicated by the lowest two bits of the 7-bit I2C address 302 output by master device 10, simultaneously output A signal 304 indicating an affirmative response. Upon receiving A signal 304, master device 10 begins reading out 32 bits of data (8 bits x 4).

[0036] For example, slave device 20a21 outputs 8-bit data 305. Slave device 20a21 then waits for data signal 207 at a low level, indicating a Stop Condition, and stops output. While slave device 20a21 is outputting 8-bit data 305, slave devices 20a22, 20a23, and 20a24 are each in a standby state. Master device 10 receives 8-bit data 305. Master device 10 then outputs signal A 306, indicating an acknowledgment.

[0037] Slave devices 20a22, 20a23, and 20a24 each confirm A signal 306. Slave device 20a22 then outputs 8-bit data 307. Slave device 20a22 waits for data signal 207 to go low, indicating a Stop Condition, and stops output. While slave device 20a22 is outputting 8-bit data 307, each of slave devices 20a21, 20a23, and 20a24 is in a standby state. Master device 10 receives 8-bit data 307. Master device 10 then outputs A signal 308, indicating an acknowledgment.

[0038] Slave devices 20a23 and 20a24 each confirm A signal 308. Slave device 20a23 then outputs 8-bit data 309. Slave device 20a23 waits for data signal 207 to go low, indicating a Stop Condition, and stops output. While slave device 20a23 is outputting 8-bit data 309, each of slave devices 20a21, 20a22, and 20a24 is in a standby state. Master device 10 receives 8-bit data 309. Master device 10 then outputs A signal 310, indicating an acknowledgment.

[0039] Slave device 20a24 confirms A signal 310. Then, slave device 20a24 outputs 8-bit data 311. Slave device 20a24 waits for low-level data signal 207, which indicates a Stop Condition, and stops output. While slave device 20a24 is outputting 8-bit data 311, slave devices 20a21, 20a22, and 20a23 are each in a standby state. Master device 10 receives 8-bit data 311. Then, master device 10 outputs Ab signal 312, which indicates a negative acknowledgement. Master device 10 outputs low-level data signal 207, which indicates a Stop Condition. The read cycle thus ends.

[0040] (advantage)

[0041] The processing system 1 according to some embodiments of the present disclosure has been described above. In the processing system 1, the slave device 20a is a slave device that communicates using the Inter-Integrated Circuit communication method. The slave device 20a receives a read request from the master device 10. When the slave device 20a receives the read request, it outputs data at a timing according to a set identifier.

[0042] This slave device 20a allows multiple slave devices 20a with the same I2C address to exist in the processing system 1, and even when a read request is made from the master device, data can be transmitted at an appropriate timing.

[0043] Next, a slave device 20 according to some embodiments of the present disclosure will be described. Fig. 10 is a diagram illustrating an example of the configuration of the slave device 20 according to some embodiments of the present disclosure. The slave device 20 is a slave device that performs communication using an Inter-Integrated Circuit communication method. As shown in Fig. 10, the slave device 20 includes a receiving means 801 and an output means 802.

[0044] The receiving means 801 receives a read request from a master device. When the receiving means 801 receives the read request, the output means 802 outputs data at a timing according to the set identifier.

[0045] The slave device 20 can be realized, for example, using the functions of the slave devices 20a, 20a1, 20a2, 20a3, 20a4, 20a5, 20a6, 20a7, 20a8, 20a9, 20a10, 20a11, 20a12, 20a13, 20a14, 20a15, and 20a16 shown in FIG. 1 and the slave devices 20a21, 20a22, 20a23, and 20a24 shown in FIG. 7. That is, the receiving means 801 and the output means 802 can be realized, for example, using the functions possessed by slave devices 20a, 20a1, 20a2, 20a3, 20a4, 20a5, 20a6, 20a7, 20a8, 20a9, 20a10, 20a11, 20a12, 20a13, 20a14, 20a15, and 20a16 shown in FIG. 1, and slave devices 20a21, 20a22, 20a23, and 20a24 shown in FIG. 7.

[0046] Next, a description will be given of processing performed by the slave device 20 according to some embodiments of the present disclosure. Fig. 11 is a diagram showing an example of a processing flow of the slave device 20 according to some embodiments of the present disclosure. Here, the processing of the slave device 20 will be described with reference to Fig. 11.

[0047] In the slave device 20, the receiving means 801 receives a read request from the master device (step S101). When the receiving means 801 receives the read request, the output means 802 outputs data at a timing according to the set identifier (step S102).

[0048] The above describes the slave device 20 according to some embodiments of the present disclosure. This slave device 20 allows multiple slave devices with the same I2C address to exist in the system, and can transmit data at an appropriate timing even when a read request is received from the master device.

[0049] The order of the processes in each embodiment of the present disclosure may be changed as long as the processes are performed appropriately.

[0050] While the embodiments of the present disclosure have been described, the processing system 1, master device 10, slave devices 20a, 20a1, 20a2, 20a3, 20a4, 20a5, 20a6, 20a7, 20a8, 20a9, 20a10, 20a11, 20a12, 20a13, 20a14, 20a15, 20a16, 20a21, 20a22, 20a23, 20a24, and other control devices may have an internal computer system. The above-described processing steps are stored in the form of a program on a computer-readable recording medium, and the computer reads and executes this program to perform the above processing. Specific examples of computers are shown below.

[0051] 12 is a schematic block diagram showing the configuration of a computer according to at least one embodiment. As shown in FIG. 12, the computer 5 includes a CPU (Central Processing Unit) 6, a main memory 7, a storage 8, and an interface 9.

[0052] For example, the above-described processing system 1, master device 10, slave devices 20a, 20a1, 20a2, 20a3, 20a4, 20a5, 20a6, 20a7, 20a8, 20a9, 20a10, 20a11, 20a12, 20a13, 20a14, 20a15, 20a16, 20a21, 20a22, 20a23, and 20a24, and other control devices are each implemented in a computer 5. The operation of each of the above-described processing units is stored in the form of a program in storage 8. CPU 6 reads the program from storage 8, loads it into main memory 7, and executes the above-described processing in accordance with the program. CPU 6 also allocates storage areas in main memory 7 corresponding to each of the above-described storage units in accordance with the program.

[0053] Examples of storage 8 include a hard disk drive (HDD), a solid state drive (SSD), a magnetic disk, a magneto-optical disk, a compact disc read-only memory (CD-ROM), a digital versatile disc read-only memory (DVD-ROM), and a semiconductor memory. Storage 8 may be an internal medium directly connected to the bus of computer 5, or an external medium connected to computer 5 via interface 9 or a communication line. In addition, when this program is distributed to computer 5 via a communication line, computer 5 that receives the program may load the program into main memory 7 and execute the above-mentioned processing. In at least one embodiment, storage 8 is a non-transitory tangible storage medium.

[0054] The program may also implement some of the functions described above. Furthermore, the program may be a file that can implement the functions described above in combination with a program already recorded in the computer system, a so-called differential file (differential program).

[0055] Although several embodiments of the present disclosure have been described, these embodiments are merely examples and do not limit the scope of the disclosure. Various additions, omissions, substitutions, and modifications may be made to these embodiments without departing from the spirit of the disclosure.

[0056] Note that part or all of the above-described embodiments can be described as, but are not limited to, the following supplementary notes.

[0057] (Appendix 1) A slave device that communicates using an Inter-Integrated Circuit communication method, receiving means for receiving a read request from a master device; an output means for outputting data at a timing according to a set identifier when the receiving means receives the read request; a slave device comprising:

[0058] (Appendix 2) The identifier is set by a number, The output means outputting the data at a timing determined in ascending order of the number or at a timing determined in ascending order of the number; 1. A slave device as defined in Appendix 1.

[0059] (Appendix 3) One of the plurality of slave devices assigned the same address in the Inter-Integrated Circuit communication system, The output means When the receiving means receives the read request in the plurality of slave devices assigned the same address, the data is output at a timing according to the set identifier. A slave device as defined in Appendix 1 or Appendix 2.

[0060] (Appendix 4) One of the plurality of slave devices assigned the same address in the Inter-Integrated Circuit communication system, The output means When the receiving means receives the read request, the receiving means goes into a standby state while a slave device other than the receiving means itself among the plurality of slave devices is outputting data. 10. A slave device according to any one of claims 1 to 3.

[0061] (Appendix 5) a slave device according to any one of Supplementary Note 1 to Supplementary Note 4; a master device that transmits a read request to the slave device; A processing system comprising:

[0062] (Appendix 6) A processing method executed by a slave device that communicates using an Inter-Integrated Circuit communication method, receiving a read request from a master device; When the read request is received, outputting the data at a timing according to the set identifier; A processing method comprising:

[0063] (Appendix 7) The identifier is set by a number, outputting the data at a timing determined in ascending order of the numbers or at a timing determined in ascending order of the numbers; 6. The method of claim 5, further comprising:

[0064] (Appendix 8) A processing method executed by one of a plurality of slave devices assigned the same address in the Inter-Integrated Circuit communication system, When the read request is received, the plurality of slave devices assigned the same address output the data at a timing according to the set identifier; 10. The method of claim 6 or 7,

[0065] (Appendix 9) A processing method executed by one of a plurality of slave devices assigned the same address in the Inter-Integrated Circuit communication system, When the read request is received, the device enters a standby state while a slave device other than the device itself among the plurality of slave devices outputs data; 9. The processing method according to any one of appendices 6 to 8, including:

[0066] (Appendix 10) The slave device computer that communicates using the Inter-Integrated Circuit communication method receiving a read request from a master device; When the read request is received, the data is output at a timing according to the set identifier; A program that executes the following.

[0067] (Appendix 11) The identifier is set by a number, outputting the data at a timing determined in ascending order of the numbers or at a timing determined in ascending order of the numbers; 11. The program according to claim 10, which causes the computer to execute the above steps.

[0068] (Appendix 12) In the Inter-Integrated Circuit communication system, a computer of one of the slave devices assigned the same address is When the read request is received, the plurality of slave devices assigned the same address output the data at a timing according to the set identifier; 12. The program according to claim 10 or 11, which causes the program to execute the above.

[0069] (Appendix 13) In the Inter-Integrated Circuit communication system, a computer of one of the slave devices assigned the same address is When the read request is received, the device enters a standby state while a slave device other than the device itself among the plurality of slave devices outputs data; 13. The program according to any one of claims 10 to 12, [Explanation of symbols]

[0070] 1. Processing System 5. Computer 6 CPU 7. Main memory 8. Storage 9. Interface 10. Master device 20, 20a, 20a1, 20a2, 20a3, 20a4, 20a5, 20a6, 20a7, 20a8, 20a9, 20a10, 20a11, 20a12, 20a13, 20a14, 20a15, 20a16, 20a21, 20a22, 20a23, 20a24... Slave devices 180, 181...Pull-up resistor 801... Receiving means 802 Output means T1, T2, T3, T4, T5, T6, T7, T8...terminals

Claims

1. A slave device that communicates using an Inter-Integrated Circuit communication method, receiving means for receiving a read request from a master device; an output means for outputting data at a timing according to a set identifier when the receiving means receives the read request; a slave device comprising:

2. The identifier is set by a number, The output means outputting the data at a timing determined in ascending order of the number or at a timing determined in ascending order of the number; 2. The slave device of claim 1.

3. One of a plurality of slave devices assigned the same address in the Inter-Integrated Circuit communication system, The output means When the receiving means receives the read request in the plurality of slave devices assigned the same address, the data is output at a timing according to the set identifier.

2. The slave device of claim 1.

4. One of a plurality of slave devices assigned the same address in the Inter-Integrated Circuit communication system, The output means When the receiving means receives the read request, the receiving means goes into a standby state while a slave device other than the receiving means itself among the plurality of slave devices is outputting data.

2. The slave device of claim 1.

5. A slave device according to any one of claims 1 to 4; a master device that transmits a read request to the slave device; A processing system comprising:

6. A processing method executed by a slave device that communicates using an Inter-Integrated Circuit communication method, comprising: receiving a read request from a master device; When the read request is received, outputting the data at a timing according to the set identifier; A processing method comprising:

7. A slave device computer that communicates using the Inter-Integrated Circuit communication method, receiving a read request from a master device; When the read request is received, the data is output at a timing according to the set identifier; A program that executes the following.

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