Encoding and decoding using probabilistic shaping

Abstract

To achieve probabilistic constellation shaping in a transceiver.SOLUTION: An optical communication device 100 employing a probabilistic constellation shaping circuit (PCS) 116 includes a processing circuit 104 coupled to an optical transceiver 108. With respect to the transmission function, the processing circuitry 104 generates one or more drive signals that control the optical transceiver 108 to map transmission information bits to be transmitted into transmission symbols and to generate optical transmission symbols for transmission over one or more suitable optical communication media, such as one or more optical cables, free space, etc. For the receive function, the optical transceiver receives optical transmission symbols via one or more optical media and generates received electrical signals corresponding to the received optical transmission symbols, and the processing circuitry extracts received information bits encoded in the received electrical signals.SELECTED DRAWING: Figure 1

Description

[Technical Field]

[0001] [CROSS-REFERENCE TO RELATED APPLICATIONS] This application claims the benefit of U.S. Provisional Patent Application No. 63 / 671,986, filed July 16, 2024, entitled "Efficient Encoding and Decoding in Probabilistic Shaping," which is hereby incorporated by reference in its entirety for all purposes.

[0002] The present disclosure relates generally to communications technologies, and more particularly to probabilistic constellation shaping in a transceiver. [Background technology]

[0003] The approaches described in this Background section are approaches that could be pursued, but not necessarily approaches that have been previously conceived or pursued. Thus, unless otherwise indicated, it should not be assumed that any of the approaches described in this section qualify as prior art merely by virtue of their inclusion in this section.

[0004] Networking speed requirements are rapidly evolving. In the early days of the Internet, for example, popular applications were limited to email, message boards, and browsing primarily information and text-based web pages, and the amount of data transferred was typically relatively small compared to today. Now, Internet and mobile communication applications require significantly larger amounts of bandwidth (even compared to 15 years ago) to transfer photos, videos, music, and other multimedia files. For example, some popular social media networks generate approximately 4 petabytes (PB) of data per day. As another example, some artificial intelligence / machine learning (AI / ML) systems require extremely high bandwidth to train and operate AI / ML models.

[0005] As a result of ever-increasing demand for communication bandwidth, existing data communication systems must continually increase their capacity.

[0006] Optical communications is a critical technology field that is growing to address the increasing bandwidth demands of communications networks. The performance of optical communications systems is adversely affected by channel impairments caused by the characteristics of the transmitter, receiver, and / or the optical fiber between the transmitter and receiver. In addition, power usage in optical communications networks is also a factor in their performance; therefore, improving performance typically also involves reducing power consumption.

[0007] One technique for improving the performance of optical communication networks is called "constellation shaping." Constellation shaping involves modifying the distribution of transmit symbols to better match the characteristics of the communication channel. For example, in a channel with additive noise, constellation shaping typically involves transmitting high-energy transmit symbols less frequently than low-energy transmit symbols. More generally, constellation shaping typically involves transmitting some types of transmit symbols more frequently and other types of transmit symbols less frequently to optimize signal quality at the destination and / or to maintain the same signal quality while using less power consumption.

[0008] In probabilistic constellation shaping, a "distribution matcher" at the transmitter maps user data to constellation points such that the probability of a high-energy constellation point being transmitted is lower than the probability of a low-energy constellation point being transmitted. Summary of the Invention

[0009] In one embodiment, the transceiver comprises a processing circuit configured to: receive information to be transmitted over one or more optical communication media, the information including a first set of information bits; and generate a second set of transmit symbols corresponding to the first set of information bits. The generating the second set of transmit symbols comprises: performing probabilistic constellation shaping to set a quantity n1 of transmit symbols having maximum transmit symbol amplitude values ​​in the second set of transmit symbols, the performing probabilistic constellation shaping comprising performing a recursive procedure to map the first set of information bits to a third set of amplitude indicators corresponding to amplitudes of transmit symbols in the second set of transmit symbols, the third set of amplitude indicators including n1 amplitude indicators set to indicate the maximum transmit symbol amplitude value. The processing circuit is further configured to generate one or more drive signals based on the second set of transmit symbols. The transceiver also comprises an optical transceiver configured to generate one or more optical transmit signals based on the one or more drive signals.

[0010] In another embodiment, a method for transmitting information in a communication system comprises: receiving, in a processing circuit of a transceiver, information to be transmitted, the information including a first set of information bits; and generating, by the processing circuit, a second set of transmit symbols corresponding to the first set of information bits. Generating the second set of transmit symbols comprises: performing stochastic constellation shaping to set a quantity n1 of transmit symbols in the second set of transmit symbols having maximum transmit symbol amplitude values, wherein performing the stochastic constellation shaping comprises performing a recursive procedure to map the first set of information bits to a third set of amplitude indicators corresponding to amplitudes of transmit symbols in the second set of transmit symbols, the third set of amplitude indicators including n1 amplitude indicators set to indicate the maximum transmit symbol amplitude value. The method also comprises generating, by the transceiver, a transmit signal based on the second set of transmit symbols.

[0011] In yet another embodiment, a method for decoding a received signal in a communication system includes: receiving, in processing circuitry of a transceiver, a first set of amplitude indicators corresponding to amplitudes of transmitted symbols in a second set of transmitted symbols received by the transceiver, the first set of amplitude indicators having n amplitude indicators set to indicate a maximum transmitted symbol amplitude value, the second set of transmitted symbols being transmitted by a transmitter using stochastic constellation shaping; determining, by the processing circuitry, a plurality of indices corresponding to respective subsets of the first set of amplitude indicators, each subset of the first set of amplitude indicators indicating the maximum transmitted symbol amplitude value; the first set of amplitude indicators having n1' amplitude indicators set to indicate the maximum transmitted symbol amplitude value, each index designating a respective subset from a group of potential subsets having n1' indicators set to indicate the maximum transmitted symbol amplitude value; performing, by the processing circuitry, a recursive procedure using the multiple indices corresponding to respective subsets of the first set of amplitude indicators to generate a single index designating the first set of amplitude indicators from a group of potential sets of n1 indicators set to indicate the maximum transmitted symbol amplitude value; and mapping, by the processing circuitry, the single index to a third set of information bits.

[0012] In yet another embodiment, a transceiver comprises: an optical transceiver configured to receive one or more optical signals, the one or more optical signals being transmitted by a transmitter using probabilistic constellation shaping; and processing circuitry configured to: receive a first set of amplitude indicators corresponding to amplitudes of transmitted symbols in the one or more optical signals, the first set of amplitude indicators having n amplitude indicators set to indicate a maximum transmitted symbol amplitude value; determine a plurality of indices corresponding to respective subsets of the first set of amplitude indicators, each subset of the first set of amplitude indicators having n′ amplitude indicators set to indicate the maximum transmitted symbol amplitude value, each index designating a respective subset from among a group of potential subsets having n′ indicators set to indicate the maximum transmitted symbol amplitude value; perform a recursive procedure using the plurality of indices corresponding to respective subsets of the first set of amplitude indicators to generate a single index designating the first set of amplitude indicators from among a group of potential sets of amplitude indicators having n′ indicators set to indicate the maximum transmitted symbol amplitude value; and map the single index to a second set of information bits.

[0013] In another embodiment, an apparatus comprises a processing circuit configured to: receive information to be transmitted over one or more optical communication media, the information including a first set of information bits; and generate a second set of transmit symbols corresponding to the first set of information bits, wherein the generating the second set of transmit symbols includes: performing probabilistic constellation shaping to set a quantity n1 of transmit symbols in the second set of transmit symbols having maximum transmit symbol amplitude values, wherein performing the probabilistic constellation shaping includes performing a recursive procedure to map the first set of information bits to a third set of amplitude indicators corresponding to amplitudes of transmit symbols in the second set of transmit symbols, the third set of amplitude indicators including n1 amplitude indicators set to indicate the maximum transmit symbol amplitude value.

[0014] In yet another embodiment, a method for generating a communication signal comprises: receiving, in a processing circuit, information to be transmitted, the information including a first set of information bits; and generating, by the processing circuit, a second set of transmit symbols corresponding to the first set of information bits, wherein generating the second set of transmit symbols comprises: performing probabilistic constellation shaping to set a quantity n1 of transmit symbols in the second set of transmit symbols having maximum transmit symbol amplitude values, wherein performing the probabilistic constellation shaping comprises performing a recursive procedure to map the first set of information bits to a third set of amplitude indicators corresponding to amplitudes of transmit symbols in the second set of transmit symbols, the third set of amplitude indicators including n1 amplitude indicators set to indicate the maximum transmit symbol amplitude value.

[0015] In yet another embodiment, an apparatus comprises a processing circuit configured to: receive a first set of amplitude indicators corresponding to amplitudes of transmitted symbols received over the one or more communication media, the first set of amplitude indicators having n amplitude indicators set to indicate a maximum transmitted symbol amplitude value; determine a plurality of indices corresponding to respective subsets of the first set of amplitude indicators, each subset of the first set of amplitude indicators having n′ amplitude indicators set to indicate the maximum transmitted symbol amplitude value, each index designating a respective subset from among a group of potential subsets having n′ indicators set to indicate the maximum transmitted symbol amplitude value; perform a recursive procedure using the plurality of indices corresponding to respective subsets of the first set of amplitude indicators to generate a single index designating the first set of amplitude indicators from among a group of potential sets of amplitude indicators having n′ indicators set to indicate the maximum transmitted symbol amplitude value; and map the single index to a second set of information bits. [Brief explanation of the drawings]

[0016] [Figure 1] FIG. 1 is a simplified block diagram of an example optical communication device employing probabilistic constellation shaping, according to one embodiment.

[0017] [Figure 2] 2 is a simplified block diagram of an example distributed matcher encoder circuit of the optical communication device of FIG. 1 according to one embodiment.

[0018] [Figure 3] 2 is exemplary pseudocode for implementing a multiplication function associated with probabilistic constellation shaping employed by the optical communication device of FIG. 1 according to one embodiment.

[0019] [Figure 4] 3 is exemplary pseudocode for implementing the truncation function performed by the distributed matcher encoder circuit of FIG. 2 according to one embodiment.

[0020] [Figure 5A] FIG. 4 illustrates the number of sequences represented by the product A·B for different numbers of iterations of the multiplication function shown in FIG. 3 , according to one embodiment. [Figure 5B] FIG. 4 illustrates the number of sequences represented by the product A·B for different numbers of iterations of the multiplication function shown in FIG. 3 , according to one embodiment. [Figure 5C] FIG. 4 illustrates the number of sequences represented by the product A·B for different numbers of iterations of the multiplication function shown in FIG. 3 , according to one embodiment.

[0021] [Figure 6] 3 is exemplary pseudocode for implementing a non-isotropic distributed matcher encoding operation for implementing the truncation function performed by the distributed matcher encoder circuit of FIG. 2 according to one embodiment.

[0022] [Figure 7] 3 is exemplary pseudocode for implementing operations performed by the distributed matcher encoder circuit of FIG. 2 to determine the number of logical 1s in a sequence to be generated in the distributed matcher encoder circuit, according to one embodiment.

[0023] [Figure 8] 3 is exemplary pseudocode for implementing the division operation performed by the distributed matcher encoder circuit of FIG. 2 according to one embodiment.

[0024] [Figure 9] 3 is exemplary pseudocode for generating the contents of the memory of the distributed matcher encoder circuit of FIG. 2 according to one embodiment.

[0025] [Figure 10]3 is an exemplary pseudocode describing the operation of the distributed matcher encoder circuit of FIG. 2 according to one embodiment.

[0026] [Figure 11] 2 is a simplified block diagram of an example distributed matcher decoder circuit of the optical communication device of FIG. 1 according to one embodiment.

[0027] [Figure 12] 12 is exemplary pseudocode for implementing the multiplication function performed by the distributed matcher decoder circuit of FIG. 11 according to one embodiment.

[0028] [Figure 13] 12 is exemplary pseudocode describing the operation of the distributed matcher decoder circuit of FIG. 11 according to one embodiment.

[0029] [Figure 14] 12 is exemplary pseudocode for implementing the non-constant distributed matcher decoding operation performed by the distributed matcher decoder circuit of FIG. 11 according to one embodiment.

[0030] [Figure 15] FIG. 1 is a flow diagram of an example method for transmitting information in a communication system using probabilistic constellation shaping, according to one embodiment.

[0031] [Figure 16] 4 is a flow diagram of an example method for decoding a received signal in a communication system according to another embodiment. DETAILED DESCRIPTION OF THE INVENTION

[0032] Embodiments of improved techniques for implementing stochastic constellation shaping are described below. For example, according to one embodiment, a processing circuit in a transceiver performs stochastic constellation shaping to set a quantity n1 of transmit symbols having a particular transmit symbol amplitude value (e.g., the largest transmit amplitude value from a set of different transmit amplitudes) in a sequence of transmit symbols, where n1 is a suitable positive integer. Performing stochastic constellation shaping, according to one embodiment, includes performing a recursive isocratic matcher encoding procedure to map a sequence of information bits to a sequence of amplitude indicators corresponding to the amplitudes of the transmit symbols. For example, according to one embodiment, the quantity n1 is determined, and the recursive isocratic matcher encoding procedure uses n1 to successively generate a set of increasingly smaller sequences, each set of sequences indicating n1 transmit symbols having a particular transmit symbol amplitude value.

[0033] In one embodiment, performing stochastic constellation shaping includes, according to one embodiment, i) performing a non-constant distribution matcher encoding procedure using a set of information bits to determine a) a quantity n1 and b) an index that identifies a sequence of n1 transmit symbol amplitude indicators having amplitudes set to a particular transmit symbol amplitude value (e.g., a maximum transmit amplitude value); and ii) performing a constant distribution matcher encoding procedure using n1 and the index to map the index to a sequence of n1 transmit symbol amplitude indicators having amplitudes set to a particular transmit symbol amplitude value (e.g., a maximum transmit amplitude value).

[0034] According to another embodiment, in receiving a communication signal, a transceiver receives a set of transmit symbols having a quantity n1 of transmit symbols having a particular transmit symbol amplitude value (e.g., a maximum transmit amplitude value), the set of transmit symbols being transmitted by a transmitter performing stochastic constellation shaping. According to one embodiment, processing circuitry of the transceiver performs a recursive isocratic matcher decoding procedure to map a sequence of amplitude indicators corresponding to the amplitudes of the transmit symbols in the set received by the transceiver to a sequence of information bits. For example, according to one embodiment, the quantity n1 is determined, and the recursive isocratic matcher decoding procedure uses n1 to successively generate larger sets of sequences, each set of sequences indicating n1 transmit symbols having a particular transmit symbol amplitude value.

[0035] In one embodiment, processing a sequence of amplitude indicators corresponding to a received communication signal includes, according to one embodiment, i) performing a constant-constant matcher decoding procedure using n1 and the sequence of transmit symbol amplitude indicators to map the sequence of transmit symbol amplitude indicators to an index that identifies the sequence of transmit symbol amplitude indicators from among a set of possible sequences of transmit symbol amplitude indicators with n1 amplitudes set to a particular transmit symbol amplitude value (e.g., a maximum transmit amplitude value); and ii) performing a non-constant-constant matcher decoding procedure using the index and the quantity n1 to determine a set of information bits.

[0036] 1 is a simplified block diagram of an exemplary optical communication device 100 employing probabilistic constellation shaping, according to one embodiment. The optical communication device 100 includes a processing circuit 104 coupled to an optical transceiver 108. With respect to the transmit function, the processing circuit 104 generally generates one or more drive signals configured to control the optical transceiver 108 to map information bits to be transmitted ("transmit information bits") to transmit symbols and generate optical transmit symbols for transmission via one or more suitable optical communication media, such as one or more optical cables, free space, etc. With respect to the receive function, the optical transceiver 108 receives the optical transmit symbols via one or more optical media and generates electrical signals ("receive electrical signals") corresponding to the received optical transmit symbols. The processing circuit 104 generally extracts the information bits ("receive information bits") encoded in the receive electrical signals.

[0037] Processing circuitry 104 includes probabilistic constellation shaping (PCS) circuitry 116 configured to perform PCS processing procedures such as data framing, data encoding, data decoding, scrambling, descrambling, etc. For transmit functions, PCS circuitry 116 is configured to receive transmit information bits and generate frames of PCS-encoded transmit information bits. For receive functions, PCS circuitry 116 is configured to receive frames of PCS-encoded receive information bits and output decoded receive information bits.

[0038] The forward error correction (FEC) encoder 120 is configured to receive a frame of encoded transmit information bits and perform an FEC encoding procedure to generate an FEC codeword. The constellation mapping circuit 124 is configured to map the FEC codeword symbols to constellation points and generate a constellation point signal indicative of the constellation point. The digital-to-analog converter (DAC) 128 is configured to convert the digital signal indicative of the constellation point into an analog drive signal configured to control the optical transceiver 108 to generate optical transmit symbols for transmission.

[0039] The analog-to-digital converter (ADC) 140 is configured to convert the received electrical signal to a digital received signal. The constellation demapping circuit 144 is configured to detect constellation symbols based on the digital received signal and generate FEC code words corresponding to the detected constellation points. The FEC decoder 148 is configured to perform an FEC decoding procedure to decode the FEC code words and generate frames of PCS encoded data.

[0040] The PCS circuit 116 includes a distributed matcher encoder circuit 160 configured to perform a stochastic constellation shaping operation. For example, according to one embodiment, the distributed matcher encoder circuit 160 is configured to determine, for a sequence of transmit symbols to be transmitted by the transceiver 100, a quantity n1 of transmit symbols having a particular transmit symbol amplitude value (e.g., a maximum transmit amplitude value from a set of different transmit amplitudes), where n1 is a suitable positive integer. As described in more detail below, performing stochastic constellation shaping, according to one embodiment, includes performing a recursive isocratic distributed matcher encoding procedure to map a sequence of information bits to a sequence of amplitude indicators corresponding to the amplitudes of the transmit symbols. For example, according to one embodiment, the distributed matcher encoder circuit 160 determines, for the sequence of transmit symbols, the quantity n1, and then performs a recursive isocratic distributed matcher encoding procedure using n1 to successively generate a set of progressively smaller sequences, each set of sequences indicating n1 transmit symbols having a particular transmit symbol amplitude value.

[0041] PCS circuit 116 also includes a distributed matcher decoder circuit 164 that, according to one embodiment, is configured to perform a recursive isocratic distributed matcher decoding procedure to map a sequence of amplitude indicators corresponding to the amplitudes of transmitted symbols in a set received by transceiver 100 to a sequence of information bits. For example, according to one embodiment, distributed matcher decoder circuit 164 determines a quantity n1 for the set of transmitted symbols received by transceiver 100, and the recursive isocratic distributed matcher decoding procedure uses n1 to successively generate larger sets of sequences, each set of sequences indicating n1 transmitted symbols having a particular transmitted symbol amplitude value.

[0042] Figure 2 is a simplified block diagram of a distributed matcher encoder circuit 200 according to one embodiment. According to one embodiment, the distributed matcher encoder circuit 200 is included in the distributed matcher encoder circuit 160 of Figure 1, and Figure 2 will be described with reference to Figure 1 for ease of explanation. In other embodiments, the distributed matcher encoder circuit 160 has another suitable structure different from the distributed matcher encoder circuit 200. In addition, in other embodiments, the distributed matcher encoder circuit 200 is included in another suitable transceiver different from the transceiver 100 of Figure 1.

[0043] 2, vector X corresponds to a set of information bits to be transmitted by transceiver 100, and vector C corresponds to a set of transmit symbol amplitudes corresponding to a set of transmit symbols to be transmitted by transceiver 100. In the exemplary embodiment, vector X has a length of 116, and vector C has a length of 128. Thus, distributed matcher encoder circuit 200 maps the set of 116 information bits to a set of 128 amplitudes corresponding to a set of 128 transmit symbols. In other embodiments, vector X has another suitable length different from 116 and / or vector C has another suitable length different from 128.

[0044] The distributed matcher encoder circuit 200 is configured to operate in a transceiver configured to generate transmit symbols that can have one of two amplitudes, namely, a first transmit symbol amplitude and a second transmit symbol amplitude, where the second transmit symbol amplitude is greater than the first transmit symbol amplitude. With such a transceiver, the second transmit symbol amplitude corresponds to a maximum transmit symbol amplitude. To improve the performance of a communication system including the transceiver 100, it is useful to perform probabilistic constellation shaping to limit the amount of transmit symbols having the second transmit symbol amplitude that are transmitted by the transceiver.

[0045] Each element of vector C, in one embodiment, can have one of two logical values, e.g., logical 0 and logical 1, where logical 0 represents the first transmit symbol amplitude and logical 1 represents the second transmit symbol amplitude.

[0046] The distributed matcher encoder circuit 200 includes a first stage circuit 204 and a second stage circuit 208. The first stage circuit 204 (sometimes referred to as the “encoder non-constant composition stage 204” or “encoder NCC stage 204”) is configured to map a vector X to a vector C according to a mapping DM: C=DM(X) Equation 1 The mapping is bijective (i.e., every element in the set of possible values ​​of X maps to a unique element in the set of possible values ​​of C) and invertible, so that a vector C maps to an inverse mapping DM -1 can be mapped to a vector according to: X=DM -1 (C) Equation 2

[0047] As part of mapping vector X to vector C, first stage circuit 204 is configured to generate: i) a parameter n1 indicating the amount of logical ones in vector C; and ii) an index X' that identifies a corresponding value of C among a set of possible values ​​of C having n1 ones. In one embodiment, first stage circuit 204 is configured to perform mapping DM using a non-constant composition (NCC) distribution-matched encoding technique. Mapping DM is "non-constant" in that X is mapped to C such that the number of logical ones in C may vary depending on the value of X, i.e., the number of logical ones in C is not constant for different values ​​of X. The mapping performed by first stage circuit 204 is described in further detail below.

[0048] The index X' output by the first stage circuit 204 has a length of 128 bits in one embodiment. In other embodiments, the index X' has another suitable length different from 128 bits.

[0049] Second stage circuit 208 (sometimes referred to herein as “encoder core 208”), according to one embodiment, is configured to perform a recursive isocratic matcher encoding procedure to map index X′ to vector C using parameter n1. For example, according to one embodiment, second stage circuit 208 successively generates sets of progressively smaller indices X′ as part of the recursive isocratic matcher encoding procedure, with each set of indices X′ indicating respective subsets of C that together contain n1 logical 1s. The recursive isocratic matcher encoding procedure is “constant” in that for each sub-stage in the procedure, the number n1 of logical 1s in C remains constant.

[0050] The second stage circuit 208 includes multiple sub-stages. In the example of Figure 2, the second stage circuit 208 includes five sub-stages. In other embodiments, the second stage circuit 208 includes another suitable number of sub-stages other than five.

[0051] The first substage includes divider circuit 220-1-1, which is configured to receive input index X' and parameter n1, where n1 indicates the amount of logical ones in C and X' is an index that selects vector C from a subset of possible values ​​of C having n1 logical ones. Divider circuit 220-1-1 is configured to determine the number n1' of logical ones in each subset of vector C, where the sum of the numbers n1' is equal to n1. For example, in the example of FIG. 2, divider circuit 220-1-1 is configured to determine i) the number n1a of logical ones in the first half of vector C (e.g., bits 0-63 of C), and ii) the number n1b of logical ones in the second half of vector C (e.g., bits 64-127 of C), where n1 = n1a + n1b.

[0052] Additionally, divider circuit 220-1-1 is configured to calculate respective indices X'' that identify values ​​of a subset of C within a respective set of possible values ​​of the subset of C having a respective n1' number of ones. For example, in the example of FIG. 2, divider circuit 220-1-1 is configured to determine i) an index Xa that identifies a value of a first half of vector C (e.g., bits 0-63 of C) from a set of possible values ​​of the first half of vector C having a number n1a number of logical ones, and ii) an index Xb that identifies a value of a second half of vector C (e.g., bits 64-127 of C) from a set of possible values ​​of the second half of vector C having a number n1b number of logical ones.

[0053] The second sub-stage includes divider circuit 220-2-1 and divider circuit 220-2-2. Divider circuit 220-2-1 receives parameter n1a and index Xa from the first sub-stage and operates in a manner similar to divider circuit 220-1-1 to determine, based on parameter n1a and index Xa, the number n1' of logical ones in each subset of vector C[0:63], where the sum of numbers n1' is equal to n1a. For example, in the example of FIG. 2, divider circuit 220-2-1 is configured to determine i) the number n1a' of logical ones in the first half (e.g., bits 0 through 31) of vector C[0:63], and ii) the number n1b' of logical ones in the second half (e.g., bits 32 through 63) of vector C[0:63], where n1a = n1a' + n1b' (from the first sub-stage).

[0054] Additionally, divider circuit 220-2-1 is configured to calculate respective indices X'' that identify values ​​of a subset of vector C[0:63] from a respective set of possible values ​​of the subset of C[0:63] having n1' number of ones. For example, in the example of FIG. 2, divider circuit 220-2-1 is configured to determine i) an index Xa that identifies a value of the first half (e.g., bits 0-31) of vector C[0:63] from a set of possible values ​​of the first half of vector C[0:63] having n1' number of logical ones, and ii) an index Xb that identifies a value of the second half (e.g., bits 32-63) of vector C[0:63] from a set of possible values ​​of the second half of vector C[0:63] having n1' number of logical ones.

[0055] In addition, divider circuit 220-2-2 receives parameters n1b and index Xb from the first sub-stage and operates in a manner similar to divider circuit 220-1-1 to determine the number n1' of logical ones in each subset of vector C[64:127] based on parameters n1b and index Xb, where the sum of numbers n1' is equal to n1b. For example, in the example of FIG. 2, divider circuit 220-2-2 is configured to determine i) the number n1a' of logical ones in the first half (e.g., bits 64-95) of vector C[64:127], and ii) the number n1b' of logical ones in the second half (e.g., bits 96-127) of vector C[64:127], where n1b = n1a' + n1b' (from the first sub-stage).

[0056] Additionally, divider circuit 220-2-2 is configured to calculate respective indices X'' that identify values ​​of a subset of vector C[64:127] from a respective set of possible values ​​of the subset of vector C[64:127] having a respective number n1' of logical ones. For example, in the example of FIG. 2, divider circuit 220-2-2 is configured to determine i) an index Xa that identifies a value of the first half (e.g., bits 64-95) of vector C[64:127] from a set of possible values ​​of the first half of vector C[64:127] having a number n1a' of logical ones, and ii) an index Xb that identifies a value of the second half (e.g., bits 96-127) of vector C[64:127] from a set of possible values ​​of the second half of vector C[64:127] having a number n1b' of logical ones.

[0057] The third and fourth sub-stages also include divider circuits 220 that operate in a similar manner to generate respective parameters n1a and n1b and respective indices Xa and Xb based on the output of the divider circuit in the immediately preceding stage.

[0058] The fifth sub-stage includes multiple memories 240, each storing a set of possible values ​​for a respective subset of vector C. For example, memory 240-1 stores the set of possible values ​​for C[0:7]; memory 240-2 stores the set of possible values ​​for C[8:15]; memory 240-3 stores the set of possible values ​​for C[16:23]; and so on.

[0059] The value n1a / n1b output by the corresponding divider circuit 220-4 of the fourth sub-stage selects, in memory 240, a group of possible values ​​of the corresponding subset of vector C having n1a / n1b logical 1s. Additionally, the index Xa / Xb output by the corresponding divider circuit 220-4 of the fourth sub-stage selects a particular value from the group of possible values ​​having n1a / n1b logical 1s. Thus, each memory 240, in one embodiment, is configured to select a memory location using n1a / n1b and the index Xa / Xb output by the corresponding divider circuit 220-4 of the fourth sub-stage, and to output the value stored in the selected memory location.

[0060] 2, each divider circuit 220 receives an input sequence X' of length Nst and generates two smaller sequences Xa and Xb, each of which has a length of Nst / 2. Additionally, each divider circuit 220 receives a parameter n1 and generates two parameters n1a and n1b, where n1a + n1b = n1.

[0061] The distributed matcher encoder circuit 200 converts uniformly distributed information bits into an alphabet that follows a desired distribution.

number

number

number

[0062] As discussed above, distributed matcher encoder circuit 200 maps a K-bit input vector X to an N-bit output vector C according to mapping DM (see Equation 1). In the example of FIG. 2, K is 116 and N is 128. In other embodiments, distributed matcher encoder circuit 200 operates with suitable different values ​​of K and / or suitable different values ​​of N. As discussed above, mapping DM is invertible, which means that X can be mapped to the inverse mapping DM -1 This means that it can be recovered from C at the receiver by applying (see equation 2).

[0063] Mapping DM rate R DM is determined by:

number

[0064] As discussed above, each division circuit 220 receives an input sequence X' of length Nst, which corresponds to a vector C having n1 logical 1s, and generates two smaller sequences Xa and Xb corresponding to respective smaller vectors C having n1a and n1b logical 1s, each of which has a length of Nst / 2.

[0065] The number of possible different sequences of length n composed of i bits set to logic 1 and n i bits set to logic 0 received by each divider circuit 220 is denoted by S n,i The number of words of length 2n with i bit set to logic 1 is given by:

number

number

[0066] Exemplary pseudocode for implementing the function trunc(·) is shown in FIG. 4. In other embodiments, the function trunc(·) is implemented in another suitable manner. As discussed further below, the functions r and n iter is a design parameter that affects the performance of the distributed matcher encoder circuit 200.

[0067] Let T be the threshold defined by the total number of generated sequences C of length n in which at most i bits are set to logic 1. n,i For example,

number

[0068] Let the i-th bit of sequence C be C i Then, j≦i≦k, C i Subsequence by taking

number

number

[0069] Given values ​​A and B (see Equations 5 and 6), the total number of sequences represented by the product A·B (see FIG. 3) depends on the number of iterations used to approximate the product A·B as shown in the pseudocode of FIG. 3. FIGS. 5A-5C show the number of sequences represented by the product A·B for different numbers of iterations of the "multiplication" operation shown in FIG. 3. In FIGS. 5A-5C, the set of possible sequences that can be represented by the product A·B for an unlimited number of iterations is represented by rectangle 500. FIG. 5A shows a subset 504 of possible sequences represented after one iteration of the product A·B, where the set 508 of possible sequences is ignored. In FIG. 5A, the term "a1" is a truncation of A to one most significant bit (see FIGS. 3 and 4).

[0070] 5B shows the subset of possible sequences of the product A·B (the union of subsets 504 and 512) represented after two iterations, where set 516 of possible sequences is ignored. For the second iteration, input parameter A is set to parameter B (shown as A2 in FIG. 5B), and input parameter B is set to A-a1 (shown as B2 in FIG. 5B). The term "a2" is a truncation of A2 to one most significant bit (see FIGS. 3 and 4). Subset 512 corresponds to the subset of possible sequences of the product A2·B2, where subset 516 of possible sequences of the product A2·B2 is ignored.

[0071] Figure 5C shows the subset of possible sequences (the union of subsets 504, 512, and 520) represented after three iterations of the product A·B, where set 524 of possible sequences is ignored. For the third iteration, input parameter A is set to parameter B2 (shown as A3 in Figure 5C), and input parameter B is set to A2-a2 (shown as B3 in Figure 5C). The term "a3" is a truncation of A3 to one most significant bit (see Figures 3 and 4). Subset 520 corresponds to the subset of possible sequences of the product A3·B3, where subset 524 of possible sequences of the product A3·B3 is ignored.

[0072] In one embodiment, the parameters r and n iter The penalty for choosing a particular value for σ can be expressed by:

number

[0073] As a purely illustrative example, in the case of pulse amplitude modulation (PAM) with four levels ±3 and ±1 (PAM4), and if the bits of the generated sequence C are mapped to symbol amplitudes according to 0 → 1 and 1 → 3, the average power of the constellation can be expressed by:

number

number

number

number

[0074] On the other hand, for a constellation generated by a distributed matcher encoder with the highest possible rate for the same block length N, the probabilities p' of logic 0 and logic 1 at the output of an ideal distributed matcher encoder are respectively (0) and p' (1) can be expressed as:

number

number

number

[0075] As merely an illustrative example, r and n iter The value of is selected to provide a penalty (Equation 11) of less than 0.01 dB for the distributed matcher encoder circuit 200 at a block length of N=128. In such an embodiment, r=9 (the number of significant bits) and n iter is the length N of the words generated in each sub-stage of the encoder core 208 st Depends on, for example:

number

[0076] In other embodiments, the penalty (see Equation 11), r, and / or n iter Other suitable values ​​of may be used.

[0077] 2, encoder NCC stage 204 receives a set of information bits X and uses X to generate: i) a value n1 that specifies the amount of logical ones in an output sequence C; and ii) an index X' that identifies a particular sequence C from among the possible sequences C having n1 logical ones. In one embodiment, the set of all possible represented sequences C can be considered to be arranged in order from the lowest number of logical ones to the highest number of logical ones. According to one embodiment, value n1 that specifies the amount of logical ones in the output sequence C corresponds to an offset into the order of sequence C, and index X' is an index into the order of sequence C starting from offset n1.

[0078] Exemplary pseudo-code for implementing the encoder NCC stage 204 is shown in Figure 6. In other embodiments, the encoder NCC stage 204 is implemented in another suitable manner.

[0079] As discussed above, each divider circuit 220 receives an input sequence X' of length Nst and generates two smaller sequences Xa and Xb that indicate respective sequences of amplitude indicators having n1a and n1b logical 1's, respectively, each of which has a length of Nst / 2. In other words, each divider circuit 220 generates a tuple (n 1a ,n 1b ) and enter the value (X a ,X b ) to define two new subsequences based on the initial values ​​of n1 and X.

[0080] Exemplary pseudocode for implementing the function Select_n1b is shown in FIG. 7. The function Select_n1b determines the number of logical ones, n1b, in the smaller sequence Xb based on the input sequence X and the parameter n1, i.e., the number of logical ones in the input sequence X. The number of logical ones, n1a, in the smaller sequence Xa can then be determined as n1a=n1-n1b. In other embodiments, the divider circuit 220 may divide the tuple (n 1a ,n 1b ) is determined.

[0081] In Figure 7, U n,i,j has i logical ones, and

number

[0082] Exemplary pseudocode for implementing function Div is shown in Figure 8. Function Div determines two smaller sequences Xa and Xb as discussed above based on input sequence X', where each of the smaller sequences Xa and Xb has length Nst / 2, where Nst is the length of input sequence X'. Function Div is performed for a finite number of iterations. In other embodiments, division circuit 220 generates smaller sequences Xa and Xb in another suitable manner.

[0083] In the Div function in Figure 8, the behavior is:

number

[0084] As discussed above, in one embodiment, the fifth sub-stage of encoder core 208 includes memories 240 that store possible values ​​for each subset of vector C, each subset consisting of L bits. For example, L=8, and memory 240-1 stores the set of possible values ​​for C[0:7]; memory 240-2 stores the set of possible values ​​for C[8:15]; memory 240-3 stores the set of possible values ​​for C[16:23]; and so on. Thus, each memory 240 stores a sequence of L bits.

[0085] An example pseudocode for generating the sequences to be stored in memory 240 is shown in Figure 9. In Figure 9, E denotes the set of all pre-computed sequences, and E n ⊆E is the subset of sequences with exactly n bits set to logic 1.

number

[0086] As discussed above, encoder core 208 is implemented in a recursive manner. For example, in each of the sub-stages of encoder core 208: i) two sub-sequences (X a ,X b ) is generated from a sequence X' of length N; ii) a tuple (n 1a ,n 1b ) is generated from input n1. Exemplary pseudocode describing the operation of encoder core 208 is shown in Figure 10. In other embodiments, encoder core 208 operates in another suitable manner.

[0087] 2 , according to one embodiment, encoder NCC stage 204 is implemented using hardware circuitry configured to perform the operations of encoder NCC stage 204, such as those described herein. In another embodiment, encoder NCC stage 204 is additionally or alternatively implemented using a processor executing machine-readable instructions stored in a memory coupled to the processor. The machine-readable instructions, according to one embodiment, when executed by the processor, cause the processor to perform the operations of encoder NCC stage 204, such as those described herein.

[0088] Each divider circuit 220, according to one embodiment, is implemented using hardware circuitry configured to perform the operations of divider circuit 220, such as those described herein. In another embodiment, each divider circuit 220 is additionally or alternatively implemented using a processor executing machine-readable instructions stored in a memory coupled to the processor. The machine-readable instructions, according to one embodiment, when executed by the processor, cause the processor to perform the operations of divider circuit 220, such as those described herein.

[0089] Although the divider circuits 220 are shown as separate blocks in FIG. 2, in some embodiments, the same set of physical circuits is reused (e.g., using time division) to implement multiple sets of divider circuits 220 shown in FIG. 2.

[0090] Memory 240, in one embodiment, includes read-only memory (ROM). In other embodiments, memory 240 includes other suitable memory, such as solid-state memory, random access memory (RAM), etc.

[0091] Figure 11 is a simplified block diagram of a distributed matcher decoder circuit 1000 according to one embodiment. The distributed matcher decoder circuit 1000, according to one embodiment, is included in the distributed matcher decoder circuit 164 of Figure 1, and Figure 11 will be described with reference to Figure 1 for ease of explanation. The distributed matcher decoder circuit 164 may have another suitable structure different from the distributed matcher decoder circuit 1000 in another embodiment. Additionally, the distributed matcher decoder circuit 1000 may be included in another suitable transceiver different from the transceiver 100 of Figure 1 in another embodiment.

[0092] According to one embodiment, the distributed matcher decoder circuit 1000 is configured to perform a recursive isocratic distributed matcher decoding procedure to map a sequence of amplitude indicators corresponding to the amplitudes of transmit symbols in a set of transmit symbols received by the transceiver 100 to a sequence of information bits. For example, according to one embodiment, the distributed matcher decoder circuit 1000 determines a quantity n1 for the set of transmit symbols received by the transceiver 100, and the recursive isocratic distributed matcher decoding procedure uses n1 to successively generate larger sets of sequences, each set of sequences indicating n1 transmit symbols having a particular transmit symbol amplitude value.

[0093] 11 , vector C corresponds to a set of transmit symbol amplitudes corresponding to a set of transmit symbols received by transceiver 100, and vector X corresponds to a set of information bits decoded from vector C. In the exemplary embodiment, vector X has a length of 116, and vector C has a length of 128. Thus, distributed matcher decoder circuit 1000 maps a set of 128 amplitudes corresponding to a set of 128 transmit symbols to a set of 116 information bits. In other embodiments, vector X has another suitable length different from 116 and / or vector C has another suitable length different from 128.

[0094] The distributed matcher decoder circuit 1000 is configured to operate in a transceiver configured to receive transmit symbols that can have one of two amplitudes, namely, a first transmit symbol amplitude and a second transmit symbol amplitude, where the second transmit symbol amplitude is greater than the first transmit symbol amplitude. With such a transceiver, the second transmit symbol amplitude corresponds to the maximum transmit symbol amplitude.

[0095] Each element of vector C, in one embodiment, can have one of two logical values, e.g., logical 0 and logical 1, where logical 0 represents the first transmit symbol amplitude and logical 1 represents the second transmit symbol amplitude.

[0096] The distributed matcher decoder circuit 1000 includes a first stage circuit 1004 and a second stage circuit 1008. The first stage circuit 1004 (sometimes referred to herein as "decoder core 1004"), according to one embodiment, is configured to perform a recursive isocratic distributed matcher decoding procedure to map a vector C to an index X' using a parameter n1, where n1 is the amount of logical ones in the vector C. For example, according to one embodiment, the first stage circuit 1004 successively generates sets of increasingly larger indexes X' as part of the recursive isocratic distributed matcher decoding procedure, with each set of indexes X' indicating respective subsets of C that together contain n1 logical ones. The recursive isocratic distributed matcher decoding procedure is "constant" in that for each sub-stage in the procedure, the number n1 of logical ones in C remains constant.

[0097] The second stage circuit 1008 (sometimes referred to as the "decoder non-constant composition stage 1008" or "decoder NCC stage 1008") performs the inverse mapping DM -1 It is configured to map vector C to vector X according to (Equation 2).

[0098] Second stage circuit 1008 is configured to receive, as part of the mapping of vector C to vector X, i) a parameter n1 indicating the amount of logical ones in vector C, and ii) an index X' identifying the corresponding value of C among a set of possible values ​​of C having n1 ones. Parameter x1 and index X' are output by first stage circuit 1004, as described below.

[0099] In one embodiment, the second stage circuit 1008 uses an NCC distribution matching decoding technique to perform the inverse mapping DM -1 It is configured to perform the reverse mapping DM. -1 is "non-constant" in that the number of logic 1's in C varies, i.e., the number of logic 1's is not constant. The mapping performed by second stage circuit 1008 is described in more detail below.

[0100] The index X' output by the first stage circuit 1004 has a length of 128 bits in one embodiment. In other embodiments, the index X' has another suitable length different from 128 bits.

[0101] The first stage circuit 1004 includes multiple sub-stages. In the example of Figure 11, the second stage circuit 208 includes five sub-stages. In other embodiments, the first stage circuit 1004 includes another suitable number of sub-stages other than five.

[0102] The first substage includes multiple memories 1020, each storing a set of possible values ​​of vector X' corresponding to a respective subset of vector C. For example, memory 1020-1 stores the set of possible values ​​of vector X' for C[0:7]; memory 1020-2 stores the set of possible values ​​of vector X' for C[8:15]; memory 1020-3 stores the set of possible values ​​of vector X' for C[16:23]; and so on. Each memory 1020 also outputs a value n1a / n1b indicating the amount of logic 1's in its respective subset of vector C.

[0103] In one embodiment, each memory 1020 stores multiple tuples (Xa / Xb, n1a / n1b), and each subset of vector C is used as an index to select one of the tuples. In another embodiment, each memory 1020 stores multiple values ​​of Xa / Xb, and each subset of vector C is used as an index to select one of the values ​​of Xa / Xb; memory 1020 includes circuitry to determine and output the quantity n1a / n1b of logical 1s.

[0104] The first sub-stage includes multiplication circuits 1040-1-1 through 1040-1-8, each configured to receive an index Xa, an index Xb, a parameter n1a, and a parameter n1b from a respective pair of memories 1020. The multiplication circuit 1040-1 is configured to generate a larger index X' from Xa and Xb, the larger index corresponding to a larger subset of vector C. Additionally, the multiplication circuit 1040-1 is configured to generate a number n1 of logical 1's in the larger subset of vector C, where the sum of n1a and n1b is equal to n1. For example, in the example of FIG. 11, the multiplication circuit 1040-1-1 is configured to determine i) the number n1 of logical 1's in vector C[0:15], and ii) the index X' corresponding to vector C[0:15]. X' output by multiplication circuit 1040-1-1 identifies the value of vector C[0:15] among the set of possible values ​​of vector C[0:15] each having n1' logical ones.

[0105] The second sub-stage includes multiplication circuits 1040-2-1 through 1040-2-4, each configured to receive an index Xa, an index Xb, a parameter n1a, and a parameter n1b from a respective pair of multiplication circuits 1040-1 in the first stage. The multiplication circuit 1040-2 is configured to generate a larger index X' from Xa and Xb, the larger index corresponding to a larger subset of vector C. Additionally, the multiplication circuit 1040-2 is configured to generate a number n1 of logical 1s in the larger subset of vector C, where the sum of n1a and n1b is equal to n1. For example, in the example of FIG. 11, the multiplication circuit 1040-2-1 is configured to determine: i) the number n1 of logical 1s in vector C[0:31]; and ii) the index X' corresponding to vector C[0:31]. X' output by multiplication circuit 1040-2-1 identifies the value of vector C[0:31] among the set of possible values ​​of vector C[0:31] each having n1' logical ones.

[0106] The third and fourth sub-stages also include multiplier circuits 1040 that operate in a similar manner to generate respective parameters n1a and n1b and respective indices Xa and Xb based on the output of the respective multiplier circuit in the immediately preceding stage.

[0107] The fifth sub-stage includes multiplier circuit 1040-4-1 that operates in a similar manner to generate respective parameters n1a and n1b and respective indexes Xa and Xb based on the outputs of the respective multiplier circuits in the fourth sub-stage. Multiplier circuit 1040-4-1 generates index X' from Xa and Xb, where index X' has a length of 128 and corresponds to vector C[0:127]. In addition, multiplier circuit 1040-4-1 is configured to generate a number n1 of logical ones in a larger subset of vector C[0:127], where the sum of n1a and n1b equals n1, the number n1 of logical ones in vector C[0:127].

[0108] 11, each multiplier circuit 1040 receives input sequences Xa and Xb, each of length Nst, and produces a larger sequence X' having a length of 2*Nst. In addition, each multiplier circuit 1040 receives input sequences n1a and n1b, and outputs a parameter n1=n1a+n1b. In other words, each multiplier circuit 1040 produces a tuple (n 1a ,n 1b ) and vector (X a ,X b ), generate a larger vector X' and parameter n1.

[0109] Exemplary pseudocode for implementing function Mu1 is shown in FIG. 12. Function Mu1 generates a larger sequence X based on input sequences Xa and Xb arriving from the previous sub-stage, as discussed above, where each of smaller sequences Xa and Xb has length N / 2 and output sequence X has length N. Inputs to function Mu1 are Xa, Xb, A (which is the number of possible sequences of length N / 2 with n1a logical 1s), B (which is the number of possible sequences of length N / 2 with n1b logical 1s), and N. Function Mu1 is implemented recursively for a finite number of iterations. In other embodiments, multiplier circuit 1040 generates larger sequence X based on Xa and Xb in another suitable manner.

[0110] The decoder core 1004 divides the received vector C into subsets of L bits, and each subset of L bits is used to read an initial index stored in a respective memory 1020. Given a subsequence C' of length L with n bits set to 1, this index is

number

[0111] Exemplary pseudocode describing the operation of decoder core 1004 is shown in Figure 13. In other embodiments, decoder core 1004 operates in another suitable manner.

[0112] Decoder NCC stage 1008 receives from decoder core 1004 i) a parameter n1 indicating the amount of logical ones in vector C, and ii) an index X' that identifies the corresponding value of C among a set of possible values ​​of C having n1 ones. Exemplary pseudocode describing the operation of decoder NCC stage 1008 is shown in Figure 14. In other embodiments, decoder NCC stage 1008 operates in another suitable manner.

[0113] 11 , the decoder NCC stage 1008, according to one embodiment, is implemented using hardware circuitry configured to perform the operations of the decoder NCC stage 1008, such as those described herein. In another embodiment, the decoder NCC stage 1008 is additionally or alternatively implemented using a processor executing machine-readable instructions stored in a memory coupled to the processor. The machine-readable instructions, according to one embodiment, when executed by the processor, cause the processor to perform the operations of the decoder NCC stage 1008, such as those described herein.

[0114] Each multiplier circuit 1040, according to one embodiment, is implemented using hardware circuitry configured to perform the operations of the multiplier circuit 1040, such as those described herein. In another embodiment, each multiplier circuit 1040 is additionally or alternatively implemented using a processor executing machine-readable instructions stored in a memory coupled to the processor. The machine-readable instructions, according to one embodiment, when executed by the processor, cause the processor to perform the operations of the multiplier circuit 1040, such as those described herein.

[0115] Although the multiplication circuits 1040 are shown as separate blocks in FIG. 11, in some embodiments, the same set of physical circuits is reused (e.g., using time division) to implement multiple sets of multiplication circuits 1040 shown in FIG. 11.

[0116] The memory 1020, in one embodiment, includes ROM. In other embodiments, the memory 1020 includes other suitable memory, such as solid-state memory, RAM, etc.

[0117] 15 is a flow diagram of an example method 1400 for transmitting information in a communication system using probabilistic constellation shaping, according to one embodiment. Method 1400, according to some embodiments, is implemented by transceiver 100 of FIG. 1 and / or distributed matcher encoder circuit 200 of FIG. 2, and method 1400 is described with reference to FIG. 1 and FIG. 2 for ease of explanation. In other embodiments, method 1400 is implemented by another suitable transceiver different from transceiver 100 and / or by another suitable distributed matcher encoder circuit different from distributed matcher encoder circuit 200.

[0118] In block 1404, information to be transmitted is received by a processing circuit of the transceiver, the information including a first set of information bits. For example, the processing circuit 104 receives the information to be transmitted. As another example, the distributed matcher encoder circuit 160 / 200 receives the information to be transmitted.

[0119] In block 1408, the processing circuit generates a second set of transmit symbols corresponding to the first set of information bits. For example, the processing circuit 104 generates the second set of transmit symbols. As another example, the distributed matcher encoder circuit 160 / 200 generates the second set of transmit symbols. Generating the second set of transmit symbols in block 1408 includes performing stochastic constellation shaping to set a quantity n1 of transmit symbols having maximum transmit symbol amplitude values ​​in the second set of transmit symbols. Performing stochastic constellation shaping includes performing a recursive distributed matcher procedure to map the first set of information bits to a third set of amplitude indicators corresponding to amplitudes of the transmit symbols in the second set of transmit symbols, the third set of amplitude indicators including n1 amplitude indicators set to indicate the maximum transmit symbol amplitude values.

[0120] At block 1412, the transceiver generates a transmit signal based on the second set of transmit symbols. For example, the optical transceiver 108 generates the transmit signal.

[0121] In one embodiment, performing a recursive procedure to map the first set of information bits to a third set of amplitude indicators at block 1408 includes: performing a recursive isocratic distribution matcher procedure to map the first set of information bits to the third set of amplitude indicators.

[0122] In another embodiment, performing probabilistic constellation shaping in block 1408 further includes: determining, by the processing circuitry, a quantity n1 of transmit symbols having a maximum transmit symbol amplitude value based on the first set of information bits.

[0123] In another embodiment, determining the quantity n1 of transmit symbols having the maximum transmit symbol amplitude value includes: performing, by the processing circuitry, a non-constant distribution matcher procedure to determine the quantity n1 of transmit symbols having the maximum transmit symbol amplitude value based on the first set of information bits.

[0124] In another embodiment, performing probabilistic constellation shaping further includes: generating an index X′ based on the first set of information bits, where the index X′ designates a third set of amplitude indicators from among a group of potential third sets having n1 bits set to indicate maximum transmitted symbol amplitude values; and performing a recursive distribution matcher procedure includes performing a recursive isocratic distribution matcher procedure to map X′ to the third set of amplitude indicators using the value n1.

[0125] Figure 16 is a flow diagram of an example method 1500 for decoding a received signal in a communication system according to another embodiment. Method 1500, according to some embodiments, is implemented by transceiver 100 of Figure 1 and / or distributed matcher decoder circuit 1000 of Figure 11, and method 1500 will be described with reference to Figures 1 and 11 for ease of explanation. In other embodiments, method 1500 is implemented by another suitable transceiver different from transceiver 100 and / or by another suitable distributed matcher decoder circuit different from distributed matcher decoder circuit 1000.

[0126] In block 1504, the transceiver processing circuitry receives a first set of amplitude indicators corresponding to amplitudes of transmit symbols in a second set of transmit symbols received by the transceiver. According to one embodiment, the first set of amplitude indicators includes n amplitude indicators set to indicate maximum transmit symbol amplitude values, and the second set of transmit symbols was transmitted by the transmitter using stochastic constellation shaping. For example, the processing circuitry 104 receives the first set of amplitude indicators. As another example, the distributed matcher decoder circuitry 164 / 1000 receives the first set of amplitude indicators.

[0127] In block 1508, the processing circuit determines a plurality of indices corresponding to respective subsets of the first set of amplitude indicators, each subset of the first set of amplitude indicators having n1' amplitude indicators set to indicate a maximum transmitted symbol amplitude value, each index designating a respective subset from among a group of potential subsets having n1' indicators set to indicate a maximum transmitted symbol amplitude value. For example, the processing circuit 104 determines the plurality of indices. As another example, the distributed matcher decoder circuit 164 / 1000 determines the plurality of indices.

[0128] In block 1512, the processing circuit performs a recursive procedure using multiple indices corresponding to respective subsets of the first set of amplitude indicators to generate a single index that designates the first set of amplitude indicators from a group of potential sets of amplitude indicators having n indicators set to indicate the maximum transmitted symbol amplitude value. For example, the processing circuit 104 performs the recursive procedure. As another example, the distributed matcher decoder circuit 164 / 1000 performs the recursive procedure. As another example, the decoder core 1004 performs the recursive procedure.

[0129] In block 1516, the processing circuit maps the single index to the third set of information bits. For example, the processing circuit 104 maps the single index to the third set of information bits. As another example, the distributed matcher decoder circuit 164 / 1000 maps the single index to the third set of information bits. As another example, the decoder NCC stage 1008 maps the single index to the third set of information bits.

[0130] In another embodiment, performing the recursive procedure at block 1512 includes: successively generating larger indexes based on the multiple indexes to generate a single index.

[0131] In another embodiment, performing the recursive procedure at block 1512 includes performing a recursive isocratic distribution matcher procedure to generate a single index.

[0132] In another embodiment, mapping the single index to the third set of information bits in block 1516 includes mapping the single index to the third set of information bits using: n1.

[0133] In another embodiment, mapping the single index to the third set of information bits in block 1516 includes: performing, by the processing circuitry, a non-constant distribution matching operation using n1 to map the single index to the third set of information bits.

[0134] Embodiment 1: A transceiver including a processing circuit. The processing circuit is configured to: receive information to be transmitted over one or more optical communication media, the information including a first set of information bits; and generate a second set of transmit symbols corresponding to the first set of information bits. The generating the second set of transmit symbols includes: performing probabilistic constellation shaping to set a quantity n1 of transmit symbols having maximum transmit symbol amplitude values ​​in the second set of transmit symbols, wherein performing the probabilistic constellation shaping includes performing a recursive procedure to map the first set of information bits to a third set of amplitude indicators corresponding to amplitudes of transmit symbols in the second set of transmit symbols, the third set of amplitude indicators including n1 amplitude indicators set to indicate the maximum transmit symbol amplitude value. The processing circuit is further configured to generate one or more drive signals based on the second set of transmit symbols. The transceiver also includes an optical transceiver configured to generate one or more optical transmit signals based on the one or more drive signals.

[0135] Embodiment 2: The transceiver of embodiment 1, wherein the processing circuitry is further configured to, as part of performing the recursive procedure: perform a recursive isocratic matching procedure to map the first set of information bits to the third set of amplitude indicators.

[0136] Embodiment 3: The transceiver of any of embodiments 1 or 2, wherein the processing circuitry is further configured to: determine, based on the first set of information bits, a quantity n1 of the transmit symbols having the maximum transmit symbol amplitude value.

[0137] Embodiment 4: The transceiver of embodiment 3, wherein the processing circuitry is further configured to: perform a non-constant distribution matching procedure to determine, based on the first set of information bits, the quantity n1 of the transmit symbols having the maximum transmit symbol amplitude value.

[0138] Embodiment 5: The transceiver of embodiment 4, wherein the processing circuitry is further configured to: generate an index X' based on the first set of information bits, the index X' specifying the third set of amplitude indicators from among a group of potential third sets having n1 bits set to indicate the maximum transmitted symbol amplitude value; and perform a recursive isocratic distribution matching procedure to map X' to the third set of amplitude indicators using the value n1.

[0139] Embodiment 6: A method for transmitting information in a communication system, the method comprising: receiving, in a processing circuit of a transceiver, information to be transmitted, the information including a first set of information bits; and generating, by the processing circuit, a second set of transmit symbols corresponding to the first set of information bits. Generating the second set of transmit symbols comprises: performing probabilistic constellation shaping to set a quantity n1 of transmit symbols in the second set of transmit symbols having maximum transmit symbol amplitude values, the performing of probabilistic constellation shaping comprising performing a recursive procedure to map the first set of information bits to a third set of amplitude indicators corresponding to amplitudes of transmit symbols in the second set of transmit symbols, the third set of amplitude indicators including n1 amplitude indicators set to indicate the maximum transmit symbol amplitude value. The method also comprises generating, by the transceiver, a transmit signal based on the second set of transmit symbols.

[0140] Embodiment 7: The method for transmitting information of embodiment 6, wherein performing the recursive procedure to map the first set of information bits to the third set of amplitude indicators comprises: performing a recursive isocratic distribution matching procedure to map the first set of information bits to the third set of amplitude indicators.

[0141] Embodiment 8: The method for transmitting information of any of embodiments 6 or 7, wherein the step of performing probabilistic constellation shaping further includes: determining, by the processing circuit, a quantity n1 of the transmission symbols having the maximum transmission symbol amplitude value based on the first set of information bits.

[0142] Embodiment 9: The step of determining the quantity n1 of the transmission symbols having the maximum transmission symbol amplitude value comprises: 9. The method for transmitting information of embodiment 8, comprising performing, by the processing circuit, a non-constant distribution matching procedure to determine, based on the first set of information bits, a quantity n1 of the transmit symbols having the maximum transmit symbol amplitude value.

[0143] Embodiment 10: The method for transmitting information of embodiment 9, wherein performing probabilistic constellation shaping further comprises: generating an index X' based on the first set of information bits, the index X' designating the third set of amplitude indicators from among a group of potential third sets having n1 bits set to indicate the maximum transmitted symbol amplitude value; and performing the recursive distribution matching procedure comprises performing a recursive isocratic distribution matching procedure to map X' to the third set of amplitude indicators using the value n1.

[0144] Embodiment 11: A method for decoding a received signal in a communication system, the method comprising: receiving, in processing circuitry of a transceiver, a first set of amplitude indicators corresponding to amplitudes of transmitted symbols in a second set of transmitted symbols received by the transceiver, the first set of amplitude indicators having n amplitude indicators set to indicate maximum transmitted symbol amplitude values, the second set of transmitted symbols being transmitted by a transmitter using stochastic constellation shaping; and determining, by the processing circuitry, a plurality of indices corresponding to respective subsets of the first set of amplitude indicators, each subset of the first set of amplitude indicators set to indicate the maximum transmitted symbol amplitude value. a first set of n1′ amplitude indicators set to indicate the maximum transmitted symbol amplitude value, each index designating a respective subset from among a group of potential subsets having n1′ indicators set to indicate the maximum transmitted symbol amplitude value; performing, by the processing circuitry, a recursive procedure using the multiple indices corresponding to respective subsets of the first set of amplitude indicators to generate a single index designating the first set of amplitude indicators from among a group of potential sets of n1 indicators set to indicate the maximum transmitted symbol amplitude value; and mapping, by the processing circuitry, the single index to a third set of information bits.

[0145] Embodiment 12: The method for decoding the received signal of embodiment 11, wherein the step of performing the recursive procedure comprises: performing a recursive isocratic distribution matching procedure to generate the single index.

[0146] Embodiment 13: The method for decoding the received signal of either embodiment 11 or 12, wherein the step of mapping the single index to the third set of information bits includes a step of mapping the single index to the third set of information bits using: n1.

[0147]

[0033] Embodiment 14: The step of mapping the single index to the third set of information bits comprises: 14. The method for decoding the received signal of embodiment 13, further comprising performing, by the processing circuitry, a non-constant distribution matching operation using n1 to map the single index to the third set of information bits.

[0148] Embodiment 15: The method for decoding the received signal of embodiment 14, wherein the step of performing the recursive procedure includes the step of: successively generating larger indices based on the multiple indices to generate the single index.

[0149] Embodiment 16: An optical transceiver configured to receive one or more optical signals, the one or more optical signals being transmitted by a transmitter using probabilistic constellation shaping; and a processing circuit. The processing circuit is configured to: receive a first set of amplitude indicators corresponding to amplitudes of transmitted symbols in the one or more optical signals, the first set of amplitude indicators having n1 amplitude indicators set to indicate a maximum transmitted symbol amplitude value; determine a plurality of indices corresponding to respective subsets of the first set of amplitude indicators, each subset of the first set of amplitude indicators having n1′ amplitude indicators set to indicate the maximum transmitted symbol amplitude value, each index designating a respective subset from among a group of potential subsets having n1′ indicators set to indicate the maximum transmitted symbol amplitude value; perform a recursive procedure using the plurality of indices corresponding to respective subsets of the first set of amplitude indicators to generate a single index designating the first set of amplitude indicators from among a group of potential sets of amplitude indicators having n1 indicators set to indicate the maximum transmitted symbol amplitude value; and map the single index to a second set of information bits.

[0150] Embodiment 17: The transceiver of embodiment 16, wherein the processing circuitry is configured to: perform a recursive isocratic distribution matching procedure to generate the single index.

[0151] Embodiment 18: The transceiver of any of embodiments 16 or 17, wherein the processing circuitry is configured to map the single index to the third set of information bits using: n1.

[0152] Embodiment 19: The transceiver of embodiment 18, wherein the processing circuitry is configured to perform a non-constant distribution matching operation to map the single index to the third set of information bits using: n1.

[0153] Embodiment 20: The transceiver of embodiment 19, wherein the processing circuitry is configured to: successively generate larger indices based on the multiple indices to generate the single index.

[0154] Embodiment 21: An apparatus comprising a processing circuit configured to: receive information to be transmitted over one or more optical communication media, the information including a first set of information bits; and generate a second set of transmit symbols corresponding to the first set of information bits, wherein the generating the second set of transmit symbols includes: performing probabilistic constellation shaping to set a quantity n1 of transmit symbols in the second set of transmit symbols having maximum transmit symbol amplitude values, wherein performing the probabilistic constellation shaping includes performing a recursive procedure to map the first set of information bits to a third set of amplitude indicators corresponding to amplitudes of transmit symbols in the second set of transmit symbols, the third set of amplitude indicators including n1 amplitude indicators set to indicate the maximum transmit symbol amplitude value.

[0155] Embodiment 22: The apparatus of embodiment 21, wherein the processing circuitry is further configured to, as part of performing the recursive procedure: perform a recursive isocratic distribution matching procedure to map the first set of information bits to the third set of amplitude indicators.

[0156] Embodiment 23: The device of any of embodiments 21 or 22, wherein the processing circuitry is further configured to: determine, based on the first set of information bits, the quantity n1 of the transmitted symbols having the maximum transmitted symbol amplitude value.

[0157] Embodiment 24: The device of embodiment 23, wherein the processing circuit is further configured to: perform a non-constant distribution matching procedure to determine the quantity n1 of the transmitted symbols having the maximum transmitted symbol amplitude value based on the first set of information bits.

[0158] Embodiment 25: The apparatus of embodiment 24, wherein the processing circuitry is further configured to: generate an index X' based on the first set of information bits, the index X' specifying the third set of amplitude indicators from among a group of potential third sets having n1 bits set to indicate the maximum transmitted symbol amplitude value; and perform a recursive isocratic distribution matching procedure to map X' to the third set of amplitude indicators using the value n1.

[0159] Embodiment 26: A method for generating a communication signal, the method comprising: receiving, in a processing circuit, information to be transmitted, the information including a first set of information bits; and generating, by the processing circuit, a second set of transmit symbols corresponding to the first set of information bits, wherein generating the second set of transmit symbols comprises: performing probabilistic constellation shaping to set a quantity n1 of transmit symbols in the second set of transmit symbols having maximum transmit symbol amplitude values, wherein performing the probabilistic constellation shaping comprises performing a recursive procedure to map the first set of information bits to a third set of amplitude indicators corresponding to amplitudes of transmit symbols in the second set of transmit symbols, the third set of amplitude indicators including n1 amplitude indicators set to indicate the maximum transmit symbol amplitude value.

[0160] Embodiment 27: The method of embodiment 26, wherein performing the recursive procedure to map the first set of information bits to the third set of amplitude indicators includes: performing a recursive isocratic distribution matching procedure to map the first set of information bits to the third set of amplitude indicators.

[0161] Embodiment 28: The method of any of embodiments 26 or 27, wherein the step of performing probabilistic constellation shaping further includes: determining, by the processing circuit, a quantity n1 of the transmitted symbols having the maximum transmitted symbol amplitude value based on the first set of information bits.

[0162] Embodiment 29: The step of determining the quantity n1 of the transmitted symbols having the maximum transmitted symbol amplitude value comprises: 29. The method of embodiment 28, comprising performing, by the processing circuit, a non-constant distribution matching procedure to determine, based on the first set of information bits, the quantity n1 of the transmitted symbols having the maximum transmitted symbol amplitude value.

[0163] Embodiment 30: The method of embodiment 29, wherein performing probabilistic constellation shaping further comprises: generating an index X' based on the first set of information bits, the index X' designating the third set of amplitude indicators from among a group of potential third sets having n1 bits set to indicate the maximum transmitted symbol amplitude value; and performing the recursive distribution matching procedure comprises performing a recursive isocratic distribution matching procedure to map X' to the third set of amplitude indicators using the value n1.

[0164]

[0033] Embodiment 31: An apparatus comprising a processing circuit configured to: receive a first set of amplitude indicators corresponding to amplitudes of transmitted symbols received over the one or more communication media, the first set of amplitude indicators having n amplitude indicators set to indicate a maximum transmitted symbol amplitude value; determine a plurality of indices corresponding to respective subsets of the first set of amplitude indicators, each subset of the first set of amplitude indicators having n′ amplitude indicators set to indicate the maximum transmitted symbol amplitude value, each index designating a respective subset from among a group of potential subsets having n′ indicators set to indicate the maximum transmitted symbol amplitude value; perform a recursive procedure using the plurality of indices corresponding to respective subsets of the first set of amplitude indicators to generate a single index designating the first set of amplitude indicators from among a group of potential sets of amplitude indicators having n′ indicators set to indicate the maximum transmitted symbol amplitude value; and map the single index to a second set of information bits.

[0165] Embodiment 32: The apparatus of embodiment 31, wherein the processing circuitry is configured to: perform a recursive isocratic distribution matching procedure to generate the single index.

[0166] Embodiment 33: The apparatus of any of embodiments 31 or 32, wherein the processing circuitry is configured to map the single index to the third set of information bits using: n1.

[0167] Embodiment 34: The apparatus of embodiment 33, wherein the processing circuitry is configured to perform a non-constant distribution matching operation to map the single index to the third set of information bits using: n1.

[0168] Embodiment 35: The apparatus of embodiment 34, wherein the processing circuitry is configured to: successively generate larger indexes based on the plurality of indexes to generate the single index.

[0169] At least some of the various blocks, operations, and techniques described above may be implemented using hardware, a processor executing firmware instructions, a processor executing software instructions, or any combination thereof. When implemented using a processor executing software or firmware instructions, the software or firmware instructions may be stored in any computer-readable memory coupled to the processor, such as RAM, ROM, solid-state memory, etc. The software or firmware instructions may include machine-readable instructions that, when executed by one or more processors, cause the one or more processors to perform various operations.

[0170] When implemented in hardware, the hardware may comprise one or more of discrete components, integrated circuits, application-specific integrated circuits (ASICs), programmable logic devices (PLDs), etc.

[0171] Although the present invention has been described with reference to particular examples, these examples are intended to be merely illustrative and not limiting of the invention, and various modifications, additions and / or deletions may be made to the disclosed embodiments without departing from the scope of the invention.

Claims

1. A transceiver comprising:

1. A processing circuit comprising: receiving information to be transmitted over one or more optical communication media, the information including a first set of information bits; generating a second set of transmit symbols corresponding to the first set of information bits; and wherein the generating of the second set of transmit symbols comprises: performing probabilistic constellation shaping to set a quantity n1 of transmit symbols having maximum transmit symbol amplitude values ​​in the second set of transmit symbols, wherein performing the probabilistic constellation shaping includes performing a recursive procedure to map the first set of information bits to a third set of amplitude indicators corresponding to amplitudes of transmit symbols in the second set of transmit symbols, the third set of amplitude indicators including n1 amplitude indicators set to indicate the maximum transmit symbol amplitude value; The processing circuitry is further configured to generate one or more drive signals based on the second set of transmit symbols; and an optical transceiver configured to generate one or more optical transmit signals based on the one or more drive signals; A transceiver comprising:

2. As part of executing the recursive procedure, the processing circuitry:

2. The transceiver of claim 1, further configured to perform a recursive isocratic matching procedure to map the first set of information bits to the third set of amplitude indicators.

3. The processing circuitry: The transceiver of claim 1 or 2, further configured to determine a quantity n1 of the transmit symbols having the maximum transmit symbol amplitude value based on the first set of information bits.

4. The processing circuitry:

4. The transceiver of claim 3, further configured to perform a non-constant distribution matching procedure to determine, based on the first set of information bits, a quantity n1 of the transmit symbols having the maximum transmit symbol amplitude value.

5. The processing circuitry: generating an index X′ based on the first set of information bits, the index X′ specifying the third set of amplitude indicators from among a group of potential third sets having n1 bits set to indicate the maximum transmitted symbol amplitude value; and performing a recursive isocratic distribution matching procedure to map X′ to the third set of amplitude indicators using said value n1; The transceiver of claim 4 , further configured to:

6. 1. A method for transmitting information in a communication system, the method comprising: receiving, in a processing circuit of a transceiver, information to be transmitted, said information including a first set of information bits; generating, by the processing circuitry, a second set of transmit symbols corresponding to the first set of information bits, the generating step comprising: performing probabilistic constellation shaping to set a quantity n1 of transmit symbols having maximum transmit symbol amplitude values ​​in the second set of transmit symbols, the performing of the probabilistic constellation shaping including performing a recursive procedure to map the first set of information bits to a third set of amplitude indicators corresponding to amplitudes of transmit symbols in the second set of transmit symbols, the third set of amplitude indicators including n1 amplitude indicators set to indicate the maximum transmit symbol amplitude value; and generating, by the transceiver, a transmit signal based on the second set of transmit symbols; 1. A method for transmitting information, comprising:

7. Executing the recursive procedure to map the first set of information bits to the third set of amplitude indicators comprises:

7. The method for transmitting information of claim 6, including performing a recursive isocratic distribution matching procedure to map the first set of information bits to the third set of amplitude indicators.

8. The steps for performing probabilistic constellation shaping are:

8. The method for transmitting information according to claim 6 or 7, further comprising a step of determining, by the processing circuitry, a quantity n1 of the transmission symbols having the maximum transmission symbol amplitude value based on the first set of information bits.

9. The step of determining the quantity n1 of the transmitted symbols having the maximum transmitted symbol amplitude value comprises:

9. The method for transmitting information as recited in claim 8, further comprising: performing, by the processing circuitry, a non-constant distribution matching procedure to determine, based on the first set of information bits, the quantity n1 of the transmit symbols having the maximum transmit symbol amplitude value.

10. The steps for performing probabilistic constellation shaping are: generating an index X′ based on the first set of information bits, the index X′ designating the third set of amplitude indicators from among a group of potential third sets having n1 bits set to indicate the maximum transmitted symbol amplitude value; 10. The method for transmitting information of claim 9, wherein performing the recursive procedure includes performing a recursive isocratic distribution matching procedure using the value n1 to map X′ to the third set of amplitude indicators.

11. 1. A method for decoding a received signal in a communication system, the method comprising: receiving, in a processing circuit of a transceiver, a first set of amplitude indicators corresponding to amplitudes of transmit symbols in a second set of transmit symbols received by the transceiver, the first set of amplitude indicators having n1 amplitude indicators set to indicate maximum transmit symbol amplitude values, the second set of transmit symbols being transmitted by the transmitter using probabilistic constellation shaping; determining, by the processing circuitry, a plurality of indices corresponding to respective subsets of the first set of amplitude indicators, each subset of the first set of amplitude indicators having n amplitude indicators set to indicate the maximum transmitted symbol amplitude value, each index designating a respective subset from among a group of potential subsets having n indicators set to indicate the maximum transmitted symbol amplitude value; performing, by the processing circuitry, a recursive procedure using the plurality of indices corresponding to respective subsets of the first set of amplitude indicators to generate a single index designating the first set of amplitude indicators from among a group of potential sets of amplitude indicators having n1 indicators set to indicate the maximum transmitted symbol amplitude value; and mapping, by the processing circuitry, the single index to a third set of information bits.

1. A method for decoding a received signal, comprising:

12. The step of performing the recursive procedure comprises:

12. The method for decoding the received signal of claim 11, comprising performing a recursive isocratic distribution matching procedure to generate the single index.

13. Mapping the single index to the third set of information bits comprises:

13. A method for decoding the received signal as claimed in claim 11 or 12, comprising mapping the single index to the third set of information bits using n1.

14. Mapping the single index to the third set of information bits comprises:

14. The method for decoding the received signal of claim 13, further comprising performing, by the processing circuitry, a non-constant distribution matching operation using n1 to map the single index to the third set of information bits.

15. The steps of performing the recursive procedure include:

15. The method for decoding the received signal of claim 14, comprising generating successively larger indices based on the plurality of indices to generate the single index.

16. A transceiver comprising: an optical transceiver configured to receive one or more optical signals, the one or more optical signals being transmitted by a transmitter using probabilistic constellation shaping; and 1. A processing circuit comprising: receiving a first set of amplitude indicators corresponding to amplitudes of transmitted symbols in the one or more optical signals, the first set of amplitude indicators having n1 amplitude indicators set to indicate maximum transmitted symbol amplitude values; determining a plurality of indices corresponding to respective subsets of the first set of amplitude indicators, each subset of the first set of amplitude indicators having n amplitude indicators set to indicate the maximum transmitted symbol amplitude value, each index specifying a respective subset from among a group of potential subsets having n indicators set to indicate the maximum transmitted symbol amplitude value; performing a recursive procedure using the plurality of indices corresponding to respective subsets of the first set of amplitude indicators to generate a single index that designates the first set of amplitude indicators from among a group of potential sets of amplitude indicators having n indicators set to indicate the maximum transmitted symbol amplitude value; and mapping the single index to a second set of information bits; a processing circuit configured to perform A transceiver comprising:

17. The processing circuitry:

17. The transceiver of claim 16, configured to perform a recursive isocratic distribution matching procedure to generate the single index.

18. The processing circuitry:

18. The transceiver of claim 16 or 17, configured to map the single index to the third set of information bits using n1.

19. The processing circuitry:

20. The transceiver of claim 18, configured to perform a non-isotropic distribution matching operation to map the single index to the third set of information bits using n1.

20. The processing circuitry:

20. The transceiver of claim 19, configured to generate successively larger indexes based on the multiple indexes to generate the single index.

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