Display device and driving method thereof

Abstract

To provide a display device capable of reproducing a high-quality image, and a method for driving the same.SOLUTION: The display device includes a backlight unit having a light emitting element, a plurality of pixels, a gate line drive circuit, a signal line drive circuit, and a control substrate. The plurality of pixels are arranged so that light from the light-emitting element enters the pixels, and are arranged in a matrix having a plurality of rows and a plurality of columns. The source line driver circuit and the signal line driver circuit are electrically connected to the plurality of pixels. The control substrate is electrically connected to the backlight unit, the gate line drive circuit, and the signal line drive circuit. The plurality of rows include a plurality of row groups having the same number of rows and sequentially arranged in the column direction. The control substrate is configured to supply, to the gate line drive circuit and the signal line drive circuit, a control signal for performing precharge by simultaneously supplying the same potential to all of the plurality of pixels in the first frame period.SELECTED DRAWING: Figure 6

Description

[Technical Field]

[0001] One embodiment of the present invention relates to a display device and a driving method thereof. [Background technology]

[0002] Liquid crystal display devices are used in a variety of electronic devices, including smartphones, mobile phones, tablets, televisions, computers, and signage. Therefore, various methods for driving liquid crystal display devices have been proposed depending on their size and application. For example, a blanking drive method, in which the backlight is turned on for only a portion of each frame period, and an overlap drive method, in which multiple pixels are driven in an overlapping manner, have been proposed (see Patent Documents 1 and 2). By adopting such drive methods, it is possible to prevent degradation of image quality due to flicker and brightness deviation. [Prior art documents] [Patent documents]

[0003] [Patent Document 1] Japanese Patent Application Laid-Open No. 2024-51618 [Patent Document 2] Japanese Patent Publication No. 2020-24412 Summary of the Invention [Problem to be solved by the invention]

[0004] An object of one embodiment of the present invention is to provide a display device having a novel structure and a driving method thereof, or to provide a display device capable of reproducing high-quality images and a driving method thereof. [Means for solving the problem]

[0005] One embodiment of the present invention is a method for driving a display device. The display device includes a backlight having light-emitting elements and a plurality of pixels arranged to receive light from the light-emitting elements. The plurality of pixels are arranged in a matrix having a plurality of rows and a plurality of columns. The plurality of rows are composed of a plurality of row groups, each having the same number of rows and arranged in order in the column direction. The driving method includes precharging the plurality of pixels by simultaneously supplying the same potential to all of the plurality of pixels during a first frame period, and, after the precharging is completed, supplying a video signal to the pixels in each of the plurality of row groups sequentially by supplying a video signal to each of the plurality of row groups.

[0006] One embodiment of the present invention is a display device. The display device includes a backlight unit having light-emitting elements, a plurality of pixels, a gate line driving circuit, a signal line driving circuit, and a control substrate. The plurality of pixels are arranged in a matrix having a plurality of rows and a plurality of columns so that light from the light-emitting elements is incident thereon. The gate line driving circuit and the signal line driving circuit are electrically connected to the plurality of pixels. The control substrate is electrically connected to the backlight unit, the gate line driving circuit, and the signal line driving circuit. The plurality of rows are composed of a plurality of row groups, each having the same number of rows and arranged sequentially in the column direction. The control substrate is configured to supply control signals to the gate line driving circuit and the signal line driving circuit to execute precharging by simultaneously supplying the same potential to all of the plurality of pixels during a first frame period, and, after the precharging is completed, sequentially supplying a video signal to each row group, thereby supplying a video signal to the pixels in each of the plurality of row groups. [Brief explanation of the drawings]

[0007] [Figure 1] 1 is a schematic development view of a display device according to an embodiment of the present invention. [Figure 2] 1 is a schematic top view of a display device according to an embodiment of the present invention. [Figure 3] 1 is an equivalent circuit diagram of a pixel of a display device according to an embodiment of the present invention. [Figure 4] 1 is a schematic end view of a display device according to an embodiment of the present invention; [Figure 5] 1 is a schematic end view of a display device according to an embodiment of the present invention; [Figure 6] 4 is a timing chart showing a method for driving a display device according to an embodiment of the present invention. [Figure 7] 4 is a timing chart showing a method for driving a display device according to an embodiment of the present invention. [Figure 8] 10 is a timing chart showing a conventional method for driving a display device. [Figure 9] 4 is a timing chart showing a method for driving a display device according to an embodiment of the present invention. [Figure 10] 4 is a timing chart showing a method for driving a display device according to an embodiment of the present invention. DETAILED DESCRIPTION OF THE INVENTION

[0008] Hereinafter, various embodiments of the present invention will be described with reference to the drawings, etc. However, the present invention can be embodied in various forms without departing from the spirit of the present invention, and should not be construed as being limited to the description of the embodiments exemplified below.

[0009] In order to clarify the description, the drawings may show the width, thickness, shape, etc. of each part schematically compared to the actual embodiment, but these are merely examples and do not limit the interpretation of the present invention. In this specification and each drawing, elements having the same function as those described in the previous drawings may be given the same reference numerals, and duplicated explanations may be omitted. This reference numeral is used to collectively represent multiple identical or similar structures, and when these are individually represented, a hyphen and a natural number are added after the reference numeral.

[0010] In this specification and claims, when expressing an aspect of placing another structure on top of a certain structure, the term "on top" is used, unless otherwise specified, to include both a case in which another structure is placed directly on top of a certain structure so as to be in contact with the certain structure, and a case in which another structure is placed above a certain structure via yet another structure.

[0011] 1. Overall configuration of the display device 1 and 2 are a schematic exploded view and a top view, respectively, of a display device 100 according to an embodiment of the present invention. The display device 100 is a liquid crystal display device, and includes a backlight unit 110 and a display unit 120 arranged to overlap the backlight unit 110.

[0012] The backlight unit 110 is provided to supply light, including visible light, to the display unit 120 and includes one or more light-emitting elements 116. The light-emitting elements 116 shown in FIG. 1 are inorganic light-emitting diodes (LEDs), and multiple light-emitting elements 116 are arranged on a light source substrate 114. The light source substrate 114 is disposed within the housing 112. Although not shown, an optical unit, such as a light diffusion plate or a prism sheet, is provided on the light source substrate 114, thereby enabling the light from the light-emitting elements 116 to be uniformly irradiated onto the display unit 120. The configuration of the backlight unit 110 is not limited to the configuration described above. For example, the backlight unit 110 may be configured to use multiple LEDs arranged in one direction as the light-emitting elements 116 and supply light emitted from these LEDs to the side surfaces of the optical unit. Alternatively, cold-cathode tubes may be used as the light-emitting elements 116.

[0013] The display unit 120 has a substrate 122 and an opposing substrate (not shown in FIGS. 1 and 2) opposed to the substrate 122. Between the substrate 122 and the opposing substrate, various conductive films, semiconductor films, insulating films, etc. are arranged and patterned using a photolithography process. By appropriately combining these conductive films, semiconductor films, insulating films, etc., a plurality of pixels 140, each including a display element, are formed, as well as drive circuits (gate line drive circuit 124, signal line drive circuit 126) for driving the pixels 140, and a plurality of terminals 128 electrically connected to the drive circuits. Note that a portion of the drive circuit (for example, the entire or part of the signal line drive circuit 126) may be formed using an integrated circuit formed on a semiconductor substrate.

[0014] As shown in FIG. 2, a plurality of pixels 140 are arranged in a matrix having a plurality of rows and a plurality of columns. As will be described later, each pixel 140 is provided with a liquid crystal display element as a display element, and each pixel 140 functions as a minimum unit for providing color information. The minimum area including a plurality of pixels 140 and adjacent pixels 140 is the display area, and the area surrounding the display area and in which the drive circuit, terminals 128, etc. are provided is the frame area. Although not shown in FIGS. 1 and 2, a plurality of gate lines, a plurality of video signal lines, etc. are formed on the substrate 122 by a patterned conductive film. The plurality of gate lines extend in the row direction from the gate line drive circuit 124 to reach the display area, and the plurality of video signal lines extend in the column direction from the signal line drive circuit 126 to reach the display area.

[0015] The terminals 128 are arranged in parallel in the row direction. The display unit 120 further includes a flexible printed circuit board (hereinafter, FPC) 130 electrically connected to the terminals 128, and a control board 132 electrically connected to the FPC 130. The control board 132 is disposed below the light source board 114 and housed in the housing 112. The control board 132 is configured to control the gate line drive circuit 124 and the signal line drive circuit 126. Specifically, the control board 132 supplies various control signals and power for driving the display device 100 to the drive circuits via the FPC 130 and the terminals 128. The gate line drive circuit 124 generates gate signals based on the control signals supplied from the control board 132 and supplies the gate signals to the pixels 140 via the gate lines. Meanwhile, the signal line drive circuit 126 generates various signals, including video signals, based on the control signals supplied from the control board 132 and supplies the signals to the pixels 140 via the video signal lines. A plurality of pixels 140 are controlled by these signals, thereby reproducing an image in the display area.

[0016] 2. Pixels 3 shows an equivalent circuit diagram of multiple pixels 140. Shown here are some of the pixels 140 arranged in the first to 2mth rows and the first to nth columns. m and n are set independently of each other and are each selected from integers of 2 or greater, preferably integers of 4 or greater. There are no restrictions on the maximum values ​​of m and n; for example, the maximum value of m may be 2160 and the maximum value of n may be 7680. Hereinafter, k may be used as an integer arbitrarily selected from the integers 1 to m, and j may be used as an integer arbitrarily selected from the integers 1 to n.

[0017] Each pixel 140 is formed with a pixel circuit and a display element 160. The pixel circuit is connected to a corresponding gate line G k(1) or G k(2) , and one corresponding signal line S j The display element 160 is electrically connected to the common wiring COM together with the pixel circuit. k(1) or G k(2) is electrically connected to n pixel circuits arranged in the row direction, and one signal line Sj is electrically connected to 2m pixel circuits. A common wiring COM is electrically connected to the display elements 160 of all the pixels 140. There are no restrictions on the configuration of the pixel circuits. For example, as shown in FIG. 3, each pixel circuit can be configured with a switching transistor 144 and a capacitance element 142. In this case, the gate of the switching transistor 144 is connected to the gate line G k(1) or G k(2) and one terminal is electrically connected to the signal line S j , and the other terminal is electrically connected to one terminal of the capacitor 142 and the display element 160. The other terminal of the capacitor 142 is electrically connected to a capacitor line (not shown) to which a constant potential is supplied. The configuration of the pixel circuit is not limited to the configuration shown in FIG. 3, and each pixel circuit may further include one or more transistors and one or more capacitors.

[0018] The structure of the display element 160 is not limited. For example, the display element 160 may be a so-called TN (Twist Nematic) liquid crystal display element or a VA (Vertical Alignment) liquid crystal display element. A schematic end view of a display unit 120 including one pixel 140 in this case is shown in FIG. 4. Elements constituting the pixel circuit (e.g., a switching transistor 144) are provided directly on the substrate 122 or on an undercoat 134 of any desired configuration. In the example shown in FIG. 4, the switching transistor 144 is a top-gate transistor and includes a semiconductor film 146, a gate insulating film 148 covering the semiconductor film 146, a gate electrode 150 overlapping the semiconductor film 146 via the gate insulating film 148, an interlayer insulating film 152 covering the gate electrode 150, and a pair of terminals 154 and 156 electrically connected to the semiconductor film 146 via openings provided in the interlayer insulating film 152 and the gate insulating film 148. The structure of the switching transistor 144 is not limited to the above-described structure; a bottom-gate transistor may also be used as the switching transistor 144. Alternatively, the switching transistor 144 may be a transistor having a pair of gate electrodes sandwiching a channel from above and below.

[0019] A planarization film 136 that absorbs irregularities caused by the switching transistor 144 and the like to provide a flat surface is provided on the pixel circuit, and a display element 160 is disposed on this planarization film 136. The display element 160 has a pixel electrode 162 electrically connected to the terminal 156, a first alignment film 164 on the pixel electrode 162, a liquid crystal layer 166 on the first alignment film 164, a second alignment film 168 on the liquid crystal layer 166, and a common electrode 170 on the second alignment film 168. Meanwhile, on the counter substrate 138 (below the counter substrate 138 in FIG. 4 ), a color filter 174 overlapping the pixel electrode 162, a light-shielding film 176 provided so as to overlap the pixel circuit, an overcoat 178 provided so as to cover the color filter 174 and the light-shielding film 176, and the like may be provided.

[0020] Alternatively, the display element 160 may be an IPS (In-Plane-Switching) liquid crystal display element. In this case, as shown in Fig. 5, a common electrode 170 is disposed on the planarization film 136, and a pixel electrode 162 having a comb-like upper surface is provided so as to overlap the common electrode 170 via an inter-electrode insulating film 172. A first alignment film 164, a liquid crystal layer 166, and a second alignment film 168 are provided on the pixel electrode 162 and the common electrode 170.

[0021] 3. Display device driving method 3-1.Frame Period 6 shows a timing chart illustrating a method for driving the display device 100. In this diagram, the first gate line G 1(1) The gate line G in the 2mth row from 2m(2) The time for each frame period can be set arbitrarily, and can be selected from a range of, for example, 1 / 60 seconds to 1 / 240 seconds. In this driving method, each frame period is divided into a pre-charge period P pc , retention period P h , a write period P w , blanking period P b, and the light emitting period Pi progress in sequence. The control board 132 is configured to supply control signals to the gate line driving circuit 124 and the signal line driving circuit 126 and to control the light emitting element 116 so that the pixel 140 operates in accordance with these periods.

[0022] (1) Precharge period Precharge period P pc In this case, the same potential is simultaneously supplied to all the pixels 140 based on a control signal from the control board 132. More specifically, all the gate lines G 1(1) From G 2m(2) At this time, a potential (here, high) for turning on the switching transistor 144 is simultaneously applied to all the signal lines S1 to S n The same potential (precharge potential V Pc ) is applied to the pixel electrodes 162 of all the pixels 140. Pc The potential for turning on and off the switching transistor 144 depends on the polarity of the switching transistor 144. Therefore, depending on the polarity of the switching transistor 144, the potential for turning on and off the switching transistor 144 may be low and high, respectively. In the following, the explanation will be continued assuming that the potential for turning on and off the switching transistor 144 is high and low, respectively.

[0023] (2) Retention period Precharge period P pc When the retention period P h The retention period P h In this case, all the gate lines G 1(1) From G 2m(2) At the same time, a low potential is applied to the gate lines G 1(1) From G 2m(2) The potential of is maintained low for this period. h is.

[0024] (3) Writing period Retention period P h After the write period P w Then, a video signal is written to the pixel 140 based on a control signal from the control board 132. At this time, a pair of gate lines G k(1) , G k(2) In this embodiment, a gate grouping driving method is adopted in which two gate lines G adjacent to each other in the column direction are driven simultaneously. More specifically, a plurality of rows in which pixels 140 are arranged are divided into a plurality of row groups (i.e., m number of row groups), each of which includes the same number of rows. The plurality of row groups are sequentially arranged in the column direction. Here, each row group is composed of two rows. Therefore, as shown in FIG. 6, each row group includes two gate lines G adjacent to each other in the column direction. k(1) and G k(2) Specifically, the first row group includes two adjacent gate lines G 1(1) , G 1(2) The second row group includes two adjacent gate lines G 2(1) , G 2(2) In general, the k-th row group includes two gate lines G k(1) , G k(2) The kth row group and the (k+1)th row group (where k≠m) are adjacent to each other in the column direction. k(1) , G k(2) ) are driven simultaneously. Therefore, the total number of gate lines is a multiple of 2, that is, 2m.

[0025] Explaining this using the example shown in FIG. 6, first, two gate lines G connected to the pixels 140 included in the first row group 1(1) and G 1(2) For the write period P w A high potential is simultaneously supplied to all the gate lines of the first row group. At this time, the other gate lines are all maintained at a low potential. w In this case, the signal lines S1 to S nA video signal corresponding to the gradation of each pixel 140 is supplied to each pixel electrode 162. As a result, the video signal is written to the pixel electrodes 162 of the pixels 140 located in the first and second rows. Therefore, in each column, the same potential is written to the pixels 140 located in the first and second rows.

[0026] When the writing of the video signal to the pixels 140 included in the first row group is completed, the gate line G connected to the pixels 140 included in the first row group is turned off. 1(1) and G 1(2) A low potential is supplied to the pixels 140 in the second row group adjacent to the first row group in the column direction, and a write period P w That is, the gate line G 2(1) and G 2(2) A high potential is supplied to the signal lines S1 to S n A video signal corresponding to the gradation of each pixel 140 is supplied to the pixel electrodes 162 of the pixels 140 located in the third and fourth rows. As a result, the video signal is written to the pixel electrodes 162 of the pixels 140 located in the third and fourth rows. Therefore, in each column, the same potential is written to the pixels 140 located in the third and fourth rows. A similar operation is performed sequentially, and the writing of the video signal to the pixels 140 included in the m-th row group is completed.

[0027] (4) Blanking period When the writing of the video signals to all the pixels 140 is completed, a blanking period P b During this period, the potential of all gate lines is set to low based on a control signal from the control board 132. Specifically, after writing to all pixels 140 is completed (i.e., after writing to the pixels 140 included in the m-th row group is completed), the low potential is maintained on all gate lines for a certain period. Blanking period P b may be set to, for example, 10% or more and 50% or less of one frame period.

[0028] (5) Light-emitting period Blanking period Pb After the elapse of the period, the light emitting element 116 included in the backlight unit 110 is turned on based on a signal from the control board 132. The period during which the light emitting element 116 is turned on, that is, the light emitting period P i may be set to, for example, 5% to 50% of one frame period. As a result, light from the light emitting elements 116 passes through the pixels 140, and light of a gradation corresponding to the video signal is obtained from each pixel 140. The light is also colored by the color filters 174. As a result, the color and gradation of each pixel 140 are combined to form an image.

[0029] Light emission period P i After this period has elapsed, the light emitting elements 116 included in the backlight unit 110 are turned off based on a signal from the control board 132. This ends one frame period (first frame period) and the subsequent frame period (second frame period) begins. During the second frame period, the display device 100 is driven in the same manner as during the first frame period.

[0030] 3-2. Pixel behavior in each period The behavior of the pixel 140 in each period will be described in more detail with reference to Fig. 7. In Fig. 7, the common potential V com In addition, two gate lines G that drive the first row group 1(1) , G 1(2) , and the gate lines G 1(2) , and one gate line G that drives the pixels 140 in the second row group. 2(1) , as well as the potential changes of the pixel electrodes 162 of the pixels 140 in one column connected to these gate lines.

[0031] The display device 100 employs a so-called polarity inversion driving method. Therefore, between the frame periods before and after the frame period shown in FIG. j The potential Sig of the video signal supplied from the common potential V com In the following description, the potential of the video signal is set to a common potential Vcom Negative potential Sig based on - In the frame periods before and after this frame period, the common potential V com Positive potential Sig based on + The potential Sig + and potential Sig - The light emitting period P of the pixel electrode 162 is given i The potentials at these points are denoted as Pix(+) and Pix(-), respectively. Note that video signals of the same polarity are supplied to the pixels 140 located in the same column.

[0032] At the start of one frame period, the potential of the pixel electrode 162 is equal to the light emitting period P i The potential Pix(+) during the precharge period P pc When the precharge period P begins, a high potential is supplied to the gate lines connected to all the pixels 140, thereby opening the pixel circuits of all the pixels 140. pc Then, all signal lines are supplied with the same precharge potential V pc At this time, as shown in FIG. pc Common potential V com The polarity of the video signal potential Sig + , that is, the potential Sig of the video signal supplied to the pixel 140 during the frame period in which the precharge is performed. - The common potential V com Precharge potential V pc The magnitude of the common potential V com The pre-precharge is performed so that the potential is smaller than the potential of the video signal that gives the maximum gradation. For example, the pre-charge potential V pc may be set in the range of 20% to 80% of the video signal that gives the maximum gradation.

[0033] Precharge is completed and the retention period P h, a low potential is supplied to all gate lines, which closes the pixel circuits of all pixels 140. Therefore, in all pixels 140, the potential of the pixel electrode 162 becomes the precharge potential V pc (Also, due to a phenomenon called gate field-through, the precharge potential V pc The potential is maintained at a level lower than the holding potential P h By providing the holding period P, the alignment of the liquid crystal molecules contained in the liquid crystal layer 166 can be completed in all the pixels 140. h may be set appropriately within the range of 0% to 45% of the frame period.

[0034] Then, during the write period P w In this example, a video signal is written sequentially for each row group to the pixels 140 included in the first row group to the pixels 140 included in the m-th row group. 1(1) and G 1(2) At the same time, a high potential is supplied to the signal lines S1 to S2, thereby opening the pixel circuits of the pixels 140 included in the first row group. n In the example shown in FIG. - The video signal is written to the pixels 140 in one column. When writing to these pixels 140 is completed, the gate line G 1(1) and G 1(2) At the same time, a low potential is supplied to the pixel electrodes 162 and the pixel circuits connected to them are closed. However, due to a phenomenon called gate field-through, the potential of the pixel electrode 162 drops immediately after the pixel circuits are closed, and the potential Sig - changes to a lower value.

[0035] Then, writing is performed on the pixels 140 included in the second row group. That is, the two gate lines G connected to the pixels 140 included in the second row group 2(1) and G 2(2)At the same time, a high potential is supplied to the signal lines S1 to S2, thereby opening the pixel circuits of the pixels 140 included in the second row group. n As a result, the pixel electrodes 162 of the pixels 140 included in the second row group are supplied with a precharge potential V pc to potential Sig - When writing to these pixels 140 is completed, the gate line G 2(1) and G 2(2) At the same time, a low potential is supplied to the pixels 140 in the second row group, and the pixel circuits connected to these pixels are closed. Even at this time, the potential of the pixel electrode 162 drops immediately after the pixel circuits are closed due to gate field through, and the potential Pix(-) of the pixel electrode 162 of the pixel 140 in the second row group 2(1) is the potential Sig - changes to a lower value.

[0036] Here, during the write period P w In this example, the pixel circuits of the pixels 140 included in the first row group are in a closed state. In addition, a capacitance (C ssv ) exists. Therefore, the pixel 140 in the first row group adjacent to the pixel 140 in the second row group in the column direction, that is, the pixel 140 in the second row group adjacent to the pixel 140 in the first row group adjacent to the pixel 140 in the second row group adjacent to the pixel 140 in the column direction, that is, the pixel 140 in the second row group adjacent to the pixel 140 in the first row group adjacent to the pixel 140 in the second row 1(2) The pixels 140 connected to the second row group are capacitively coupled by the potential fluctuation of the pixel electrodes 162 of the pixels 140 included in the second row group, and as a result, the potential of the pixel electrodes 162 drops as shown by the dotted circle in FIG. 7. This capacitive coupling (C ssv Coupling) occurs when the same video signal is supplied to the gate line G 1(1) and G 1(2) The potential Pix(-) of the pixel electrode 162 of the pixel 140 connected to 1(1) and Pix(-) 1(2) This can cause a difference in gradation between these pixels. ssv Coupling occurs between adjacent row groups, so the gate lines G k(1) and G k(2)The potential Pix(-) of the pixel electrode 162 of the pixel 140 connected to k(1) and Pix(-) k(2) When such a difference in gray scale occurs, stripes appear in the row direction in the image, which can lead to a decrease in image quality.

[0037] However, in this driving method, the precharge period P pc is provided, the precharge period P pc Compared with the drive method without C ssv The influence of coupling can be significantly reduced. pc A timing chart showing a driving method without the precharge period P is shown in FIG. pc If the potential Pix(+) is not provided, the potential change occurring in the pixel electrode 162 in each pixel 140 due to the writing of a video signal is the difference between two potentials of different polarities, that is, the potential Pix(+) of the pixel electrode 162 in the previous frame period. k(1) or Pix(+) k(2) and the potential Sig of the video signal supplied during the frame period - Difference (Pix(+) k(1) -Sig - , or Pix(+) k(2) -Sig - In contrast, in this driving method, the potential change occurring in the pixel electrode 162 due to the writing of the video signal is the precharge potential V pc and the video signal potential Sig - Difference with (V pc -Sig - ) As mentioned above, the precharge potential V pc and the video signal potential Sig - Therefore, the polarity of the precharge period P pc By providing this, the potential change occurring in the pixel electrode 162 due to the writing of the video signal is reduced, and C ssvThe influence of coupling can be significantly reduced. As a result, the gray level difference between adjacent pixels 140 in the column direction in the same row group can also be significantly reduced, making it possible to provide high-quality images even when the gate grouping driving method is adopted. The gate grouping driving method is a driving method that can achieve both high resolution and responsiveness, and is suitable for, for example, head-mounted small display devices used for games and VR displays. Therefore, by applying the embodiments of the present invention, a high-definition, high-speed responsive display device that can provide high-quality images can be realized.

[0038] Furthermore, in the display device 100, after the writing of the video signals to all the pixels 140 is completed, a blanking period P b As a result, the liquid crystal molecules contained in the liquid crystal layer 166 are supplied with the potential Sig of the video signal. + or Sig - Furthermore, the control board 132 can secure a period necessary for the liquid crystal display 100 to take on an orientation state according to the blanking period P b After the lapse of time, the light emitting element 116 of the backlight unit 110 is turned on, and the lighting period P i After the writing period p has elapsed, the light emitting element 116 is turned off at the time of transition to the next frame period or before the transition. w In addition, the precharge period P pc and retention period P h , blanking period P b Therefore, in one frame period, the precharge potential V pc The light of the gradation determined by the potential Sig of the video signal is not emitted from the pixel 140. + or Sig - Light of a gradation determined by the state before transitioning to an orientation state according to the signal supplied from the control substrate 132 is also not emitted from the pixel 140. Therefore, in each frame period, all pixels 140 can emit light that accurately reflects the gradation determined by the signal supplied from the control substrate 132, preventing display defects.

[0039] 4. Variations The display device 100 and its driving method are not limited to the above-described examples. Modified examples of the display device 100 and its driving method will be described below.

[0040] 4-1. Variation 1 In the above example, each row group is composed of two rows, but the number of rows constituting each row group is arbitrary, and may be three as shown in FIG. 9. In this case, the total number of gate lines is a multiple of three (3m). w In each row group, a high potential is simultaneously applied to three consecutive gate lines in the column direction within the row group, and a video signal is written to the pixels within the row group. There is no restriction on the maximum number of rows that make up each row group, but it is preferably three or four.

[0041] 4-2. Variation 2 In the above example, the precharge potential V pc is the common potential V com and the common potential V com The polarity of the video signal potential Sig + or Sig - However, the precharge potential V pc For example, as shown in FIG. 10, the precharge potential V pc is the common potential V com Even in this case, the write period P w The potential change of the pixel electrode 162 in the frame period is smaller by the potential Pix(+) or Pix(-) of the pixel electrode 162 in the previous frame period. ssv The influence of coupling (potential fluctuations indicated by dotted circles in the figure) can be significantly reduced.

[0042] Although not shown, the precharge potential V pcFor example, the potential Sig of the video signal of the pixel 140 with the highest gray level in each frame period and the common potential V com The potential between pc and a precharge potential V pc The control board 132 may be configured to change the

[0043] The above-described embodiments of the present invention can be combined as appropriate as long as they are not mutually inconsistent. Furthermore, even if a person skilled in the art appropriately adds or deletes components or modifies designs, or adds or omits processes or modifies conditions based on the embodiments, such combinations are included within the scope of the present invention as long as they include the gist of the present invention.

[0044] Even if there are other effects and advantages different from those brought about by the aspects of each of the above-mentioned embodiments, those that are clear from the description in this specification or that can be easily predicted by a person skilled in the art are naturally understood to be brought about by the present invention. [Explanation of symbols]

[0045] 100: display device, 110: backlight unit, 112: housing, 114: light source substrate, 116: light emitting element, 120: display unit, 122: substrate, 124: gate line driving circuit, 126: signal line driving circuit, 128: terminal, 130: FPC, 132: control substrate, 134: undercoat, 136: planarization film, 138: opposing substrate, 140: pixel, 142: capacitance element, 144: switching transistor, 146: semiconductor film, 148: gate insulating film, 150: gate electrode, 152: interlayer insulating film, 154: terminal, 156: terminal, 160: display element, 162: pixel electrode, 164: first alignment film, 166: liquid crystal layer, 168: second alignment film, 170: common electrode, 172: interelectrode insulating film, 174: color filter, 176: light-shielding film, 178: overcoat

Claims

1. A method for driving a display device including a backlight unit having a light-emitting element and a plurality of pixels arranged to receive light from the light-emitting element, the plurality of pixels are arranged in a matrix having a plurality of rows and a plurality of columns, the plurality of rows are composed of a plurality of row groups each having the same number of rows and arranged in order in the column direction; In the driving method, in a first frame period, precharging the plurality of pixels by simultaneously supplying the same potential to all of the plurality of pixels; and a driving method including: after the precharging is completed, supplying a video signal to the pixels in each of the plurality of row groups by sequentially supplying a video signal to each of the row groups.

2. The driving method according to claim 1 , further comprising turning on the light-emitting element after supplying the video signal to all of the plurality of pixels.

3. 3. The driving method according to claim 2, further comprising turning off the light-emitting element before the precharge is performed in a second frame period following the first frame period.

4. 2. The driving method according to claim 1, wherein a period from when the supply of the video signal to all of the plurality of pixels is completed to when the light emitting element is turned on is 10% to 50% of the first frame period.

5. each of the plurality of pixels includes a pixel electrode, a common electrode, and a liquid crystal layer between the pixel electrode and the common electrode; The potential supplied in the precharge is supplied to the pixel electrode, The driving method according to claim 1 , wherein the potential is the same as a potential supplied to the common electrode.

6. each of the plurality of pixels includes a pixel electrode, a common electrode, and a liquid crystal layer between the pixel electrode and the common electrode; The potential supplied in the precharge is supplied to the pixel electrode, The driving method according to claim 1 , wherein the potential has the same polarity as the potential of the video signal with respect to the potential supplied to the common electrode.

7. each of the plurality of pixels includes a pixel electrode, a common electrode, and a liquid crystal layer between the pixel electrode and the common electrode; 2. The driving method according to claim 1, wherein the polarity of the potential of the video signal relative to the potential supplied to the common electrode differs between the first frame period and a second frame period subsequent to the first frame period.

8. The driving method according to claim 1 , wherein the number of rows in each of the plurality of row groups is equal to or greater than 2 and equal to or less than 4.

9. a backlight unit having a light-emitting element; a plurality of pixels arranged in a matrix having a plurality of rows and a plurality of columns, the pixels being arranged so as to receive light from the light-emitting elements; a gate line driving circuit and a signal line driving circuit electrically connected to the plurality of pixels; and a control board electrically connected to the backlight unit, the gate line driving circuit, and the signal line driving circuit; the plurality of rows are composed of a plurality of row groups each having the same number of rows and arranged in order in the column direction; The control board, in a first frame period, precharging the plurality of pixels by simultaneously supplying the same potential to all of the plurality of pixels; and a display device configured to supply a control signal to the gate line driving circuit and the signal line driving circuit to execute supplying of the video signal to the pixels in each of the plurality of row groups by sequentially supplying a video signal to each row group after the precharging is completed.

10. 10. The display device according to claim 9, wherein the control board is further configured to light up the light-emitting elements after supplying the video signal to all of the plurality of pixels during the first frame period.

11. The display device according to claim 10 , wherein the control board is further configured to turn off the light-emitting element before the precharge is performed in a second frame period following the first frame period.

12. 10. The display device according to claim 9, wherein a period from when the supply of the video signal to all of the plurality of pixels is completed to when the light emitting element is turned on is 10% to 50% of the first frame period.

13. each of the plurality of pixels includes a pixel electrode, a common electrode, and a liquid crystal layer between the pixel electrode and the common electrode; The potential supplied in the precharge is supplied to the pixel electrode, The display device according to claim 9 , wherein the potential is the same as the potential supplied to the common electrode.

14. each of the plurality of pixels includes a pixel electrode, a common electrode, and a liquid crystal layer between the pixel electrode and the common electrode; The potential supplied in the precharge is supplied to the pixel electrode, 10. The display device according to claim 9, wherein the potential has the same polarity as the potential of the video signal with respect to the potential supplied to the common electrode.

15. each of the plurality of pixels includes a pixel electrode, a common electrode, and a liquid crystal layer between the pixel electrode and the common electrode; 10. The display device according to claim 9, wherein the polarity of the potential of the video signal relative to the potential supplied to the common electrode differs between the first frame period and a second frame period subsequent to the first frame period.

16. The display device according to claim 9 , wherein the number of rows in each of the plurality of row groups is equal to or greater than 2 and equal to or less than 4.

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