Semiconductor device

Abstract

To provide a semiconductor device having improved electrical characteristics and reliability, and to provide a method of manufacturing the same.SOLUTION: A semiconductor device includes an upper conductive line, a first lower conductive line, a second lower conductive line, and a third lower conductive line arranged in a first direction, a lower active contact connected to one of the first, second, and third lower conductive lines, and a first tall cell, a second tall cell, a first small cell, and a second small cell arranged between the upper conductive line and the first, second, and third lower conductive lines, wherein each of the first tall cell and the second tall cell includes a tall pattern and a tall source / drain pattern connected to the tall pattern. Each of the first small cell and the second small cell includes a small pattern and a small source / drain pattern connected to the small pattern.SELECTED DRAWING: Figure 1B

Description

[Technical Field]

[0001] The present invention relates to semiconductor devices, and more particularly to semiconductor devices including fin patterns. [Background technology]

[0002] Semiconductor devices include integrated circuits configured with MOS (Metal Oxide Semiconductor) field effect transistors (FETs). As the size and design rules of semiconductor devices continue to shrink, the scale down of MOS field effect transistors is also accelerating. As the size of MOS field effect transistors shrinks, the operating characteristics of semiconductor devices deteriorate. Therefore, various methods are being researched to form semiconductor devices with better performance while overcoming technological limitations associated with the high integration of semiconductor devices. [Prior art documents] [Patent documents]

[0003] [Patent Document 1] U.S. Patent No. 11,256,844 Summary of the Invention [Problem to be solved by the invention]

[0004] The present invention has been made in view of the above-mentioned conventional techniques, and an object of the present invention is to provide a semiconductor device with improved electrical characteristics and reliability, and a method for manufacturing the same. [Means for solving the problem]

[0005] In order to achieve the above object, according to one aspect of the present invention, a semiconductor device includes an upper conductive line, a first lower conductive line, a second lower conductive line, and a third lower conductive line arranged in a first direction, a lower active contact connected to one of the first, second, and third lower conductive lines, and a first tall cell, a second tall cell, a first small cell, and a second small cell arranged between the upper conductive line and the first, second, and third lower conductive lines and arranged in the first direction, each of the first tall cell and the second tall cell including a tall pattern and a tall source / drain pattern connected to the tall pattern, each of the first small cell and the second small cell including a small pattern and a small source / drain pattern connected to the small pattern, a width of the tall pattern in the first direction being larger than a width of the small pattern in the first direction, and the lower active contact is connected to the tall source / drain pattern or the small source / drain pattern.

[0006] In order to achieve the above object, according to another aspect of the present invention, a semiconductor device includes an upper conductive line, a first lower conductive line, a second lower conductive line, and a third lower conductive line arranged in a first direction, and a first tall cell, a second tall cell, a first small cell, and a second small cell arranged between the upper conductive line and the first, second, and third lower conductive lines and arranged in the first direction, wherein the first lower conductive line overlaps the first tall cell and the second tall cell, the second lower conductive line overlaps the second tall cell and the first small cell, and the third lower conductive line overlaps the first small cell and the second small cell, a width of the first lower conductive line in the first direction is larger than a width of the second lower conductive line in the first direction, and the width of the second lower conductive line in the first direction is larger than a width of the third lower conductive line in the first direction.

[0007] In order to achieve the above object, a semiconductor device according to some embodiments of the present invention includes upper conductive lines extending in a first direction, gate electrodes extending in a second direction intersecting the first direction, first lower conductive lines, second lower conductive lines, and third lower conductive lines arranged in the second direction, first tall patterns, second tall patterns, third tall patterns, fourth tall patterns, first small patterns, second small patterns, third small patterns, and fourth small patterns arranged between the upper conductive lines and the first, second, and third lower conductive lines and arranged in the second direction, a first gate isolation layer, a second gate isolation layer, a third gate isolation layer, a fourth gate isolation layer, and a fifth gate isolation layer arranged in the second direction, a tall source / drain pattern connected to each of the first, second, third, and fourth tall patterns, and a gate electrode connected to each of the first, second, third, and fourth small patterns. the first and second tall patterns are disposed between the first and second gate isolation layers, the third and fourth tall patterns are disposed between the second and third gate isolation layers, the first and second small patterns are disposed between the third and fourth gate isolation layers, the third and fourth small patterns are disposed between the fourth and fifth gate isolation layers, the first lower conductive line overlaps the second gate isolation layer, the second tall pattern, and the third tall pattern, the second lower conductive line overlaps the third gate isolation layer, the fourth tall pattern, and the first small pattern, and the third lower conductive line overlaps the fourth gate isolation layer, the second small pattern, and the third small pattern. [Effects of the Invention]

[0008] The semiconductor device according to the present invention can increase the efficiency of power supply and improve the frequency characteristics of the transistor. [Brief explanation of the drawings]

[0009] [Figure 1A] FIG. 1 is a plan view of a semiconductor device according to some embodiments. [Figure 1B] FIG. 1B is an enlarged view of the Q1 region of FIG. 1A. [Figure 1C] FIG. 2 is a cross-sectional view taken along line AA' in FIG. 1B. [Figure 1D] FIG. 2 is a cross-sectional view taken along line BB' in FIG. 1B. [Figure 1E] FIG. 2 is a cross-sectional view taken along line CC' in FIG. 1B. [Figure 1F] FIG. 1C is a cross-sectional view taken along line DD' in FIG. 1B. [Figure 1G] FIG. 1C is a cross-sectional view taken along line EE' in FIG. 1B. [Figure 2] FIG. 1 is a plan view of a semiconductor device according to some embodiments. [Figure 3] 1 is a cross-sectional view of a semiconductor device according to some embodiments. DETAILED DESCRIPTION OF THE INVENTION

[0010] FIG. 1A is a plan view of a semiconductor device according to some embodiments. FIG. 1B is an enlarged view of region Q1 of FIG. 1A. FIG. 1C is a cross-sectional view taken along line A-A' of FIG. 1B. FIG. 1D is a cross-sectional view taken along line B-B' of FIG. 1B. FIG. 1E is a cross-sectional view taken along line C-C' of FIG. 1B. FIG. 1F is a cross-sectional view taken along line D-D' of FIG. 1B. FIG. 1G is a cross-sectional view taken along line E-E' of FIG. 1B.

[0011] 1A, the semiconductor device includes tall cells TC, small cells SC, tall merged cells TMC, and small merged cells SMC. Each of the tall cells TC, small cells SC, tall merged cells TMC, and small merged cells SMC constitutes a logic cell. In the present invention, a logic cell refers to a logic element (e.g., AND, OR, XOR, XNOR, inverter, etc.) that performs a specific function. A logic cell includes transistors for constituting the logic element.

[0012] Two adjacent tall cells TC form a double height cell (DHC). As an example, the tall cells TC include a first tall cell TC1 and a second tall cell TC2 adjacent to each other, and a third tall cell TC3 and a fourth tall cell TC4 adjacent to each other, where the first tall cell TC1 and the second tall cell TC2 form a double height cell, and the third tall cell TC3 and the fourth tall cell TC4 form a double height cell.

[0013] Two adjacent small cells SC form a double height cell (DHC). As an example, the small cells SC include a first small cell SC1 and a second small cell SC2, and a third small cell SC3 and a fourth small cell SC4 that are adjacent to each other, where the first small cell SC1 and the second small cell SC2 form a double height cell, and the third small cell SC3 and the fourth small cell SC4 form a double height cell.

[0014] The tall cells TC and the small cells SC are arranged in a first direction D1. Two tall cells TC and two small cells SC are arranged alternately in the first direction D1. As an example, a first tall cell TC1, a second tall cell TC2, a first small cell SC1, a second small cell SC2, a third tall cell TC3, a fourth tall cell TC4, a third small cell SC3, and a fourth small cell SC4 are arranged sequentially along the first direction D1.

[0015] The first tall cell TC1 and the first small cell SC1 are adjacent to the second tall cell TC2 in the first direction D1. In other words, the cells arranged closest to the second tall cell TC2 in the first direction D1 are the first tall cell TC1 and the first small cell SC1. The second tall cell TC2 and the second small cell SC2 are adjacent to the first small cell SC1 in the first direction D1.

[0016] The second toll cell TC2 and the first small cell SC1 are arranged between the second small cell SC2 and the first toll cell TC1. The second toll cell TC2 is arranged between the first toll cell TC1 and the first small cell SC1. The first small cell SC1 is arranged between the second toll cell TC2 and the second small cell SC2. The first and second small cells SC1 and SC2 are arranged between the second toll cell TC2 and the third toll cell TC3. The third and fourth toll cells TC3 and TC4 are arranged between the second small cell SC2 and the third small cell SC3.

[0017] The toll merge cells TMC are disposed between the toll cells TC spaced apart in the second direction D2. The toll merge cells TMC are adjacent to the toll cells TC in the second direction D2. The toll merge cells TMC include a first toll merge cell TMC1 adjacent to the first and second toll cells TC1 and TC2 in the second direction D2, and a second toll merge cell TMC2 adjacent to the third and fourth toll cells TC3 and TC4 in the second direction D2.

[0018] The small merge cells SMC are arranged between the small cells SC spaced apart in the second direction D2. The small merge cells SMC are adjacent to the small cells SC in the second direction D2. The small merge cells SMC include a first small merge cell SMC1 adjacent to the first and second small cells SC1 and SC2 in the second direction D2, and a second small merge cell SMC2 adjacent to the third and fourth small cells SC3 and SC4 in the second direction D2.

[0019] The width W1 of the tall cell TC in the first direction D1 is larger than the width W2 of the small cell SC in the first direction D1. The width W3 of the tall merge cell TMC in the first direction D1 is twice the width W1 of the tall cell TC in the first direction D1. The width W4 of the small merge cell SMC in the first direction D1 is twice the width W2 of the small cell SC in the first direction D1. The width W3 of the tall merge cell TMC in the first direction D1 is larger than the width W4 of the small merge cell SMC in the first direction D1.

[0020] 1B, 1C, 1D, 1E, 1F, and 1G, the semiconductor device includes a lower insulating film 102. The lower insulating film 102 includes an insulating material. In some embodiments, the lower insulating film 102 may be a multi-layer film including multiple insulating films.

[0021] The lower insulating film 102 has a plate shape extending along a plane defined by a first direction D1 and a second direction D2. The first direction D1 and the second direction D2 intersect with each other. For example, the first direction D1 and the second direction D2 are horizontal directions that are perpendicular to each other.

[0022] Lower conductive lines 104 are disposed within the lower insulating film 102. The lower conductive lines 104 extend in a second direction D2. The lower conductive lines 104 are spaced apart from each other in a first direction D1. The lower conductive lines 104 are power lines. A source voltage or a drain voltage is applied to the lower conductive lines 104. For example, a ground voltage or a power voltage is applied to the lower conductive lines 104. The lower conductive lines 104 include a conductive material.

[0023] A fin pattern FP is provided on the lower insulating layer 102. The fin pattern FP extends in a second direction D2. The fin patterns FP are spaced apart from each other in the first direction D1. The fin pattern FP includes an insulating material. For example, the fin pattern FP includes nitride.

[0024] In some embodiments, the fin pattern FP includes a semiconductor material, such as silicon. In some embodiments, a semiconductor substrate is provided on the lower insulating film 102, and the fin pattern FP is a portion of the semiconductor substrate that protrudes in a third direction D3. In this case, the fin patterns FP are connected to each other by the lower portion of the semiconductor substrate. The third direction D3 intersects with the first direction D1 and the second direction D2. For example, the third direction D3 is a vertical direction that is perpendicular to the first direction D1 and the second direction D2.

[0025] An isolation layer 101 is provided. The isolation layer 101 surrounds the fin pattern FP. The fin pattern FP is separated by the isolation layer 101. The isolation layer 101 includes an insulating material. For example, the isolation layer 101 includes an oxide. In some embodiments, the isolation layer 101 may be a multi-layer including multiple insulating layers.

[0026] The fin pattern FP overlapping the first tall cell TC1 in the third direction D3 and the fin pattern FP overlapping the first tall merge cell TMC1 in the third direction D3 are separated from each other. An isolation layer 101 is provided between the fin pattern FP overlapping the first tall cell TC1 in the third direction D3 and the fin pattern FP overlapping the first tall merge cell TMC1 in the third direction D3.

[0027] The fin pattern FP overlapping the first small cell SC1 in the third direction D3 and the fin pattern FP overlapping the first small merge cell SMC1 in the third direction D3 are separated from each other. An isolation layer 101 is provided between the fin pattern FP overlapping the first small cell SC1 in the third direction D3 and the fin pattern FP overlapping the first small merge cell SMC1 in the third direction D3.

[0028] A lower active contact LAC is provided. The lower active contact LAC is provided on the lower conductive line 104. The lower active contact LAC is electrically connected to the lower conductive line 104. A lower surface of the lower active contact LAC contacts an upper surface of the lower conductive line 104. The lower active contact LAC penetrates the fin pattern FP in a third direction D3. The lower active contact LAC includes a conductive material.

[0029] On the fin pattern FP and the element isolation film 101, tall cells TC, small cells SC, tall merge cells TMC, and small merge cells SMC are provided.

[0030] The tall cell TC includes a tall source / drain pattern TS. The small cell SC includes a small source / drain pattern SS. The tall merge cell TMC includes a tall merge source / drain pattern TMS and a tall source / drain pattern TS. The small merge cell SMC includes a small merge source / drain pattern SMS and a small source / drain pattern SS. The tall source / drain pattern TS, the small source / drain pattern SS, the tall merge source / drain pattern TMS, and the small merge source / drain pattern SMS are provided on the fin pattern FP. The tall source / drain pattern TS, the small source / drain pattern SS, the tall merge source / drain pattern TMS, and the small merge source / drain pattern SMS are epitaxial patterns formed by a selective epitaxial growth (SEG) process. The tall source / drain pattern TS, the small source / drain pattern SS, the tall merge source / drain pattern TMS, and the small merge source / drain pattern SMS include semiconductor materials. For example, the tall source / drain pattern TS, the small source / drain pattern SS, the tall merged source / drain pattern TMS, and the small merged source / drain pattern SMS include at least one of silicon (Si), silicon-germanium (SiGe), or germanium (Ge). The tall source / drain pattern TS, the small source / drain pattern SS, the tall merged source / drain pattern TMS, and the small merged source / drain pattern SMS are doped with impurities.

[0031] The fin pattern FP is disposed between the lower conductive line 104, and the tall source / drain pattern TS, the small source / drain pattern SS, the tall merge source / drain pattern TMS, and the small merge source / drain pattern SMS.

[0032] The tall cell TC includes a tall pattern TP. The small cell SC includes a small pattern SP. The tall merge cell TMC includes a tall merge pattern TMP and a tall pattern TP. The small merge cell SMC includes a small merge pattern SMP and a small pattern SP. The tall patterns TP overlap each other in the third direction D3. The small patterns SP overlap each other in the third direction D3. The tall merge patterns TMP overlap each other in the third direction D3. The small merge patterns SMP overlap each other in the third direction D3. The tall pattern TP, small pattern SP, tall merge pattern TMP, and small merge pattern SMP include semiconductor materials. As an example, the tall pattern TP, small pattern SP, tall merge pattern TMP, and small merge pattern SMP include silicon, silicon-germanium, or germanium.

[0033] The tall source / drain pattern TS is connected to the tall pattern TP. The small source / drain pattern SS is connected to the small pattern SP. The tall merge source / drain pattern TMS is connected to the tall merge pattern TMP. The small merge source / drain pattern SMS is connected to the small merge pattern SMP.

[0034] Each of the tall cell TC, small cell SC, tall merge cell TMC, and small merge cell SMC includes a gate electrode GE. The gate electrode GE intersects with the fin pattern FP. The gate electrode GE overlaps with the fin pattern FP in the third direction D3. The gate electrode GE extends in the first direction D1. The gate electrode GE overlaps with the tall pattern TP, small pattern SP, tall merge pattern TMP, or small merge pattern SMP in the third direction D3. The gate electrode GE, together with the tall pattern TP, small pattern SP, tall merge pattern TMP, or small merge pattern SMP, forms a three-dimensional field effect transistor (e.g., MBCFET or GAAFET).

[0035] A gate isolation layer IL is provided. The gate isolation layer IL extends in a second direction D2. The gate isolation layer IL is disposed between the gate electrodes GE. The gate isolation layer IL includes an insulating material. For example, the gate isolation layer IL includes a nitride.

[0036] Each of the tall cell TC, the small cell SC, the tall merge cell TMC, and the small merge cell SMC includes a gate insulating film GI. The gate insulating film GI is in contact with the gate electrode GE. The gate insulating film GI includes an insulating material. For example, the gate insulating film GI includes an oxide.

[0037] Each of the tall cell TC, the small cell SC, the tall merge cell TMC, and the small merge cell SMC includes a gate spacer GS. A pair of gate spacers GS is disposed on both sides of the gate electrode GE. The gate spacers GS extend in a first direction D1. The gate spacers GS include an insulating material.

[0038] Each of the tall cell TC, the small cell SC, the tall merge cell TMC, and the small merge cell SMC includes a gate capping pattern GP. The gate capping pattern GP is provided on the gate electrode GE. The gate capping pattern GP extends in a first direction D1. The gate capping pattern GP includes an insulating material.

[0039] A first interlayer insulating film 110 is provided. The first interlayer insulating film 110 is provided on the tall source / drain pattern TS, the small source / drain pattern SS, the tall merged source / drain pattern TMS, the small merged source / drain pattern SMS, and the gate spacer GS. A second interlayer insulating film 120 is provided on the first interlayer insulating film 110. The second interlayer insulating film 120 is provided on the first interlayer insulating film 110, the gate spacer GS, and the gate capping pattern GP. The first and second interlayer insulating films 110 and 120 include an insulating material. For example, the first and second interlayer insulating films 110 and 120 include an oxide.

[0040] An upper active contact UAC is provided and penetrates the first and second interlayer insulating layers 110 and 120. The upper active contact UAC includes a conductive material.

[0041] A gate contact GC is provided. The gate contact GC is electrically connected to the gate electrode GE. The gate contact GC penetrates the second interlayer insulating film 120 and the gate capping pattern GP. The gate contact GC includes a conductive material.

[0042] An upper insulating film 130 is provided on the second interlayer insulating film 120. The upper insulating film 130 includes an insulating material.

[0043] Upper conductive lines 131 are provided in the upper insulating film 130. The upper conductive lines 131 extend in the second direction D2. The upper conductive lines 131 are spaced apart from each other in the first direction D1. The upper conductive lines 131 include a conductive material.

[0044] The gate contact GC is electrically connected to the upper conductive line 131. An upper surface of the gate contact GC contacts a lower surface of the upper conductive line 131. The upper active contact UAC is electrically connected to the upper conductive line 131. An upper surface of the upper active contact UAC contacts a lower surface of the upper conductive line 131.

[0045] The tall cells TC, small cells SC, tall merge cells TMC, and small merge cells SMC are arranged between the upper conductive line 131 and the lower conductive line 104. The tall cells TC, small cells SC, tall merge cells TMC, and small merge cells SMC are arranged at a level lower than the upper conductive line 131 and at a level higher than the lower conductive line 104.

[0046] The lower conductive lines 104 include a first lower conductive line 104a, a second lower conductive line 104b, and a third lower conductive line 104c that are sequentially arranged in a first direction D1. The first tall cell TC1, the second tall cell TC2, the first small cell SC1, the second small cell SC2, the first tall merge cell TMC1, and the first small merge cell SMC1 are disposed between the first to third lower conductive lines 104a, 104b, and 104c and the upper conductive line 131.

[0047] The first lower conductive line 104a overlaps the first tall cell TC1, the second tall cell TC2, and the first tall merge cell TMC1 in the third direction D3. The second lower conductive line 104b overlaps the second tall cell TC2, the first small cell SC1, the first tall merge cell TMC1, and the first small merge cell SMC1 in the third direction D3. The third lower conductive line 104c overlaps the first small cell SC1, the second small cell SC2, and the first small merge cell SMC1 in the third direction D3.

[0048] The width W11 of the first lower conductive line 104a in the first direction D1 is larger than the width W12 of the second lower conductive line 104b in the first direction D1. The width W12 of the second lower conductive line 104b in the first direction D1 is larger than the width W13 of the third lower conductive line 104c in the first direction D1. The width W14 of the upper conductive line 131 in the first direction D1 is smaller than the width W11 of the first lower conductive line 104a in the first direction D1, the width W12 of the second lower conductive line 104b in the first direction D1, and the width W13 of the third lower conductive line 104c in the first direction D1.

[0049] The width of the upper conductive line 131 in the second direction D2 is smaller than the width of the lower conductive line 104 in the second direction D2.

[0050] The first lower conductive line 104a includes a first portion 104a1 overlapping the first Thor cell TC1 in the third direction D3 and a second portion 104a2 overlapping the second Thor cell TC2 in the third direction D3. A width W21 of the first portion 104a1 of the first lower conductive line 104a in the first direction D1 is equal to a width W22 of the second portion 104a2 of the first lower conductive line 104a in the first direction D1.

[0051] The second lower conductive line 104b includes a first portion 104b1 overlapping the second tall cell TC2 and the first tall merge cell TMC1 in the third direction D3, and a second portion 104b2 overlapping the first small cell SC1 and the first small merge cell SMC1 in the third direction D3. A width W23 of the first portion 104b1 of the second lower conductive line 104b in the first direction D1 is greater than a width W24 of the second portion 104b2 of the second lower conductive line 104b in the first direction D1.

[0052] The third lower conductive line 104c includes a first portion 104c1 overlapping the first small cell SC1 in the third direction D3 and a second portion 104c2 overlapping the second small cell SC2 in the third direction D3. A width W25 of the first portion 104c1 of the third lower conductive line 104c in the first direction D1 is the same as a width W26 of the second portion 104c2 of the third lower conductive line 104c in the first direction D1.

[0053] A width W21 in the first direction D1 of the first portion 104a1 of the first lower conductive line 104a, a width W22 in the first direction D1 of the second portion 104a2 of the first lower conductive line 104a, and a width W23 in the first direction D1 of the first portion 104b1 of the second lower conductive line 104b are larger than a width W24 in the first direction D1 of the second portion 104b2 of the second lower conductive line 104b, a width W25 in the first direction D1 of the first portion 104c1 of the third lower conductive line 104c, and a width W26 in the first direction D1 of the second portion 104c2 of the third lower conductive line 104c.

[0054] The first lower conductive line 104a includes a first sidewall 104a_S1 overlapping the first toll cell TC1 in the third direction D3 and a second sidewall 104a_S2 overlapping the second toll cell TC2 in the third direction D3. The first sidewall 104a_S1 and the second sidewall 104a_S2 of the first lower conductive line 104a extend in the second direction D2. The first sidewall 104a_S1 and the second sidewall 104a_S2 of the first lower conductive line 104a are opposite to each other.

[0055] The second lower conductive line 104b includes a first sidewall 104b_S1 overlapping the second tall cell TC2 in the third direction D3 and a second sidewall 104b_S2 overlapping the first small cell SC1 in the third direction D3. The first sidewall 104b_S1 and the second sidewall 104b_S2 of the second lower conductive line 104b extend in the second direction D2. The first sidewall 104b_S1 and the second sidewall 104b_S2 of the second lower conductive line 104b are opposite to each other.

[0056] The third lower conductive line 104c includes a first sidewall 104c_S1 overlapping the first small cell SC1 in the third direction D3 and a second sidewall 104c_S2 overlapping the second small cell SC2 in the third direction D3. The first sidewall 104c_S1 and the second sidewall 104c_S2 of the third lower conductive line 104c extend in the second direction D2. The first sidewall 104c_S1 and the second sidewall 104c_S2 of the third lower conductive line 104c are opposite to each other.

[0057] The gate isolation layer IL includes a first gate isolation layer IL1, a second gate isolation layer IL2, a third gate isolation layer IL3, a fourth gate isolation layer IL4, and a fifth gate isolation layer IL5, which are sequentially arranged in a first direction D1.

[0058] A first tall cell TC1 is arranged between the first gate isolation film IL1 and the second gate isolation film IL2. A second tall cell TC2 is arranged between the second gate isolation film IL2 and the third gate isolation film IL3. A first small cell SC1 is arranged between the third gate isolation film IL3 and the fourth gate isolation film IL4. A second small cell SC2 is arranged between the fourth gate isolation film IL4 and the fifth gate isolation film IL5. A first tall merge cell TMC1 is arranged between the first gate isolation film IL1 and the third gate isolation film IL3. A first small merge cell SMC1 is arranged between the third gate isolation film IL3 and the fifth gate isolation film IL5.

[0059] The distance in the first direction D1 between the first sidewall 104a_S1 of the first lower conductive line 104a and the second gate isolation layer IL2 is the same as the width W21 of the first portion 104a1 of the first lower conductive line 104a in the first direction D1. The distance in the first direction D1 between the second sidewall 104a_S2 of the first lower conductive line 104a and the second gate isolation layer IL2 is the same as the width W22 of the second portion 104a2 of the first lower conductive line 104a in the first direction D1.

[0060] The distance in the first direction D1 between the first sidewall 104b_S1 of the second lower conductive line 104b and the third gate isolation layer IL3 is the same as the width W23 of the first portion 104b1 of the second lower conductive line 104b in the first direction D1. The distance in the first direction D1 between the second sidewall 104b_S2 of the second lower conductive line 104b and the third gate isolation layer IL3 is the same as the width W24 of the second portion 104b2 of the second lower conductive line 104b in the first direction D1.

[0061] The distance in the first direction D1 between the first sidewall 104c_S1 of the third lower conductive line 104c and the fourth gate isolation layer IL4 is the same as the width W25 of the first portion 104c1 of the third lower conductive line 104c in the first direction D1. The distance in the first direction D1 between the second sidewall 104c_S2 of the third lower conductive line 104c and the fourth gate isolation layer IL4 is the same as the width W26 of the second portion 104c2 of the third lower conductive line 104c in the first direction D1.

[0062] The distance in the first direction D1 between the first sidewall 104a_S1 of the first lower conductive line 104a and the second gate isolation film IL2, the distance in the first direction D1 between the second sidewall 104a_S2 of the first lower conductive line 104a and the second gate isolation film IL2, and the distance in the first direction D1 between the first sidewall 104b_S1 of the second lower conductive line 104b and the third gate isolation film IL3 are greater than the distance in the first direction D1 between the second sidewall 104b_S2 of the second lower conductive line 104b and the third gate isolation film IL3, the distance in the first direction D1 between the first sidewall 104c_S1 of the third lower conductive line 104c and the fourth gate isolation film IL4, and the distance in the first direction D1 between the second sidewall 104c_S2 of the third lower conductive line 104c and the fourth gate isolation film IL4.

[0063] The first lower conductive line 104a overlaps the second gate isolation layer IL2 in the third direction D3, the second lower conductive line 104b overlaps the third gate isolation layer IL3 in the third direction D3, and the third lower conductive line 104c overlaps the fourth gate isolation layer IL4 in the third direction D3.

[0064] The first tall cell TC1 includes a first tall pattern TP1 and a second tall pattern TP2. The second tall cell TC2 includes a third tall pattern TP3 and a fourth tall pattern TP4. The first small cell SC1 includes a first small pattern SP1 and a second small pattern SP2. The second small cell SC2 includes a third small pattern SP3 and a fourth small pattern SP4. The first tall merge cell TMC1 includes a fifth tall pattern TP5, a sixth tall pattern TP6, and a first tall merge pattern TMP1. The first small merge cell SMC1 includes a fifth small pattern SP5, a sixth small pattern SP6, and a first small merge pattern SMP1.

[0065] The second tall pattern TP2 is a tall pattern TP adjacent to the second tall cell TC2 of the first tall cell TC1 in the first direction D1. The third tall pattern TP3 is a tall pattern TP adjacent to the first tall cell TC1 of the second tall cell TC2 in the first direction D1. The second small pattern SP2 is a small pattern SP adjacent to the second small cell SC2 of the first small cell SC1 in the first direction D1. The third small pattern SP3 is a small pattern SP adjacent to the first small cell SC1 of the second small cell SC2 in the first direction D1. The sixth tall pattern TP6 is a tall pattern TP adjacent to the first small cell SC1 or the first small merge cell SMC1 of the first tall merge cell TMC1 in the first direction D1. The fifth small pattern SP5 is a small pattern SP adjacent to the first tall merge cell TMC1 of the first small merge cell SMC1 in the first direction D1.

[0066] The first tall pattern TP1, the second tall pattern TP2, the third tall pattern TP3, the fourth tall pattern TP4, the first small pattern SP1, the second small pattern SP2, the third small pattern SP3, and the fourth small pattern SP4 are sequentially arranged in the first direction D1.

[0067] The fifth tall pattern TP5, the first tall merge pattern TMP1, the sixth tall pattern TP6, the first small pattern SP1, the second small pattern SP2, the third small pattern SP3, and the fourth small pattern SP4 are sequentially arranged in the first direction D1.

[0068] The fifth tall pattern TP5, the first tall merge pattern TMP1, the sixth tall pattern TP6, the fifth small pattern SP5, the first small merge pattern SMP1, and the sixth small pattern SP6 are sequentially arranged in the first direction D1.

[0069] The first tall merge pattern TMP1 is arranged between the fifth tall pattern TP5 and the sixth tall pattern TP6, and the first small merge pattern SMP1 is arranged between the fifth small pattern SP5 and the sixth small pattern SP6.

[0070] The second tall pattern TP2, the third tall pattern TP3, and the first tall merge pattern TMP1 overlap the first lower conductive line 104a in the third direction D3. The fourth tall pattern TP4, the sixth tall pattern TP6, the first small pattern SP1, and the fifth small pattern SP5 overlap the second lower conductive line 104b in the third direction D3. The second small pattern SP2, the third small pattern SP3, and the first small merge pattern SMP1 overlap the third lower conductive line 104c in the third direction D3.

[0071] The width of the tall pattern TP in the first direction D1 is larger than the width of the small pattern SP in the first direction D1. As an example, the width W31 of the fourth tall pattern TP4 in the first direction D1 is larger than the width W32 of the first small pattern SP1 in the first direction D1.

[0072] In some embodiments, the distance in the first direction D1 between the fourth tall pattern TP4 and the third gate isolation film IL3 is greater than the distance in the first direction D1 between the first small pattern SP1 and the third gate isolation film IL3.

[0073] The width of the tall merge pattern TMP in the first direction D1 is larger than the width of the small merge pattern SMP in the first direction D1. As an example, the width W33 of the first tall merge pattern TMP1 in the first direction D1 is larger than the width W34 of the first small merge pattern SMP1 in the first direction D1.

[0074] The width of the tall merge pattern TMP in the first direction D1 is more than twice the width of the tall pattern TP in the first direction D1. The width W33 of the first tall merge pattern TMP1 in the first direction D1 is more than twice the width W31 of the fourth tall pattern TP4 in the first direction D1.

[0075] The width of the small merge pattern SMP in the first direction D1 is more than twice the width of the small patterns SP in the first direction D1. The width W34 of the first small merge pattern SMP1 in the first direction D1 is more than twice the width W32 of the first small pattern SP1 in the first direction D1.

[0076] The widths of the tall patterns TP in the first direction D1 are the same. The widths of the small patterns SP in the first direction D1 are the same. The widths of the tall merge patterns TMP in the first direction D1 are the same. The widths of the small merge patterns SMP in the first direction D1 are the same.

[0077] The first and second tall patterns TP1 and TP2 are disposed between the first and second gate isolation films IL1 and IL2. The third and fourth tall patterns TP3 and TP4 are disposed between the second and third gate isolation films IL2 and IL3. The first and second small patterns SP1 and SP2 are disposed between the third and fourth gate isolation films IL3 and IL4. The third and fourth small patterns SP3 and SP4 are disposed between the fourth and fifth gate isolation films IL4 and IL5.

[0078] The fifth tall pattern TP5, the first tall merge pattern TMP1, and the sixth tall pattern TP6 are disposed between the first and third gate isolation films IL1 and IL3. The fifth small pattern SP5, the first small merge pattern SMP1, and the sixth small pattern SP6 are disposed between the third and fifth gate isolation films IL3 and IL5. The first tall merge pattern TMP1 is spaced apart from the second gate isolation film IL2 in the second direction D2. The first small merge pattern SMP1 is spaced apart from the fourth gate isolation film IL4 in the second direction D2.

[0079] The maximum width W41 of the tall source / drain pattern TS in the first direction D1 is larger than the maximum width W42 of the small source / drain pattern SS in the first direction D1. The maximum width W43 of the tall merge source / drain pattern TMS in the first direction D1 is larger than the maximum width W41 of the tall source / drain pattern TS in the first direction D1, the maximum width W42 of the small source / drain pattern SS in the first direction D1, and the maximum width W44 of the small merge source / drain pattern SMS in the first direction D1. The maximum width W44 of the small merge source / drain pattern SMS in the first direction D1 is larger than the maximum width W42 of the small source / drain pattern SS in the first direction D1.

[0080] The lower active contacts LAC include a first lower active contact LAC1 connected to the tall source / drain pattern TS, a second lower active contact LAC2 connected to the small source / drain pattern SS, a third lower active contact LAC3 connected to the tall merge source / drain pattern TMS, and a fourth lower active contact LAC4 connected to the small merge source / drain pattern SMS.

[0081] The first lower active contacts LAC1 include a first lower active contact LAC1 connected to the first lower conductive line 104a and a first lower active contact LAC1 connected to the second lower conductive line 104b.

[0082] The second lower active contacts LAC2 include a second lower active contact LAC2 connected to the second lower conductive line 104b and a second lower active contact LAC2 connected to the third lower conductive line 104c.

[0083] The third lower active contacts LAC3 include a third lower active contact LAC3 connected to the first lower conductive line 104a, and the fourth lower active contacts LAC4 include a fourth lower active contact LAC4 connected to the third lower conductive line 104c.

[0084] The width W51 of the first lower active contact LAC1 in the first direction D1 is larger than the width W52 of the second lower active contact LAC2 in the first direction D1. The width W53 of the third lower active contact LAC3 in the first direction D1 is larger than the width W51 of the first lower active contact LAC1 in the first direction D1, the width W52 of the second lower active contact LAC2 in the first direction D1, and the width W54 of the fourth lower active contact LAC4 in the first direction D1. The width W54 of the fourth lower active contact LAC4 in the first direction D1 is larger than the width W52 of the second lower active contact LAC2 in the first direction D1.

[0085] Each of the tall source / drain pattern TS, the small source / drain pattern SS, the tall merge source / drain pattern TMS, and the small merge source / drain pattern SMS is connected to the lower active contact LAC or the upper active contact UAC. Each of the tall source / drain pattern TS, the small source / drain pattern SS, the tall merge source / drain pattern TMS, and the small merge source / drain pattern SMS contacts the lower active contact LAC or the upper active contact UAC.

[0086] In a semiconductor device according to some embodiments, two tall cells TC and two small cells SC are alternately arranged, thereby increasing the efficiency of power supply and improving the frequency characteristics of the transistor. Since the power voltage can be efficiently provided depending on whether the lower conductive line 104 is arranged on the backside, it is not necessary to alternately arrange one tall cell TC and one small cell SC, but two tall cells TC and two small cells SC are alternately arranged.

[0087] Figure 2 is a plan view of a semiconductor device according to some embodiments, which is similar to the semiconductor device described in Figures 1A-1G, except as described below.

[0088] Referring to FIG. 2, the semiconductor device includes a tall cell TCa, a small cell SCa, a tall merge cell TMCa, and a small merge cell SMCa.

[0089] The width of the tall merge cell TMCa in the first direction D1 is the same as the sum of the widths of the three tall cells TCa in the first direction D1. The width of the small merge cell SMCa in the first direction D1 is the same as the sum of the widths of the three small cells SCa in the first direction D1.

[0090] The tall merge cell TMCa has a structure in which three tall cells TCa are merged. In some embodiments, the tall merge cell TMCa may have a structure in which four or more tall cells TCa are merged. The small merge cell SMCa has a structure in which three small cells SCa are merged. In some embodiments, the small merge cell SMCa may have a structure in which four or more small cells SCa are merged.

[0091] The tall cell TCa includes a tall pattern TPa. The small cell SCa includes a small pattern SPa. The tall merge cell TMCa includes a tall pattern TPa, a first tall merge pattern TMP1a, and a second tall merge pattern TMP2a. The first tall merge pattern TMP1a and the second tall merge pattern TMP2a are arranged between the tall patterns TPa of the tall merge cell TMCa. The tall patterns TPa, the first tall merge pattern TMP1a, and the second tall merge pattern TMP2a of the tall merge cell TMCa are arranged in the first direction D1.

[0092] The small merge cell SMCa includes a small pattern SPa, a first small merge pattern SMP1a, and a second small merge pattern SMP2a. The first small merge pattern SMP1a and the second small merge pattern SMP2a are arranged between the small patterns SPa of the small merge cell SMCa. The small patterns SPa, the first small merge pattern SMP1a, and the second small merge pattern SMP2a of the small merge cell SMCa are arranged in a first direction D1.

[0093] Figure 3 is a cross-sectional view of a semiconductor device according to some embodiments. The semiconductor device of Figure 3 is similar to the semiconductor device described in Figures 1A-1G, except as described below.

[0094] 3, one fin pattern FPb overlaps the tall cell TCb and the tall merge cell TMCb in the third direction D3. The tall cell TCb and the tall merge cell TMCb are disposed on one fin pattern FPb. An isolation structure DSb is provided between the tall cell TCb and the tall merge cell TMCb. The bottom of the isolation structure DSb is disposed within the fin pattern FPb. The isolation structure DSb contacts the tall source / drain pattern TS and the tall merge source / drain pattern TMS. The isolation structure DSb includes an insulating material.

[0095] Although the embodiments of the present invention have been described above with reference to the drawings, the present invention may be embodied in other specific forms without changing the technical concept or essential features thereof. Therefore, it should be understood that the embodiments described above are illustrative in all respects and are not limiting. [Explanation of symbols]

[0096] 101 Element isolation film 102 Lower insulating film 104, 104a, 104b, 104c lower conductive lines 110, 120 Interlayer insulating film 130 Upper insulating film 131 Upper Conductive Line FP Fin Pattern GE gate electrode GC Gate Contact IL gate isolation membrane LAC Lower Active Contact SC, SC1 to SC4 small cells SMC Small Merge Cell SMS Small Merged Source / Drain Pattern SMP Small Merge Pattern SP Small Pattern SS Small Source / Drain Pattern TC, TC1~TC4 Thor Cells TMC Thor merge cell TMP tall merge pattern TMS Thor merge source / drain pattern TP Tall Pattern TS Tall Source / Drain Pattern UAC Upper Active Contact

Claims

1. an upper conductive line; a first lower conductive line, a second lower conductive line, and a third lower conductive line arranged in a first direction; a lower active contact connected to one of the first, second, and third lower conductive lines; a first tall cell, a second tall cell, a first small cell, and a second small cell arranged between the upper conductive line and the first, second, and third lower conductive lines and arranged in the first direction; Each of the first and second toll cells comprises: Tall pattern and a toll source / drain pattern connected to the toll pattern, Each of the first small cell and the second small cell Small patterns and a small source / drain pattern connected to the small pattern; a width of the tall pattern in the first direction is larger than a width of the small pattern in the first direction; The lower active contact is connected to the tall source / drain pattern or the small source / drain pattern.

2. the first tall cell and the first small cell are adjacent to the second tall cell in the first direction; The semiconductor device according to claim 1 , wherein the second tall cell and the second small cell are adjacent to the first small cell in the first direction.

3. the first lower conductive line overlaps the first and second threshold cells; the second lower conductive line overlaps the second tall cell and the first small cell; The semiconductor device of claim 1 , wherein the third lower conductive line overlaps the first small cell and the second small cell.

4. a width of the first lower conductive line in the first direction is greater than a width of the second lower conductive line in the first direction; 4. The semiconductor device according to claim 3, wherein the width of the second lower conductive line in the first direction is greater than the width of the third lower conductive line in the first direction.

5. the first lower conductive line overlaps the toll pattern of the first toll cell and the toll pattern of the second toll cell; the second lower conductive line overlaps the tall pattern of the second tall cell and the small pattern of the first small cell; The semiconductor device of claim 3 , wherein the third lower conductive line overlaps the small pattern of the first small cell and the small pattern of the second small cell.

6. 2. The semiconductor device according to claim 1, wherein the maximum width of the tall source / drain pattern in the first direction is greater than the maximum width of the small source / drain pattern in the first direction.

7. a fin pattern between the second lower conductive line and the toll source / drain pattern of the second toll cell; an isolation layer surrounding the fin pattern, 2. The semiconductor device according to claim 1, wherein the lower active contact penetrates the fin pattern.

8. the second lower conductive line includes a first portion overlapping the second tall cell and a second portion overlapping the first small cell; 2. The semiconductor device according to claim 1, wherein the width of the first portion of the second lower conductive line in the first direction is greater than the width of the second portion of the second lower conductive line in the first direction.

9. an upper conductive line; a first lower conductive line, a second lower conductive line, and a third lower conductive line arranged in a first direction; a first tall cell, a second tall cell, a first small cell, and a second small cell arranged between the upper conductive line and the first, second, and third lower conductive lines and arranged in the first direction; the first lower conductive line overlaps the first and second threshold cells; the second lower conductive line overlaps the second tall cell and the first small cell; the third lower conductive line overlaps the first small cell and the second small cell; a width of the first lower conductive line in the first direction is greater than a width of the second lower conductive line in the first direction; The width of the second lower conductive line in the first direction is greater than the width of the third lower conductive line in the first direction.

10. a tall merge cell overlapping the first lower conductive line and the second lower conductive line; the toll merge cell includes a toll merge pattern overlapping the first lower conductive line and a first toll pattern overlapping the second lower conductive line; 10. The semiconductor device according to claim 9, wherein the width of the tall merge pattern in the first direction is larger than the width of the first tall pattern in the first direction.

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