Semiconductor device and communication system

Abstract

To provide a semiconductor device capable of effectively configuring a communication system by using a device corresponding to a protocol different from its own protocol.SOLUTION: The semiconductor integrated circuit (1) according to claim 1, wherein when the bridge selection signal (BR) included in the reception signal (RX) indicates an ON state of a through-output in which the bit signal is outputted as it is, the signal (SPDT) for the first device (100) included in the reception signal is through-outputted from the second output terminal (1C), the transmission datum (BTX) received by the second reception portion (13) via the second input-terminal (1D) at the time of the through-output of the reception datum is stored in a buffer (152), and the transmission datum read from the buffer after the through-output of the reception datum is outputted by the second transmission portion (14) via the first output-terminal (1B).SELECTED DRAWING: Figure 11

Description

[Technical Field]

[0001] The present disclosure relates to semiconductor devices. [Background technology]

[0002] Semiconductor devices having a serial communication function are used in a variety of applications.

[0003] An example of circuit technology relating to serial communication is disclosed in Patent Document 1. [Prior art documents] [Patent documents]

[0004] [Patent Document 1] Japanese Patent Application Publication No. 2017-224946

[0005] [overview] In some applications, a communication system may be constructed using a semiconductor device (device) that performs serial communication using a communication method different from that of the semiconductor device itself, along with the semiconductor device itself.

[0006] A semiconductor device according to one aspect of the present disclosure includes: a first input terminal; a first output terminal; A second output terminal; a second input terminal; a first receiving unit configured to be able to receive reception data, which is serial data, from an external transmitting device via the first input terminal; a first transmitting unit configured to be connectable to an external first device via the second output terminal; a second receiving unit configured to be connectable to the first device via the second input terminal; a second transmitting unit configured to be connectable to the transmitting device via the first output terminal; a buffer; the first receiving unit and the first transmitting unit are configured to, when bridge selection data included in the received data indicates on of a through output that outputs bit data as is, through-output the data for the first device included in the received data from the second output terminal; The transmission data received by the second receiving unit via the second input terminal during through output of the reception data is stored in the buffer; The transmission data read from the buffer after the through output of the received data is output by the second transmission unit via the first output terminal. [Brief explanation of the drawings]

[0007] [Figure 1] FIG. 1 is a diagram showing a configuration of a communication system according to a first comparative example. [Figure 2] FIG. 2 is a diagram illustrating a configuration of a communication system according to a second comparative example. [Figure 3] FIG. 3 is a diagram illustrating a configuration of a communication system according to an exemplary embodiment of the present disclosure. [Figure 4] FIG. 4 is a block diagram of a semiconductor device according to an exemplary embodiment of the present disclosure. [Figure 5] FIG. 5 is a block diagram of a semiconductor device according to an exemplary embodiment of the present disclosure. [Figure 6] FIG. 6 is a diagram showing the data structure of received data RX when writing or reading is performed with the semiconductor device 1 as the target device. [Figure 7] FIG. 7 is a diagram illustrating a configuration example of a communication system according to an embodiment of the present disclosure. [Figure 8] FIG. 8 is a diagram showing the data structure of received data RX when writing or reading is performed with the device 10 as the target device. [Figure 9] FIG. 9 is a timing chart showing communication control when writing to the device 10. In FIG. [Figure 10]FIG. 10 is a timing chart showing communication control when reading from the device 10. In FIG. [Figure 11] FIG. 11 is a diagram illustrating a configuration example of a communication system according to an embodiment of the present disclosure. [Figure 12A] FIG. 12A is a table showing communication method setting information BRIFSEL. [Figure 12B] FIG. 12B is a table showing the clock edge setting information CPOL. [Figure 12C] FIG. 12C is a table showing the chip select signal setting information CSF. [Figure 12D] FIG. 12D is a table showing the clock edge setting information CPOLR. [Figure 13] FIG. 13 is a timing chart showing an example of an operation when writing to an SPI device. [Figure 14] FIG. 14 is a diagram showing the data structure of received data RX when writing or reading is performed with an SPI device as the target device. [Figure 15] FIG. 15 is a timing chart showing an example of an operation when reading from an SPI device. [Figure 16] FIG. 16 is a diagram showing an outline of an example of operation of full duplex SPI communication. [Figure 17] FIG. 17 is a diagram illustrating the configuration of a CAN transceiver. [Figure 18] FIG. 18 is a timing chart showing in more detail the processing after the second data number frame ND2 in FIG. [Figure 19] FIG. 19 is a diagram illustrating an example of the configuration of a motor driver. [Figure 20] FIG. 20 is an external view showing an example of a vehicle.

[0008] [Detailed explanation] Hereinafter, exemplary embodiments of the present disclosure will be described with reference to the drawings.

[0009] <1. Communication Systems> 1 is a diagram showing the configuration of a communication system 501 according to a first comparative example for comparison with an embodiment of the present disclosure. The communication system 501 includes an MCU (Micro Controller Unit) 20, a CAN (Controller Area Network) transceiver 30, a CAN transceiver 40, a semiconductor device 1, and n (n is an integer equal to or greater than 1) devices 10. The communication system 501 is, as an example, for use in a vehicle, and the same applies to the other communication systems described below.

[0010] Communication between the MCU 20 and the CAN transceiver 30 is performed using UART (Universal Asynchronous Receiver / Transmitter). UART is a format for exchanging serial data between two devices. With UART, bidirectional communication is performed between the sender and receiver using two lines.

[0011] Communication between the CAN transceivers 30 and 40 is performed via a CAN bus 35. CAN is a serial communication protocol standardized by international standards such as ISO11898. CAN uses a differential voltage method for transmitting data based on the level of the voltage difference generated between two communication lines. Communication between the CAN transceiver 40 and the semiconductor device 1 and the n devices 10 is performed via UART.

[0012] The CAN transceiver 30 has a TXD (transmit data input) terminal 30A and an RXD (receive data output) terminal 30B. The CAN transceiver 30 outputs data input to the TXD terminal 30A to the CAN bus 35, and outputs data input from the CAN bus 35 from the RXD terminal 30B.

[0013] The CAN transceiver 40 has an RXD terminal 40A and a TXD terminal 40B. The CAN transceiver 40 outputs data input to the TXD terminal 40B to the CAN bus 35, and outputs data input from the CAN bus 35 from the RXD terminal 40A.

[0014] The semiconductor device 1 is an IC (integrated circuit) in which circuits with predetermined functions are integrated, and is configured as, for example, an LED (light emitting diode) driver IC. The n devices 10 are ICs in which circuits with predetermined functions are integrated, and are configured as, for example, matrix switch ICs.

[0015] The semiconductor device 1 has an RX (receive data input) terminal 1A and a TX (transmit data output) terminal 1B. The device 10 has an RX terminal 10A and a TX terminal 10B. The RX terminal 1A and the n RX terminals 10A are commonly connected to an RXD terminal 40A. The TX terminal 1B and the n TX terminals 10B are commonly connected to a TXD terminal 40B.

[0016] 1, the semiconductor device 1 and the n devices 10 support the same protocol, so the semiconductor device 1 and the n devices 10 can be commonly connected to the same CAN transceiver 40. Received data RX output from the RXD terminal 40A is input to the RX terminal 1A and the n RX terminals 10A. The received data RX specifies the device address of one of the semiconductor device 1 and the n devices 10. Transmitted data TX output from the TX terminal 1B and the n TX terminals 10B is input to the TXD terminal 40B.

[0017] However, if the protocols supported by the semiconductor device 1 and the n devices 10 are different, it becomes difficult to deal with the configuration of the first comparative example shown in Fig. 1. In such a case, the configuration of the second comparative example shown in Fig. 2 can be adopted.

[0018] 2 differs from the first comparative example in that CAN transceivers 301 and 302 are used instead of CAN transceiver 30, and CAN transceivers 401 and 402 are used instead of CAN transceiver 40. A semiconductor device 1 is connected to MCU 20 via CAN transceiver 301 and CAN transceiver 401, and n devices 10 are connected to MCU 20 via CAN transceiver 302 and CAN transceiver 402. CAN transceivers 401 and 402 perform CAN communication with CAN transceivers 301 and 302, respectively.

[0019] In this way, by grouping devices with different protocols (a group of semiconductor device 1 and a group of n devices 10), communication control can be performed using devices with different protocols. However, an increase in the number of CAN transceivers, such as CAN transceivers 301, 302, 401, and 402, and an increase in the amount of wiring pose a problem of increased costs.

[0020] Therefore, in order to solve such problems, the embodiment of the present disclosure is implemented as described below. Figure 3 is a diagram showing the configuration of a communication system 50 according to an exemplary embodiment of the present disclosure.

[0021] In the configuration shown in FIG. 3, UART communication is performed between the CAN transceiver 40, the semiconductor device 1, and n devices 10. In addition to an RX terminal 1A and a TX terminal 1B, the semiconductor device 1 has an RXD (receive data output) terminal 1C and a TXD (transmit data input) terminal 1D. The RX terminal 1A is connected to the RXD terminal 40A of the CAN transceiver 40. The TX terminal 1B is connected to the TXD terminal 40B of the CAN transceiver 40. In other words, the RX terminal 1A and the TX terminal 1B are connected to the RXD terminal 40A and the TXD terminal 40B by a bus BS1. Communication of receive data RX and transmit data TX is possible via the bus BS1. The receive data RX and transmit data TX are serial data.

[0022] The RXD terminal 1C is connected to the RX terminals 10A of the n devices 10. The TXD terminal 1D is connected to the TX terminals 10B of the n devices 10. That is, the RXD terminal 1C and the TXD terminal 1D are connected to the RX terminals 10A and TX terminals 10B by a bus (local bus) BS2. Communication of receive data BRX and transmit data BTX is possible via the bus BS2. The receive data BRX and transmit data BTX are serial data.

[0023] The semiconductor device 1 also has a CS terminal (chip select terminal) 1E and an SCK terminal (clock terminal) 1F. As will be described later, the CS terminal 1E is a terminal for outputting a chip select signal, and the SCK terminal 1F is a terminal for outputting a clock signal. As will be described later, the terminals 1E and 1F are used when using a device that supports SPI (Serial Peripheral Interface) as a communication method, and as shown in FIG. 3, the terminals 1E and 1F are not used when using a device 10 that supports UART.

[0024] In the configuration according to the embodiment of the present disclosure shown in FIG. 3, the semiconductor device 1 and the n devices 10 support different protocols. When the CAN transceiver 40 writes or reads to the semiconductor device 1, the received data RX output from the RXD terminal 40A to the RX terminal 1A consists only of data that supports the protocol of the semiconductor device 1. Note that "write" refers to the process of writing data to the target device, and "read" refers to the process of reading data from the target device. In the case of a read, the semiconductor device 1 receives the received data RX and then outputs the transmitted data TX from the TX terminal 1B to the TXD terminal 40B.

[0025] On the other hand, when the CAN transceiver 40 writes to or reads from the device 10, the receive data RX output from the RXD terminal 40A to the RX terminal 1A includes data corresponding to the protocol of the device 10. At this time, the semiconductor device 1 turns on the bridge function and through-outputs the data included in the receive data RX and corresponding to the protocol of the device 10 as receive data BRX from the RXD terminal 1C. Through-output means outputting bit data as is. The device address of the device 10 is specified in the receive data BRX.

[0026] In the case of a read, the device 10, which is the target device (the device specified by the device address), outputs transmission data BTX from the TX terminal 10B to the TXD terminal 1D. Since the bridge function of the semiconductor device 1 is on, the transmission data BTX is output as transmission data TX from the TX terminal 1B.

[0027] As described above, according to the embodiment of the present disclosure, even if the protocols of the semiconductor device 1 and the device 10 are different, the CAN transceiver 40 can write and read to and from the semiconductor device 1 and the device 10. Compared to the second comparative example (FIG. 2), the number of CAN transceivers can be reduced, and the amount of wiring can be reduced, thereby reducing costs.

[0028] <2. Configuration of semiconductor device> 4 is a block diagram of a semiconductor device 1 according to an embodiment of the present disclosure. The semiconductor device 1 includes functional blocks including a first receiving unit 11, a first transmitting unit 12, a second receiving unit 13, a second transmitting unit 14, and a control unit 15. Note that FIG. 4 illustrates only functional blocks related to communication functions, and other functional blocks may also be included. For example, if the semiconductor device 1 is an LED driver, it includes a block function related to LED driving.

[0029] The first receiver 11 receives reception data RX via an RX terminal 1A. The first transmitter 12 outputs reception data BRX via an RXD terminal 1C. The second receiver 13 receives transmission data BTX via a TXD terminal 1D. The second transmitter 14 outputs transmission data TX via a TX terminal 1B.

[0030] The control unit 15 controls the first receiving unit 11, the first transmitting unit 12, the second receiving unit 13, and the second transmitting unit 14. The control unit 15 has a register 151 and a buffer 152. The buffer 152 is configured as a FIFO (First In First Out) memory.

[0031] As shown in FIG. 4, the semiconductor device 1 also includes a chip select signal output unit 16 and a clock signal output unit 17. FIG. 4 is a diagram showing the state of the semiconductor device 1 when a UART-compatible device 10 is used, as shown in FIG. 3. The chip select signal output unit 16 and the clock signal output unit 17 are not used in the state shown in FIG. 4. On the other hand, FIG. 5 is a diagram showing the state of the semiconductor device 1 when a SPI-compatible device is used, as will be described later. As shown in FIG. 5, the chip select signal output unit 16 outputs a chip select signal CS via a CS terminal 1E. The clock signal output unit 17 outputs a clock signal SCK via an SCK terminal 1F. The chip select signal CS and the clock signal SCK are signals necessary for SPI communication and are used together with the received data BRX and the transmitted data BTX.

[0032] <3. Structure of received data> 6 is a diagram showing the data structure of received data RX when writing or reading is performed using the semiconductor device 1 as the target device. The received data RX shown in FIG.

[0033] In UART, communication is carried out in data units called frames. As shown in Figure 6, a frame FR is made up of bit data from a start bit S to a stop bit P. The start bit S is at low level, and the stop bit P is at high level. A predetermined number of bits of bit data are placed between the start bit S and the stop bit P. In the example of Figure 6, 8 bits of bit data are placed. In other words, the frame FR is made up of 10 bits of bit data.

[0034] As shown in FIG. 6, the received data RX includes, from the beginning, a synchronization frame SYN, a read / write etc. frame RWD, a data number frame ND, a register address frame AD, a data frame DT, and CRC (Cyclic Redundancy Check) frames CRL and CRH.

[0035] The synchronization frame SYN is bit data for setting the baud rate in the semiconductor device 1 .

[0036] The Read / Write etc. frame RWD includes a device address DA, a bridge bit BR, a broadcast / parity bit B / PA, and a Read / Write bit RW. The device address DA is bit data indicating the address of the target device (semiconductor device 1) (5-bit data in the example of Figure 6). The bridge bit BR is bit data indicating the on / off of the bridge function of the semiconductor device 1. The broadcast / parity bit B / PA is bit data indicating the on / off of the broadcast of the semiconductor device 1 or the parity of the data address DA. The Read / Write bit RW is bit data indicating Read or Write.

[0037] Here, the bridge bit BR=0 indicates that the bridge function is off, i.e., normal mode (the bridge function is off in the received data RX shown in Figure 6). In this case, the broadcast / parity bit B / PA indicates whether broadcast is on or off. When the broadcast / parity bit B / PA=0, it indicates that broadcast is off, and when the broadcast / parity bit B / PA=1, it indicates that broadcast is on.

[0038] When broadcasting the semiconductor device 1, multiple semiconductor devices 1 are connected to the CAN transceiver 40 as shown in Fig. 7. A device 10 is connected to each semiconductor device 1. When broadcasting is on, all of the multiple semiconductor devices 1 become target devices.

[0039] The bridge bit BR=1 indicates that the bridge function is on (the bridge function is on in the received data RX shown in FIG. 8, which will be described later). In this case, the broadcast / parity bit B / PA becomes the parity of the device address DA. This makes it possible to detect errors in the device address DA. In the configuration shown in FIG. 7, if the protocols differ for each group of devices 10 connected to each of the multiple semiconductor devices 1, turning on the broadcast of the semiconductor device 1 will result in the same received data RX being sent as received data BRX to devices 10 with different protocols, making the protocols incompatible with some of the devices 10. Therefore, when the bridge function is turned on, broadcasting is not performed.

[0040] The data number frame ND is bit data indicating the number of data frames DT, which are frames of data for writing to the target device.

[0041] The register address frame AD is bit data indicating an address in the register 151. The data frame DT is bit data including write data. In FIG. 6, the number of frames in the data frame DT (the number of frames indicated by the data number frame ND) is set to 1 as an example, but it may be 2 or more. The CRC frames CRL and CRH are bit data indicating an error detection code added to the data frame DT. The 16-bit data of the CRC is divided into two frames: CRL (lower 8 bits) and CRH (upper 8 bits).

[0042] In the first receiving unit 11, a baud rate is set using the synchronization frame SYN, and thereafter, each bit of each frame is sampled according to the set baud rate to obtain the bit value. During the write process, the write data included in the data frame DT is checked based on the CRC data included in the CRC frames CRL and CRH, and if no abnormalities are found, the write data is written to the register 151. Therefore, the write data is temporarily stored in the buffer 152.

[0043] 8 is a diagram showing the data structure of received data RX when performing write or read with the device 10 as the target device. The synchronization frame SYN and read / write etc. frame RWD in the received data RX shown in FIG. 8 are as described above.

[0044] In the received data RX shown in Figure 8, the second data number frame ND2 is followed by device data DDT. The device data DDT is data that complies with the protocol of the device 10 and is the target to be output as received data BRX. The device data DDT includes a device address BDA. The device address BDA indicates the address of the device 10, which is the target device. The device address BDA is placed in the device data DDT at a position that corresponds to the protocol of the device 10.

[0045] <4. Through output control> Here, the through output control by the semiconductor device 1, that is, the control when the bridge function is on, will be described.

[0046] 9 is a timing chart showing communication control when writing to the device 10. From the top to bottom of FIG. 9, receive data RX, receive data output selection signal (RX output select), transmit data output selection signal (TX output select), receive data BRX, transmit data BTX, and transmit data TX are shown (similar to FIG. 10). The receive data RX has the configuration shown in FIG. 8.

[0047] The received data RX is received by the first receiving unit 11 (FIG. 4). Upon receiving the start bit S1 (low level) at the beginning of the received data RX, the control unit 15 recognizes the start of reception of the received data RX. Thereafter, the control unit 15 recognizes that the bridge function is on from the bridge bit BR included in the received data RX, and also recognizes that it is a write from the read / write bit RW.

[0048] Thereafter, when the second data number frame ND2 is received, the control unit 15 changes the received data output selection signal in the register 151 from low to high at the stop bit P1 of the second data number frame ND2 (timing t1). This starts the through output of the received data RX, and the first receiving unit 11 and the first transmitting unit 12 output the received data RX as is as received data BRX. That is, the device data DDT (FIG. 8) is through output.

[0049] When the received data output selection signal goes high, the control unit 15 starts counting the number of frames of the received data RX (i.e., the number of frames of the device data DDT). When the counted number of frames reaches the number of frames indicated by the received second data number frame ND2, the control unit 15 switches the received data output selection signal to low and stops the through output (timing t2). Thereafter, the received data BRX is fixed at high. In this case, the number of frames indicated by the second data number frame ND2 and the number of frames indicated by the first data number frame ND1 match.

[0050] 10 is a timing chart showing communication control when performing a read from the device 10. In this case, the received data RX has the structure shown in FIG.

[0051] After receiving the start bit S1 (low level) at the beginning of the received data RX, the control unit 15 recognizes that the bridge function is on from the bridge bit BR included in the received data RX, and also recognizes that it is a read from the read / write bit RW.

[0052] Thereafter, when the second data number frame ND2 is received, the control unit 15 changes both the receive data output selection signal and the transmit data output selection signal in the register 151 from low to high at the stop bit P1 of the second data number frame ND2 (timing t1). This initiates through-output of the receive data RX and the transmit data BTX. The first receive unit 11 and the first transmit unit 12 output the receive data RX as it is as receive data BRX, i.e., through-output of the device data DDT (FIG. 8) is performed. After completing output of the receive data BRX, the second receive unit 13 and the second transmit unit 14 through-output the transmit data BTX sent from the device 10 as transmit data TX.

[0053] When the reception data output selection signal and the transmission data output selection signal go high, the control unit 15 starts counting the number of frames of the reception data RX that are received. When the sum of the number of counted frames of the reception data RX and the number of counted frames of the transmission data BTX that are received thereafter reaches the number of frames indicated by the first data number frame ND1, the control unit 15 switches both the reception data output selection signal and the transmission data output selection signal to low, stopping the through output (timing t2). Thereafter, the transmission data TX is fixed to Hi-z (high impedance).

[0054] As described above, in this embodiment, the condition for ending the through output can be determined based on the number of frames received by the semiconductor device 1. In particular, with this embodiment, even if transmission of the received data RX from the MCU 20 is interrupted due to interrupt processing in the MCU 20, the frame count does not advance during the interruption, so it is possible to avoid erroneously interrupting the through output. In other words, because interruption of the through output can be avoided regardless of the interrupt time, it is less subject to restrictions imposed by the specifications of the MCU 20.

[0055] <5.Conversion between UART and SPI> An external device compatible with SPI communication can also be connected to the semiconductor device 1 of this embodiment. Fig. 11 is a diagram showing a communication system 55 configured from the semiconductor device 1 and an SPI device 100 compatible with SPI. The SPI device 100 is configured as a semiconductor device having various functions, such as a motor driver as described below.

[0056] The SPI device 100 has an RX terminal 100A, a TX terminal 100B, a CS terminal 100C, and an SCK terminal 100D.

[0057] The RXD terminal 1C of the semiconductor device 1 is connected to the RX terminal 100A. The TXD terminal 1D of the semiconductor device 1 is connected to the TX terminal 100B. The received data BRX output from the RXD terminal 1C is input to the RX terminal 100A. The transmitted data BTX output from the TX terminal 100B is input to the TXD terminal 1D.

[0058] The CS terminal 1E of the semiconductor device 1 is connected to the CS terminal 100C. The SCK terminal 1F of the semiconductor device 1 is connected to the SCK terminal 100D. The chip select signal CS output from the CS terminal 1E is input to the CS terminal 100C. The clock signal SCK output from the SCK terminal 1F is input to the SCK terminal 100D. In other words, communication is performed between the semiconductor device 1 and the SPI device 100 via the bus BS2 using the signals BRX, BTX, CS, and SCK.

[0059] The semiconductor device 1 operates as a master, and the SPI device 100 operates as a slave. When transmitting reception data BRX from the semiconductor device 1 to the SPI device 100, the semiconductor device 1 transmits a clock signal SCK to the SPI device 100. The semiconductor device 1 transmits the reception data BRX in synchronization with the clock signal SCK. The SPI device 100 receives the reception data BRX in synchronization with the clock signal SCK.

[0060] When transmitting data from the SPI device 100 to the semiconductor device 1, the semiconductor device 1 also transmits a clock signal SCK to the SPI device 100. The SPI device 100 transmits the clock signal SCK and transmission data BTX in synchronization with each other. The semiconductor device 1 receives the clock signal SCK and transmission data BTX in synchronization with each other.

[0061] Next, the operation of the communication system 55 configured as described above will be described in more detail. Here, the register 151 of the semiconductor device 1 can be set with communication method setting information BRIFSEL as shown in FIG. 12A. The communication method setting information BRIFSEL indicates a communication method supported by a device connected to the semiconductor device 1. In the example of FIG. 12A, communication method setting information BRIFSEL=0 indicates UART, BRIFSEL=1 indicates SPI using half duplex (half-duplex communication), and BRIFSEL=2 indicates SPI using full duplex (full-duplex communication). Half duplex is a method of performing bidirectional communication by alternately transmitting data between two devices. Full duplex is a method of performing bidirectional communication by simultaneously transmitting data between two devices. For example, when a device 10 (FIG. 3) compatible with UART is connected, BRIFSEL=0 is set, and when an SPI device 100 (FIG. 11) is connected, BRIFSEL=1 or 2 is set. The operation is switched depending on the setting of BRIFSEL.

[0062] Note that various settings using the communication method setting information BRIFSEL and the like are not limited to settings in registers, but can also be made using, for example, resistors connected to the outside of the semiconductor device.

[0063] <<SPI(Half Duplex)> > Here, the operation when half-duplex SPI is set as the communication method in the semiconductor device 1 (BRIFSEL=1) will be described. First, the operation when writing to the SPI device 100 will be described with reference to the timing chart shown in Fig. 13. Fig. 13 (and Fig. 15, described later) shows, from the top, example waveforms of receive data RX, transmit data TX, receive data BRX, transmit data BTX, chip select signal CS, and clock signal SCK.

[0064] 13 shows waveforms classified by the value of the clock edge setting information CPOL. The clock edge setting information CPOL can be set in the register 151, and is information indicating the edge (rising or falling) of the clock signal SCK at the center of each bit of the received data BRX. In the example shown in FIG. 12B, CPOL=0 indicates a rising edge, and CPOL=1 indicates a falling edge.

[0065] In FIG. 13 (and FIG. 15), hatching indicates signal control other than through output.

[0066] As shown in Fig. 14, the received data RX includes a synchronization frame SYN, a read / write etc. frame RWD, a first data number frame ND1, and a second data number frame ND2, similar to Fig. 8. The received data RX shown in Fig. 14 includes data SPDT for the SPI device 100 after the second data number frame ND2.

[0067] After receiving the start bit (low level) at the beginning of the received data RX, the control unit 15 recognizes that the bridge function is on from the bridge bit BR included in the received data RX, and also recognizes that it is Write from the Read / Write bit RW.

[0068] Thereafter, when the second data number frame ND2 is received, the control unit 15 starts through-output of the received data RX at the stop bit ST of the second data number frame ND2 (timing t11). As a result, the data SPDT is through-output as received data BRX to the SPI device 100. At this time, the chip select signal output unit 16 switches the chip select signal CS to active at the start bit at the beginning of the data SPDT (timing t12).

[0069] Here, chip select signal setting information CSF can be set in register 151. The chip select signal setting information CSF is information that sets the level at which the chip select signal CS is made active. For example, as shown in FIG. 12C, when CSF=0, the chip select signal CS is made active at a low level, and when CSF=1, the chip select signal CS is made active at a high level. FIG. 13 shows a case where the chip select signal CS is set to be active at a low level.

[0070] Furthermore, when the clock edge setting information CPOL=0, the clock signal SCK is output so that the rising edge coincides with the center of each bit (bit sandwiched between the start bit and stop bit) of the transmission data BRX that has been output as a through-output of the data SPDT, and when CPOL=1, the clock signal SCK is output so that the falling edge coincides with the center of each bit of the transmission data BRX that has been output as a through-output of the data SPDT (timing t13).

[0071] When the number of frames of the received data RX to be through-output reaches the number of frames indicated by the second data number frame ND2 (number of frames=2 in FIG. 13), the control unit 15 stops the through-output (timing t14). In this case, the number of frames indicated by the second data number frame ND2 matches the number of frames indicated by the first data number frame ND1.

[0072] Next, the operation when reading from the SPI device 100 will be described with reference to the timing chart shown in FIG. 15. Note that FIG. 15 shows waveforms for different cases depending on the value of the clock edge setting information CPOLR. The clock edge setting information CPOLR can be set in the register 151, and is information that indicates the edge (rising or falling) of the clock signal SCK at the beginning of each bit of the transmission data BTX. In the example shown in FIG. 12D, CPOLR=0 indicates a rising edge, and CPOLR=1 indicates a falling edge. Also, in FIG. 15, the chip select signal CS is active at a low level.

[0073] After receiving the start bit (low level) at the beginning of the received data RX, the control unit 15 recognizes that the bridge function is on from the bridge bit BR included in the received data RX, and also recognizes that it is a read from the read / write bit RW.

[0074] After that, when the second data number frame ND2 is received, the control unit 15 starts through-output of the received data RX at the stop bit ST of the second data number frame ND2 (timing t21). The operation of the through-output of the data SPDT thereafter is the same as that during the write operation described above, and a detailed description will be omitted. Then, when the through-output is stopped, the chip select signal CS is switched to high level and released from active (timing t22).

[0075] Then, the transmission data TX is set to low level, and the chip select signal CS is switched to low level and made active (timing t23). Then, regardless of the setting of CPOLR, the through output of the transmission data BTX begins (timing t24). As a result, the transmission data BTX is through output as the transmission data TX. A start bit STB is added to the beginning of the transmission data TX.

[0076] When CPOLR=1, the clock signal SCK falls at the beginning of each bit of the transmission data BTX. When CPOLR=0, the clock signal SCK rises at the beginning of each bit of the transmission data BTX.

[0077] When the transmission data BTX of a predetermined number of bits (8 bits in FIG. 15) is through-output, the control unit 15 sets the transmission data TX to high level and stops the through-output (timing t25). After that, the control unit 15 sets the transmission data TX to low level (timing t26). This allows the stop bit SB used in the URAT to be added to the transmission data BTX transmitted from the SPI device 100 to generate the transmission data TX.

[0078] Thereafter, the through output of the transmission data BTX is resumed (timing t27), and the clock signal SCK is output. When the number of frames of the transmission data TX generated based on the transmitted transmission data BTX reaches the number of frames indicated by the first data number frame ND1 minus the number of frames indicated by the second data number frame ND2 (in the example of FIG. 15, the number of frames = 4 - 2 = 2), the process is completed.

[0079] As described above, the semiconductor device 1 of this embodiment enables conversion between the UART format and the SPI format, and the MCU 20 can write or read data to or from the SPI device 100 via the semiconductor device 1.

[0080] <<SPI(Full Duplex)> > Next, the operation when Full Duplex SPI is set as the communication method in the semiconductor device 1 (BRIFSEL=2) will be described.

[0081] Fig. 16 is a diagram showing an overview of an example of operation of full duplex SPI communication. In Fig. 16, from the top, received data RX, received data BRX, transmitted data BTX, data stored in the buffer 152 (FIFO), and transmitted data TX are shown.

[0082] When the first receiving unit 11 receives the frames from the synchronization frame SYN to the second data number frame ND2 in the received data RX, the number of frames (number of frames for Write) indicated by the second data number frame ND2 (i.e., data SPDT) is output as the received data BRX. In the example of Fig. 16, the number of frames indicated by the second data number frame ND2 is 2.

[0083] At this time, because of full duplex, transmission data BTX is output from the SPI device 100 and stored in the buffer 152. The transmission data BTX is, for example, status information of the SPI device 100. Thereafter, the data stored in the buffer 152 is read out, converted into frames, and transmitted as transmission data TX. The number of frames transmitted at this time is a value obtained by subtracting the number of frames indicated by the second data number frame from the number of frames indicated by the first data number frame ND1 (total number of frames). In the example of FIG. 16, the number of frames indicated by the first data number frame ND1 is set to 4. Note that the data stored in the buffer 152 corresponds to the number of frames in the transmission data BRX, so the number of frames indicated by the first data number frame ND1 is twice the number of frames indicated by the second data number frame ND2.

[0084] In this way, even when the semiconductor device 1 transmits receive data BRX to the SPI device 100 in full duplex mode and the SPI device 100 transmits transmit data BTX at the same time, the semiconductor device 1 can transmit the transmit data TX after receiving the receive data RX. If the transmit data BTX is not stored in a buffer and is output as transmit data TX as is, the transmit data TX is mirrored by the CAN transceiver 40 (FIG. 11) to become receive data RX, which causes a conflict with the original receive data RX. Therefore, the transmit data BTX needs to be temporarily stored in a buffer.

[0085] 17 is a diagram showing the configuration of a CAN transceiver 40. The CAN transceiver 40 has a driver control unit 41, a driver 42, a receiver 43, and an output unit 44. The CAN transceiver 40 also has a TXD terminal 40B, an RXD terminal 40A, a CANH terminal, and a CANL terminal.

[0086] The CANH terminal and the CANL terminal are connected to the respective lines of the CAN bus 35. Termination resistors R1 and R2 are connected in series between the CANH terminal and the CANL terminal. The resistance value of the termination resistors is specified by ISO 11898, and each of the termination resistors R1 and R2 is configured as a 60 Ω resistor. One end of the capacitor C1 is connected to a connection node N1 where the resistors R1 and R2 are connected to each other.

[0087] The driver 42 has a PMOS transistor (P-channel metal-oxide-semiconductor field-effect transistor (MOSFET)) 42A, a diode 42B, an NMOS transistor (N-channel MOSFET) 42C, and a diode 42D. The source of the PMOS transistor 42A is connected to the application terminal of the power supply voltage VCC. The drain of the PMOS transistor 42A is connected to the anode of the diode 42B. The cathode of the diode 42B is connected to the CANH terminal. The source of the NMOS transistor 42C is connected to the ground terminal. The drain of the NMOS transistor 42C is connected to the cathode of the diode 42D. The anode of the diode 42D is connected to the CANL terminal. The diodes 42B and 42D are used to prevent backflow when a surge occurs.

[0088] The driver control unit 41 controls the on / off of the PMOS transistor 42A and the NMOS transistor 42C based on the transmission data TX input from the outside via the TXD terminal 40B. do.

[0089] More specifically, when the PMOS transistor 42A and the NMOS transistor 42C are turned on, the current flowing through the termination resistors R1 and R2 is the same, so the voltage drops across the termination resistors R1 and R2 are the same, and the high-side signal CANH generated at the CANH terminal is a voltage higher than the voltage at the connection node N1 (=midpoint voltage) by the voltage drop, while the low-side signal CANL generated at the CANL terminal is a voltage lower than the voltage at the connection node N1 (=midpoint voltage) by the voltage drop. In this case, the high-side signal CANH is at a high level, and the low-side signal CANL is at a low level.

[0090] Here, the CANH terminal and the CANL terminal are connected to the application terminal of the power supply voltage VCC2 via resistors R41 and R42, respectively. When the PMOS transistor 42A and the NMOS transistor 42C are turned off, the voltage of the connection node N1 gradually approaches the second power supply voltage VCC2 due to the action of the resistors R41 and R42, which have relatively high resistance values. The second power supply voltage VCC2 is the low level of the high-side signal CANH and the high level of the low-side signal CANL, and is the same voltage as the intermediate voltage.

[0091] In this way, the transmission data TX input to the TXD terminal 40B is output to the CAN bus 35 from the CANH terminal and the CANL terminal.

[0092] On the other hand, the output section 44 has a PMOS transistor 44A and an NMOS transistor 44B. The source of the PMOS transistor 44A is connected to the terminal to which the power supply voltage VCC is applied. The drain of the PMOS transistor 44A is connected to the drain of the NMOS transistor 44B at a node N42. The source of the NMOS transistor 44B is connected to the ground terminal. The voltages at the CANH terminal and the CANL terminal are input to the receiver 43. The output terminal of the receiver 43 is connected to a node N41 to which the gates of the PMOS transistor 44A and NMOS transistor 44B are connected. The node N42 is connected to the RXD terminal 40A.

[0093] The receiver 43 applies a high-level or low-level signal to the node N41 depending on the difference in the input voltage. Therefore, the output unit 44 outputs a signal that is the logical inversion of the output of the receiver 43 from the RXD terminal 40A to the outside as received data RX. In this way, the data input from the CAN bus 35 is output from the RXD terminal 40A.

[0094] When the high-side signal CANH is high and the low-side signal CANL is low, it is called "dominant." When the high-side signal CANH is low and the low-side signal CANL is high, it is called "recessive." Dominant signals take priority over recessive signals.

[0095] With this configuration, when transmit data TX is input to the CAN transceiver 40, the driver 42 is driven. At this time, when receive data RX is sent from the CAN transceiver 30 (CAN bus 35), the receive data RX may be changed by the high-side signal CANH and low-side signal CANL driven by the driver 42. This is because when the CAN transceiver 30 side is recessive, the high-side signal CANH and low-side signal CANL based on the transmit data TX may be dominant.

[0096] It is also possible not to provide a CAN transceiver between the MCU 20 and the semiconductor device 1. In that case, if the MCU 20 is not capable of simultaneously transmitting the received data RX and receiving the transmitted data TX, it is necessary to store the transmitted data BTX in a buffer as in this embodiment.

[0097] Fig. 18 is a timing chart showing in more detail the processing after the second data number frame ND2 in Fig. 16. Fig. 18 shows, from the top to the bottom, example waveforms of the receive data RX, the transmit data TX, the receive data BRX, the transmit data BTX, the chip select signal CS, and the clock signal SCK.

[0098] When the second data number frame ND2 is received, the control unit 15 starts through-output of the received data RX at the stop bit ST of the second data number frame ND2 (timing t31). As a result, the data SPDT is through-output to the SPI device 100 as received data BRX. At this time, the chip select signal output unit 16 switches the chip select signal CS to active at the start bit S at the beginning of the data SPDT (timing t32). In FIG. 18, the chip select signal CS is active at a low level as an example (chip select signal setting information CSF=0 (FIG. 12C)).

[0099] In full duplex, the SPI device 100 transmits transmit data BTX simultaneously with the transmission of receive data BRX. In FIG. 18, as an example, clock edge setting information CPOL=1 (FIG. 12B), and the clock signal SCK is output so that the falling edge coincides with the center of each bit of the transmit data BRX that has been through-output as data SPDT (timing t34). In other words, the transmit data BTX is output at the rising edge of the clock signal SCK (timing t33). The transmit data BTX is stored in the buffer 152 as described above.

[0100] When the number of frames of the received data RX to be through-output reaches the number of frames indicated by the second data number frame ND2, the through-output is stopped by the control unit 15 (timing t35). At this time, the chip select signal CS is set to high level and released from active mode.

[0101] Thereafter, the second transmitter 14 adds a start bit S and a stop bit P to the data read from the buffer 152 to form a frame, and transmits it as transmission data TX. When the number of frames of transmission data TX obtained by subtracting the number of frames indicated by the second data number frame ND2 from the number of frames indicated by the first data number frame ND1 has been transmitted, the process is completed.

[0102] <6. Application Examples> Next, a motor driver will be described as a specific example of the SPI device 100 according to this embodiment.

[0103] The motor driver 1001 is configured to drive a two-phase excitation stepping motor 60 (hereinafter simply referred to as motor 60). The motor 60 has an excitation coil 61 of a first excitation phase, an excitation coil 62 of a second excitation phase, and a rotor 63. When the motor 60 is driven to rotate, the motor driver 1001 supplies drive currents I1 and I2 to the excitation coils 61 and 62, respectively.

[0104] The motor driver 1001 includes an integrated SPI communication unit 1001A, a control logic unit 1001B, a pre-driver 1001C, a half-bridge 1001D, and a half-bridge 1001E. The motor driver 1001 also has an RX terminal 100A, a TX terminal 100B, a CS terminal 100C, and an SCK terminal 100D as external terminals for establishing electrical connection with the outside. The motor driver 1001 also has output terminals OUT1A, OUT1B, OUT2A, and OUT2B as external terminals.

[0105] The SPI communication unit 1001A communicates with the semiconductor device 1 using SPI. That is, as shown in FIG. 19, communication is performed using receive data BRX, transmit data BTX, a chip select signal CS, and a clock signal SCK. As described above, the semiconductor device 1 converts between UART and SPI, so the SPI communication unit 1001A can communicate with an MCU (not shown) via the semiconductor device 1. The inclusion of the SPI communication unit 1001A makes it possible to perform various settings for the motor driver 1001 and output the state of the motor driver 1001 to the outside.

[0106] The control logic unit 1001B controls the entire motor driver 1001. The pre-driver 1001C drives the half bridges 1001D and 1001E under the control of the control logic unit 1001B. The half bridge 1001D controls the drive current I1 by generating a voltage signal across the output terminals OUT1A and OUT1B. The half bridge 1001E controls the drive current I2 by generating a voltage signal across the output terminals OUT2A and OUT2B.

[0107] <7. Vehicles> 20 is an external view showing an example of the configuration of a vehicle X. The vehicle X of this example is equipped with various electronic devices X11 to X18 that operate by receiving power supply from a battery (not shown). Note that the installation positions of the electronic devices X11 to X18 in FIG. 20 may differ from the actual positions for convenience of illustration.

[0108] The electronic device X11 is an engine control unit that performs engine-related controls (injection control, electronic throttle control, idling control, oxygen sensor heater control, auto-cruise control, etc.).

[0109] The electronic device X12 is a lamp control unit that controls the turning on and off of HID (high intensity discharged lamp) and DRL (daytime running lamp).

[0110] The electronic device X13 is a transmission control unit that controls transmission-related functions.

[0111] The electronic device X14 is a body control unit that performs control related to the movement of the vehicle X (ABS [anti-lock brake system] control, EPS [electric power steering] control, electronic suspension control, etc.).

[0112] The electronic device X15 is a security control unit that controls the operation of door locks, burglar alarms, and other devices.

[0113] The electronic device X16 is an electronic device that is installed in the vehicle X at the time of shipment from the factory as a standard equipment or a manufacturer option, such as a wiper, an electric door mirror, a power window, a damper (shock absorber), an electric sunroof, and an electric seat.

[0114] The electronic device X17 is an electronic device that is optionally installed in the vehicle X as a user option, such as an in-vehicle A / V (audio / visual) device, a car navigation system, and an ETC (electronic toll collection system).

[0115] The electronic device X18 is an electronic device equipped with a high-voltage motor, such as an in-vehicle blower, oil pump, water pump, or battery cooling fan.

[0116] The communication system including the semiconductor device 1 and the motor driver 1001 (SPI device) and the motor 60 may be used to drive any of the electronic devices X11 to X18. If the vehicle X is an electric vehicle or a hybrid vehicle, the motor driver 1001 may be used as a means for controlling a motor for driving the wheels.

[0117] <8.Other> In addition to the above-described embodiments, the various technical features disclosed in this specification can be modified in various ways without departing from the spirit of the technical creation. In other words, the above-described embodiments should be considered to be illustrative and not restrictive in all respects, and the technical scope of the present invention should not be limited to the above-described embodiments, but should be understood to include all modifications that fall within the meaning and scope equivalent to the claims.

[0118] <9. Notes> As described above, the semiconductor device (1) according to one embodiment of the present disclosure is A first input terminal (1A), a first output terminal (1B); A second output terminal (1C); A second input terminal (1D), a first receiving unit (11) configured to be able to receive received data (RX), which is serial data, from an external transmitting device (20) via the first input terminal; a first transmitting unit (12) configured to be connectable to an external first device (100) via the second output terminal; a second receiving unit (13) configured to be connectable to the first device via the second input terminal; a second transmitting unit (14) configured to be connectable to the transmitting device via the first output terminal; a buffer (152); the first receiving unit and the first transmitting unit are configured to, when bridge selection data (BR) included in the received data indicates on of a through output that outputs bit data as is, through output the data for the first device (SPDT) included in the received data from the second output terminal; The transmission data (BTX) received by the second receiving unit via the second input terminal during the through output of the reception data is stored in the buffer; The transmission data read from the buffer after the through output of the reception data is output by the second transmission unit via the first output terminal (first configuration).

[0119] With the above configuration, full duplex communication can be performed between the semiconductor device and the first device that supports a different protocol, thereby effectively configuring a communication system using the semiconductor device and the device that supports a different protocol.

[0120] In addition, in the first configuration, in a write process for writing to a register (151) included in the semiconductor device, the received data may include data for write and data for CRC check, and the buffer may be used to temporarily store the data for write (second configuration).

[0121] In addition, in the first or second configuration, the mode may be configured to be switchable between a full duplex mode in which the transmission data is transmitted from the first device when the reception data is output through, and a half duplex mode in which the transmission data is transmitted from the first device after the reception data is output through (third configuration).

[0122] Furthermore, any of the first to third configurations may be configured to include a clock signal output unit (17) configured to output a clock signal (SCK) so that the falling edge or rising edge is at the center of the bit of the received data that is output through (fourth configuration).

[0123] Furthermore, in any of the first to fourth configurations, the received data may include first frame number information indicating the number of frames for which the received data is to be output through, and second frame number information indicating the number of frames that is twice the number of frames indicated by the first frame number information (fifth configuration).

[0124] In addition, in any of the first to fifth configurations, a start bit and a stop bit may be added to the transmission data read from the buffer to form a frame, and the frame may be output via the first output terminal (sixth configuration).

[0125] In addition, in any of the above first to sixth configurations, the serial communication method between the transmitting device and the semiconductor device may be UART, and the serial communication method between the first device and the semiconductor device may be SPI (seventh configuration).

[0126] Another aspect of the present disclosure is a communication system (eighth configuration) including the semiconductor device having any one of the first to seventh configurations, the transmitting device, and the first device.

[0127] In the eighth configuration, a differential voltage type transceiver (30, 40) may be provided between the transmitting device and the semiconductor device (ninth configuration).

[0128] In the eighth or ninth configuration, the first device may be configured as a motor driver (1001) (tenth configuration).

[0129] Furthermore, the tenth configuration may be configured to be mountable on a vehicle (X) (eleventh configuration). [Industrial Applicability]

[0130] The present disclosure can be used, for example, in communication systems for various applications. [Explanation of symbols]

[0131] 1. Semiconductor device 1A RX terminal 1B TX terminal 1C RXD terminal 1D TXD terminal 1E CS terminal 1F SCK terminal 10 devices 10A RX terminal 10B TX terminal 11 First receiving unit 12 First transmission unit 13 Second receiving unit 14 Second transmission unit 15 Control Unit 16 Chip select signal output section 17 Clock signal output section 30,40 CAN transceiver 30A TXD terminal 30B RXD terminal 35 CAN bus 40A RXD terminal 40B TXD terminal 50 Communication Systems 55 Communication Systems 60 stepping motor 61,62 Excitation coil 63 Rotor 100 SPI devices 100A RX terminal 100B TX terminal 100C CS terminal 100D SCK terminal 1001 Motor Driver 1001A SPI communication section 1001B Control logic section 1001C Pre-driver 1001D, 1001E Half Bridge 151 registers 152 buffers 301,302 CAN transceiver 401,402 CAN transceiver 501,502 Communication Systems BS1, BS2 bus OUT1A, OUT1B, OUT2A, OUT2B output terminals X vehicle X11~X18 Electronic equipment

Claims

1. a first input terminal; a first output terminal; a second output terminal; a second input terminal; a first receiving unit configured to be able to receive reception data, which is serial data, from an external transmitting device via the first input terminal; a first transmitting unit configured to be connectable to an external first device via the second output terminal; a second receiving unit configured to be connectable to the first device via the second input terminal; a second transmitting unit configured to be connectable to the transmitting device via the first output terminal; a buffer; the first receiving unit and the first transmitting unit are configured to, when bridge selection data included in the received data indicates an on state of through output for outputting bit data as is, through output the data for the first device included in the received data from the second output terminal; the transmission data received by the second receiving unit via the second input terminal during through output of the reception data is stored in the buffer; The transmission data read from the buffer after the through output of the reception data is output by the second transmission unit via the first output terminal.

2. 2. The semiconductor device according to claim 1, wherein in a write process for writing to a register included in the semiconductor device, the received data includes data for write and data for CRC check, and the buffer is used to temporarily store the data for write.

3. 2. The semiconductor device according to claim 1, wherein the semiconductor device is configured to be switchable between a Full Duplex mode in which the transmission data is transmitted from the first device when the reception data is through-output, and a Half Duplex mode in which the transmission data is transmitted from the first device after the reception data is through-output.

4. 2. The semiconductor device according to claim 1, further comprising a clock signal output section configured to output a clock signal so that a falling edge or a rising edge is positioned at the center of a bit of said received data that is output through.

5. 2. The semiconductor device according to claim 1, wherein the received data includes first frame number information indicating a number of frames for which the received data is to be through-output, and second frame number information indicating a number of frames that is twice the number of frames indicated by the first frame number information.

6. 2. The semiconductor device according to claim 1, wherein a start bit and a stop bit are added to the transmission data read from the buffer to form a frame, and the frame is output via the first output terminal.

7. 2. The semiconductor device according to claim 1, wherein a method of serial communication between said transmitting device and said semiconductor device is UART, and a method of serial communication between said first device and said semiconductor device is SPI.

8. 8. A communication system comprising: the semiconductor device according to claim 1; the transmitting device; and the first device.

9. 9. The communication system according to claim 8, wherein a transceiver of a differential voltage system is provided between said transmitting device and said semiconductor device.

10. The communication system of claim 8 , wherein the first device is configured as a motor driver.

11. The communication system according to claim 10, which is mountable in a vehicle.

Images