Receiver synchronization

Abstract

A receiver circuit includes a feedback loop (390, 391, 392) including a device. The receiver circuit also includes a register and a sequencer (340). The sequencer (340) is configured to cause the register to store a value indicative of a state of the feedback loop in response to an error signal being below a threshold. The sequencer (340) is also configured to cause the feedback loop to transition to a lower power state and, in response to a detected wake-up event, cause the previously stored value indicative of the state of the feedback loop (390, 391, 392) to be loaded from the register into the device and enable the feedback loop.

Description

Background Technology

[0001] Energy-efficient Ethernet (EEE) is the ability of the Ethernet physical layer (PHY) at both ends of a communication link to conserve power during periods of low link utilization. When the control software determines that data transmission via the communication link is unnecessary, it issues a Low Power Idle (LPI) request to the Ethernet controller PHY. The PHY then sends an LPI symbol to the link for a specified time, and subsequently, both PHYs at both ends of the link enter a low-power state. The transmitter PHY periodically sends refresh signals to attempt to maintain link signaling integrity. When data transmission is required, a normal idle signal is sent within a predetermined time period. The receiver responds by transitioning its PHY from a low-power state to a fully operational state. Summary of the Invention

[0002] In one example, a method includes: storing a feedback loop state value in response to an error signal falling below a threshold. The method further includes: switching a device within the feedback loop to a lower power state; detecting a wake-up event; and, in response to the detected wake-up event, loading the previously stored feedback loop state value and enabling the feedback loop.

[0003] In another example, a receiver circuit includes a feedback loop comprising a device. The receiver circuit also includes a register and a sequencer. The sequencer is configured to, in response to an error signal falling below a threshold, cause the register to store a value indicating the state of the feedback loop. The sequencer is also configured to cause the feedback loop to transition to a lower power state, and in response to a detected wake-up event, cause the previously stored value indicating the state of the feedback loop to be loaded from the register into the device and the feedback loop to be enabled. Attached Figure Description

[0004] To illustrate the various examples in detail, reference will now be made to the accompanying drawings, in which:

[0005] Figure 1 The diagram illustrates two devices 110 and 120 that communicate with each other via a communication link.

[0006] Figure 2 This diagram illustrates an example of the timing sequence between two devices communicating via a communication link.

[0007] Figure 3 This diagram illustrates an example of at least a portion of the circuitry of a receiver for an Ethernet physical interface (PHY).

[0008] Figure 4 This example demonstrates a portion of the timing loop within the receiver's circuitry.

[0009] Figure 5This example demonstrates a portion of the decision feedback equalization loop within the receiver's circuitry.

[0010] Figure 6 The diagram illustrates an example of the order used to customize the mean squared error threshold.

[0011] Figure 7 This diagram illustrates an example of the state diagram of the sequencer within the receiver's circuit system. Detailed Implementation

[0012] Figure 1 The diagram illustrates two devices 110 and 120 communicating with each other via a communication link 115 (e.g., Ethernet). Each device has a PHY. Device 110 has a PHY 111 and device 120 has a PHY 121. Devices 110 and 120 use their respective PHYs to send and receive packets back and forth. If a device (e.g., device 110) does not have data to transmit, then according to the protocol (EEE) described above, both PHYs can be caused to enter a lower power state (i.e., consuming less power than in a fully operational state).

[0013] Figure 2 The diagram illustrates the timing sequence of two Ethernet-enabled devices entering the LPI state during the time period when transmitting packets without crossing the communication link. Figure 2 The diagram illustrates two operational states, 201 and 203, separated by LPI state 202. When operational state 201 ends, the control software of a device (110 or 120) sends an LPI request to its PHY (111, 121), which then transmits an LPI symbol for a specified time (Ts) onto the link. During LPI state 202, some of the analog and / or digital components of the transmitting and receiving PHYs are in a power-off state and / or a low-power consumption operating mode to conserve power. Furthermore, during LPI state 202, a refresh cycle 205 occurs at intervals defined by Tq. In one example, Tq is 20 milliseconds (ms) to 22 ms, and therefore a refresh cycle occurs every 20 ms to 22 ms during LPI state 202. Each refresh cycle is Tr seconds wide (e.g., 200 microseconds to 220 microseconds). Each refresh cycle involves one PHY sending one or more symbols via a link to wake up another PHY and attempt to resynchronize its feedback loop (e.g., adjust its gain settings, equalizer filter coefficients, etc.). The Ts time period is the maximum time during which a PHY can transition to a lower power state (e.g., sleep).

[0014] When data needs to be transmitted during LPI state 202, the transmitting device sends a normal idle signal within a predetermined time period to wake up the receiver PHY. The receiver PHY responds by transitioning from its low-power state to a fully operational state. The time period Tw is the period during which the receiver PHY must transition to a fully operational state. During the relatively short Tw time period, the receiver PHY resynchronizes its internal feedback loops and equalizer states. Given the complexity of the receiver PHY, some receiver PHYs may not be able to resynchronize their states within a sufficient time to meet the Tw specification. In one instance, Tw is 30 to 35 microseconds, meaning that the receiver PHY should be fully operational and ready to receive data within 35 microseconds. The PHY has multiple feedback loops, such as those described below, and each feedback loop takes time to reach a locked state (i.e., a steady state). The loops operate in parallel, and noise on the first loop can increase the time it takes for the second loop to reach its locked state.

[0015] Figure 3 This diagram illustrates an example of at least a portion of the receiver circuitry system for an Ethernet PHY. Figure 3 Examples include a high-pass filter (HPF) 302, a programmable gain amplifier (PGA) 304, an analog-to-digital converter (ADC) 306, an energy detector 308, a phase interpolator 309, and a digital signal processor (DSP) 310. The DSP 310 includes a coarse automatic gain control (CAGC) 312, a DC cutoff 314, a mixer 316, a digital equalizer (DEQ) 318, a feedforward equalizer (FFE) 320, a summer 322, a slicer 324, a decision feedback equalizer (DFE) 326, a gain circuit 327, a mean square error (MSE) 328, a timing error detector (TED) 330, a loop filter 332, a numerically controlled oscillator 334, and a sequencer 340. These will be described below. Figure 3 The example receiver circuitry includes multiple feedback loops—timing loop 390, digital gain loop 391, and DFE loop 392. The feedback loops described below include timing loop 390, digital gain loop 391, and DFE loop 392. The loops typically operate in parallel, and an error in one loop can detrimentally affect the speed at which another loop reaches its locked state. For example, an error in DFE loop 392 can cause timing loop 390 to take extra time to lock. Various techniques for reducing the time required for the receiver circuitry to resynchronize its loops after a wake-up event are also described below.

[0016] In addition to other possible components, timing loop 390 also includes slicer 324, TED 330, loop filter 332, NCO 334, and phase interpolator 309. In addition to other possible components, digital gain loop 391 also includes mixer 316, DEQ 318, FFE 320, slicer 324, and gain circuit 327. In addition to other possible components, DFE loop 392 also includes slicer 324, DFE 326, and summer 322.

[0017] HPF 302 includes input 301 and output 303. A receive (Rx) signal 300 is provided to input 301 of HPF 302. HPF 302 high-pass filters the RX signal and provides the filtered output signal from its output 303 to input 305 of PGA 304. PGA 304 has a gain programmable via control signal 313 from CAGC 312. Control signal 313 can provide multiple bit values ​​to PGA 304 to specify a particular gain setting for the PGA. PGA 304 has multiple programmable gain settings based on control signal 313. CAGC 312 generates control signal 313 based on the magnitude of the digital signal from the output of ADC 306. Output 307 of PGA 304 is coupled to input of ADC 306. ADC 306 converts the output signal from PGA 304 into a digital representation (digital signal 317). The clock (CLK) 321 provided to the ADC 306 by the phase interpolator 309 is used by the ADC for timing its conversion of the signal from the PGA into a digital signal 317. Accordingly, CLK 321 instructs the ADC 306 when it should sample its input analog signal from the PGA 304. The frequency and phase of CLK 321 are continuously adjusted by the timing loop 390 to ensure that the output signal of the PGA is sampled by the ADC 306 at a suitable eye opening point (e.g., the middle of the eye).

[0018] The output 311 of ADC 306 is coupled to input 315 of DC removal 314 and to CAGC 312. DC removal 314 adjusts the DC level of the digital output signal 317 of the ADC to remove any DC offset. Digital gain loop 391 boosts the magnitude of the digital signal from ADC 306 to an appropriate level so that slicer 324 can make the correct output decision. DEQ 318 performs digital equalization, which uses the inverse of the channel impulse response to filter the digital signal to remove high-frequency noise. Feedforward equalization implemented by FFE 320 is used to eliminate residual preamble inter-symbol interference (ISI) present in the signal. The output 331 of FFE 320 is coupled to input 333 of summer 322. Summer 322 has another input to which output 341 of DFE 326 is coupled. Summer 322 subtracts the output from DFE 326 from the output from FFE 320. The summed output signal (x(n)) is provided to the input 337 of the slicer 324 by the output 335 of the summer 322. The slicer 324 includes a comparator that outputs a decision (e.g., -1, 0, +1) based on the input x(n) of the slicer 324. The output 343 of the slicer 324 is coupled to the corresponding inputs of the DFE 326, the gain circuit 328, the MSE circuit 328, and the TED 330. The DFE 326 includes another equalization filter that eliminates ISI caused by the previous decision symbol, also known as post-symbol ISI equalization. The MSE circuit 328 determines the output signal of the slicer (x(n)). The mean square error (MSE) of the input signal (x(n)) is given by the sequencer 340, and the output MSE value is 345. The MSE value 345 is a measure of the noise on the input signal Rx and is provided to the sequencer 340.

[0019] The output 343 of slicer 324 is coupled to the input of a first-in-first-out (FIFO) buffer 382 that stores the decisions from slicer 324. The output of FIFO buffer 382 is coupled to the input of descrambler 383. The output of descrambler 383 is provided to the subsequent decoder stage (not shown) of the receiver's PHY. In response to descrambler 383 achieving its own lock state, descrambler 383 asserts a descrambler lock signal 384 toward sequencer 340. Sequencer 340 uses descrambler lock signal 384 to control state transitions implemented by sequencer 340 (e.g., from a waiting state to a stable state, such as...). Figure 7 (The diagrams and descriptions below illustrate this point.)

[0020] TED 330 receives slicer output The input of TED 330 is coupled to the output of multiplexer 336. Multiplexer 336 has 0-input and 1-input. The 0-input is coupled to the output of FFE 320 and the 1-input of multiplexer 336 is coupled to the input 337 of slicer 324. Therefore, TED 330 receives either the output signal of FFE or the input signal of slicer via multiplexer 336. Sequencer 340 controls multiplexer 336 via control signal 347. If the output of FFE is selected to be provided to TED 330, then the input signal does not include DFE correction. On the other hand, if the input of slicer (the output of summer 322) is selected to be provided to TED 330, then the input signal ( Includes DFE correction.

[0021] The TED 330 estimates timing errors by estimating the ISI between the current symbol and the previous symbol. The TED 330 attempts to bring the ISI to zero to lock onto a suitable eye opening point. The output 339 of the TED 330 is coupled to a loop filter 332. The loop filter 332 filters the timing error value from the TED 330. The filtered timing error value from the loop filter 332 is then provided to the NCO 334, which generates rising / falling pulses. The rising / falling pulses are provided to a phase interpolator 309. In response to the rising / falling pulses, the phase interpolator adjusts the phase of the CLK 321 in incrementing steps. In one embodiment, the phase interpolator 309 is a 6-bit interpolator providing 64 steps. The phase interpolator responds to rising pulses by lagging the clock signal. In response to falling pulses, the phase interpolator causes the phase of the clock signal to lead.

[0022] Energy detector 308 is a voltage comparator that compares the voltage of the input signal (RX input) with a threshold voltage to determine the presence or absence of the signal. In response to the RX input voltage exceeding the threshold, energy detector 308 asserts a wake-up signal 381 to sequencer 340 to indicate the presence of the input signal. As will be described below, sequencer 340 responds to the asserted wake-up signal 381 to control the timing loop, digital gain loop, and DFE loop during the time period during which they reach their locked states.

[0023] In LPI phase 202 ( Figure 2During this period, every Tq seconds (e.g., 20 ms to 22 ms), the transmitter initiates refresh cycle 205. During each refresh cycle, the DFE loop, digital gain loop, and timing loop are enabled for a short time period (e.g., 200 microseconds to 220 microseconds). However, this time period may be short enough that any given feedback loop within the receiver's PHY may not have sufficient time to fully calm down to a steady-state level (also known as a locked state). When this occurs, the refresh cycle terminates if there is a residual error in one or more of the loops. After the refresh cycle ends, the loop is frozen, for example, meaning that the clock to the loop stops and the loop's state no longer advances. Any residual error present in the loop while the loop's state is frozen persists in the loop and thus carries over to the next refresh cycle or wake-up event. The described example reduces or avoids the accumulation of residual errors.

[0024] Figure 4 A portion of timing loop 390 is shown, including TED 330, loop filter 332, and NCO 334. Loop filter 332 includes a proportional signal path 402 and an integral signal path 404, each containing variable gains labeled Kp and Kf, respectively. Adder 430 adds the signal from proportional signal path 402 to the signal from integral signal path 404 to produce an error value (in...). Figure 4 (Shown as FREQ 425), the error value indicates the frequency at which the ADC 306 is clocked for sampling and converting the analog signal from the PGA 304. The integration signal path 404 includes an accumulator 410 and a register 420. The accumulator 410 includes a summer 411 and a register 412. The output of register 412 is added to the next value and updated from the summer 411, used to overwrite the current register value.

[0025] When sequencer 340 detects that the MSE value 345 from MSE circuit 328 has fallen below the MSE threshold 365 stored in the sequencer or otherwise accessible by the sequencer, the sequencer asserts that the control signal 361 (shown in) goes to register 420. Figure 3 and 4The current FREQ value 425, being accumulated by accumulator 410, is stored in the register 410. When the MSE value is less than a threshold, the FREQ value 425 from the accumulator is a "good" frequency value, meaning that the frequency value present in the receiver circuitry has a sufficiently high SNR. Register 420 holds this frequency value until a wake-up event occurs (signaled by control signal 361 from sequencer 340 to loop filter 332), at which point the frequency value from register 420 is loaded into accumulator 410. Timing loop 390 thus begins its synchronization process (to achieve its locked state) immediately after the wake-up event, with loop filter 332 loaded with the frequency value previously determined to be used when the timing loop is at a stable state level.

[0026] Decision feedback equalization (implemented by DFE 326) eliminates the postscript ISI present in the received signal and thereby reduces the noise present at the slicer input due to postscript ISI. DFE 326 includes a FIFO buffer storing N previous decisions. Individual decisions are multiplied by individual coefficients, which represent the equivalent value of the postscript ISI weight added to the current signal by the individual decision.

[0027] Figure 5 This demonstrates the approach used for DFE circuit 392, which is similar to the one described above. Figure 4 The technology described in the text is similar to that described in the text. Figure 5 At least a portion of the DFE loop 392 is shown, including a DFE 326, an adder 322, and a slicer 324. The DFE 326 includes an accumulator for accumulating the DFE coefficients. When the sequencer 340 determines that the MSE value is less than a previously mentioned threshold, a control signal 361 causes the DFE coefficients 525 to be stored in register 520. The DFE coefficients stored in register 520 are immediately loaded into accumulator 510 after a subsequent wave event, causing the DFE loop to be synchronized from the initial DFE coefficients determined during previous steady-state operation of the DFE loop 392.

[0028] The Ethernet protocol supports the use of cables of different lengths between two devices (e.g., devices 110 and 120). Ethernet cables can be up to, for example, 200 meters long. Longer cable lengths result in lower SNR compared to shorter cable lengths. In the described example, the MSE threshold 365 used by sequencer 340 is customized based on the cable length between the transmitter and receiver. For longer cable lengths and therefore smaller received signal values, CAGC 312 programs PGA 304 with a higher gain setting, and for shorter cable lengths, CAGC 312 programs the PGA with a lower gain setting due to the higher received signal value. In at least one example, as a proxy for cable length, sequencer 340 uses the gain setting programmed into PGA 304 by CAGC 312 to determine the MSE threshold 365. Figure 3 In one example, sequencer 340 includes a lookup table (LUT) 367 for storing the mapping between gain settings and MSE thresholds. Based on control signals 313 from CAGC 312 to PGA 304 (which sets the PGA gain), sequencer 340 accesses LUT 367 to determine the corresponding MSE threshold and stores the specific MSE threshold as MSE threshold 365 for controlling specific loops as described herein (e.g., those described above regarding...). Figure 4 and 5 Synchronization of the described timing loop 390 and DFE loop 392.

[0029] Figure 6 The diagram illustrates that CAGC 312 provides a channel length estimate to sequencer 340. The channel length estimate may include control signals 313 from CAGC 312. At 610, sequencer 340 selects an MSE threshold based on the channel length estimate using, for example, LUT 367. At 615, sequencer 340 determines whether the current MSE value 345 from MSE circuitry 328 is less than the threshold. If the current MSE value drops below the threshold, a loop state value is stored. For example, the stored loop state value is a frequency value in loop filter 332 and / or a DFE coefficient as described above.

[0030] As described above, an error in one loop can harmfully affect the other. For example, an error in the DFE loop can affect the timing loop. The accumulation of residual errors in DFE loop 392 can lead to incorrect back-index ISI estimation, which in turn leads to incorrect noise correction at the slicer input and output. This noisy slicer input, when provided to timing loop 390, can then harmfully affect the timing loop feedback path behavior, causing it to lock onto a point far from the appropriate eye opening point. This problem is addressed by using multiplexer 336 ( Figure 1This is resolved by... In response to a wake-up event, sequencer 340 asserts control signal 347 to multiplexer 336 to select 0-input (the output signal from FFE 320 before summer 322 and therefore not DFE-corrected). In response to timing loop 390 achieving its locked state (which can be determined based on MSE value 345 being below a predetermined threshold), sequencer 340 asserts control signal 347 to cause multiplexer 336 to select its 1-input, which causes signal x(n) after summer 322 and therefore DFE-corrected to be provided to TED 330. During the locked phase, TED determines the timing error value based on the input (FFE output signal) that is unaffected by the DFE loop and therefore unaffected by any errors that may exist in the DFE loop. In the absence of any errors from the DFE loop, the timing loop will typically calm down faster than if TED 330 always uses the DFE-equalized value x(n). During the post-locked phase, the TED 330 receives the slicer input (which includes DFE correction) and the TED then determines the timing error value based on the input, which is at least partially affected by the DFE loop 392.

[0031] Ideally, the receiver's signal is received and converted into a symbol within the symbol interval. However, when the signal travels through a lossy communication link, the conversion to a symbol extends to adjacent intervals. This effect is called inter-symbol interference (ISI). Post-symbol ISI refers to the effect of signals received in the symbol period preceding the current symbol on the current slicer's decision. Pre-symbol ISI refers to the effect of signals received in the symbol period following the current symbol on the current slicer's decision. In one implementation of the timing error detector, the timing error detector implements logic to balance post-symbol ISI and pre-symbol ISI as shown in Equation (1):

[0032] (1)

[0033] As described above, x(n) and x(n-1) are the input signals to slicer 324 during symbol periods n and n-1, respectively. and This is the output decision of slicer 324. The first term in equation (1) It is the suffix ISI and the second item It is preceded by ISI.

[0034] During a wake-up event, if the initial sampling interval happens to occur approximately midway through the symbol period, the magnitudes of the pre-index ISI and post-index ISI components can be relatively large and approximately equal. Since the pre-index ISI is subtracted from the post-index ISI in Equation (1), the timing error detection value (TED in Equation 1 above) will be smaller. Because the timing error detection value will be smaller initially when the timing loop attempts to converge to a steady-state level, the TED 330 will have a relatively low gain and therefore take a substantially longer time to converge to the locked state.

[0035] However, Figure 3 The TED 330 implements a first timing error detection technique when attempting to achieve its locked state and a second timing error detection technique after achieving its locked state. The first timing error detection technique determines the timing error detection value based on suffix ISI but not on prefix ISI. This suffix-only ISI technique is used when the timing error loop begins to converge to achieve the locked state. When attempting to achieve the locked state, the TED 330 implements suffix-only ISI according to the following Equation 2:

[0036] (2)

[0037] Alternatively, the ISI values ​​of only the postscript in equation (2) can be averaged together to generate the timing error value.

[0038] Control signal 371 from sequencer 340 to TED 330 ( Figure 1 This causes TED to implement post-index ISI in response to an assertion from wake-up signal 381 from energy detector 308 to initially reach a locked state. Once timing loop 390 reaches its locked state, sequencer 340 changes the logic level of control signal 371 to cause TED 330 to balance both the pre-ISI and post-ISI shown in equation (1) above.

[0039] Figure 7 The diagram illustrates an example of a state diagram implemented by sequencer 340. Sequencer 340 is an implementation... Figure 7The state diagram of the instance represents the logical state machine. At 705, the receiver is in an "idle" state, meaning there is no signal on the line from the other PHY or neither PHY has started transmitting a signal. At 710, the state diagram includes a training operation, during which the timing loop, digital gain loop, and DFE loop reach their respective locked states. At 720, the sequencer 340 is in a steady state. During the steady state, the sequencer 340 receives MSE value updates from the MSE circuit 328. Once the MSE value drops below a threshold 365, the state of the feedback loop is immediately stored. The feedback loop state may include a value indicating the frequency of the loop filter 332 and / or a value indicating the DFE coefficients of the DFE 326.

[0040] At 730, sequencer 340 enters the LPI freeze state. This state can be entered by determining through the transmitter's control software that data transmission to the receiver via the communication link is unnecessary and issuing an LPI request to the transmitter's Ethernet controller PHY. The transmitter's PHY then sends the LPI symbol for the specified time to the receiver and then deactivates its transmitter. The receiving PHY (e.g., Figure 3 The example receiver circuitry responds by entering a freeze state. A freeze state may involve powering off one or more analog components within the receiver circuitry (e.g., HPF 302, PGA 304, ADC 306, and phase interpolator 309). Additionally, timing loops, digital gain loops, and DFE loops are frozen (i.e., the clock is stopped, thereby preventing these loops from updating their states).

[0041] Once the energy detector 308 detects energy at the receiver's input, the sequencer 340 enters the LPI acquisition state 740. During the LPI acquisition state, previously stored feedback loop states (stored as a portion of state 720, such as the frequency of the indicator loop filter 332 and the value of the DFE coefficients of the DFE 326) are reloaded into their respective loops. Furthermore, in the LPI state, the sequencer 340 asserts the control signal 347 such that the multiplexer 336 selects a 0-input to provide the output signal of the FFE to the TED 330 instead of the input signal to the slicer containing the DFE-equalized value.

[0042] After the timing loop reaches the locked state, the sequencer 340 immediately enters the LPI recovery state 750, in which the remaining loops (digital gain loop and DFE loop) are enabled. The sequencer 340 also asserts the control signal 347 so that the multiplexer 336 selects its 1-input so that the slicer input value equalized by the DFE is provided as input to the TED 330.

[0043] The sequencer 340 then immediately enters the LPI wait state 760 after the predetermined timer expires. During the LPI wait state 760, the sequencer waits for the descrambler 383 to achieve lock. In response to the descrambler achieving its lock state (as indicated by the assertion of the descrambler lock signal 384), the sequencer 340 transitions back to the steady state 720.

[0044] If the energy detector 308 stops detecting energy exceeding the threshold during any of the LPI acquisition state 740, LPI recovery state 760, or LPI waiting state 760, then the sequencer 340 will change the state back to the LPI frozen state 730.

[0045] The term "coupled" is used throughout this specification. This term can cover a connection, communication, or signaling path that achieves a functional relationship consistent with this specification. For example, if device A generates a signal to control device B to perform an action, then in a first instance, device A is coupled to device B; or in a second instance, if intervening component C substantially does not alter the functional relationship between device A and device B such that control signals generated by device B via device A are controlled by device A, then device A is coupled to device B via intervening component C.

[0046] Modifications are possible in the described embodiments, and other embodiments are possible within the scope of the claims.

Claims

1. A method for synchronizing a communication system, comprising: In response to an error signal falling below a threshold, a state value of a feedback loop is stored, wherein the feedback loop includes a loop filter, and wherein storing the state value of the feedback loop includes storing a value indicating a frequency error. The loop filter within the feedback loop is switched to a lower power state; and Detect wake-up events; In response to the detected wake-up event, the previously stored state value of the feedback loop is loaded; and Enable the feedback loop.

2. The method of claim 1, wherein the feedback loop further comprises a decision feedback equalizer, wherein storing the state value of the feedback loop further comprises storing values ​​indicating equalizer coefficients, and wherein the method further comprises switching the decision feedback equalizer within the feedback loop to a lower power state.

3. The method according to claim 1, wherein the error signal includes a mean square error value.

4. The method of claim 1, further comprising adjusting the threshold based on a value indicating the cable length.

5. The method of claim 4, wherein the value indicating the cable length includes a gain value.

6. The method of claim 5, wherein adjusting the threshold comprises increasing the threshold in response to an increase in the gain value.

7. The method of claim 1, further comprising: In response to the error signal being higher than a threshold, the timing error value is determined without performing decision feedback equalization; and In response to the error signal being lower than the threshold, the timing error value is determined while performing the decision feedback equalization.

8. The method of claim 1, wherein the feedback loop comprises a timing error detector (TED), and the method further comprises: Before the TED reaches a locked state, the timing error value is determined by the TED based on the interference between suffix symbols but not on the interference between prefix symbols; and After the TED reaches the locked state, the timing error value is determined by the TED based on both the interference between suffix symbols and the interference between prescript symbols.

9. A receiver circuit, comprising: The feedback loop includes a loop filter; Registers, which are coupled to the loop filter within the feedback loop; and A sequencer coupled to the loop filter within the feedback loop, the sequencer being configured to: In response to an error signal falling below a threshold, the register is caused to store the state value of the feedback loop, wherein storing the state value of the feedback loop includes storing a value indicating the frequency error; This causes the loop filter within the feedback loop to switch to a lower power state; In response to a detected wake-up event, the previously stored state value of the feedback loop is loaded from the register into the loop filter; and Enable the feedback loop.

10. The receiver circuit of claim 9, wherein the feedback loop further includes a decision feedback equalizer, wherein the state value of the feedback loop further includes a value indicating the equalizer coefficient, and wherein the sequencer is further configured to cause the decision feedback equalizer within the feedback loop to transition to a lower power state.

11. The receiver circuit according to claim 9, wherein the error signal includes a mean square error value.

12. The receiver circuit of claim 9, wherein the sequencer is configured to: Before the timing loop within the receiver circuit reaches a locked state, the timing loop is configured to determine the timing error value without decision feedback equalization; and In response to the timing loop reaching the locked state, the timing loop is configured to determine the timing error value while performing the decision feedback equalization.

13. The receiver circuit of claim 9, wherein the feedback loop includes a timing error detector (TED) coupled to the sequencer, and the sequencer is configured such that: Before the TED reaches a locked state, the TED determines the timing error value based on the interference between suffix symbols but not on the interference between prefix symbols; and After the TED reaches the locked state, the TED determines the timing error value based on both the interference between suffix symbols and the interference between prescript symbols.

14. A receiver circuit, comprising: The feedback loop includes a loop filter; A register, which is coupled to the loop filter within the feedback loop; and A sequencer coupled to the loop filter within the feedback loop, the sequencer being configured to: The threshold is adjusted based on the value indicating the cable length. In response to an error signal falling below the threshold, the register is caused to store the state value of the feedback loop, wherein storing the state value of the feedback loop includes storing a value indicating the frequency error; This causes the loop filter within the feedback loop to switch to a lower power state; In response to a detected wake-up event, the previously stored state value of the feedback loop is loaded from the register into the loop filter; and Enable the feedback loop.

15. The receiver circuit of claim 14, wherein the feedback loop further includes a decision feedback equalizer, wherein the state value of the feedback loop further includes a value indicating the equalizer coefficient, and wherein the sequencer is further configured to cause the decision feedback equalizer within the feedback loop to transition to a lower power state.

16. The receiver circuit of claim 14, wherein the error signal includes a mean square error value.

17. The receiver circuit of claim 14, further comprising automatic gain control circuitry, wherein the value indicating the cable length includes a gain value programmed into the automatic gain control circuitry.

18. The receiver circuit of claim 17, wherein the sequencer is configured to increase the threshold in response to an increase in the gain value.

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