Electronic device

Abstract

To provide an electronic device capable of providing a uniform driving voltage to pixels.SOLUTION: An electronic device includes a base substrate, a power line, a pixel unit including pixels each including a light emitting element, a contact electrode surrounding the light emitting element and disposed in a non-emission area, an interlayer insulating layer disposed between the power line and the contact electrode, and a groove overlapping the non-emission area and exposing at least a portion of the contact electrode. An interlayer insulating layer disposed on the interlayer insulating layer, wherein the second electrode is connected to the contact electrode in an area overlapping the groove, and the contact electrode is connected to the power line through a contact hole passing through the interlayer insulating layer.SELECTED DRAWING: Figure 7A

Description

[Technical Field]

[0001] The present invention relates to electronic devices, and more particularly to electronic devices with improved display quality. [Background technology]

[0002] Generally, electronic devices that provide images to users, such as smartphones, digital cameras, laptops, navigation systems, and smart televisions, include an electronic device for displaying images, which generates images and provides the generated images to users through a display screen.

[0003] The electronic device includes a plurality of pixels for generating an image and a plurality of lines connected to the pixels, the pixels being driven by receiving driving signals through the lines.

[0004] In large-sized electronic devices with large areas, such as tablets and smart TVs, differences in driving voltages transmitted to each pixel may occur, and a design that compensates for this difference is required. [Prior art documents] [Patent documents]

[0005] [Patent Document 1] Chinese Patent Application Publication No. 111969034 Summary of the Invention [Problem to be solved by the invention]

[0006] SUMMARY OF THE INVENTION An object of the present invention is to provide an electronic device capable of providing a uniform driving voltage to pixels. [Means for solving the problem]

[0007] According to an embodiment of the present invention, an electronic device includes a base substrate including a display region and a non-display region, each including a light-emitting region and a non-light-emitting region disposed between the light-emitting regions; a power line overlapping the display region and disposed on the base substrate; pixel units including pixels including light-emitting elements, each including a first electrode, a second electrode disposed on the first electrode, and a common layer disposed between the first electrode and the second electrode; contact electrodes surrounding the light-emitting elements and disposed in the non-light-emitting region; an interlayer insulating layer disposed between the power line and the contact electrode; and an interlayer insulating layer overlapping the non-light-emitting region, each including a groove exposing at least a portion of the contact electrode and disposed on the interlayer insulating layer, wherein the second electrode is connected to the contact electrode in a region overlapping the groove, and the contact electrode is connected to the power line through a contact hole penetrating the interlayer insulating layer.

[0008] The light-emitting device may further include a first sealing layer and a second sealing layer that cover the light-emitting element and contact each other in the light-emitting region and the non-light-emitting region, and the first sealing layer and the second sealing layer may include an inorganic material.

[0009] The pixel defining layer may further include a pixel defining layer including an inorganic material, an insulating layer between the pixel defining layer and the common layer, a via insulating layer including an organic material, and a protective layer disposed on the second electrodes, the pixel defining layer having openings that expose at least a portion of each of the first electrodes, and the via insulating layer, the pixel defining layer, the common layer, the second electrodes, and the protective layer being disconnected within the groove.

[0010] A sealing region of the pixel definition layer overlapping the non-emitting region and disposed between adjacent light-emitting elements may be exposed by the common layer, the second electrode, the protective layer, and the first sealing layer, and the pixel definition layer may be in contact with the second sealing layer in the sealing region.

[0011] The insulating layer may be disposed between the insulating layers, and the insulating layer may be disposed between the insulating layers.

[0012] The contact electrode may have a side surface adjacent to the light emitting region exposed from the insulating layer by a groove, and the second electrode may be in contact with the exposed side surface.

[0013] The side surface may have a predetermined curvature, and the contact electrode may contain molybdenum.

[0014] The semiconductor device may include a first pattern layer and a second pattern layer overlapping the contact electrode and sequentially stacked on the interlayer insulating layer, the first pattern layer and the second pattern layer including different inorganic materials.

[0015] A portion of the first pattern layer may be exposed from the second pattern layer.

[0016] The common layer may be in contact with a side surface of the portion of the first pattern layer and a side surface of the second pattern layer within the groove.

[0017] A portion of the insulating layer adjacent to the groove and disposed in the non-light-emitting region may protrude from the contact electrode in a direction toward the light-emitting region, and the portion may protrude upward to define a trench that defines a predetermined internal space.

[0018] The pixel defining layer may further include a dam pattern overlapping the non-light-emitting region and surrounding at least a portion of the light-emitting region, the dam pattern including a first pattern disposed on the pixel defining layer and a second pattern disposed on the first pattern.

[0019] The first pattern and the second pattern may include different inorganic materials, and the thickness of the first pattern may be greater than the thickness of the second pattern, and the width of the first pattern may be smaller than the width of the second pattern.

[0020] The common layer, the second electrode, and the protective layer disposed in the non-light-emitting region may be disconnected by the dam pattern, and the dam pattern may be covered by the first sealing layer and the second sealing layer.

[0021] A portion of an upper surface of the contact electrode may be exposed from the insulating layer by the groove, and the second electrode may be in contact with the exposed upper surface.

[0022] The contact electrode may include first to third conductive layers sequentially stacked on the interlayer insulating layer, the first conductive layer and the third conductive layer including titanium, and the second conductive layer including aluminum.

[0023] The side of the insulating layer defining the groove that overlaps the non-light-emitting region may have a predetermined curvature.

[0024] The pixel defining layer may further include a pixel defining layer including an inorganic material and disposed on the insulating layer between the first electrodes, the pixel defining layer having an opening that exposes at least a portion of each of the first electrodes, and an auxiliary electrode that is disposed on the insulating layer between the first electrodes and disposed in the non-light-emitting region and covered by the pixel defining layer, the auxiliary electrode being connected to the contact electrode through a contact hole defined in the pixel defining layer.

[0025] A portion of the upper surface of the contact electrode is exposed from the insulating layer therebetween by the groove, and a portion of the common layer is disposed on the upper surface exposed within the groove.

[0026] The second electrode may be disposed on the portion of the common layer within the groove, and a side of the auxiliary electrode adjacent to the light emitting region may be in contact with the second electrode.

[0027] The auxiliary electrode may include the same material as the first electrode.

[0028] The pixel may include a first pixel, a second pixel, and a third pixel that provide light of different colors, and the light emitting region may include a first light emitting region overlapping the first pixel and providing red light, a second light emitting region overlapping the second pixel and spaced apart from the first light emitting region along a first direction, extending along a second direction intersecting the first direction, and providing blue light, and a third light emitting region overlapping the third pixel and spaced apart from the first light emitting region along the second direction, and providing green light, wherein an area of ​​the first light emitting region is smaller than an area of ​​the second light emitting region and larger than an area of ​​the third light emitting region.

[0029] The pixels may include a 1-1 pixel, a 1-2 pixel, a 2nd pixel, and a 3rd pixel that provide light of different colors, and the light emitting regions may include a 1-1 light emitting region overlapping with the 1-1 pixel and providing green light, a 1-2 light emitting region overlapping with the 1-2 pixel and spaced apart from the 1-1 light emitting region along a first direction and providing the green light, a second light emitting region overlapping with the 2nd pixel and spaced apart from the 1-1 light emitting region along a diagonal direction of each of the 1-1 light emitting region and the 1-2 light emitting region and providing red light, and a third light emitting region overlapping with the 3rd pixel and spaced apart from the second light emitting region along a second direction intersecting the first direction and providing blue light, and each of the 1-1 to 3rd light emitting regions may have a rectangular shape.

[0030] One pixel may include sub-pixels that provide light of different colors, and one contact electrode may surround the sub-pixels included in the pixel. [Effects of the Invention]

[0031] According to an embodiment of the present invention, since each pixel in a display area is individually connected to a power supply line that supplies a driving voltage and a light emitting element, a constant driving voltage can be provided regardless of the size / area of ​​the display area, thereby providing an electronic device with improved reliability and reducing unnecessary area in the non-display area. [Brief explanation of the drawings]

[0032] [Figure 1A] 1 is a perspective view of an electronic device according to one embodiment of the present invention; [Figure 1B] 1 is a block diagram of an electronic device according to one embodiment of the present invention. [Figure 2] 1 is a cross-sectional view of an electronic device according to one embodiment of the present invention. [Figure 3] 1 is a cross-sectional view of a display panel according to an embodiment of the present invention; [Figure 4A] FIG. 2 is a block diagram of a display module according to one embodiment of the present invention. [Figure 4B] 4B is an equivalent circuit diagram of one of the pixels shown in FIG. 4A. [Figure 5A] FIG. 2 is a plan view of a pixel unit according to an embodiment of the present invention. [Figure 5B] FIG. 2 is a plan view of a pixel according to an embodiment of the present invention. [Figure 5C] FIG. 2 is a plan view of a pixel unit according to an embodiment of the present invention. [Figure 6] FIG. 5B is a cross-sectional view taken along line II' in FIG. 5A. [Figure 7A] FIG. 7 is an enlarged cross-sectional view of the area AA′ in FIG. 6. [Figure 7B] 1 is a cross-sectional view of a display panel according to an embodiment of the present invention; [Figure 7C] 1 is a cross-sectional view of a display panel according to an embodiment of the present invention; [Figure 7D] 1 is a cross-sectional view of a display panel according to an embodiment of the present invention; [Figure 8] FIG. 5B is a cross-sectional view taken along line II-II' in FIG. 5A. [Figure 9] FIG. 5B is a cross-sectional view taken along line III-III' in FIG. 5A. [Figure 10A] 1A to 1C are cross-sectional views illustrating a method of manufacturing a display panel according to an embodiment of the present invention. [Figure 10B] 1A to 1C are cross-sectional views illustrating a method of manufacturing a display panel according to an embodiment of the present invention. [Figure 10C] 1A to 1C are cross-sectional views illustrating a method of manufacturing a display panel according to an embodiment of the present invention. [Figure 10D] 1A to 1C are cross-sectional views illustrating a method of manufacturing a display panel according to an embodiment of the present invention. [Figure 10E] 1A to 1C are cross-sectional views illustrating a method of manufacturing a display panel according to an embodiment of the present invention. [Figure 10F] 1A to 1C are cross-sectional views illustrating a method of manufacturing a display panel according to an embodiment of the present invention. [Figure 10G] 1A to 1C are cross-sectional views illustrating a method of manufacturing a display panel according to an embodiment of the present invention. [Figure 10H] 1A to 1C are cross-sectional views illustrating a method of manufacturing a display panel according to an embodiment of the present invention. [Figure 10I] 1A to 1C are cross-sectional views illustrating a method of manufacturing a display panel according to an embodiment of the present invention. [Figure 10J] 1A to 1C are cross-sectional views illustrating a method of manufacturing a display panel according to an embodiment of the present invention. [Figure 10K] 1A to 1C are cross-sectional views illustrating a method of manufacturing a display panel according to an embodiment of the present invention. [Figure 11A] 1A to 1C are cross-sectional views illustrating a method of manufacturing a display panel according to an embodiment of the present invention. [Figure 11B] 1A to 1C are cross-sectional views illustrating a method of manufacturing a display panel according to an embodiment of the present invention. [Figure 11C] 1A to 1C are cross-sectional views illustrating a method of manufacturing a display panel according to an embodiment of the present invention. [Figure 11D] 1A to 1C are cross-sectional views illustrating a method of manufacturing a display panel according to an embodiment of the present invention. [Figure 11E] 1A to 1C are cross-sectional views illustrating a method of manufacturing a display panel according to an embodiment of the present invention. [Figure 11F] 1A to 1C are cross-sectional views illustrating a method of manufacturing a display panel according to an embodiment of the present invention. [Figure 11G] 1A to 1C are cross-sectional views illustrating a method of manufacturing a display panel according to an embodiment of the present invention. [Figure 12A] 1 is a cross-sectional view of a display panel according to an embodiment of the present invention; [Figure 12B] 1 is a cross-sectional view of a display panel according to an embodiment of the present invention; [Figure 13A] 1A to 1C are cross-sectional views illustrating a method of manufacturing a display panel according to an embodiment of the present invention. [Figure 13B] 1A to 1C are cross-sectional views illustrating a method of manufacturing a display panel according to an embodiment of the present invention. [Figure 13C] 1A to 1C are cross-sectional views illustrating a method of manufacturing a display panel according to an embodiment of the present invention. [Figure 13D] 1A to 1C are cross-sectional views illustrating a method of manufacturing a display panel according to an embodiment of the present invention. [Figure 13E] 1A to 1C are cross-sectional views illustrating a method of manufacturing a display panel according to an embodiment of the present invention. [Figure 13F] 1A to 1C are cross-sectional views illustrating a method of manufacturing a display panel according to an embodiment of the present invention. [Figure 13G] 1A to 1C are cross-sectional views illustrating a method of manufacturing a display panel according to an embodiment of the present invention. [Figure 14] 1 is a cross-sectional view of a display panel according to an embodiment of the present invention; [Figure 15A] 1A to 1C are cross-sectional views illustrating a method of manufacturing a display panel according to an embodiment of the present invention. [Figure 15B] 1A to 1C are cross-sectional views illustrating a method of manufacturing a display panel according to an embodiment of the present invention. [Figure 15C] 1A to 1C are cross-sectional views illustrating a method of manufacturing a display panel according to an embodiment of the present invention. [Figure 15D] 1A to 1C are cross-sectional views illustrating a method of manufacturing a display panel according to an embodiment of the present invention. [Figure 15E] 1A to 1C are cross-sectional views illustrating a method of manufacturing a display panel according to an embodiment of the present invention. [Figure 15F]1A to 1C are cross-sectional views illustrating a method of manufacturing a display panel according to an embodiment of the present invention. [Figure 15G] 1A to 1C are cross-sectional views illustrating a method of manufacturing a display panel according to an embodiment of the present invention. [Figure 15H] 1A to 1C are cross-sectional views illustrating a method of manufacturing a display panel according to an embodiment of the present invention. [Figure 15I] 1A to 1C are cross-sectional views illustrating a method of manufacturing a display panel according to an embodiment of the present invention. [Figure 16] 1 is a cross-sectional view of a light-emitting device according to an embodiment of the present invention. DETAILED DESCRIPTION OF THE INVENTION

[0033] In this specification, when a certain component (or region, layer, portion, etc.) is described as being "on," "coupled," or "bonded" to another component, it means that it can be directly disposed / coupled / bonded to the other component, or that a third component can be disposed therebetween.

[0034] The same reference numerals refer to the same elements. Also, in the drawings, thickness, ratio, and size of elements are exaggerated for efficient explanation of technical content. "And / or" includes all one or more combinations that the associated elements can define.

[0035] Terms such as "first," "second," etc. may be used to describe various components, but the components should not be limited by these terms. These terms are used only to distinguish one component from another. For example, a first component may be referred to as a "second component," and similarly, a second component may be referred to as a "first component" without departing from the scope of the present invention. A singular expression includes a plural expression unless the context clearly dictates otherwise.

[0036] Furthermore, terms such as "under," "below," "on," and "above" are used to describe the relationship between components shown in the drawings. These terms are relative concepts and are described based on the directions shown in the drawings.

[0037] It should be understood that the use of terms such as "comprises" or "having" is intended to specify the presence of a stated feature, number, step, operation, component, part, or combination thereof, but does not preclude the presence or possible addition of one or more other features, numbers, steps, operations, components, parts, or combinations thereof.

[0038] Unless otherwise defined, all terms (including technical and scientific terms) used herein have the same meaning as commonly understood by those skilled in the art to which this invention belongs. Furthermore, terms such as those defined in commonly used dictionaries should be interpreted as having a meaning consistent with the meaning they have in the context of the relevant art, and should not be interpreted as being overly ideal or overly formal unless explicitly defined herein.

[0039] Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings.

[0040] FIG. 1A is a perspective view of an electronic device according to an embodiment of the present invention. FIG. 1B is a block diagram of an electronic device according to an embodiment of the present invention. FIG. 2 is a cross-sectional view of an electronic device according to an embodiment of the present invention. FIG. 3 is a cross-sectional view of a display panel according to an embodiment of the present invention. FIG. 4A is a block diagram of a display module according to an embodiment of the present invention. FIG. 4B is an equivalent circuit of one of the pixels shown in FIG. 4A.

[0041] 1A , an electronic device DD according to an embodiment of the present invention may have long sides extending parallel to a first direction DR1 and short sides extending parallel to a second direction DR2 intersecting the first direction DR1. Corners of the electronic device DD connecting the long and short sides may have a curved shape. Corners of the electronic device DD having a curved shape may be defined as rounded corners. The shape of such an electronic device DD may be defined as a rounded-corner rectangle. However, this is merely an example of the shape of an electronic device DD and is not limited to a rounded-corner rectangle.

[0042] Hereinafter, a direction substantially perpendicular to the plane defined by the first direction DR1 and the second direction DR2 is defined as a third direction DR3. In addition, in this specification, the meaning of "in plan view" is defined as a state viewed from the third direction DR3.

[0043] The front surface of the electronic device DD may be defined as a display surface DS, which may have a plane defined by a first direction DR1 and a second direction DR2. An image IM generated by the electronic device DD may be provided to a user through the display surface DS.

[0044] The display surface DS may include a display area DA and a non-display area NDA surrounding the display area DA. The display area DA may display an image, while the non-display area NDA may not display an image. The non-display area NDA may surround the display area DA and define a border of the electronic device DD that is printed in a predetermined color.

[0045] The display area DA may have a rounded-corner rectangular shape depending on the shape of the electronic device DD. For example, the display area DA may include rectangular sides extending in a first direction DR1 and a second direction DR2 and rounded corners connecting the sides. Among the four sides, the side extending in the first direction DR1 may be defined as a long side, and among the four sides, the side extending in the second direction DR2 may be defined as a short side.

[0046] The electronic device DD can detect inputs applied from outside the electronic device DD. For example, the electronic device DD can detect a first input by a touch pen PEN and a second input by a touch TC. The touch pen PEN can be defined as an input device.

[0047] The touch pen PEN can be an active pen that outputs a signal. The second input by the touch TC can include various forms of external input, such as a part of the user's body, light, heat, or pressure.

[0048] The electronic device DD and the touch pen PEN can communicate in both directions. The electronic device DD can provide an uplink signal to the touch pen PEN. For example, the uplink signal can include information such as panel information and protocol version, but is not limited thereto.

[0049] The touch pen PEN can provide a downlink signal to the electronic device DD. The downlink signal can include a synchronization signal or status information of the touch pen PEN. For example, the downlink signal can include, but is not limited to, coordinate information of the touch pen PEN, battery information of the touch pen PEN, gradient information of the touch pen PEN, and / or various information stored in the touch pen PEN.

[0050] The electronic device DD can be used as a large electronic device such as a television, a monitor, or an external billboard. The electronic device DD can also be used in small and medium-sized electronic devices such as a personal computer, a laptop computer, a personal digital assistant, an automobile navigation system, a game console, a smartphone, a tablet, or a camera. However, these are merely exemplary embodiments, and the electronic device DD can also be used in other electronic devices without departing from the concept of the present invention.

[0051] 1B is a block diagram of an electronic device DD according to an embodiment. Referring to FIG. 1B, the electronic device DD outputs various information through a display module DM within an operating system. When the processor 110 executes an application stored in the memory 120, the display module DM provides application information to a user through a display panel DP.

[0052] The processor 110 acquires an external input through the input module 130 or the sensor module 161 and executes an application corresponding to the external input. For example, if a user selects a camera icon displayed on the display panel DP, the processor 110 acquires the user input through the input sensor 161-2 and activates the camera module 171. The processor 110 transmits image data corresponding to the captured image acquired through the camera module 171 to the display module DM. The display module DM can display an image corresponding to the captured image on the display panel DP.

[0053] As another example, when personal information authentication is performed on the display module DM, the fingerprint sensor 161-1 acquires input fingerprint information as input data. The processor 110 compares the input data acquired through the fingerprint sensor 161-1 with authentication data stored in the memory 120 and executes an application according to the comparison result. The display module DM can display information executed according to the logic of the application on the display panel DP.

[0054] As another example, when a music streaming icon displayed on the display module DM is selected, the processor 110 acquires a user input through the input sensor 161-2 and activates a music streaming application stored in the memory 120. When a music execution command is input in the music streaming application, the processor 110 activates the audio output module 163 to provide the user with audio information corresponding to the music execution command.

[0055] The operation of the electronic device DD has been briefly described above. The configuration of the electronic device DD will be described in detail below. Some of the components of the electronic device DD described below may be integrated and provided as a single component, or one component may be provided as two or more separate components.

[0056] 1B , the electronic device DD can communicate with an external electronic device 102 through a network (e.g., a short-range wireless communication network or a long-range wireless communication network). According to one embodiment, the electronic device DD can include a processor 110, a memory 120, an input module 130, a display module DM, a power module 150, an internal module 160, and an external module 170. According to one embodiment, the electronic device DD can omit at least one of the above components or can include one or more other components. According to one embodiment, some of the above components (e.g., the sensor module 161, the antenna module 162, or the acoustic output module 163) can be integrated into another component (e.g., the display module DM).

[0057] The processor 110 can execute software to control at least one other component (e.g., a hardware or software component) of the electronic device DD coupled to the processor 110, and can perform various data processing or calculations. According to one embodiment, as at least part of the data processing or calculation, the processor 110 can store instructions or data received from other components (e.g., the input module 130, the sensor module 161, or the communication module 173) in the volatile memory 121, process the instructions or data stored in the volatile memory 121, and store the resulting data in the non-volatile memory 122.

[0058] The processor 110 may include a main processor 111 and an auxiliary processor 112. The main processor 111 may include one or more of a central processing unit (CPU) 111-1 or an application processor (AP). The main processor 111 may further include one or more of a graphics processing unit (GPU) 111-2, a communication processor (CP), and an image signal processor (ISP). The main processor 111 may further include a neural network processing unit (NPU) 111-3. The neural network processing unit is a processor specialized in processing an artificial intelligence model, and the artificial intelligence model can be generated through machine learning. The artificial intelligence model may include multiple artificial neural network layers. The artificial neural network may be one of a deep neural network (DNN), a convolutional neural network (CNN), a recurrent neural network (RNN), a restricted Boltzmann machine (RBM), a deep belief network (DBN), a bidirectional recurrent deep neural network (BRDNN), a deep Q-network, or a combination of two or more of the above, but is not limited to the above examples. The artificial intelligence model may include a software structure in addition to or instead of a hardware structure. At least two of the above processing units and processors may be implemented in an integrated structure (e.g., a single chip) or each may be implemented in an independent structure (e.g., multiple chips).

[0059] The auxiliary processor 112 may include a drive controller 112-1. The drive controller 112-1 may include an interface conversion circuit and a timing control circuit. The drive controller 112-1 receives image signals from the main processor 111, converts the data format of the image signals to conform to the interface specifications with the display module DM, and outputs image data. The drive controller 112-1 may output various control signals required to drive the display module DM.

[0060] The auxiliary processor 112 may further include a data conversion circuit 112-2, a gamma correction circuit 112-3, a rendering circuit 112-4, etc. The data conversion circuit 112-2 receives image data from the drive controller 112-1 and compensates the image data so that an image is displayed at a desired brightness according to the characteristics of the electronic device DD or user settings, or converts the image data to reduce power consumption or compensate for image lag. The gamma correction circuit 112-3 converts image data or a gamma reference voltage, etc. so that an image displayed on the electronic device DD has a desired gamma characteristic. The rendering circuit 112-4 receives image data from the drive controller 112-1 and renders the image data taking into account the pixel layout of the display panel DP applied to the electronic device DD, etc. At least one of the data conversion circuit 112-2, the gamma correction circuit 112-3, and the rendering circuit 112-4 may be integrated into another component (e.g., the main processor 111 or the drive controller 112-1). At least one of the data conversion circuit 112-2, the gamma correction circuit 112-3, and the rendering circuit 112-4 may be integrated into a data driver DDV, which will be described later.

[0061] The memory 120 may store various data used by at least one component of the electronic device DD (e.g., the processor 110 or the sensor module 161) and input or output data for instructions associated therewith. The memory 120 may include at least one of a volatile memory 121 and a non-volatile memory 122.

[0062] The input module 130 can receive instructions or data from outside the electronic device DD (e.g., from a user or an external electronic device 102) for use by components of the electronic device DD (e.g., the processor 110, the sensor module 161, or the acoustic output module 163).

[0063] The input module 130 may include a first input module 131 through which commands or data are input from a user and a second input module 132 through which commands or data are input from the external electronic device 102. The first input module 131 may include a microphone, a mouse, a keyboard, keys (e.g., buttons), or a pen (e.g., a passive pen or an active pen). The second input module 132 may support a specified protocol for wired or wireless connection to the external electronic device 102. According to an embodiment, the second input module 132 may include a high definition multimedia interface (HDMI), a universal serial bus (USB), an SD card interface, or an audio interface. The second input module 132 may include a connector that can be physically connected to the external electronic device 102, such as an HDMI connector, a USB connector, an SD card connector, or an audio connector (e.g., a headset connector).

[0064] The display module DM provides visual information to a user and may include a display panel DP, a scan driver SDC, and a data driver DDV. The display module DM may further include a window, a chassis, and a bracket for protecting the display panel DP.

[0065] The display panel DP may include a liquid crystal display panel, an organic light-emitting display panel, or an inorganic light-emitting display panel, and the type of the display panel DP is not particularly limited. The display panel DP may be a rigid type, a rollable type, or a foldable type. The display module DM may further include a supporter, a bracket, a heat dissipation member, etc. that support the display panel DP.

[0066] The scan driver SDC can be implemented in the display panel DP as a driver chip. Alternatively, the scan driver SDC can be integrated into the display panel DP. For example, the scan driver SDC can include an ASG (Amorphous Silicon TFT Gate driver circuit), an LTPS (Low Temperature Polycrystalline Silicon) TFT Gate driver circuit, or an OSG (Oxide Semiconductor TFT Gate driver circuit) built into the display panel DP. The scan driver SDC receives control signals from the driver controller 112-1 and outputs scan signals to the display panel DP in response to the control signals.

[0067] The display panel DP may further include a light emitting driver that outputs a light emitting control signal to the display panel DP in response to a control signal received from the drive controller 112-1. The light emitting driver may be formed separately from the scan driver SDC or may be integrated into the scan driver SDC.

[0068] The data driver DDV receives a control signal from the drive controller 112-1, converts image data into an analog voltage (for example, a data voltage) in response to the control signal, and then outputs the data voltage to the display panel DP.

[0069] The data driver DDV can be integrated into other components (for example, the driver controller 112-1). The functions of the interface conversion circuit and timing control circuit of the driver controller 112-1 described above may be integrated into the data driver DDV.

[0070] The display module DM may further include a light emitting driver and a voltage generating circuit, etc. The voltage generating circuit can output various voltages required to drive the display panel DP.

[0071] The power supply module 150 supplies power to the components of the electronic device DD. The power supply module 150 may include a battery that charges the power supply voltage. The battery may include a non-rechargeable primary battery, a rechargeable secondary battery, or a fuel cell. The power supply module 150 may include a power management integrated circuit (PMIC). The PMIC supplies optimized power to each of the modules described above and below. The power supply module 150 may include a wireless power transmitting / receiving member electrically connected to the battery. The wireless power transmitting / receiving member may include a plurality of antenna radiators in the form of coils.

[0072] The electronic device DD may further include an internal module 160 and an external module 170. The internal module 160 may include a sensor module 161, an antenna module 162, and an acoustic output module 163. The external module 170 may include a camera module 171, a light module 172, and a communication module 173.

[0073] The sensor module 161 can sense input from the user's body or input from a pen in the first input module 131 and generate an electrical signal or data value corresponding to the input. The sensor module 161 can include at least one of a fingerprint sensor 161-1, an input sensor 161-2, and a digitizer 161-3.

[0074] The fingerprint sensor 161-1 can generate a data value corresponding to a user's fingerprint and can include either an optical or capacitive fingerprint sensor.

[0075] The input sensor 161-2 can generate data values ​​corresponding to coordinate information of input by the user's body or pen. The input sensor 161-2 generates data values ​​based on the amount of capacitance change due to the input. The input sensor 161-2 can sense input by a passive pen or transmit and receive data to and from an active pen.

[0076] The input sensor 161-2 may measure a biological signal such as blood pressure, water content, or body fat. For example, if a user keeps a part of their body in contact with the sensor layer or sensing panel and does not move for a certain period of time, the input sensor 161-2 may detect the biological signal based on a change in an electric field caused by the part of their body and output information desired by the user to the display module DM.

[0077] The digitizer 161-3 can generate data values ​​corresponding to the coordinate information of the input by the pen. The digitizer 161-3 converts the electromagnetic change caused by the input into data values. The digitizer 161-3 can sense input by a passive pen or can send and receive data to and from an active pen.

[0078] At least one of the fingerprint sensor 161-1, the input sensor 161-2, and the digitizer 161-3 may be implemented as a sensor layer formed on the display panel DP through a continuous process. The fingerprint sensor 161-1, the input sensor 161-2, and the digitizer 161-3 may be disposed on the upper side of the display panel DP, and one of the fingerprint sensor 161-1, the input sensor 161-2, and the digitizer 161-3, for example, the digitizer 161-3, may be disposed on the lower side of the display panel DP.

[0079] At least two of the fingerprint sensor 161-1, the input sensor 161-2, and the digitizer 161-3 may be formed to be integrated into one sensing panel through the same process. When integrated into one sensing panel, the sensing panel may be disposed between the display panel DP and a window disposed above the display panel DP. According to one embodiment, the sensing panel may be disposed above the window, and the position of the sensing panel is not particularly limited.

[0080] At least one of the fingerprint sensor 161-1, the input sensor 161-2, and the digitizer 161-3 may be embedded in the display panel DP. That is, at least one of the fingerprint sensor 161-1, the input sensor 161-2, and the digitizer 161-3 may be formed simultaneously through a process for forming elements (e.g., light emitting elements, transistors, etc.) included in the display panel DP.

[0081] Additionally, the sensor module 161 may generate an electrical signal or a data value corresponding to an internal or external state of the electronic device DD. The sensor module 161 may further include, for example, a gesture sensor, a gyro sensor, a barometric pressure sensor, a magnetic sensor, an acceleration sensor, a grip sensor, a proximity sensor, a color sensor, an IR (infrared) sensor, a biometric sensor, a temperature sensor, a humidity sensor, or an illuminance sensor.

[0082] The antenna module 162 may include one or more antennas for transmitting or receiving signals or power to or from an external device. According to an embodiment, the communication module 173 may transmit or receive signals to or from an external electronic device through an antenna compatible with a communication method. The antenna pattern of the antenna module 162 may be integrated into one component of the display module DM (e.g., the display panel DP) or the input sensor 161-2.

[0083] The audio output module 163 is a device for outputting audio signals to the outside of the electronic device DD, and may include a speaker used for general purposes such as multimedia playback or recording playback, and a receiver used exclusively for receiving telephone calls. According to an embodiment, the receiver may be formed integrally with or separately from the speaker. The audio output pattern of the audio output module 163 may also be integrated into the display module DM.

[0084] The camera module 171 can capture still images and video. According to an embodiment, the camera module 171 can include one or more lenses, image sensors, or image signal processors. The camera module 171 can further include an infrared camera that can measure the presence or absence of a user, the user's position, the user's line of sight, etc.

[0085] The light module 172 can provide light. The light module 172 can include a light emitting diode or a xenon lamp. The light module 172 can operate in conjunction with the camera module 171 or independently.

[0086] The communication module 173 can support the establishment of a wired or wireless communication channel between the electronic device DD and the external electronic device 102 and the execution of communication through the established communication channel. The communication module 173 can include any one or all of a wireless communication module such as a cellular communication module, a short-range wireless communication module, or a global navigation satellite system (GNSS) communication module, and a wired communication module such as a local area network (LAN) communication module or a power line communication module. The communication module 173 can communicate with the external electronic device 702 through a short-range communication network such as Bluetooth, WiFi Direct, or infrared data association (IrDA), or a long-range communication network such as a cellular network, the Internet, or a computer network (e.g., LAN or WAN). The various types of communication modules 173 described above can be implemented on a single chip, or each can be implemented on a separate chip.

[0087] The input module 130, the sensor module 161, the camera module 171, etc. may be used in conjunction with the processor 110 to control the operation of the display module DM.

[0088] The processor 110 outputs commands or data to the display module DM, the audio output module 163, the camera module 171, or the light module 172 based on input data received from the input module 130. For example, the processor 110 may generate image data corresponding to input data applied through a mouse, an active pen, or the like, and output the image data to the display module DM, or may generate command data corresponding to the input data and output the command data to the camera module 171 or the light module 172. If the processor 110 does not receive input data from the input module 130 for a certain period of time, it may switch the operation mode of the electronic device DD to a low power mode or a sleep mode to reduce power consumption by the electronic device DD.

[0089] The processor 110 outputs commands or data to the display module DM, the audio output module 163, the camera module 171, or the light module 172 based on the sensing data received from the sensor module 161. For example, the processor 110 may compare authentication data applied by the fingerprint sensor 161-1 with authentication data stored in the memory 120 and then execute an application according to the comparison result. The processor 110 may execute commands or output corresponding image data to the display module DM based on the sensing data sensed by the input sensor 161-2 or the digitizer 161-3. If the sensor module 161 includes a temperature sensor, the processor 110 may receive temperature data on the measured temperature from the sensor module 161 and further perform brightness correction, etc. on the image data based on the temperature data.

[0090] The processor 110 can receive measurement data regarding the presence or absence of a user, the user's position, the user's line of sight, etc. from the camera module 171. The processor 110 can further perform brightness correction, etc. on the image data based on the measurement data. For example, the processor 110, which determines the presence or absence of a user through input from the camera module 171, can output image data whose brightness has been corrected to the display module DM via the data conversion circuit 112-2 or the gamma correction circuit 112-3.

[0091] Some of the components may be connected to each other via a peripheral communication method, such as a bus, a general purpose input / output (GPIO), a serial peripheral interface (SPI), a mobile industry processor interface (MIPI), or an ultrapath interconnect (UPI) link, to exchange signals (e.g., commands or data). The processor 110 may communicate with the display module DM via a mutually agreed-upon interface, and may use, for example, any one of the above-mentioned communication methods, but is not limited to, the above-mentioned communication methods.

[0092] The electronic device DD according to various embodiments disclosed herein may be a device of various forms. For example, the electronic device DD may include at least one of a portable communication device (e.g., a smartphone), a computer device, a portable multimedia device, a portable medical device, a camera, a wearable device, or a consumer electronic device. The electronic device DD according to embodiments of this document is not limited to the aforementioned devices.

[0093] 2 is a diagram showing an example of a cross section of the electronic device DD shown in FIG. 1A. FIG. 2 shows a cross section of the electronic device DD as seen from a second direction DR2. Some of the components of the electronic device DD described in FIG. 1B are omitted in FIG. 2.

[0094] 2, the electronic device DD may include a display panel DP, an input sensor ISP, an anti-reflection layer RPL, a window WIN, a panel protection film PPF, and first and second adhesive layers AL1 and AL2. The input sensor ISP shown in FIG. 2 may have the same configuration as the input sensor 161-2 described in FIG. 1B.

[0095] The display panel DP according to an embodiment of the present invention may be an emissive display panel. For example, the display panel DP may be an organic light-emitting display panel or an inorganic light-emitting display panel. The light-emitting layer of an organic light-emitting display panel may include an organic light-emitting material. The light-emitting layer of an inorganic light-emitting display panel may include quantum dots, quantum rods, etc. Hereinafter, the display panel DP will be referred to as an organic light-emitting display panel.

[0096] The input sensor ISP may be disposed on the display panel DP. The input sensor ISP may include a plurality of sensing units (not shown) for sensing external inputs in a capacitive manner. The input sensor ISP may be directly fabricated on the display panel DP during the manufacture of the electronic device DD. Therefore, according to one embodiment, the input sensor ISP may be directly disposed on the display panel DP. However, the present invention is not limited thereto, and the input sensor ISP may be fabricated as a separate panel from the display panel DP and attached to the display panel DP by an adhesive layer.

[0097] The anti-reflection layer RPL may be disposed on the input sensor ISP. The anti-reflection layer RPL may be manufactured by being disposed directly on the input sensor ISP when manufacturing the electronic device DD. However, the anti-reflection layer RPL is not limited thereto, and may be manufactured as a separate panel and attached to the input sensor ISP by an adhesive layer.

[0098] The anti-reflection layer RPL can be defined as an external light anti-reflection film. The anti-reflection layer RPL can reduce the reflectance of external light incident from the electronic device DD toward the display panel DP. The anti-reflection layer RPL may prevent the external light from being visible to the user.

[0099] When external light traveling toward the display panel DP is reflected by the display panel DP and provided to an external user, the user may view the external light like a mirror. To prevent this phenomenon, the anti-reflection layer RPL may, for example, include a plurality of color filters that display the same colors as the pixels of the display panel DP.

[0100] The color filter can filter external light with the same color as the pixel. In this case, the external light may not be visible to the user. However, the anti-reflection layer RPL is not limited thereto, and may include a retarder and / or a polarizer to reduce the reflectance of external light.

[0101] The window WIN may be disposed on the anti-reflection layer RPL, and the window WIN may protect the display panel DP, the input sensor ISP, and the anti-reflection layer RPL from external scratches and impacts.

[0102] The panel protection film PPF may be disposed under the display panel DP. The panel protection film PPF can protect the lower part of the display panel DP. The panel protection film PPF may include a flexible plastic material such as polyethylene terephthalate (PET).

[0103] The first adhesive layer AL1 is disposed between the display panel DP and the panel protective film PPF, and the first adhesive layer AL1 can bond the display panel DP and the panel protective film PPF to each other. The second adhesive layer AL2 is disposed between the window WIN and the anti-reflection layer RPL, and the second adhesive layer AL2 can bond the window WIN and the anti-reflection layer RPL to each other.

[0104] Figure 3 is a diagram illustrating an example of a cross section of the display panel illustrated in Figure 2. Exemplarily, Figure 3 illustrates a cross section of the display panel DP as viewed from a second direction DR2.

[0105] Referring to FIG. 3, the display panel DP may include a substrate SUB, a circuit element layer DP-CL disposed on the substrate SUB, a display element layer DP-OLED disposed on the circuit element layer DP-CL, and a thin-film encapsulation layer TFE disposed on the display element layer DP-OLED.

[0106] The substrate SUB may include a display area DA and a non-display area NDA surrounding the display area DA. The substrate SUB may include glass or a flexible plastic material such as polyimide (PI). The display element layer DP-OLED may be disposed on the display area DA.

[0107] A plurality of pixels may be disposed on the circuit element layer DP-CL and the display element layer DP-OLED, and each pixel may include a transistor disposed on the circuit element layer DP-CL and a light emitting element disposed on the display element layer DP-OLED and connected to the transistor.

[0108] The thin-film encapsulation layer TFE may be disposed on the circuit element layer DP-CL to cover the display element layer DP-OLED. The thin-film encapsulation layer TFE may protect the pixels from moisture, oxygen, and external foreign substances. The thin-film encapsulation layer TFE may include an inorganic layer and an organic layer. The organic layer may be disposed between the inorganic layers and sealed from the inorganic layers to provide a flat surface. According to an embodiment, the organic layer may be disposed on the inorganic layer or may be omitted, and is not limited to any one embodiment.

[0109] FIG. 4A is a block diagram of the electronic device shown in FIG. 1A.

[0110] Referring to FIG. 4A, the electronic device DD may include a display panel DP, a timing controller TC, a scan driver SDV, a data driver DDV, a light emission driver EDV, and a voltage generator VG.

[0111] The display panel DP includes a plurality of scan lines GIL1 to GILm, GCL1 to GCLm, GWL1 to GWLm, GBL1 to GBLm, a plurality of light emitting lines EML1 to EMLm, a plurality of data lines DL1 to DLn, and a plurality of pixels PX, where m and n are natural numbers.

[0112] The pixels PX may be electrically connected to the scan lines GIL1 to GILm, GCL1 to GCLm, GWL1 to GWLm, GBL1 to GBLm, the light emitting lines EML1 to EMLm, and the data lines DL1 to DLn, respectively.

[0113] Each of the pixels PX may be electrically connected to four corresponding scan lines, one corresponding data line, and one corresponding emission line.

[0114] The scan lines GIL1 to GILm, GCL1 to GCLm, GWL1 to GWLm, and GBL1 to GBLm may include a plurality of initialization scan lines GIL1 to GILm, a plurality of compensation scan lines GCL1 to GCLm, a plurality of write scan lines GWL1 to GWLm, and a plurality of bias scan lines GBL1 to GBLm.

[0115] Each of the pixels PX may be connected to a corresponding one of the initialization scan lines GIL1 to GILm, a corresponding one of the compensation scan lines GCL1 to GCLm, a corresponding one of the write scan lines GWL1 to GWLm, and a corresponding one of the bias scan lines GBL1 to GBLm.

[0116] The scan lines GIL1 to GILm, GCL1 to GCLm, GWL1 to GWLm, and GBL1 to GBLm are connected to the scan driver SDV, extended in the first direction DR1, and arranged in the second direction DR2. The light emitting lines EML1 to EMLm are connected to the light emitting driver EDV, extended in the first direction DR1, and arranged in the second direction DR2. The data lines DL1 to DLn are connected to the data driver DDV, extended in the second direction DR2, and arranged in the first direction DR1.

[0117] The scan driver SDV, the emission driver EDV, and the data driver DDV may be substantially arranged on the display panel DP, and this configuration is shown in FIG. 4 below.

[0118] The timing controller TC receives the image signal RGB and the control signal CTRL. The timing controller TC converts the data format of the image signal RGB to conform to the interface specification with the data driver DDV and generates the image data signal DAS. The timing controller TC outputs the scan control signal SCS, the data control signal DCS, and the light emission control signal ECS in response to the control signal CTRL.

[0119] The voltage generator VG generates voltages necessary for the operation of the display panel DP. The voltage generator VG generates a first driving voltage ELVDD, a second driving voltage ELVSS, a first initialization voltage VINT, and a second initialization voltage VAINT. The first driving voltage ELVDD, the second driving voltage ELVSS, the first initialization voltage VINT, and the second initialization voltage VAINT can be applied to the pixels PX.

[0120] The scan driver SDV may receive a scan control signal SCS from the timing controller TC. The scan driver SDV may output scan signals to the scan lines GIL1 to GILm, GCL1 to GCLm, GWL1 to GWLm, and GBL1 to GBLm in response to the scan control signal SCS. The scan signals may be applied to the pixels PX through the scan lines GIL1 to GILm, GCL1 to GCLm, GWL1 to GWLm, and GBL1 to GBLm.

[0121] The data driver DDV can receive a data control signal DCS and an image data signal DAS from the timing controller TC. The data driver DDV can convert the image data signal DAS into a data signal and output the converted data signal. The data signal can be defined as an analog voltage corresponding to the gray level of the image data signal DAS. The data signal can be applied to the pixels PX through the data lines DL1 to DLn.

[0122] The light emitting driver EDV may receive a light emitting control signal ECS from the timing controller TC. The light emitting driver EDV may output light emitting signals to the light emitting lines EML1 to EMLm in response to the light emitting control signal ECS. The light emitting signals may be applied to the pixels PX through the light emitting lines EML1 to EMLm.

[0123] The pixel PX can receive a data voltage in response to a scan signal, and can emit light of a brightness corresponding to the data voltage in response to a light emitting signal to display an image.

[0124] FIG. 4B is a diagram showing an equivalent circuit of one of the pixels shown in FIG. 4A.

[0125] 4B illustrates a pixel PXij connected to the j-th data line DLj, the i-th scan lines GWLi, GCLi, GILi, and GBLi, and the i-th emission line EMLi, where i and j are natural numbers.

[0126] 4B, the pixel PXij may include a pixel circuit PC and a light-emitting element OLED connected to the pixel circuit PC. The pixel circuit PC may drive the light-emitting element OLED.

[0127] The pixel circuit PC may include a plurality of transistors T1 to T8 and a capacitor CST. The transistors T1 to T8 and the capacitor CST may control the amount of current flowing to the light emitting element OLED. The light emitting element OLED may generate light having a predetermined brightness according to the amount of current received.

[0128] The i-th write scan line GWLi can receive the i-th write scan signal GWi, the i-th compensation scan line GCLi can receive the i-th compensation scan signal GCi, the i-th initialization scan line GILi can receive the i-th initialization scan signal GIi, the i-th bias scan line GBLi can receive the i-th bias scan signal GBi, and the i-th emission line EMLi can receive the i-th emission signal EMi.

[0129] The pixel PXij may be connected to the jth data line DLj, the ith write scan line GWLi, the ith compensation scan line GCLi, the ith initialization scan line GILi, the ith bias scan line GBLi, the ith emission line EMLi, the first initialization line VIL1, the second initialization line VIL2, the bias line VBL, and the first and second power supply lines PL1 and PL2.

[0130] The first initialization line VIL1 receives the first initialization voltage VINT, the second initialization line VIL2 receives the second initialization voltage VAINT, the bias line VBL receives the bias voltage VBIAS, the first power supply line PL1 receives the first driving voltage ELVDD, and the second power supply line PL2 receives the second driving voltage ELVSS.

[0131] Each of the transistors T1 to T8 includes a source electrode, a drain electrode, and a gate electrode. Hereinafter, in FIG. 4B, for convenience, one of the source electrode and the drain electrode is defined as a first electrode, and the other is defined as a second electrode. Also, the gate electrode is defined as a control electrode.

[0132] The transistors T1 to T8 may include first to eighth transistors T1 to T8. The first, second, and fifth to eighth transistors T1, T2, and T5 to T8 may be PMOS transistors. The third and fourth transistors T3 and T4 may be NMOS transistors.

[0133] The first transistor T1 can be defined as a driving switching transistor, the second transistor T2 can be defined as a switching transistor, the third transistor T3 can be defined as a compensation transistor, the fourth transistor T4 and the seventh transistor T7 can be defined as initialization transistors, the fifth transistor T5 and the sixth transistor T6 can be defined as light-emitting control transistors, and the eighth transistor T8 can be defined as a bias transistor.

[0134] The light emitting element OLED may be defined as an organic light emitting element. The light emitting element OLED may include a first electrode AE ​​and a second electrode CE. The first electrode AE ​​may receive a first driving voltage ELVDD through the sixth, first, and fifth transistors T6, T1, and T5. The first driving voltage ELVDD may be applied to the pixel circuit PC through a first power line PL1.

[0135] The second electrode CE may receive a second driving voltage ELVSS having a lower level than the first driving voltage ELVDD, and the second driving voltage ELVSS may be applied to the pixel circuit PC through a second power line PL2.

[0136] The first transistor T1 may be disposed between the fifth transistor T5 and the sixth transistor T6 and may be connected to the fifth transistor T5 and the sixth transistor T6. The first transistor T1 may be connected to the first power line PL1 through the fifth transistor T5 and to the first electrode AE ​​through the sixth transistor T6.

[0137] The first transistor T1 may include a first electrode connected to the first power line PL1 through the fifth transistor T5, a second electrode connected to the first electrode AE ​​through the sixth transistor T6, and a control electrode connected to the first node N1.

[0138] A first electrode of the first transistor T1 may be connected to the fifth transistor T5, and a second electrode of the first transistor T1 may be connected to the sixth transistor T6. The first transistor T1 may control the amount of current flowing to the light emitting element OLED in response to a voltage of a first node N1 applied to a control electrode of the first transistor T1.

[0139] The second transistor T2 may be disposed between the first transistor T1 and the j-th data line DLj and may be connected to the first transistor T1 and the j-th data line DLj. The second transistor T2 may include a first electrode connected to the j-th data line DLj, a second electrode connected to the first electrode of the first transistor T1, and a control electrode connected to the ith write scan line GWLi.

[0140] The second transistor T2 is turned on in response to the i-th write scan signal GWi received through the i-th write scan line GWLi to electrically connect the j-th data line DLj to the first electrode of the first transistor T1, and performs a switching operation to provide the data voltage VD (corresponding to the data signal described above) received through the j-th data line DLj to the first electrode of the first transistor T1.

[0141] The third transistor T3 may be connected to the second electrode of the first transistor T1 and the first node N1, and may include a first electrode connected to the second electrode of the first transistor T1, a second electrode connected to the first node N1, and a control electrode connected to the i-th compensation scan line GCLi.

[0142] The third transistor T3 is turned on in response to an i-th compensation scan signal GCi received through an i-th compensation scan line GCLi to electrically connect the second electrode of the first transistor T1 to the control electrode of the first transistor T1. When the third transistor T3 is turned on, the first transistor T1 and the third transistor T3 may be connected in a diode configuration.

[0143] The fourth transistor T4 may be connected to the first node N1. The fourth transistor T4 may include a first electrode connected to the first node N1, a second electrode connected to the first initialization line VIL1, and a control electrode connected to the i-th initialization scan line GILi. The fourth transistor T4 may be turned on in response to the i-th initialization scan signal GIi received through the i-th initialization scan line GILi to provide the first initialization voltage VINT received through the first initialization line VIL1 to the first node N1.

[0144] The fifth transistor T5 may include a first electrode connected to the first power line PL1, a second electrode connected to the first electrode of the first transistor T1, and a control electrode connected to the i-th light emitting line EMLi.

[0145] The sixth transistor T6 may include a first electrode connected to the second electrode of the first transistor T1, a second electrode connected to the first electrode AE, and a control electrode connected to the i-th light-emitting line EMLi.

[0146] The fifth transistor T5 and the sixth transistor T6 may be turned on by the i-th light emitting signal EMi received through the i-th light emitting line EMLi. The turned-on fifth transistor T5 and the sixth transistor T6 provide the first driving voltage ELVDD to the light emitting element OLED, allowing a driving current to flow through the light emitting element OLED. Therefore, the light emitting element OLED may emit light.

[0147] The seventh transistor T7 may include a first electrode connected to the first electrode AE, a second electrode connected to the second initialization line VIL2, and a control electrode connected to the i-th bias scan line GBLi. The seventh transistor T7 may be turned on in response to the i-th bias scan signal GBi received through the i-th bias scan line GBLi to provide the second initialization voltage VAINT received through the second initialization line VIL2 to the first electrode AE ​​of the light emitting element OLED.

[0148] In the embodiment of the present invention, the second initialization voltage VAINT may have a different level from the first initialization voltage VINT, but is not limited thereto, and may have the same level as the first initialization voltage VINT.

[0149] The seventh transistor T7 can improve the black expression capability of the pixel PXij. When the seventh transistor T7 is turned on, a parasitic capacitor (not shown) of the light emitting element OLED can be discharged. Therefore, when black brightness is realized, the light emitting element OLED does not emit light due to the leakage current of the first transistor T1, and therefore the black expression capability can be improved.

[0150] The capacitor CST may include a first electrode connected to the first power line PL1 and a second electrode connected to the first node N1. When the fifth transistor T5 and the sixth transistor T6 are turned on, the amount of current flowing through the first transistor T1 may be determined according to the voltage stored in the capacitor CST.

[0151] The eighth transistor T8 may include a first electrode connected to the bias line VBL, a second electrode connected to the first electrode of the first transistor T1, and a control electrode connected to the i-th bias scan line GBLi.

[0152] The eighth transistor T8 is turned on by the i-th bias scan signal GBi and can provide the bias voltage VBIAS received through the bias line VBL to the first electrode of the first transistor T1, although the transistors included in the pixel PXij are not limited thereto.

[0153] Figure 5A is a plan view of a pixel unit according to an embodiment of the present invention, Figure 5B is a plan view of a pixel according to an embodiment of the present invention, Figure 5C is a plan view of a pixel unit according to an embodiment of the present invention, and Figure 6 is a cross-sectional view taken along line II' in Figure 5A.

[0154] 5A, in this embodiment, one pixel unit PXU may include the pixels described in FIGS. 4A and 4B. A plurality of pixel units PXU may be provided and arranged along first and second directions DR1 and DR2 within the display area DA described in FIG. 1A.

[0155] According to one embodiment, the pixel unit PXU may include first, second, and third pixels PX-R, PX-G, and PX-B. The first pixel PX-R may provide red light. The light generated by the first pixel PX-R may be provided to the display area DA (see FIG. 1A) through the first light-emitting region PXA-R. In this embodiment, the first light-emitting region PXA-R may have a rounded-corner rectangular shape (a rectangular shape with curved corners).

[0156] The second pixel PX-G may provide green light. The light generated by the second pixel PX-G may be provided to the display area DA (see FIG. 1A) through the second light-emitting region PXA-G. The second light-emitting region PXA-G may be spaced apart from the first light-emitting region PXA-R along the second direction DR2. The second light-emitting region PXA-G may have a rectangular shape with rounded corners.

[0157] The third pixel PX-B may provide blue light. The light generated by the third pixel PX-B may be provided to the display area DA (see FIG. 1A) through the third light-emitting region PXA-B. The third light-emitting region PXA-B may be spaced apart from the first light-emitting region PXA-R along the first direction DR1. When viewed in the second direction DR2, the third light-emitting region PXA-B may overlap the first and second light-emitting regions PXA-R and PXA-G. The third light-emitting region PXA-B may have a rounded-corner rectangular shape elongated along the second direction DR2.

[0158] The areas between the first to third light-emitting areas PXA-R, PXA-G, and PXA-B can be defined as non-light-emitting areas NPXA. In the example of FIG. 5A, each of the first to third light-emitting areas PXA-R, PXA-G, and PXA-B is surrounded by a non-light-emitting area NPXA.

[0159] According to the present invention, the first to third contact electrodes PE-R, PE-G, and PE-B may be included to surround the first to third light-emitting regions PXA-R, PXA-G, and PXA-B, respectively. Each of the first to third contact electrodes PE-R, PE-G, and PE-B may overlap the non-light-emitting region NPXA.

[0160] The first contact electrode PE-R can surround the first light-emitting region PXA-R, the second contact electrode PE-G can surround the second light-emitting region PXA-G, and the third contact electrode PE-B can surround the third light-emitting region PXA-B.

[0161] According to this embodiment, the first to third contact electrodes PE-R, PE-G, and PE-B are illustrated as having a closed-line shape surrounding the entire corresponding light-emitting area, but may have a shape in which at least a portion is open, and are not limited to any one embodiment.

[0162] The first contact electrode PE-R may be connected to the second electrode CE-R included in the first pixel PX-R via the non-emitting region NPXA. The second contact electrode PE-G may be connected to the second electrode CE-G included in the second pixel PX-G via the non-emitting region NPXA. The third contact electrode PE-B may be connected to the second electrode CE-B included in the third pixel PX-B via the non-emitting region NPXA. According to this embodiment, the second electrodes CE-R, CE-G, and CE-B included in each pixel may be disconnected via the non-emitting region NPXA. That is, each of the second electrodes CE-R, CE-B, and CE-G is separated via the corresponding non-emitting region NPX. In other words, each of the second electrodes CE-R, CE-B, and CE-G extends from the first, second, and third light-emitting regions PXA-R, PXA-G, and PXA-B to the corresponding non-emitting region NPXA and has an end within the corresponding non-emitting region NPXA. In FIG. 5A, the second electrodes CE-R, CE-G, and CE-B are shown by dotted lines.

[0163] According to this embodiment, the second power line PL2 (FIG. 4B) that applies the second driving voltage ELVSS (FIG. 4B) to the pixel is extended from the non-display area NDA (see FIG. 1A) to the display area DA (see FIG. 1A) and can overlap with each of the first to third contact electrodes PE-R, PE-G, and PE-B.

[0164] 5A, the second power line PL2 (FIG. 4B) disposed within the display area DA (see FIG. 1A) is illustrated as first to third power lines ES-R, ES-G, and ES-B. According to one embodiment, the first to third power lines ES-R, ES-G, and ES-B may be spaced apart along a first direction DR1, and each of the first to third power lines ES-R, ES-G, and ES-B may extend along a second direction DR2.

[0165] The first power supply line ES-R may overlap a portion of the first contact electrode PE-R and be connected to it through a contact hole CNT. The second power supply line ES-G may overlap a portion of the second contact electrode PE-G and be connected to it through a contact hole CNT. The third power supply line ES-B may overlap a portion of the third contact electrode PE-B and be connected to it through a contact hole CNT. The contact hole CNT may be defined in an interlayer insulating layer disposed between the power supply line and the contact electrode. The contact hole CNT may be disposed in the non-emitting region NPXA. Also, the contact hole CNT may be disposed in the encapsulation region ENA of the non-emitting region NPXA.

[0166] According to the present invention, the region between adjacent pixels in the non-emitting region NPXA may be defined as an encapsulation region ENA. The encapsulation region ENA may be defined as a region where insulating layers containing inorganic materials contact each other. According to this embodiment, the encapsulation region ENA may surround each of the pixels PX-R, PX-G, and PX-B. Therefore, the pixels PX-R, PX-G, and PX-B may be individually encapsulated. Therefore, the path of moisture / oxygen flowing into the pixels PX-R, PX-G, and PX-B may be blocked by the encapsulation region ENA. This will be described in detail later.

[0167] Unlike the present invention, in a panel in which a second electrode (or cathode) formed in a single pattern together with a common electrode is connected to a second power line PL2 (Figure 4B) in a non-emitting area NPXA, a problem may occur in which a constant voltage cannot be provided to pixels due to a voltage drop phenomenon.

[0168] According to the present invention, the second electrodes CE-R, CE-G, and CE-B included in each of the pixels PX-R, PX-G, and PX-B may be individually disconnected and connected to the corresponding first, second, and third contact electrodes PE-R, PE-G, and PE-B. The first, second, and third contact electrodes PE-R, PE-G, and PE-B may be individually connected to the first, second, and third power lines ES-R, ES-G, and ES-B through the contact holes CNT. That is, the second electrode CE-R corresponding to the first pixel PX-R is connected to the contact electrode PE-R corresponding to the first pixel PX-R, and the contact electrode PE-R is connected to the first power line ES-R through the contact hole CNT corresponding to the first pixel PX-R. The second electrode CE-G corresponding to the second pixel PX-G is connected to the contact electrode PE-G corresponding to the second pixel PX-G, and the contact electrode PE-G is connected to the second power line ES-G through the contact hole CNT corresponding to the second pixel PX-G. In addition, the second electrode CE-B corresponding to the third pixel PX-B is connected to the contact electrode PE-B corresponding to the third pixel PX-B, and the contact electrode PE-B is connected to the third power supply line ES-B via the contact hole CNT corresponding to the third pixel PX-B. Therefore, according to the configuration of the present invention, instead of supplying voltage to multiple types of pixels or multiple pixels from one power supply line, voltage can be supplied to one type of pixel (e.g., the first pixel PX-R) or one pixel from one power supply line (e.g., the first power supply line ES-R).

[0169] Therefore, it is possible to prevent voltage drop and provide a constant voltage to the pixels. For example, when a single power supply line supplies voltage to multiple types of pixels, the single power supply line may be arranged to extend across an area where multiple types of pixels are arranged. In this case, the voltage of the power supply line may drop due to the resistance of the power supply line itself, etc. The longer the length of the power supply line, the greater the voltage drop. With the above configuration, since a single power supply line supplies voltage to one type of pixel (or one pixel), the voltage drop can be suppressed compared to when a single power supply line supplies voltage to multiple types of pixels (or multiple pixels). In other words, since the length of a single power supply line supplying voltage to one type of pixel (or one pixel) is relatively short, the voltage drop can be suppressed. Therefore, an electronic device DD with improved display quality can be provided. Furthermore, compared to the comparative embodiment in which the second electrode (or cathode) is connected to the second power line PL2 (FIG. 4B) in the non-display area NDA (see FIG. 1A), the present invention can omit the additional space required to connect the second electrode (or cathode) and the second power line PL2 (FIG. 4B), thereby providing an electronic device DD with a reduced non-display area NDA (see FIG. 1A). The comparative embodiment, for example, arranges a power line in the non-display area NDA outside the display area DA, and extends an extension line from the display area DA to the non-display area NDA to connect the power line to pixels in the display area DA. In this case, a structure for connecting the extension line to the power line must be arranged in the non-display area NDA. On the other hand, according to the present invention, the power line is arranged so as to overlap the pixel in the display area DA, and the power line and the pixel are in contact with each other in the non-light-emitting area NPXA of the display area DA. This allows the area of ​​the non-display area NDA to be reduced accordingly.

[0170] 5B, one pixel PX-a may include a plurality of sub-pixels SPX-1, SPX-2, and SPX-3. A plurality of pixels PX-a may be provided and spaced apart along first and second directions DR1 and DR2 in the display area DA described in FIG. 1A.

[0171] In this embodiment, one pixel PX-a is illustrated as including three sub-pixels SPX-1, SPX-2, and SPX-3, but the number, shape, and arrangement of the sub-pixels are not limited to this.

[0172] Each of the sub-pixels SPX-1, SPX-2, and SPX-3 may include the pixel circuit PC described in FIG. 4B and a light-emitting element OLED connected to the pixel circuit PC. The sub-pixels SPX-1, SPX-2, and SPX-3 may generate light of different colors or the same color, and are not limited to any one embodiment. The light-emitting regions PXA-1, PXA-2, and PXA-3 that provide the light generated by the sub-pixels SPX-1, SPX-2, and SPX-3 may have different areas. However, the shapes and arrangements of the light-emitting regions PXA-1, PXA-2, and PXA-3 are not limited to any one embodiment.

[0173] According to this embodiment, the contact electrode PE-C is disposed to overlap the non-emitting area NPXA and may surround the sub-pixels SPX-1, SPX-2, and SPX-3. The sub-pixels SPX-1, SPX-2, and SPX-3 may include a common second electrode CE-C. The second electrode CE-C may be connected to the contact electrode PE-C in the non-emitting area NPXA.

[0174] According to one embodiment, a second power line PL2 (FIG. 4B) that applies a second driving voltage ELVSS (FIG. 4B) to the pixel may extend from the non-display area NDA (see FIG. 1A) to the display area DA (see FIG. 1A) and overlap the contact electrode PE-C. The power line ES-C may be a portion of the second power line PL2 (FIG. 4B) that extends to the display area DA (see FIG. 1A).

[0175] The power supply line ES-C may overlap a portion of the contact electrode PE-C and be connected to it through a contact hole CNT. The contact hole CNT may be defined in an interlayer insulating layer disposed between the power supply line ES-C and the contact electrode PE-C. The contact hole CNT may be disposed in the non-emitting area NPXA. The contact hole CNT may also be disposed in the encapsulation area ENA of the non-emitting area NPXA. According to this embodiment, one contact electrode PE-C is connected to one second electrode CE-C commonly disposed in the sub-pixels SPX-1, SPX-2, and SPX-3, and may provide the same voltage to the sub-pixels SPX-1, SPX-2, and SPX-3.

[0176] 5C, in this embodiment, one pixel unit PXU-A may include the pixels described in FIGS. 4A and 4B. A plurality of pixel units PXU-A may be provided and arranged along first and second directions DR1 and DR2 within the display area DA described in FIG. 1A.

[0177] According to one embodiment, pixel unit PXU-A may include 1-1, 1-2, 2nd, and 3rd pixels PX-G1, PX-G2, PX-R, and PX-B. 1-1 pixel PX-G1 may provide green light. Light generated in 1-1 pixel PX-G1 may be provided to display area DA (see FIG. 1A) through 1-1 light-emitting region PXA-G1. In this embodiment, 1-1 light-emitting region PXA-G1 may have a rectangular shape.

[0178] The first-2nd pixel PX-G2 may provide green light like the first-1st pixel PX-G1. The light generated in the first-2nd pixel PX-G2 may be provided to the display area DA (see FIG. 1A) through the first-2nd light-emitting region PXA-G2. The first-2nd light-emitting region PXA-G2 may be spaced apart from the first-1st light-emitting region PXA-G1 along the first direction DR1. In this embodiment, the first-2nd light-emitting region PXA-G2 may have a rectangular shape.

[0179] The second pixel PX-R may provide red light. The light generated by the second pixel PX-R may be provided to the display area DA (see FIG. 1A) through the second light-emitting region PXA-R. The second light-emitting region PXA-R may be spaced apart from the third light-emitting region PXA-B along the second direction DR2. The second light-emitting region PXA-R may be spaced apart from the first light-emitting region PXA-G1 along the first oblique direction CDR1 and from the first light-emitting region PXA-G2 along the second oblique direction CDR2. In this embodiment, the second light-emitting region PXA-R may have an oblique rhomboid shape.

[0180] The third pixel PX-B may provide blue light. The light generated by the third pixel PX-B may be provided to the display area DA (see FIG. 1A) through the third light-emitting region PXA-B. The third light-emitting region PXA-B may be spaced apart from the first light-emitting region PXA-G2 along the first oblique direction CDR1 and from the first light-emitting region PXA-G1 along the first oblique direction CDR1. In this embodiment, the third light-emitting region PXA-B may have an oblique rhomboid shape.

[0181] According to an embodiment, the area of ​​the second light-emitting region PXA-R may be larger than the areas of the first and second light-emitting regions PXA-G1 and PXA-G1, and smaller than the area of ​​the third light-emitting region PXA-B.

[0182] The areas between the first, second, second and third light-emitting areas PXA-G1, PXA-G2, PXA-R and PXA-B can be defined as non-light-emitting areas NPXA.

[0183] According to the present invention, the light emitting element may include 1-1, 1-2, second, and third contact electrodes PE-G1, PE-G2, PE-R, and PE-B surrounding the 1-1, 1-2, second, and third light emitting areas PXA-G1, PXA-G2, PXA-R, and PXA-B, respectively. Each of the 1-1, 1-2, second, and third contact electrodes PE-G1, PE-G2, PE-R, and PE-B may overlap the non-light emitting area NPXA.

[0184] The first-1 contact electrode PE-G1 can surround the first-1 light-emitting region PXA-G1, the first-2 contact electrode PE-G2 can surround the first-2 light-emitting region PXA-G2, the second contact electrode PE-R can surround the second light-emitting region PXA-R, and the third contact electrode PE-B can surround the third light-emitting region PXA-B.

[0185] According to this embodiment, the 1-1, 1-2, second, and third contact electrodes PE-G1, PE-G2, PE-R, and PE-B are illustrated as having a closed-line shape surrounding the entire corresponding light-emitting area, but may have a shape in which at least a portion is open, and are not limited to any one embodiment.

[0186] The first-1 contact electrode PE-G1 may be connected to the second electrode CE-G1 included in the first-1 pixel PX-G1 through a non-emitting region NPXA. The first-2 contact electrode PE-G2 may be connected to the second electrode CE-G2 included in the second pixel PX-G2 through a non-emitting region NPXA. The second contact electrode PE-R may be connected to the second electrode CE-R included in the second pixel PX-R through a non-emitting region NPXA. The third contact electrode PE-B may be connected to the second electrode CE-B included in the third pixel PX-B through a non-emitting region NPXA. According to this embodiment, the second electrodes CE-G1, CE-G2, CE-R, and CE-B included in each pixel may be disconnected through the non-emitting region NPXA. In FIG. 5C, the second electrodes CE-G1, CE-G2, CE-R, and CE-B are illustrated by dotted lines.

[0187] According to this embodiment, the second power line PL2 (FIG. 4B) that applies the second driving voltage ELVSS (FIG. 4B) to the pixel can be extended from the non-display area NDA (see FIG. 1A) to the display area DA (see FIG. 1A) and overlap with each of the first to third contact electrodes PE-G1, PE-G2, PE-R, and PE-B.

[0188] 5C illustrates the second power lines PL2 (FIG. 4B) arranged within the display area DA (see FIG. 1A) as 1-1, 1-2, second, and third power lines ES-G1, ES-G2, ES-R, and ES-B. According to one embodiment, the 1-1, 1-2, second, and third power lines ES-G1, ES-G2, ES-R, and ES-B may be spaced apart along a first direction DR1, and each of the 1-1, 1-2, second, and third power lines ES-G1, ES-G2, ES-R, and ES-B may extend along a second direction DR2.

[0189] The first-1 power supply line ES-G1 may overlap a portion of the first-1 contact electrode PE-G1 and be connected to it through a contact hole CNT. The first-2 power supply line ES-G2 may overlap a portion of the first-2 contact electrode PE-G2 and be connected to it through a contact hole CNT. The second power supply line ES-R may overlap a portion of the second contact electrode PE-R and be connected to it through a contact hole CNT. The third power supply line ES-B may overlap a portion of the third contact electrode PE-B and be connected to it through a contact hole CNT. The contact hole CNT may be defined in an interlayer insulating layer disposed between the power supply line and the contact electrode.

[0190] According to the present invention, the region between adjacent pixels in the non-emitting region NPXA may be defined as an encapsulation region ENA. The encapsulation region ENA may be defined as a region where insulating layers containing inorganic materials contact each other. According to this embodiment, the encapsulation region ENA may surround each of the pixels PX-G1, PX-G2, PX-R, and PX-B. Therefore, the pixels PX-G1, PX-G2, PX-R, and PX-B may be individually encapsulated. Therefore, the path of moisture / oxygen flowing into the pixels PX-G1, PX-G2, PX-R, and PX-B may be blocked by the encapsulation region ENA. This will be described in detail later.

[0191] According to the present invention, the second electrodes CE-G1, CE-G2, CE-R, and CE-B included in each of the pixels PX-G1, PX-G2, PX-R, and PX-B may be individually disconnected and connected to the corresponding contact electrodes 1-1, 1-2, PE-G1, PE-G2, PE-R, and PE-B. Also, the contact electrodes 1-1, 1-2, PE-G1, PE-G2, PE-R, and PE-B may be individually connected to the power supply lines 1-1, 1-2, ES-G1, ES-G2, ES-R, and ES-B through contact holes CNT.

[0192] Figure 6 is a cross-sectional view taken along line II' in Figure 5A. Figure 6 exemplarily illustrates a cross-sectional view of a portion of the light-emitting element OLED-R, the first transistor T1, the fourth transistor T4, and the sixth transistor T6 included in the first pixel PX-R described in Figure 4B. The description of the cross-sectional view can be commonly applied to the pixels PX-R, PX-G, and PX-B described in Figure 5A.

[0193] 6, the light emitting element OLED-R according to an embodiment may include a first electrode AE-R, a second electrode CE-R, and a first common layer CL-R. The first common layer CL-R may include a hole controlling layer, an electron controlling layer, an emitting layer, etc.

[0194] The second electrode CE-R may be disposed on the first electrode AE-R, and a first common layer CL-R may be disposed between the first electrode AE-R and the second electrode CE-R. According to an embodiment, the light-emitting element OLED-R may further include a protective layer CPL disposed on the second electrode CE-R. The protective layer CPL includes an organic material and may prevent damage to components disposed below the protective layer CPL in a subsequent process. According to an embodiment, the protective layer CPL may be omitted. According to the present embodiment, the components included in the light-emitting element OLED-R may be disconnected in the non-emitting region NPXA.

[0195] The first, fourth, and sixth transistors T1, T4, and T6 and the light-emitting element OLED-R may be disposed on a substrate SUB. The display area DA may include a light-emitting area PXA-R corresponding to the pixel PXij (see FIG. 4B) and a non-light-emitting area NPXA adjacent to the light-emitting area PXA-R. The light-emitting element OLED-R may be disposed in the non-light-emitting area NPXA.

[0196] The substrate SUB may include glass or a flexible plastic material such as polyimide (PI). A circuit element layer DP-CL, a display element layer DP-OLED, and a thin film encapsulation layer TFE may be disposed on the substrate SUB.

[0197] The circuit element layer DP-CL may be disposed on the substrate SUB. The circuit element layer DP-CL may include an insulating layer and a conductive pattern.

[0198] The barrier layer BRL may be disposed on the substrate SUB. The barrier layer BRL may increase the bonding strength between the semiconductor pattern included in the transistor and the substrate SUB. The barrier layer BRL may include an inorganic material.

[0199] A metal layer BML may be disposed on the barrier layer BRL. The metal layer BML may overlap the first transistor T1. According to an embodiment, the metal layer BML may receive a constant voltage. When the constant voltage is applied to the metal layer BML, the threshold voltage Vth value of the first transistor T1 disposed on the metal layer BML may be maintained unchanged.

[0200] The metal layer BML may block light incident on the first transistor T1 below the metal layer BML. The metal layer BML may include a reflective metal. According to an embodiment, the metal layer BML may be omitted.

[0201] The buffer layer BFL may be disposed on the barrier layer BRL and may cover the metal layer BML. The buffer layer BFL may include an inorganic material.

[0202] The semiconductor layers S1, A1, and D1 of the first transistor T1 and the semiconductor layers S6, A6, and D6 of the sixth transistor T6 may be disposed on the buffer layer BFL. The semiconductor layers S1, A1, D1, S6, A6, and D6 may include polysilicon. However, without being limited thereto, the semiconductor layers S1, A1, D1, S6, A6, and D6 may include amorphous silicon.

[0203] The semiconductor layers S1, A1, D1, S6, A6, and D6 may be doped with an N-type dopant or a P-type dopant. The semiconductor layers S1, A1, D1, S6, A6, and D6 may include a highly doped region and a lightly doped region. The highly doped region has a higher conductivity than the lightly doped region and may substantially serve as the source electrode and drain electrode of the first and sixth transistors T1 and T6. The lightly doped region may substantially correspond to the active region (or channel) of the first and sixth transistors T1 and T6.

[0204] The first source region S1, the first channel region A1, and the first drain region D1 of the first transistor T1 may be formed of semiconductor layers S1, A1, and D1. The sixth source region S6, the sixth channel region A6, and the sixth drain region D6 of the sixth transistor T6 may be formed of semiconductor layers S6, A6, and D6. The first channel region A1 may be disposed between the first source region S1 and the first drain region D1. The sixth channel region A6 may be disposed between the sixth source region S6 and the sixth drain region D6.

[0205] A first insulating layer INS1 may be disposed on the buffer layer BFL to cover the semiconductor layers S1, A1, D1, S6, A6, and D6. A first gate electrode G1 (or control electrode) of the first transistor T1 and a sixth gate electrode G6 (or control electrode) of the sixth transistor T6 may be disposed on the first insulating layer INS1. In a plan view, the first gate electrode G1 may overlap the first channel region A1, and the sixth gate electrode G6 may overlap the sixth channel region A6.

[0206] Although not shown, the structures of the source region, channel region, drain region, and gate electrode of each of the second, fifth, and seventh transistors T2, T5, and T7 may be substantially the same as those of the first and sixth transistors T1 and T6.

[0207] A second insulating layer INS2 may be disposed on the first insulating layer INS1 so as to cover the first and sixth gate electrodes G1 and G6. A dummy electrode DME may be disposed on the second insulating layer INS2. The dummy electrode DME is disposed on the first gate electrode G1 and may overlap the first gate electrode G1 in a plan view. The dummy electrode DME may form the aforementioned capacitor together with the first gate electrode G1.

[0208] A third insulating layer INS3 may be disposed on the second insulating layer INS2 to cover the dummy electrode DME. Semiconductor layers S4, A4, and D4 of the fourth transistor T4 may be disposed on the third insulating layer INS3. The semiconductor layers S4, A4, and D4 may include an oxide semiconductor formed of a metal oxide. The oxide semiconductor may include a crystalline or amorphous oxide semiconductor.

[0209] The semiconductor layers S4, A4, and D4 may include a plurality of regions that are distinguished depending on whether the metal oxide is reduced or not. The region where the metal oxide is reduced (hereinafter referred to as the reduced region) may have higher conductivity than the region where the metal oxide is not reduced (hereinafter referred to as the non-reduced region). The reduced region may essentially function as the source electrode or drain electrode of the fourth transistor T4. The non-reduced region may essentially correspond to the active region (or channel) of the fourth transistor T4.

[0210] The fourth source region S4, the fourth channel region A4, and the fourth drain region D4 of the fourth transistor T4 may be formed of semiconductor layers S4, A4, and D4, and the fourth channel region A4 may be disposed between the fourth source region S4 and the fourth drain region D4.

[0211] A fourth insulating layer INS4 may be disposed on the third insulating layer INS3 to cover the semiconductor layers S4, A4, and D4. A fourth gate electrode G4 of the fourth transistor T4 may be disposed on the fourth insulating layer INS4. In a plan view, the fourth gate electrode G4 may overlap the fourth channel region A4.

[0212] A fifth insulating layer INS5 may be disposed on the fourth insulating layer INS4 to cover the fourth gate electrode G4. Although not shown, the source region, channel region, drain region, and gate electrode of the third transistor T3 may have substantially the same structures as those of the fourth transistor T4.

[0213] The barrier layer BRL, the buffer layer BFL, and the first to fifth insulating layers INS1 to INS5 may include an inorganic material. Exemplarily, the barrier layer BRL, the buffer layer BFL, and the first to fifth insulating layers INS1 to INS5 may include one of silicon oxide and silicon nitride, or one insulating layer may include multiple inorganic layers, and this is not limited to any embodiment. The multiple inorganic layers may have a structure in which layers including silicon nitride and silicon oxide are alternately stacked.

[0214] A connecting electrode CNE may be disposed between the sixth transistor T6 and the light emitting element OLED-R. The connecting electrode CNE may electrically connect the sixth transistor T6 and the light emitting element OLED-R. The connecting electrode CNE may include a first connecting electrode CNE1, a second connecting electrode CNE2 disposed on the first connecting electrode CNE1, and a third connecting electrode CNE3 disposed on the second connecting electrode CNE2.

[0215] The first connecting electrode CNE1 may be disposed on the fifth insulating layer INS5 and may be connected to the sixth drain region D6 through a first contact hole CH1 defined in the first to fifth insulating layers INS1 to INS5. A sixth insulating layer INS6 may be disposed on the fifth insulating layer INS5 to cover the first connecting electrode CNE1.

[0216] The second connecting electrode CNE2 may be disposed on the sixth insulating layer INS6 and may be connected to the first connecting electrode CNE1 through a second contact hole CH2 defined in the sixth insulating layer INS6.

[0217] According to this embodiment, the first power wiring (line) ES-R may be disposed on the sixth insulating layer INS6 and covered by the seventh insulating layer INS7. The first power wiring ES-R may be disposed in the non-light-emitting region NPXA as described with reference to FIG. 5A. The first power wiring ES-R and the second connecting electrode CNE2 may be patterned using the same process and may include the same material.

[0218] A seventh insulating layer INS7 may be disposed on the sixth insulating layer INS6 to cover the second connecting electrode CNE2 and the first power wiring ES-R. The sixth and seventh insulating layers INS6 and INS7 may include an inorganic material or an organic material.

[0219] The third connecting electrode CNE3 may be disposed on the seventh insulating layer INS7. The third connecting electrode CNE3 may be connected to the second connecting electrode CNE2 through a third contact hole CH3 defined in the seventh insulating layer INS7. The seventh insulating layer INS7 may be defined as an "interlayer insulating layer" in this specification. Therefore, the contact hole CNT described in FIG. 5A may be defined in the seventh insulating layer INS7.

[0220] According to this embodiment, the first contact electrode PE-R may be disposed on the seventh insulating layer INS7 and covered by the eighth insulating layer INS8. The first contact electrode PE-R may be disposed in the non-light-emitting region NPXA as described with reference to FIG. 5A. The first contact electrode PE-R and the third connecting electrode CNE3 may be patterned using the same process and may include the same material.

[0221] An eighth insulating layer INS8 may be disposed on the seventh insulating layer INS7 to cover the third connecting electrode CNE3 and the first contact electrode PE-R. The eighth insulating layer INS8 may include an inorganic material. A groove GR exposing a portion of the first contact electrode PE-R may be defined in the eighth insulating layer INS8.

[0222] In the region overlapping with the groove GR, the side of the first contact electrode PE-R adjacent to the light emitting region PXA-R may be exposed from the eighth insulating layer INS8 by the groove GR. The eighth insulating layer INS8 may be defined as the "inter insulating layer" in this specification.

[0223] A ninth insulating layer INS9 may be disposed on the eighth insulating layer INS8. The ninth insulating layer INS9 may include an organic material. The ninth insulating layer INS9 may provide a flat surface for the structure disposed on the ninth insulating layer INS9. According to this embodiment, the ninth insulating layer INS9 may be disconnected in an area overlapping with the groove GR. The ninth insulating layer INS9 may be defined as a "via insulating layer" in this specification. According to one embodiment, the ninth insulating layer INS9 may be omitted.

[0224] The pixel defining layer PDL may be disposed on the ninth insulating layer INS9. An opening PDL-OP exposing at least a portion of the first electrode AE-R may be defined in the pixel defining layer PDL. In this embodiment, the pixel defining layer PDL may include an inorganic material. The pixel defining layer PDL may have a predetermined color and is not limited to any one embodiment. According to this embodiment, the pixel defining layer PDL may be disconnected in a region overlapping with the groove GR.

[0225] A first common layer CL-R, a second electrode CE-R, and a protective layer CPL included in the light emitting device OLED-R may be disposed on the pixel defining layer PDL. The first common layer CL-R, the second electrode CE-R, and the protective layer CPL may be disconnected in an area overlapping with the groove GR.

[0226] As shown in FIG. 7A, the side of the second electrode CE-R extending from the first light-emitting region PXA-R to the non-light-emitting region NPXA can contact the side PS of the contact electrode PE-S exposed from the eighth insulating layer INS8 through the groove GR in the area overlapping with the groove GR.

[0227] According to the present invention, the second electrode CE-R, which is disconnected by the groove GR, is in direct contact with the side surface PS of the first contact electrode PE-R in the area overlapping with the groove GR, and as described in FIG. 5A, the first contact electrode PE-R can be connected to the first power wiring ES-R by a contact hole CNT defined in the seventh insulating layer INS7, which is an interlayer insulating layer.

[0228] According to the present invention, as described above, the light emitting elements included in each pixel are individually connected to the power supply line, so that they can receive the power supply voltage uniformly regardless of the size / area of ​​the display area DA (see FIG. 1A), thereby preventing the voltage drop phenomenon and providing a display panel DP with improved reliability.

[0229] According to an embodiment, the second dummy electrode CE-D may be disposed in the non-light-emitting region NPXA. The second dummy electrode CE-D may be formed by the same process as the second electrode CE-R and may be defined as a portion of the second electrode CE-R that is disconnected from the second electrode CE-R by the groove GR and that is disposed on the non-light-emitting region NPXA. The second dummy electrode CE-D may be in a floating state.

[0230] 6, the thin-film encapsulation layer TFE may be disposed on the display element layer DP-OLED. The thin-film encapsulation layer TFE may be disposed over the entire display area DA. The thin-film encapsulation layer TFE may include a first encapsulation layer TE1 and a second encapsulation layer TE2. The second encapsulation layer TE2 may be in direct contact with the first encapsulation layer TE1 over the first light-emitting area PXA-R and the non-light-emitting area NPXA.

[0231] According to one embodiment, the thin film encapsulation layer TFE may further include an organic layer disposed on the second encapsulation layer TE2 and an additional inorganic layer covering the organic layer, and is not limited to any one embodiment.

[0232] Figure 7A is an enlarged cross-sectional view of region AA' in Figure 6. Figure 7B is a cross-sectional view of a display panel according to an embodiment of the present invention. Figure 7C is a cross-sectional view of a display panel according to an embodiment of the present invention. Figure 7D is a cross-sectional view of a display panel according to an embodiment of the present invention. Figure 8 is a cross-sectional view taken along line II-II' in Figure 5A. Figure 9 is a cross-sectional view taken along line III-III' in Figure 5A.

[0233] 7A, the first encapsulation layer TE1 may be in contact with the protective layer CPL in the region overlapping with the groove GR, and the second encapsulation layer TE2 may be in contact with the first encapsulation layer TE1. The first encapsulation layer TE1 may cover the sides of the pixel defining layer PDL, the first common layer CL-R, the second electrode CE-R, and the protective layer CPL that are disconnected by the groove GR, as well as the side of the eighth insulating layer INS8 that defines the groove GR.

[0234] Figure 7B shows an embodiment of a display panel DP-1 showing an area corresponding to Figure 7A. Differences from the display panel DP described in Figure 7A will be mainly described, and overlapping descriptions will be omitted.

[0235] 7B, the display panel DP-1 according to an embodiment may further include a dam pattern OVH overlapping the non-light-emitting region NPXA. The dam pattern OVH overlaps the first contact electrode PE-R and may have a shape corresponding to the shape of the first contact electrode PE-R in a plan view described with reference to FIG. 5A. Therefore, the dam pattern OVH may have a shape surrounding at least a portion of the first light-emitting region PXA-R (see FIG. 5A). That is, like the first contact electrode PE-R, the dam pattern OVH may have a closed line shape surrounding the entire corresponding light-emitting region or a shape with at least a portion open.

[0236] The dam pattern OVH may include a first pattern OV1 disposed on the pixel defining layer PDL and a second pattern OV2 disposed on the first pattern OV1. The thickness of the first pattern OV1 may be greater than the thickness of the second pattern OV2 in the third direction DR3, and the width of the first pattern OV1 may be smaller than the width of the second pattern OV2 in the first direction DR1. The first pattern OV1 and the second pattern OV2 may include different inorganic materials. For example, the first pattern OV1 may include silicon nitride, and the second pattern OV2 may include silicon oxide. The shape of the dam pattern OVH may be formed due to a difference in etching rate.

[0237] The first common layer CL-R, the second dummy electrode CE-D, and the protective layer CPL can be disconnected in the non-light-emitting area NPXA by the dam pattern OVH. Therefore, since the first common layer CL-R, the second dummy electrode CE-D, and the protective layer CPL are not disposed in the groove GR, the second electrode CE-R can easily contact the side surface PS of the first contact electrode PE-R.

[0238] According to an embodiment, a dummy pattern OD may be disposed on the dam pattern OVH. The dummy pattern OD may be formed by disposing a portion of each of the first common layer CL-R, the second dummy electrode CE-D, and the protective layer CPL. The first encapsulation layer TE1 and the second encapsulation layer TE2 may cover the dam pattern OVH in the non-light-emitting region NPXA.

[0239] Figure 7C shows an embodiment of a display panel DP-2 showing an area corresponding to Figure 7B. Differences from the display panel DP-1 described in Figure 7B will be mainly described, and overlapping descriptions will be omitted.

[0240] 7C, a display panel DP-2 according to an embodiment may include a first pattern layer SI1 and a second pattern layer SI2. The first pattern layer SI1 and the second pattern layer SI2 may overlap the non-emissive region NPXA and be disposed between the first contact electrode PE-R and the seventh insulating layer INS7. The first pattern layer SI1 and the second pattern layer SI2 may overlap the first contact electrode PE-R. Therefore, the first pattern layer SI1 and the second pattern layer SI2 may have a shape that surrounds at least a portion of the first light-emitting region PXA-R (see FIG. 5A). That is, the first pattern layer SI1 and the second pattern layer SI2 may have a shape that surrounds at least a portion of the first light-emitting region PXA-R, similar to the first contact electrode PE-R.

[0241] The first pattern layer SI1 may be disposed on the seventh insulating layer INS7. The second pattern layer SI2 may be disposed on the first pattern layer SI1. The first pattern layer SI1 and the second pattern layer SI2 may comprise different inorganic materials. For example, the first pattern layer SI1 may comprise silicon oxide, and the second pattern layer SI2 may comprise silicon nitride.

[0242] However, without being limited thereto, if the first pattern layer SI1 contains silicon nitride and the second pattern layer SI2 contains silicon oxide, the width of the second pattern layer SI2 in the first direction DR1 may be larger than the width of the first pattern layer SI1.

[0243] According to this embodiment, the width of the second pattern layer SI2 in the first direction DR1 may be smaller than the width of the first pattern layer SI1, so that a portion SU of the top surface of the first pattern layer SI1 may be exposed from the second pattern layer SI2.

[0244] According to this embodiment, the first contact electrode PE-R may be disposed on the second pattern layer SI2. The first common layer CL-R may be disposed as high as the thickness of the first pattern layer SI1 and the second pattern layer SI2. That is, the thickness of the first common layer CL-R is approximately the same as the total thickness of the first and second pattern layers SI1 and SI2. Therefore, the first common layer CL-R may contact only the first pattern layer SI1 and the second pattern layer SI2 and be separated from the first contact electrode PE-R. For example, the first common layer CL-R may contact a portion SU of the side and top surface of the first pattern layer SI1 and the side surface of the second pattern layer SI2. The second electrode CE-R may be disposed on the first common layer CL-R and may directly contact the side surface PS of the first contact electrode PE-R.

[0245] According to this embodiment, by including the first pattern layer SI1 and the second pattern layer SI2, the contact area between the first contact electrode PE-R and the second electrode CE-R can be increased.

[0246] According to this embodiment, the side surface PS of the first contact electrode PE-R may have a predetermined curvature. More specifically, the side surface PS of the first contact electrode PE-R may have a shape recessed in a direction toward the non-emitting region NPXA in the first light-emitting region PXA-R. In other words, the side surface PS of the first contact electrode PE-R has a shape recessed in a direction toward the second electrode CE-R and the protective layer CPL.

[0247] Figure 7D shows an embodiment of a display panel DP-3 showing an area corresponding to Figure 7C. Differences from the display panel DP-2 described in Figure 7C will be mainly described, and overlapping descriptions will be omitted.

[0248] Referring to Figure 7D, in one embodiment, a portion of the eighth insulating layer INS8 (inter insulating layer) adjacent to the groove GR and disposed in the non-emitting region NPXA may protrude from the first contact electrode PE-R in a direction toward the first light-emitting region PXA-R.

[0249] Furthermore, in the example of Figure 7D, compared to the example of Figure 7C, the protruded portion may have a trench groove TR protruded in a third direction DR3 (upward) to define a predetermined internal space.

[0250] According to this embodiment, by including the trench groove TR in the eighth insulating layer INS8 (internal insulating layer) in the non-light-emitting region NPXA, it is possible to easily disconnect components arranged on the eighth insulating layer INS8 (internal insulating layer) in the non-light-emitting region NPXA. Components arranged on the eighth insulating layer INS8 (internal insulating layer) including the trench groove TR and that may be easily disconnected by the configuration of the eighth insulating layer INS8 (internal insulating layer) may be, for example, the first common layer CL-R, the second dummy electrode CE-D, and the protective layer CPL. Therefore, the process of forming the dam pattern OVH described with reference to FIGS. 7B and 7C can be omitted.

[0251] 8 is a cross-sectional view of the space between adjacent light emitting regions shown in FIG. 5A. Description of the configuration overlapping with the configuration described in FIGS. 7 and 7A will be omitted.

[0252] As described in FIGS. 5A, 6, and 7A, the components included in the light emitting device of the present invention are separated by the groove GR, and therefore, individual sealing is required for each light emitting device to prevent oxygen / moisture penetration.

[0253] According to the present invention, the region between adjacent light-emitting elements in the non-light-emitting region NPXA can be defined as an encapsulation region ENA. The encapsulation region ENA can block a path through which moisture / oxygen can penetrate into the light-emitting element by contacting the inorganic layer.

[0254] In the encapsulation region ENA, the sixth and seventh insulating layers INS6 and INS7 disposed on the fifth insulating layer INS5 may be removed. An eighth insulating layer INS8 including an inorganic material, a pixel defining layer PDL, and a second encapsulation layer TE2 may be stacked on the fifth insulating layer INS5 exposed by removing the sixth and seventh insulating layers INS6 and INS7 and may be in contact with each other.

[0255] The encapsulation area ENA can surround each of the light-emitting areas PXA-R, PXA-G, and PXA-B described in Fig. 5A, thereby blocking the path through which moisture / oxygen can penetrate into the light-emitting element, thereby providing a display panel DP with improved reliability.

[0256] 9 shows the connection relationship between the first contact electrode PE-R and the first power supply line ES-R described in FIG. 5A. The first power supply line ES-R may be disposed on the sixth insulating layer INS6 and covered by the seventh insulating layer INS7 (interlayer insulating layer). The first contact electrode PE-R may be disposed on the seventh insulating layer INS7 (interlayer insulating layer).

[0257] The first contact electrode PE-R may be connected to the first power line ES-R through a contact hole CNT defined in a seventh insulating layer INS7 (interlayer insulating layer). According to the display panel DP-2 described with reference to FIG. 7C, a first pattern layer SI1 and a second pattern layer SI2 including holes overlapping with the contact hole CNT may be disposed on the seventh insulating layer INS7 (interlayer insulating layer).

[0258] 10A to 10K are cross-sectional views illustrating a method for manufacturing a display panel according to an embodiment of the present invention. Figures 10A to 10K are views illustrating a method for forming the display panel DP-2 described in Figure 7C. Among the components described in Figure 6, the manufacturing steps for the fifth insulating layer INS5 and the components disposed below the fifth insulating layer INS5 are omitted.

[0259] 10A, a method for manufacturing a display panel according to an embodiment may include forming a sixth insulating layer INS6 on the fifth insulating layer INS5 and forming a seventh insulating layer INS7 on the sixth insulating layer INS6. The fifth insulating layer INS5 may include an inorganic material, and the sixth insulating layer INS6 and the seventh insulating layer INS7 may include an organic material.

[0260] Thereafter, the sixth insulating layer INS6 and the seventh insulating layer INS7 may be removed to expose a portion of the fifth insulating layer INS5.

[0261] Thereafter, the method may include forming a first pattern layer SI1 on the seventh insulating layer INS7 and forming a second pattern layer SI2 on the first pattern layer SI1, where the first pattern layer SI1 includes silicon oxide and the second pattern layer SI2 includes silicon nitride.

[0262] Thereafter, a first contact electrode PE-R may be formed on the second pattern layer SI2. In this embodiment, the first contact electrode PE-R may include molybdenum. The first contact electrode PE-R may be formed by the same process as the third connecting electrode CNE3 described with reference to FIG. 6 and may include the same material.

[0263] 10B , a method for manufacturing a display panel according to an embodiment may include patterning the first pattern layer SI1, the second pattern layer SI2, and the first contact electrode PE-R. The first pattern layer SI1, the second pattern layer SI2, and the first contact electrode PE-R may be formed using a dry etching process. The first pattern layer SI1 and the second pattern layer SI2 may be patterned to overlap the first contact electrode PE-R using the first contact electrode PE-R as a mask.

[0264] 10C, the method for manufacturing a display panel according to an embodiment may include forming an eighth insulating layer INS8 on the seventh insulating layer INS7 to cover the first contact electrode PE-R. The eighth insulating layer INS8 may include an inorganic material.

[0265] Thereafter, the eighth insulating layer INS8 may be patterned. The eighth insulating layer INS8 may be etched to form a groove GR exposing a portion of a side surface of the first contact electrode PE-R. The patterning may be performed using a dry etching process.

[0266] The side surfaces of the eighth insulating layer INS8 that define the groove GR can expose the side surfaces of the first contact electrode PE-R, the side surfaces of the first pattern layer SI1, and the side surfaces of the second pattern layer SI2.

[0267] 10D , a method for manufacturing a display panel according to an embodiment may include patterning the first contact electrode PE-R. Side surfaces of the first contact electrode PE-R exposed from the eighth insulating layer INS8 by the groove GR may be etched to form side surfaces PS having a predetermined curvature. The patterning may be performed using a wet etching process. According to an embodiment, the wet etching process may be performed after a PR pattern (photoresist) is formed on the first contact electrode PE-R and then using the PR pattern as a mask.

[0268] According to this embodiment, as shown in FIG. 10D, the lower portion of the eighth insulating layer INS8 may be exposed from the patterned first contact electrode PE-R.

[0269] 10E, the method for manufacturing a display panel according to an embodiment may include patterning the second pattern layer SI2. The patterning may be performed using a dry etching process. Due to the difference in etching rate between the first pattern layer SI1 and the second pattern layer SI2, the second pattern layer SI2 may be removed relatively more. Therefore, the second pattern layer SI2 may expose a portion SU of the top surface of the first pattern layer SI1.

[0270] 10F, a method for manufacturing a display panel according to an embodiment may include forming a ninth insulating layer INS9 on the eighth insulating layer INS8. The ninth insulating layer INS9 may include an organic material. The ninth insulating layer INS9 may be formed by removing portions overlapping with the grooves GR using a photolithography process so that the ninth insulating layer INS9 does not overlap with the grooves GR.

[0271] 10G, the method for manufacturing a display panel according to an embodiment may include forming a pixel defining layer PDL on the ninth insulating layer INS9. The pixel defining layer PDL may include an inorganic material. The pixel defining layer PDL may be formed by removing a portion overlapping the groove GR using an etching process so that the pixel defining layer PDL does not overlap the groove GR.

[0272] 10H, a method for manufacturing a display panel according to an embodiment may include forming a dam pattern on a pixel defining layer PDL. The forming of the dam pattern may include forming a first pattern OV1 and a second pattern OV2. The first pattern OV1 and the second pattern OV2 may include an inorganic material. The first pattern OV1 may include silicon nitride, and the second pattern OV2 may include silicon oxide.

[0273] 10I, a method for manufacturing a display panel according to an embodiment may include patterning a first pattern OV1 and a second pattern OV2. The patterning may be performed using a dry etching process. The patterned first pattern OV1 and second pattern OV2 may overlap the first contact electrode PE-R and be formed on the pixel defining layer PDL. The shapes of the first pattern OV1 and the second pattern OV2 may be formed due to a difference in etching rate.

[0274] 6, the step of forming the first electrode AE-R is performed before the step of forming the pixel defining layer PDL. Here, since the first electrode AE-R is outside the illustrated range, the step of forming the first electrode AE-R is omitted.

[0275] 10J, a method for manufacturing a display panel according to an embodiment may include forming a first common layer CL-R on a pixel defining layer PDL, forming a second electrode CE-R on the first common layer CL-R, and forming a protective layer CPL on the second electrode CE-R. The first common layer CL-R, the second electrode CE-R, and the protective layer CPL may be primarily disconnected by the dam pattern OVH and secondarily disconnected by the groove GR. Therefore, the second dummy electrode CE-D formed on the dam pattern OVH may be defined as being in a floating state.

[0276] The disconnected first common layer CL-R may contact the side surface of the first pattern layer SI1, a portion SU of the top surface, and the side surface of the second pattern layer SI2 within the groove GR.

[0277] The disconnected second electrode CE-R can come into contact with the side surface PS of the first contact electrode PE-R within the groove GR.

[0278] A dummy pattern OD may be formed on the dam pattern OVH, and the dummy pattern OD may be formed on the dam pattern OVH by disconnecting a portion of each of the first common layer CL-R, the second dummy electrode CE-D, and the protective layer CPL through the dam pattern OVH.

[0279] Thereafter, a first encapsulation layer TE1 may be formed on the protective layer CPL. The first encapsulation layer TE1 may include an inorganic material. The first encapsulation layer TE1 may cover the disconnected portion by the dam pattern OVH and the groove GR.

[0280] 10K, a method for manufacturing a display panel according to an embodiment may include patterning the first common layer CL-R, the second dummy electrode CE-D, the protective layer CPL, and the first encapsulation layer TE1. To form the encapsulation region ENA as described with reference to FIG. 5A, the first common layer CL-R, the second dummy electrode CE-D, the protective layer CPL, and the first encapsulation layer TE1 disposed on the pixel defining layer PDL in the region between adjacent light emitting elements may be removed.

[0281] Thereafter, a second encapsulation layer TE2 may be formed on the first encapsulation layer TE1. The second encapsulation layer TE2 may include an inorganic material. The second encapsulation layer TE2 may contact the first common layer CL-R, the second dummy electrode CE-D, the protective layer CPL, and the pixel defining layer PDL exposed by removing the first encapsulation layer TE1 to form an encapsulation region ENA. The encapsulation region ENA may individually surround the light emitting elements described in FIGS. 5A and 6. Therefore, a path through which moisture / oxygen can enter the light emitting elements may be blocked.

[0282] 11A to 11G are cross-sectional views illustrating a method of manufacturing a display panel according to an embodiment of the present invention. Figures 11A to 11G are views illustrating a method of forming the display panel DP-3 described in Figure 7D. The same or similar reference numerals are used for the same or similar components as those described in Figures 10A to 10K, and redundant descriptions will be omitted. The manufacturing steps for the components disposed below the sixth insulating layer INS6 in the components described in Figure 6 are omitted.

[0283] 11A, a method for manufacturing a display panel according to an embodiment may include forming a sixth insulating layer INS6 on the fifth insulating layer INS5 and forming a seventh insulating layer INS7 on the sixth insulating layer INS6. The fifth insulating layer INS5 may include an inorganic material, and the sixth insulating layer INS6 and the seventh insulating layer INS7 may include an organic material.

[0284] Thereafter, the sixth insulating layer INS6 and the seventh insulating layer INS7 may be removed to expose a portion of the fifth insulating layer INS5.

[0285] Thereafter, the method may include forming a first pattern layer SI1 on the seventh insulating layer INS7 and forming a second pattern layer SI2 on the first pattern layer SI1, where the first pattern layer SI1 includes silicon oxide and the second pattern layer SI2 includes silicon nitride.

[0286] Thereafter, a first contact electrode PE-R may be formed on the second pattern layer SI2. In this embodiment, the first contact electrode PE-R may include molybdenum. The first contact electrode PE-R may be formed by the same process as the third connecting electrode CNE3 described with reference to FIG. 6 and may include the same material.

[0287] Thereafter, a trench pattern layer TI may be formed on the seventh insulating layer INS7 to cover the first contact electrode PE-R. The trench pattern layer TI may include silicon nitride.

[0288] 11B, the method may include patterning the trench pattern layer TI. The patterning may be performed using a dry etching process. The patterned trench pattern layer TI may be formed directly on the first contact electrode PE-R.

[0289] 11C , the method for manufacturing a display panel according to an embodiment may include forming an eighth insulating layer INS8 on the seventh insulating layer INS7 to cover the first contact electrode PE-R. The eighth insulating layer INS8 may include an inorganic material. The eighth insulating layer INS8 may cover the trench pattern layer TI and the first contact electrode PE-R exposed from the trench pattern layer TI.

[0290] Thereafter, the eighth insulating layer INS8 may be patterned. The eighth insulating layer INS8 may be etched to form a groove GR exposing a portion of the first contact electrode PE-R. The patterning may be performed using a dry etching process.

[0291] The side surfaces of the eighth insulating layer INS8 that define the groove GR can expose the side surfaces of the first contact electrode PE-R, the side surfaces of the first pattern layer SI1, and the side surfaces of the second pattern layer SI2.

[0292] 11D, a method for manufacturing a display panel according to an embodiment may include patterning the first contact electrode PE-R. A side surface of the first contact electrode PE-R exposed from the eighth insulating layer INS8 by the groove GR may be etched to form a side surface PS having a predetermined curvature. The patterning may be performed using a wet etching process. According to an embodiment, the wet etching process may be performed after forming a photoresist pattern on the first contact electrode PE-R and using the photoresist pattern as a mask.

[0293] According to this embodiment, as shown in FIG. 11D, the lower portion of the trench pattern layer TI may be exposed from the eighth insulating layer INS8 through the patterned first contact electrode PE-R.

[0294] 11E, the method for manufacturing a display panel according to an embodiment may include patterning the second pattern layer SI2. The patterning may be performed using a dry etching process. Due to the difference in etching rate between the first pattern layer SI1 and the second pattern layer SI2, the second pattern layer SI2 may be removed relatively more. Therefore, the second pattern layer SI2 may expose a portion SU of the top surface of the first pattern layer SI1.

[0295] Since the second pattern layer SI2 and the trench pattern layer TI contain silicon nitride, the trench pattern layer TI can be removed from the eighth insulating layer INS8 simultaneously with the process of patterning the second pattern layer SI2.

[0296] At this time, the eighth insulating layer INS8 may have a trench groove TR having a predetermined inner space defined therein, corresponding to the formation of the trench pattern layer TI. The trench groove TR may surround a corresponding light-emitting region, corresponding to the formation of the first contact electrode PE-R in FIG. 5A.

[0297] Thereafter, a ninth insulating layer INS9 may be formed on the eighth insulating layer INS8. The ninth insulating layer INS9 may include an organic material. The ninth insulating layer INS9 may be formed by removing a portion overlapping the groove GR using a photolithography process so that the ninth insulating layer INS9 does not overlap the groove GR.

[0298] Thereafter, a pixel defining layer PDL may be formed on the ninth insulating layer INS9. The pixel defining layer PDL may include an inorganic material. The pixel defining layer PDL may be formed by removing a portion overlapping the groove GR using an etching process so that the pixel defining layer PDL does not overlap the groove GR.

[0299] 6, the step of forming the first electrode AE-R is performed before the step of forming the pixel defining layer PDL. Here, since the first electrode AE-R is outside the illustrated range, the step of forming the first electrode AE-R is omitted.

[0300] Thereafter, referring to FIG. 11F, the method for manufacturing a display panel according to an embodiment may include forming a first common layer CL-R on the pixel defining layer PDL.

[0301] The first common layer CL-R can be disconnected within the groove GR. The disconnected first common layer CL-R can contact the side surface of the first pattern layer SI1, a portion of the top surface SU, and the side surface of the second pattern layer SI2 within the groove GR. The first common layer CL-R can be more easily disconnected by the trench groove TR.

[0302] 11G, the method may include forming a second electrode CE-R on the first common layer CL-R. The second electrode CE-R may be primarily disconnected by the trench TR and secondarily disconnected by the groove GR. Therefore, the second dummy electrode CE-D formed on the first contact electrode PE-R may be defined as being in a floating state.

[0303] The disconnected second electrode CE-R can come into contact with the side surface PS of the first contact electrode PE-R within the groove GR.

[0304] According to this embodiment, by forming the trench TR in the eighth insulating layer INS8, the step of forming the dam pattern OVH described with reference to FIGS. 10H and 10I can be omitted.

[0305] Thereafter, the steps performed on the second electrode CE-R may be the same as those described with reference to FIGS. 10J to 10K.

[0306] Figure 12A is a cross-sectional view of a display panel according to an embodiment of the present invention. Figure 12B is a cross-sectional view of a display panel according to an embodiment of the present invention. The same / similar reference symbols are used for components that are the same / similar to those described in Figures 6 to 7D, and duplicated descriptions will be omitted. Differences from Figure 7C will be mainly described. Figure 12A is an embodiment of a display panel DP-A showing a region corresponding to Figure 7C. Differences from the display panel DP-2 described in Figure 7C will be mainly described, and duplicated descriptions will be omitted.

[0307] 12A, the first contact electrode PE-R included in the display panel DP-A according to an embodiment may include first to third conductive layers C1, C2, and C3 sequentially stacked on a seventh insulating layer INS7. The thicknesses of the first and third conductive layers C1 and C3 may be smaller than the thickness of the second conductive layer C2.

[0308] The first and third conductive layers C1, C3 may include titanium, and the second conductive layer C2 may include aluminum.

[0309] An eighth insulating layer INS8 covering the first contact electrode PE-R may be disposed on the seventh insulating layer INS7. The eighth insulating layer INS8 may include an inorganic material. According to the present embodiment, a groove GR exposing a portion CU of an upper surface of the first contact electrode PE-R may be defined in the eighth insulating layer INS8. The portion CU of the upper surface of the first contact electrode PE-R may correspond to a portion of an upper surface of the third conductive layer C3. One side IS of the eighth insulating layer INS8 defining the groove GR may have a predetermined curvature.

[0310] The first common layer CL-R may be disconnected within the groove GR, and a portion of the first common layer CL-R may be disposed on a portion CU of the upper surface of the first contact electrode PE-R.

[0311] The second electrode CE-R is disconnected within the groove GR, and a portion of the second electrode CE-R may contact a portion CU of the upper surface of the first contact electrode PE-R and one side surface IS of the eighth insulating layer INS8.

[0312] According to this embodiment, the second electrode CE-R comes into contact with the upper surface of the first contact electrode PE-R, thereby making it possible to increase the contact area between the first contact electrode PE-R and the second electrode CE-R.

[0313] 12B, the first contact electrode PE-R included in the display panel DP-B according to an embodiment may include first to third conductive layers C1, C2, and C3 sequentially stacked on a seventh insulating layer INS7. The first and third conductive layers C1 and C2 may include titanium, and the second conductive layer C2 may include aluminum.

[0314] An eighth insulating layer INS8 covering the first contact electrode PE-R may be disposed on the seventh insulating layer INS7. The eighth insulating layer INS8 may include an inorganic material. According to this embodiment, a groove GR exposing a side surface of the first contact electrode PE-R may be defined in the eighth insulating layer INS8. A portion CS of the side surface of the first contact electrode PE-R may correspond to a portion of the side surface of the second conductive layer C2. The portion CS of the side surface of the first contact electrode PE-R may have a predetermined curvature. The undercut shapes of the first to third conductive layers C1, C2, and C3 may be formed due to differences in etching rates.

[0315] The first common layer CL-R is disconnected within the groove GR, and a portion of the first common layer CL-R may be disposed on the seventh insulating layer INS7.

[0316] The second electrode CE-R is disconnected within the groove GR, and a portion of the second electrode CE-R can contact a portion CS of the side surface of the first contact electrode PE-R.

[0317] Figures 13A to 13G are cross-sectional views illustrating a method of manufacturing a display panel according to an embodiment of the present invention. Figures 13A to 13G are views illustrating a method of forming the display panel DP-A described in Figure 12. The same or similar reference numerals are used to refer to the same or similar components as those described in Figures 10A to 10K, and duplicated descriptions will be omitted.

[0318] 13A, a method for manufacturing a display panel according to an embodiment may include forming a sixth insulating layer INS6 on the fifth insulating layer INS5 and forming a seventh insulating layer INS7 on the sixth insulating layer INS6. The fifth insulating layer INS5 may include an inorganic material, and the sixth insulating layer INS6 and the seventh insulating layer INS7 may include an organic material.

[0319] Thereafter, the sixth insulating layer INS6 and the seventh insulating layer INS7 may be removed to expose a portion of the fifth insulating layer INS5.

[0320] Thereafter, a step of forming a first contact electrode PE-R on the seventh insulating layer INS7 may be included. The step of forming the first contact electrode PE-R may include a step of forming a first conductive layer C1 containing titanium on the seventh insulating layer INS7, a step of forming a second conductive layer C2 containing aluminum on the first conductive layer C1, and a step of forming a third conductive layer C3 containing titanium on the second conductive layer C2.

[0321] Thereafter, the first to third conductive layers C1, C2, and C3 can be patterned to form the first contact electrode PE-R.

[0322] 13B, the method for manufacturing a display panel according to an embodiment may include forming an eighth insulating layer INS8 on the seventh insulating layer INS7 to cover the first contact electrode PE-R. The eighth insulating layer INS8 may include an inorganic material.

[0323] Thereafter, the method may include patterning the eighth insulating layer INS8. The eighth insulating layer INS8 may be etched to form a groove GR that exposes a portion CU of the top surface of the first contact electrode PE-R. The patterning may be performed using a dry etching process. A side surface IS of the eighth insulating layer INS8 that defines the groove GR may have a predetermined curvature.

[0324] 13C and 13D, a method for manufacturing a display panel according to an embodiment may include forming a ninth insulating layer INS9 on the eighth insulating layer INS8. The ninth insulating layer INS9 may include an organic material. The ninth insulating layer INS9 may be formed by removing portions overlapping with the grooves GR using a photolithography process so that the ninth insulating layer INS9 does not overlap with the grooves GR.

[0325] Thereafter, a pixel defining layer PDL may be formed on the ninth insulating layer INS9. The pixel defining layer PDL may include an inorganic material. The pixel defining layer PDL may be formed by removing a portion overlapping the groove GR using an etching process so that the pixel defining layer PDL does not overlap the groove GR. By removing the pixel defining layer PDL, a portion CU of an upper surface of the first contact electrode PE-R may be exposed.

[0326] Thereafter, a pixel defining layer PDL may be formed on the ninth insulating layer INS9. The pixel defining layer PDL may include an inorganic material. The pixel defining layer PDL may be formed by removing a portion overlapping the groove GR using an etching process so that the pixel defining layer PDL does not overlap the groove GR. The pixel defining layer PDL may expose a portion CU of an upper surface of the first contact electrode PE-R.

[0327] Thereafter, a dam pattern may be formed on the pixel defining layer PDL. The forming of the dam pattern may include forming a first pattern OV1 and a second pattern OV2. The first pattern OV1 and the second pattern OV2 may include an inorganic material. The first pattern OV1 may include silicon nitride, and the second pattern OV2 may include silicon oxide.

[0328] 13E, a method for manufacturing a display panel according to an embodiment may include patterning a first pattern OV1 and a second pattern OV2. The patterning may be performed using a dry etching process. The patterned first pattern OV1 and second pattern OV2 may overlap the first contact electrode PE-R and be formed on the pixel defining layer PDL. The shapes of the first pattern OV1 and the second pattern OV2 may be formed due to a difference in etching rate.

[0329] 6, the step of forming the first electrodes AE-R is performed before the step of forming the pixel defining layer PDL. Here, since the first electrodes AE-R are outside the illustrated range, the step of forming the first electrodes AE-R is omitted.

[0330] Thereafter, the method may include forming a first common layer CL-R on the pixel defining layer PDL, forming a second electrode CE-R on the first common layer CL-R, and forming a protective layer CPL on the second electrode CE-R. The first common layer CL-R, the second electrode CE-R, and the protective layer CPL may be primarily separated by the dam pattern OVH and secondarily separated by the groove GR. Therefore, the second dummy electrode CE-D formed on the dam pattern OVH may be defined as being in a floating state.

[0331] The disconnected first common layer CL-R may be disposed on a portion CU of the upper surface of the first contact electrode PE-R within the groove GR.

[0332] The disconnected second electrode CE-R may contact a portion CU of the upper surface of the first contact electrode PE-R within the groove GR and a side surface IS of the eighth insulating layer INS8 that defines the groove GR.

[0333] A dummy pattern OD may be formed on the dam pattern OVH, and the dummy pattern OD may be formed on the dam pattern OVH by disconnecting a portion of each of the first common layer CL-R, the second dummy electrode CE-D, and the protective layer CPL through the dam pattern OVH.

[0334] Thereafter, the steps of FIGS. 13F and 13G performed on the protective layer CPL may be the same as those described with reference to FIGS. 10J to 10K.

[0335] 14 is a cross-sectional view of a display panel according to an embodiment of the present invention. The same or similar reference numerals are used for the same or similar components as those described in FIGS. 6 to 7D, and redundant descriptions will be omitted. Differences from FIG. 7A will be mainly described.

[0336] Figure 14 shows an embodiment of a display panel DP-C showing an area corresponding to Figure 7A. Differences from the display panel DP described in Figure 7A will be mainly described, and overlapping descriptions will be omitted.

[0337] 14, in a display panel DP-C according to an embodiment, a first power line ES-R may be disposed on a sixth insulating layer INS6, and a first contact electrode PE-R may be disposed on a seventh insulating layer INS7. The first power line ES-R and the first contact electrode PE-R may be connected to each other through a contact hole CNT defined in the seventh insulating layer INS7, as described in FIG.

[0338] An eighth insulating layer INS8 may be disposed on the seventh insulating layer INS7. A groove GR exposing a portion PU of an upper surface of the first contact electrode PE-R and an auxiliary contact hole CT exposing another portion of the upper surface may be defined in the eighth insulating layer INS8.

[0339] A first electrode AE-R is arranged in the portion of the eighth insulating layer INS8 that overlaps with the first light-emitting region PXA-R, and an auxiliary electrode BE can be arranged in the portion of the eighth insulating layer INS8 that overlaps with the non-light-emitting region NPXA.

[0340] The auxiliary electrode BE is connected to the first contact electrode PE-R through the auxiliary contact hole CT, and the first contact electrode PE-R can be connected to the first power line ES-R through the contact hole CNT defined in the seventh insulating layer INS7 as described in Figure 9.

[0341] An etching prevention layer TPL may be disposed on an edge of the first electrode AE-R and the auxiliary electrode BE. The etching prevention layer TPL may prevent damage such as heat from being applied to the first electrode AE-R and the auxiliary electrode BE during a subsequent dry etching process. The etching prevention layer TPL may include an inorganic material.

[0342] A pixel defining layer PDL may be disposed on the eighth insulating layer INS8 to cover the auxiliary electrode BE and the first electrode AE-R. An opening PDL-OP exposing at least a portion of the first electrode AE-R may be defined in the pixel defining layer PDL. The pixel defining layer PDL may be disconnected within the groove GR.

[0343] A first common layer CL-R may be disposed on the first electrode AE-R. The first common layer CL-R may be disconnected within the groove GR, and a portion of the first common layer CL-R may be disposed on a portion PU of the upper surface of the first contact electrode PE-R.

[0344] A portion of the first common layer CL-R disposed in the groove GR may be in contact with a side surface of the eighth insulating layer ISN8. The first common layer CL-R has a predetermined thickness and is disposed in the groove GR, so that the second electrode CE-R may be disposed spaced apart from the seventh insulating layer INS7 by a height corresponding to the thickness of the first common layer CL-R.

[0345] A second electrode CE-R may be disposed on the first common layer CL-R. The second electrode CE-R may be disconnected within the groove GR, and a portion of the second electrode CE-R may be disposed on the first common layer CL-R within the groove GR.

[0346] The second electrode CE-R disposed in the groove GR is spaced apart from the seventh insulating layer INS7 by a distance approximately equal to the thickness of the first common layer CL-R. According to this embodiment, the thickness of the first common layer CL-R allows the disconnected second electrode CE-R to contact the side surface BS of the auxiliary electrode BE. Conversely, the thickness of the first common layer CL-R is adjusted so that the second electrode CE-R can contact the side surface BS of the auxiliary electrode BE. For example, the height (thickness) of the eighth insulating layer INS8 on the first contact electrode PE-R is approximately the same as the height (thickness) of the first common layer CL-R on the first contact electrode PE-R. Therefore, the positions of the upper surfaces of the eighth insulating layer INS8 and the first common layer CL-R on the first contact electrode PE-R are approximately the same. In the example of FIG. 14, the height (thickness) of the first common layer CL-R on the first contact electrode PE-R is slightly smaller than the height (thickness) of the eighth insulating layer INS8 on the first contact electrode PE-R. 14, the auxiliary electrode BE protrudes laterally beyond the eighth insulating layer INS8. Therefore, in the example of Fig. 14, the second electrode CE-R is in contact with the lower surface and side surface of the auxiliary electrode BE.

[0347] A protective layer CPL is disposed on the second electrode CE-R, and the protective layer CPL can be disconnected within the groove GR.

[0348] The dam pattern OVH is disposed on the pixel defining layer PDL overlapping the first contact electrode PE-R, and may include a first pattern OV1 and a second pattern OV2 disposed on the first pattern OV1.

[0349] A dummy pattern OD may be disposed on the dam pattern OVH. The dummy pattern OD may be formed by disposing a portion of each of the first common layer CL-R, the second dummy electrode CE-D, and the protective layer CPL. The first encapsulation layer TE1 and the second encapsulation layer TE2 may cover the dam pattern OVH in the non-light-emitting region NPXA.

[0350] Figures 15A to 15I are cross-sectional views illustrating a method of manufacturing a display panel according to an embodiment of the present invention. Figures 15A to 15I are views illustrating a method for illustrating the display panel DP-C described in Figure 14. The same or similar reference numerals are used for the same or similar components as those described in Figures 10A to 10K, and duplicated descriptions will be omitted.

[0351] 15A, a method for manufacturing a display panel according to an embodiment may include forming a sixth insulating layer INS6 on the fifth insulating layer INS5 and forming a seventh insulating layer INS7 on the sixth insulating layer INS6. The fifth insulating layer INS5 may include an inorganic material, and the sixth insulating layer INS6 and the seventh insulating layer INS7 may include an organic material.

[0352] Thereafter, the sixth insulating layer INS6 and the seventh insulating layer INS7 may be removed to expose a portion of the fifth insulating layer INS5.

[0353] Thereafter, a first contact electrode PE-R may be formed on the seventh insulating layer INS7. In this embodiment, the first contact electrode PE-R may include molybdenum. The first contact electrode PE-R may be formed by the same process as the third connecting electrode CNE3 described with reference to FIG. 6 and may include the same material.

[0354] 15B, the method for manufacturing a display panel according to an embodiment may include forming an eighth insulating layer INS8 on the seventh insulating layer INS7 to cover the first contact electrode PE-R. The eighth insulating layer INS8 may include an inorganic material.

[0355] Thereafter, the eighth insulating layer INS8 may be patterned. The eighth insulating layer INS8 may be etched to form a groove GR exposing a portion PU of the upper surface of the first contact electrode PE-R and an auxiliary contact hole CT exposing another portion of the upper surface of the first contact electrode PE-R.

[0356] 15C, a method for manufacturing a display panel according to an embodiment may include forming a first electrode AE-R and an auxiliary electrode BE on an eighth insulating layer INS8 and forming an etch stop layer TPL on the first electrode AE-R and the auxiliary electrode BE. The first electrode AE-R and the auxiliary electrode BE may be formed by the same process and may include the same material. The auxiliary electrode BE may also be formed in an auxiliary contact hole CT and may be connected to the first contact electrode PE-R.

[0357] The etching prevention layer TPL may include one of indium tin oxide and indium zinc oxide, and the etching prevention layer TPL may prevent damage such as heat from being applied to the first electrode AE-R and the auxiliary electrode BE during a subsequent dry etching process.

[0358] 15D and 15E, the method for manufacturing a display panel according to an embodiment may include forming a pixel defining layer PDL on the eighth insulating layer INS8. The pixel defining layer PDL may include an inorganic material. The pixel defining layer PDL may cover the etching stop layer TPL.

[0359] Thereafter, a dam pattern OVH may be formed on the pixel defining layer PDL. The forming of the dam pattern OVH may include forming a first pattern OV1 and a second pattern OV2. The first pattern OV1 and the second pattern OV2 may include an inorganic material. The first pattern OV1 may include silicon nitride, and the second pattern OV2 may include silicon oxide.

[0360] Thereafter, the method may include patterning the first pattern OV1 and the second pattern OV2. The patterning may be performed using a dry etching process. The patterned first pattern OV1 and second pattern OV2 may overlap the first contact electrode PE-R and be formed on the pixel defining layer PDL. The shapes of the first pattern OV1 and the second pattern OV2 may be formed due to a difference in etching rate.

[0361] 15F, the method may include patterning a pixel defining layer PDL. The pixel defining layer PDL may be patterned so as not to overlap the groove GR. At this time, an opening PDL-OP may be formed that overlaps the first electrode AE-R and the etching stop layer TPL. The patterning may be performed using a dry etching process.

[0362] According to the present embodiment, since the etching stopper layer TPL is already formed on the first electrodes AE-R and the auxiliary electrodes BE in the step of patterning the pixel defining layer PDL by a dry etching process, the first electrodes AE-R and the auxiliary electrodes BE can be prevented from being damaged by heat, etc. Therefore, a method for manufacturing a display panel with improved reliability can be provided.

[0363] Thereafter, the etching stop layer TPL disposed on the first electrode AE-R may be removed. The removing step may be performed using a wet etching process. At this time, the remaining etching stop layer TPL may overlap the edge of the first electrode AE-R and be covered by the pixel defining layer PDL. Also, in this step, the side surfaces of the eighth insulating layer INS8 under the auxiliary electrode BE and the side surfaces of the etching stop layer TPL under the auxiliary electrode BE are etched. As a result, as shown in FIG. 15F, the auxiliary electrode BE protrudes laterally between the eighth insulating layer INS8 and the etching stop layer TPL in the groove GR.

[0364] 15G, a method for manufacturing a display panel according to an embodiment may include forming a first common layer CL-R on a pixel defining layer PDL, forming a second electrode CE-R on the first common layer CL-R, and forming a protective layer CPL on the second electrode CE-R. The first common layer CL-R, the second electrode CE-R, and the protective layer CPL may be primarily disconnected by the dam pattern OVH and secondarily disconnected by the groove GR. Therefore, the second dummy electrode CE-D formed on the dam pattern OVH may be defined as being in a floating state.

[0365] According to this embodiment, the disconnected second electrode CE-R is disposed on the first common layer CL-R within the groove GR and can be in contact with the side surface BS of the auxiliary electrode BE.

[0366] A dummy pattern OD may be formed on the dam pattern OVH, and the dummy pattern OD may be formed on the dam pattern OVH by disconnecting a portion of each of the first common layer CL-R, the second dummy electrode CE-D, and the protective layer CPL through the dam pattern OVH.

[0367] 15H, a first encapsulation layer TE1 may be formed on the protective layer CPL. The first encapsulation layer TE1 may include an inorganic material. The first encapsulation layer TE1 may cover the disconnected portions due to the dam pattern OVH and the groove GR.

[0368] 15I, a method for manufacturing a display panel according to an embodiment may include patterning the first common layer CL-R, the second dummy electrode CE-D, the protective layer CPL, and the first encapsulation layer TE1. As described with reference to FIG. 5A, the first common layer CL-R, the second dummy electrode CE-D, the protective layer CPL, and the first encapsulation layer TE1 disposed on the pixel defining layer PDL in the region between adjacent light emitting elements may be removed to form the encapsulation region ENA.

[0369] Thereafter, a second encapsulation layer TE2 may be formed on the first encapsulation layer TE1. The second encapsulation layer TE2 may include an inorganic material. The second encapsulation layer TE2 may contact the first common layer CL-R, the second dummy electrode CE-D, the protective layer CPL, and the pixel defining layer PDL exposed by removing the first encapsulation layer TE1 to form an encapsulation region ENA. The encapsulation region ENA may individually surround the light emitting elements described in FIGS. 5A and 6. Therefore, a path through which moisture / oxygen can enter the light emitting elements may be blocked.

[0370] Figure 16 is a cross-sectional view of a light emitting device according to an embodiment of the present invention. Figure 16 can be applied to the light emitting device OLED-R described in Figure 6. It can also be applied to the light emitting devices included in each of the pixels PX-R, PX-G, and PX-B described in Figure 5A.

[0371] 16, the light emitting element OLED according to an embodiment may include a first electrode AE, a second electrode CE facing the first electrode AE, and a common layer CL disposed between the first electrode AE ​​and the second electrode CE. The common layer CL may include first and second light emitting stacks ST1 and ST2. While FIG. 16 illustrates the light emitting element OLED including two light emitting stacks, the light emitting element OLED may include more than two light emitting stacks.

[0372] The light emitting element OLED may include a first charge generation layer CGL1 disposed between the first and second light emitting stacks ST1 and ST2.

[0373] When a voltage is applied to the first charge generation layer CGL1, it generates charges (electrons and holes) by forming a complex through an oxidation-reduction reaction.The first charge generation layer CGL1 then provides the generated charges to the adjacent stacks ST1 and ST2.The first charge generation layer CGL1 can double the efficiency of the current generated in the adjacent stacks ST1 and ST2 and can also play a role in regulating the charge balance between the adjacent stacks ST1 and ST2.

[0374] Each of the first charge generation layers CGL1 may include an n-type layer and a p-type layer. The first charge generation layer CGL1 may have a structure in which an n-type layer and a p-type layer are bonded to each other. However, the first charge generation layer CGL1 is not limited thereto, and may include only one of an n-type layer and a p-type layer. The n-type layer may be a charge generation layer that provides electrons to an adjacent stack. The n-type layer may be a layer in which a base material is doped with an n-dopant. The p-type layer may be a charge generation layer that provides holes to an adjacent stack.

[0375] In one embodiment, the thickness of each first charge generation layer CGL1 may be from 1 Å to 150 Å. The concentration of the n-dopant doped in the first charge generation layer CGL1 may be from 0.1% to 3%, specifically 1% or less. If the concentration is less than 0.1%, the effect of the first charge generation layer CGL1 in controlling charge balance may not be fully realized. If the concentration is greater than 3%, the light efficiency of the light emitting element OLED may be reduced.

[0376] Each of the first charge generation layers CGL1 may include a charge generation compound selected from an arylamine-based organic compound, a metal, a metal oxide, a carbide, a fluoride, or a mixture. For example, the arylamine-based organic compound may include α-NPD, 2-TNATA, TDATA, MTDATA, sprio-TAD, or sprio-NPB. The metal may include cesium (Cs), molybdenum (Mo), vanadium (V), titanium (Ti), tungsten (W), barium (Ba), or lithium (Li). The metal oxide, carbide, and fluoride may include Re2O7, MoO3, V2O5, WO3, TiO2, Cs2CO3, BaF, LiF, or CsF. However, the materials of the first charge generation layer CGL1 are not limited to these examples.

[0377] Each of the first and second light-emitting stacks ST1 and ST2 may include a light-emitting layer. The first light-emitting stack ST1 may include a first light-emitting layer BEML1, and the second light-emitting stack ST2 may include a second light-emitting layer BEML2. The light-emitting layers included in the first and second light-emitting stacks ST1 and ST2 may emit light of the same color or different colors.

[0378] The light-emitting element OLED can emit light from the first electrode AE ​​toward the second electrode CE. In one embodiment of the light-emitting element OLED, each of the stacks ST1 and ST2 can include a hole transport region HTR1 and HTR2 and an electron transport region ETR1 and ETR2. The hole transport regions HTR1 and HTR2 can transport holes provided from the first electrode AE ​​or the first charge generation layer CGL1 to the light-emitting layer. The electron transport regions ETR1 and ETR2 can transport electrons provided from the second electrode CE or the first charge generation layer CGL1 to the light-emitting layer.

[0379] In the light emitting device OLED according to an embodiment, a structure is illustrated in which the hole transport regions HTR1 and HTR2 are disposed below the emitting layers BEML1 and BEML2 included in the stacks ST1 and ST2, and the electron transport regions ETR1 and ETR2 are disposed above the emitting layers BEML1 and BEML2 included in the stacks ST1 and ST2, based on the light emission direction. That is, the light emitting device OLED according to an embodiment may have a normal device structure. However, without being limited thereto, the light emitting device OLED may have an inverted device structure in which the electron transport regions ETR1 and ETR2 are disposed below the emitting layers BEML1 and BEML2 included in the stacks ST1 and ST2, based on the light emission direction, and the hole transport regions HTR1 and HTR2 are disposed above the emitting layers BEML1 and BEML2 included in the stacks ST1 and ST2.

[0380] Each of the hole transport regions HTR1 and HTR2 may include a hole injection layer HIL1 and HIL2 and a hole transport layer HTL1 and HTL2 disposed on the hole injection layer HIL1 and HIL2. The hole transport layers HTL1 and HTL2 may be in contact with the lower surface of the light emitting layer. However, without being limited thereto, the hole transport regions HTR1 and HTR2 may further include a hole-side additional layer disposed on the hole transport layer HTL1 and HTL2. The hole-side additional layer may include at least one of a hole buffer layer, a light-emitting auxiliary layer, and an electron blocking layer. The hole buffer layer may be a layer that compensates for the resonance distance depending on the wavelength of light emitted from the light emitting layer to increase light emission efficiency. The electron blocking layer may be a layer that prevents electron injection from the electron transport region to the hole transport region.

[0381] The electron transport regions ETR1 and ETR2 may include an electron transport layer. The electron transport regions ETR1 and ETR2 may further include an electron injection layer disposed on the electron transport layer. For example, the second electron transport region ETR2 included in the second light-emitting stack ST2 may further include a second electron injection layer EIL2 disposed on the second electron transport layer ETL2. The electron transport regions ETR1 and ETR2 may further include an additional layer on the electron side disposed between the electron transport layer and the light-emitting layer. The additional layer on the electron side may include at least one of an electron buffer layer and a hole blocking layer.

[0382] In an OLED light-emitting element according to an embodiment, the first electrode AE ​​may be a reflective electrode. For example, the first electrode AE ​​may include Ag, Mg, Cu, Al, Pt, Pd, Au, Ni, Nd, Ir, Cr, Li, Ca, LiF / Ca, LiF / Al, Mo, Ti, W, In, Zn, Sn, or a compound or mixture thereof (e.g., a mixture of Ag and Mg), which have high reflectivity. Alternatively, the first electrode AE ​​may have a multi-layer structure including a reflective film formed of the above materials and a transparent conductive film formed of indium tin oxide (ITO), indium zinc oxide (IZO), zinc oxide (ZnO), indium tin zinc oxide (ITZO), or the like. For example, the first electrode AE ​​may have a two-layer structure of ITO / Ag or a three-layer structure of ITO / Ag / ITO, but is not limited thereto. Furthermore, the embodiment is not limited thereto, and the first electrode AE ​​may include the above-mentioned metal materials, a combination of two or more metal materials selected from the above-mentioned metal materials, or oxides of the above-mentioned metal materials. The thickness of the first electrode AE ​​may be from about 70 nm to about 1000 nm, for example, from about 100 nm to about 300 nm.

[0383] In the light-emitting device OLED according to an embodiment, each of the hole transport regions HTR1 and HTR2 may have a single layer made of a single material, a single layer made of a plurality of different materials, or a multi-layer structure having a plurality of layers made of a plurality of different materials.

[0384] Each of the hole transport regions HTR1 and HTR2 can be formed using various methods such as vacuum deposition, spin coating, casting, Langmuir-Blodgett (LB) method, inkjet printing, laser printing, laser induced thermal imaging (LITI), etc.

[0385] Each of the hole transport regions HTR1 and HTR2 is made of a phthalocyanine compound such as copper phthalocyanine, DNTPD (N1,N1'-([1,1'-biphenyl]-4,4'-diyl) bis(N1-phenyl-N4,N4-di-m-tolylbenzene-1,4-diamine)), m-MTDATA (4,4',4"-[tris(3-methylphenyl)phenylamino]triphenylamine), TDATA (4,4',4"-Tris(N,N-diphenylamino) triphenylamine), 2-TNATA(4,4',4”-tris[N(2-naphthyl)-N-phenylamino]-triphenylamine), PEDOT / PSS(Poly(3,4-ethylenedioxythiophene) / Poly(4-styrenesulfonate)), PANI / DBSA(Polyaniline / Dodecylbenzenesulfonic acid), PANI / CSA(Polyaniline / Camphor sulfonicacid), PANI / PSS (Polyaniline / Poly(4-styrenesulfonate)), NPB (N, N'-di(naphthalene-l-yl)-N, N'-diphenyl-benzidine), triphenylamine-containing polyetherketone (TPAPEK) 4-Isopropyl-4'-methyldiphenyliodonium [Tetrakis(pentafluorophenyl) borate], HATCN(dipyrazino[2, 3-f:2', 3'-h] quinoxaline-2,3,6,7,10,11-hexacarbonitrile), etc.

[0386] Each of the hole transport regions HTR1 and HTR2 may be made of a carbazole derivative such as N-phenylcarbazole or polyvinylcarbazole, a fluorene derivative, a triphenylamine derivative such as TPD (N,N'-bis(3-methylphenyl)-N,N'-diphenyl-[1,1'-biphenyl]-4,4'-diamine) or TCTA (4,4',4"-tris(N-carbazolyl) triphenylamine), NPB (N,N'-di(naphthalene-l-yl)-N,N'-diphenyl-benzidine), TAPC (4,4'-Cyclohexylidene bis[N,N-bis(4-methylphenyl) benzolamine]), HMTPD (4,4'-Bis[N,N'-(3-tolyl) amino]-3,3'-dimethylbiphenyl), or mCP (1,3-Bis(N-carbazolyl) benzene). etc. may be included.

[0387] In addition, each of the hole transport regions HTR1 and HTR2 may contain CzSi (9-(4-tert-Butylphenyl)-3,6-bis(triphenylsilyl)-9H-carbazole), CCP (9-phenyl-9H-3,9'-bicarbazole), or mDCP (1,3-bis(1,8-dimethyl-9H-carbazol-9-yl) benzene), etc.

[0388] The hole transport regions HTR1 and HTR2 may contain the above-mentioned hole transport region compounds in at least one of the hole injection layers HIL1 and HIL2, the hole transport layers HTL1 and HTL2, and the hole-side additional layer.

[0389] The thickness of each of the hole transport regions HTR1 and HTR2 may be about 10 nm to about 1000 nm, for example, about 10 nm to about 500 nm. The thickness of each of the hole injection layers HIL1 and HIL2 may be about 5 nm to about 100 nm. The thickness of each of the hole transport layers HTL1 and HTL2 may be about 5 nm to about 100 nm. If the hole transport regions HTR1 and HTR2 include a hole-side additional layer, the thickness of the hole-side additional layer may be about 1 nm to about 100 nm. When the thicknesses of the hole transport regions HTR1 and HTR2 and the layers included therein satisfy the above-mentioned ranges, satisfactory hole transport characteristics can be obtained without a substantial increase in driving voltage.

[0390] In addition to the materials mentioned above, each of the hole transport regions HTR1 and HTR2 may further include a charge generation material to improve conductivity. The charge generation material may be uniformly or non-uniformly dispersed within the hole transport regions HTR1 and HTR2. The charge generation material may be, for example, a p-type dopant. Examples of p-type dopants include, but are not limited to, at least one of a metal halide compound, a quinone derivative, a metal oxide, and a cyano group-containing compound. Examples of p-type dopants include, but are not limited to, metal halide compounds such as CuI and RbI, quinone derivatives such as TCNQ (Tetracyanoquinodimethane) and F4-TCNQ (2,3,5,6-tetrafluoro-7,7',8,8-tetracyanoquinodimethane), and metal oxides such as tungsten oxide and molybdenum oxide.

[0391] The first light-emitting layer BEML1 and the second light-emitting layer BEML2 may be blue or green light-emitting layers. The blue or green light-emitting layer may include a host material and a dopant material. The blue and green light-emitting layers may each include a hole-transporting host material containing a carbazole derivative moiety or an amine derivative moiety. The blue and green light-emitting layers may each include an electron-transporting host material containing a nitrogen-containing aromatic ring structure, such as a pyridine derivative moiety, a pyridazine derivative moiety, a pyrimidine derivative moiety, a pyrazine derivative moiety, or a triazine derivative moiety.

[0392] Each of the blue and green light-emitting layers may include a host material such as an anthracene derivative, a pyrene derivative, a fluoranthene derivative, a chrysene derivative, a dihydrobenzanthracene derivative, or a triphenylene derivative, etc. Each of the blue and green light-emitting layers may further include a common host material known in the art. For example, each of the blue and green light-emitting layers may contain at least one of DPEPO (Bis[2-(diphenylphosphino)phenyl]ether oxide), CBP (4,4'-Bis(carbazol-9-yl) biphenyl), mCP (1,3-Bis(carbazol-9-yl) benzene), PPF (2,8-Bis(diphenylphosphoryl) dibenzo[b,d]furan), TCTA (4,4',4"-Tris(carbazol-9-yl)-triphenylamine), and TPBi (1,3,5-tris(1-phenyl-1H-benzo[d]imidazole-2-yl) benzene). However, the host material may be, but is not limited to, Alq3 (tris(8-hydroxyquinolino) aluminum), PVK (poly(N-vinylcarbazole), ADN (9,10-di(naphthalene-2-yl) Examples of host materials that can be used include 4,4'-bis(9-carbazolyl)-2,2'-dimethyl-biphenyl (CDBP), 2-methyl-9,10-bis(naphthalen-2-yl) anthracene (MADN), hexaphenyl cyclotriphosphazene (CP1), 1,4-bis(triphenylsilyl) benzene (UGH2), hexaphenylcyclotrisiloxane (DPSiO3), and octaphenylcyclotetra siloxane (DPSiO4).

[0393] In one embodiment, the blue light-emitting layer may contain known fluorescent dopant materials, such as styryl derivatives (e.g., 1,4-bis[2-(3-N-ethylcarbazoryl) vinyl]benzene (BCzVB), 4-(di-p-tolylamino)-4'-[(di-p-tolylamino) styryl]stilbene (DPAVB), N-(4-((E)-2-(6-((E)-4-(diphenylamino) styryl) naphthalen-2-yl) vinyl) phenyl)-N-phenylbenzenamine (N-BDAVBi)), 4,4'-bis[2-(4-(N,N-diphenylamino) phenyl] vinyl]biphenyl (DPAVBi), perylene and its derivatives (e.g., 2,5,8,11-Tetra-t-butylperylene (TBP)), pyrene and its derivatives (e.g., 1,1-dipyrene, 1,4-dipyrenylbenzene, 1,4-Bis(N,N-Diphenylamino) pyrene), etc.

[0394] The green light-emitting layer may contain a known phosphorescent dopant. For example, the phosphorescent dopant may be a metal complex containing iridium (Ir), platinum (Pt), osmium (Os), gold (Au), titanium (Ti), zirconium (Zr), hafnium (Hf), europium (Eu), terbium (Tb), or thulium (Tm). Specifically, Firpic (iridium(III) bis(4,6-difluorophenylpyridinato-N,C2') picolinate), Fir6 (Bis(2,4-difluorophenylpyridinato)-tetrakis(1-pyrazolyl)borate iridium(III)), or PtOEP (platinum octaethyl porphyrin) may be used as the phosphorescent dopant.

[0395] Each of the electron transport regions ETR1 and ETR2 may have a single layer structure made of a single material, a single layer structure made of multiple different materials, or a multilayer structure made of multiple layers made of multiple different materials. For example, at least a portion of the electron transport regions ETR1 and ETR2 may include an electron transport layer ETL4 and an electron injection layer EIL4.

[0396] Each of the electron transport regions ETR1 and ETR2 can be formed using various methods such as vacuum deposition, spin coating, casting, Langmuir-Blodgett (LB) method, inkjet printing, laser printing, laser induced thermal imaging (LITI), etc.

[0397] The electron transport regions ETR1 and ETR2 may include an anthracene-based compound, but are not limited thereto. Examples of the electron transport regions ETR1 and ETR2 include, but are not limited to, Alq3 (Tris(8-hydroxyquinolinato) aluminum), 1,3,5-tri[(3-pyridyl)-phen-3-yl]benzene, T2T (2,4,6-tris(3'-(pyridin-3-yl) biphenyl-3-yl)-1,3,5-triazine), 2-(4-(N-phenylbenzoimidazol-1-yl) phenyl)-9,10-dinaphthylanthracene, and TPBi(1,3,5-Tri(1-phenyl-1H-benzo[d]imidazol-2-yl) benzene), BCP(2,9-Dimethyl-4,7-diphenyl-1, 10-phenanthroline), Bphen(4,7-Diphenyl-1, 10-phenanthroline), TAZ(3-(4-Biphenylyl)-4-phenyl-5-tert-butylphenyl-1,2,4-triazole), NTAZ(4-(Nap hthalen-1-yl)-3, 5-diphenyl-4H-1, 2, 4-triazole), tBu-PBD(2-(4-Biphenylyl)-5-(4-tert-butylph enyl)-1,3,4-oxadiazole), BAlq(Bis(2-methyl-8-quinolinolato-N1, O8)-(1,1'-Biphenyl-4-olato) aluminum), Bebq2 (berylliumbis(benzoquinolin-10-olate)), ADN (9,10-di(naphthalene-2-yl) anthracene), BmPyPhB (1,3-Bis[3,5-di(pyridin-3-yl) phenyl]benzene), and mixtures thereof.

[0398] Each of the electron transport regions ETR1 and ETR2 may contain a metal halide such as LiF, NaCl, CsF, RbCl, RbI, CuI, or KI, a lanthanum metal such as Yb, or a co-deposition material of the above metal halide and a lanthanum metal. For example, the electron transport regions ETR1 and ETR2 may contain co-deposition materials such as KI:Yb or RbI:Yb. The electron transport regions ETR1 and ETR2 may contain two or more materials selected from Mg, Ag, Yb, and Al. For example, the electron transport regions ETR1 and ETR2 may contain Mg and Yb.

[0399] Meanwhile, the electron transport regions ETR1 and ETR2 may be made of metal oxides such as Li2O and BaO, or Liq (8-hydroxyl-lithium quinolate), but the embodiment is not limited thereto. Each of the electron transport regions ETR1 and ETR2 may also be made of a material in which an electron transport material and an insulating organometal salt are mixed. The organometal salt may have an energy band gap of approximately 4 eV or more. Specifically, the organometal salt may include, for example, metal acetate, metal benzoate, metal acetoacetate, metal acetylacetonate, or metal stearate.

[0400] Each of the electron transport regions ETR1 and ETR2 may further include at least one of BCP (2,9-dimethyl-4,7-diphenyl-1,10-phenanthroline) and Bphen (4,7-diphenyl-1,10-phenanthroline) in addition to the materials mentioned above, but the embodiment is not limited thereto.

[0401] The electron transport regions ETR1 and ETR2 may include the above-described electron transport region compounds in the electron injection layer or electron transport layer. When the electron transport regions ETR1 and ETR2 include an additional layer on the electron side, the additional layer on the electron side may include the above-described materials. In one embodiment, the electron injection layer EIL4 may be composed of two or more materials selected from Mg, Ag, Yb, and Al. The electron injection layer EIL4 may be composed of, for example, a mixture of Mg and Yb.

[0402] The thickness of each of the electron transport regions ETR1 and ETR2 may be, for example, about 10 nm to about 150 nm. The thickness of the electron transport layer may be about 0.1 nm to about 100 nm, for example, about 0.3 nm to about 50 nm. When the thickness of the electron transport layer satisfies the above-mentioned range, satisfactory electron transport properties can be obtained without a substantial increase in driving voltage.

[0403] A second electrode CE is provided on the plurality of stacks ST1 and ST2. The second electrode CE may be a common electrode. The second electrode CE may be a cathode or an anode, but the embodiment is not limited thereto. For example, if the first electrode AE ​​is an anode, the second electrode CE may be a cathode, and if the first electrode AE ​​is a cathode, the second electrode CE may be an anode.

[0404] The second electrode CE may be a semi-transparent electrode or a transparent electrode. When the second electrode CE is a transparent electrode, the second electrode CE may be made of a transparent metal oxide such as indium tin oxide (ITO), indium zinc oxide (IZO), zinc oxide (ZnO), or indium tin zinc oxide (ITZO).

[0405] When the second electrode CE is a semi-transmissive electrode or a reflective electrode, the second electrode CE may include Ag, Mg, Cu, Al, Pt, Pd, Au, Ni, Nd, Ir, Cr, Li, Ca, LiF / Ca, LiF / Al, Mo, Ti, Yb, W, In, Zn, Sn, or a compound or mixture containing any of these (e.g., AgMg, AgYb, or MgAg). Alternatively, the second electrode CE may have a multi-layer structure including a reflective or semi-transmissive film formed of the above materials and a transparent conductive film formed of indium tin oxide (ITO), indium zinc oxide (IZO), zinc oxide (ZnO), indium tin zinc oxide (ITZO), or the like. For example, the second electrode CE may include any of the above-mentioned metal materials, a combination of two or more of the above-mentioned metal materials, or oxides of the above-mentioned metal materials.

[0406] Meanwhile, in an embodiment, a protective layer CPL may be further disposed on the second electrode CE of the light emitting element OLED. The protective layer CPL may include multiple layers or a single layer.

[0407] In one embodiment, the protective layer CPL may be an organic layer or an inorganic layer. For example, when the protective layer CPL includes an inorganic material, the inorganic material may include an alkali metal compound such as LiF, an alkaline earth metal compound such as MgF, SiON, SiNX, SiOy, etc.

[0408] For example, when the protective layer CPL includes an organic material, the organic material may include α-NPD, NPB, TPD, m-MTDATA, Alq3, CuPc, TPD15 (N4,N4,N4',N4'-tetra(biphenyl-4-yl)biphenyl-4,4'-diamine), TCTA (4,4',4"-Tris(carbazolsol-9-yl)triphenylamine), etc., or may include an epoxy resin, or an acrylate such as methacrylate.

[0409] Although the present invention has been described above with reference to preferred embodiments, it will be understood that a person skilled in the art or having ordinary knowledge in the art can make various modifications and changes to the present invention without departing from the spirit and scope of the present invention as set forth in the claims below.

[0410] Therefore, the technical scope of the present invention should not be limited to the contents described in the detailed description of the specification, but should be defined by the claims. [Explanation of symbols]

[0411] DD electronic device DP display panel DA display area NDA Hidden Area PXA-R, PXA-G, PXA-B Light-emitting area NPXA non-luminous area PE-R First contact electrode ES-R 1st power line GR Groove OVH Dam Pattern ENA sealing area

Claims

1. a base substrate including a display area and a non-display area, each of the display area and the non-display area including a light-emitting area and a non-light-emitting area disposed between the light-emitting areas; a power supply line disposed on the base substrate and overlapping the display area; pixel units each including a pixel including a light-emitting element including a first electrode, a second electrode disposed on the first electrode, and a common layer disposed between the first electrode and the second electrode; contact electrodes each surrounding the light-emitting element and disposed in the non-light-emitting region; an interlayer insulating layer disposed between the power supply line and the contact electrode; an interlayer insulating layer disposed on the interlayer insulating layer, the interlayer insulating layer overlapping the non-light-emitting region and each including a groove exposing at least a portion of the contact electrode; the second electrode is connected to the contact electrode in a region overlapping the groove; The contact electrode is connected to the power line through a contact hole that penetrates the interlayer insulating layer.

2. The light-emitting element may further include a first sealing layer and a second sealing layer that cover the light-emitting element and contact each other in the light-emitting region and the non-light-emitting region, The electronic device of claim 1 , wherein the first encapsulation layer and the second encapsulation layer include an inorganic material.

3. An opening is defined to expose at least a portion of each of the first electrodes, and the pixel defining layer further includes a pixel defining layer including an inorganic material, an insulating layer between the pixel defining layers, a via insulating layer including an organic material, and a protection layer disposed on the second electrodes; The electronic device of claim 2 , wherein the via insulating layer, the pixel defining layer, the common layer, the second electrode, and the protective layer are disconnected within the groove.

4. a sealing region overlapping the non-light-emitting region in the pixel defining layer and disposed between adjacent light-emitting elements is exposed by the common layer, the second electrode, the protective layer, and the first sealing layer; The electronic device of claim 3 , wherein the pixel defining layer contacts the second sealing layer in the sealing region.

5. The electronic device according to claim 4 , wherein the interlayer insulating layer is not disposed below the sealing region, and the insulating layer is disposed between the interlayer insulating layer.

6. a side surface of the contact electrode adjacent to the light emitting region is exposed from the insulating layer therebetween by the groove; The electronic device of claim 3 , wherein the second electrode contacts the exposed side surface.

7. The side surface has a predetermined curvature, The electronic device according to claim 6 , wherein the contact electrode comprises molybdenum.

8. 2. The electronic device of claim 1, further comprising: a first pattern layer and a second pattern layer overlapping the contact electrode and sequentially stacked on the interlayer insulating layer, the first pattern layer and the second pattern layer comprising different inorganic materials.

9. The electronic device of claim 8 , wherein a portion of the first pattern layer is exposed from the second pattern layer.

10. The electronic device of claim 9 , wherein the common layer contacts the portion of the first pattern layer and the second pattern layer laterally within the groove.

11. a portion of the insulating layer adjacent to the groove and disposed in the non-light-emitting region protrudes from the contact electrode in a direction toward the light-emitting region; The electronic device of claim 6 , wherein the portion is protruded upward to define a trench that defines a predetermined internal space.

12. The non-light-emitting region further includes a dam pattern that overlaps the non-light-emitting region and surrounds at least a portion of the light-emitting region, The electronic device of claim 3 , wherein the dam pattern includes a first pattern disposed on the pixel definition layer and a second pattern disposed on the first pattern.

13. the first pattern and the second pattern include different inorganic materials; The thickness of the first pattern is greater than the thickness of the second pattern; The electronic device of claim 12 , wherein the width of the first pattern is smaller than the width of the second pattern.

14. the common layer, the second electrode, and the protective layer disposed in the non-light-emitting region are disconnected by the dam pattern; The electronic device according to claim 13 , wherein the dam pattern is covered by the first encapsulation layer and the second encapsulation layer.

15. a portion of an upper surface of the contact electrode is exposed from the insulating layer by the groove; The electronic device of claim 3 , wherein the second electrode contacts the exposed top surface.

16. the contact electrode includes first to third conductive layers sequentially stacked on the interlayer insulating layer, 16. The electronic device of claim 15, wherein the first conductive layer and the third conductive layer comprise titanium, and the second conductive layer comprises aluminum.

17. The electronic device according to claim 16 , wherein a side surface of the insulating layer defining the groove that overlaps the non-light-emitting region has a predetermined curvature.

18. a pixel defining layer including an inorganic material and disposed on the insulating layer between the first electrodes, the pixel defining layer defining an opening that exposes at least a portion of each of the first electrodes; and an auxiliary electrode disposed on the insulating layer between the first electrodes and disposed in the non-light-emitting region, the auxiliary electrode being covered by the pixel defining layer; The electronic device of claim 2 , wherein the auxiliary electrode is connected to the contact electrode through a contact hole defined in the pixel defining layer.

19. a portion of an upper surface of the contact electrode is exposed from the insulating layer by the groove; 20. The electronic device of claim 18, wherein a portion of the common layer is disposed on the top surface exposed within the groove.

20. the second electrode is disposed on a portion of the common layer within the groove, and a side of the auxiliary electrode adjacent to the light emitting region is in contact with the second electrode; The electronic device of claim 18 , wherein the auxiliary electrode includes the same material as the first electrode.

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