LDO regulator

Abstract

To provide an LDO regulator capable of protecting a low breakdown voltage transistor by suppressing an increase in output voltage due to an off-leak current.SOLUTION: The LDO regulator includes a differential amplifier that differentially amplifies a reference voltage and a detection voltage related to an output voltage and outputs a differential amplification signal, an output transistor that has a gate to which the differential amplification signal is supplied, is controlled to be conductive, has one end to which an input voltage is supplied, and outputs the output voltage from an output terminal to a load circuit, and a clamp transistor that is connected in parallel with the load circuit, is in a conductive state when the output transistor is in a non-conductive state, and is conductive when the output voltage exceeds a predetermined value.SELECTED DRAWING: Figure 1

Description

[Technical Field]

[0001] The present invention relates to an LDO (Low Drop Out) regulator that slightly drops a power supply voltage before supplying it to a load circuit. [Background technology]

[0002] LDO regulators are used in semiconductor integrated circuits to slightly drop the power supply voltage before supplying it to the load circuit. For example, if the load circuit requires a 3.3V power supply, it is difficult to create a 3.3V power supply from a 5V power supply using a standard step-down regulator, so an LDO regulator that can lower the input / output voltage difference is required. In semiconductor integrated circuits using such LDO regulators, there is also a known technology that further reduces power consumption by stopping the LDO regulator when the circuit is not operating. [Prior art documents] [Patent documents]

[0003] [Patent Document 1] Special Publication No. 2018-528547 Summary of the Invention [Problem to be solved by the invention]

[0004] However, if the LDO regulator is stopped for a long time, the voltage rises due to the difference in the off-leak current between the LDO regulator and the load circuit, causing an excessive voltage to be applied to the low-voltage transistors in the load circuit, which may lead to damage to the low-voltage transistors in the load circuit.

[0005] The present invention provides an LDO regulator that can protect low-voltage transistors by suppressing an increase in output voltage due to off-leakage current. [Means for solving the problem]

[0006] An LDO regulator according to the present invention includes a differential amplifier that differentially amplifies a reference voltage and a detection voltage related to an output voltage and outputs a differentially amplified signal; an output transistor that is supplied with the differentially amplified signal at its gate to be conduction-controlled, receives an input voltage at one end, and outputs the output voltage to a load circuit from an output terminal; and a clamp transistor that is connected in parallel with the load circuit, is made conductive when the output transistor is non-conductive, and becomes conductive when the output voltage exceeds a predetermined value. [Effects of the Invention]

[0007] According to the present invention, it is possible to provide an LDO regulator that can protect a low-voltage transistor by suppressing an increase in output voltage due to an off-leak current. [Brief explanation of the drawings]

[0008] [Figure 1] 1 is an overall configuration diagram illustrating a semiconductor device 1 according to a first embodiment. [Figure 2] 4 is a truth table for explaining the operation of the semiconductor device 1 according to the first embodiment. [Figure 3] Various currents that flow during the operation of the semiconductor device 1 of the first embodiment will be described. [Figure 4] 4 is a graph illustrating the operation of the semiconductor device 1 according to the first embodiment. [Figure 5] FIG. 4 is a circuit diagram illustrating a configuration of a semiconductor device 1 according to a second embodiment. [Figure 6] 10 is a graph illustrating the operation of the semiconductor device 1 according to the second embodiment. [Figure 7] FIG. 1 is an overall configuration diagram illustrating a semiconductor device of a comparative example. DETAILED DESCRIPTION OF THE INVENTION

[0009] Hereinafter, the present embodiment will be described with reference to the accompanying drawings. In the accompanying drawings, functionally identical elements may be designated by the same numerals. Note that the accompanying drawings show embodiments and implementation examples according to the principles of the present disclosure, but these are for understanding the present disclosure and are not to be used to interpret the present disclosure in a limiting manner. The descriptions in this specification are merely typical examples and are not intended to limit the scope or application of the present disclosure in any way.

[0010] Although the present embodiment has been described in sufficient detail to enable those skilled in the art to implement the present disclosure, it should be understood that other implementations and forms are possible, and that changes in configuration and structure and substitutions of various elements are possible without departing from the scope and spirit of the technical ideas of the present disclosure. Therefore, the following description should not be interpreted as being limited thereto.

[0011] [First embodiment] A semiconductor device 1 according to a first embodiment will be described with reference to Figure 1. The semiconductor device 1 includes an LDO regulator 10, a load circuit 20, and a capacitor 30. The LDO regulator 10 is configured to step down a power supply voltage VDD (input voltage) to generate an output voltage Vo and supply the output voltage Vo to the load circuit 20. The load circuit 20 is a group of circuits that operate using the output voltage Vo generated by the LDO regulator 10. The capacitor 30 is connected between the output terminal and the ground potential terminal of the LDO regulator 10 to stabilize the operation of the LDO regulator 10.

[0012] The LDO regulator 10 includes, for example, an OP amplifier 11 as a differential amplifier, a first transistor M1 (output transistor), a second transistor M2 (disable transistor), a third transistor M3 (clamp transistor), a switch circuit M4, inverters 12 and 13, and a voltage dividing resistor 14.

[0013] The OP amplifier 11 differentially amplifies a reference voltage VREF supplied from a reference voltage generating circuit (e.g., a bandgap reference circuit) not shown and a voltage VDET at a connection node N1 of the voltage dividing resistor 14, and outputs an output signal (differentially amplified signal) to an output terminal. The voltage VDET is an example of a detection voltage having a value related to the voltage Vo at the output terminal of the LDO regulator 10. The output terminal of the OP amplifier 11 is connected to the gate of the first transistor M1.

[0014] The first transistor M1 is a P-channel MOS transistor whose source is connected to a power supply voltage terminal (power supply voltage VDD) and whose drain is connected to the output terminal of the LDO regulator 10, and is the output transistor of the LDO regulator 10. That is, the first transistor M1 shares the power supply voltage VDD at its source and supplies an output voltage Vo, which is a dropped version of the power supply voltage VDD, to the load circuit 20 from its drain.

[0015] The second transistor M2 is a P-channel MOS transistor (disable transistor) whose source is connected to the power supply voltage terminal (power supply voltage VDD) and whose drain is connected to the output terminal of the OP amplifier 11 (the gate of the first transistor M1). An enable signal ENA for switching between enabling (activating) and disabling (deactivating) the LDO regulator 10 is supplied to its gate, and the second transistor M2 disables (sets to a non-operating state) the LDO regulator 10 in accordance with the enable signal ENA. Instead of the second transistor M2, another circuit for disabling the operation of the first transistor M1 may be installed.

[0016] When the enable signal ENA becomes "H," the operational amplifier 11 becomes active and the second transistor M2 becomes non-conductive (OFF). On the other hand, when the enable signal ENA becomes "L," the operational amplifier 11 becomes inactive, the second transistor M2 becomes conductive (ON), and the gate of the first transistor M1 is fixed at "H," so that the first transistor M1 also becomes non-conductive (OFF). By appropriately setting the enable signal ENA to "L," the operation of the LDO regulator 10 is also stopped, thereby reducing power consumption.

[0017] The third transistor M3 (clamp transistor) is a P-channel MOS transistor connected in parallel with the load circuit 20 between the output terminal of the LDO regulator 10 and the ground potential terminal (ground potential VSS). An inverted signal of a clamp enable signal CLAMP_ENA is applied to the gate of the third transistor M3 via an inverter 13. This clamp enable signal CLAMP_ENA is set to "H" when the enable signal ENA is set to "L" and the LDO regulator 10 is in an inactive state. When the LDO regulator 10 is enabled (active), the clamp enable signal CLAMP_ENA is set to "L," thereby fixing the third transistor M3 to a non-conductive state. On the other hand, when the LDO regulator 10 is disabled (inactive), the clamp enable signal CLAMP_ENA is set to "H." This allows the third transistor M3 to conduct when the output voltage Vo exceeds a predetermined value, thereby suppressing an increase in the output voltage Vo.

[0018] The switch circuit M4 is a CMOS switch connected in series with a voltage dividing resistor 14 between the output terminal of the LDO regulator 10 and the ground potential terminal. An enable signal ENA and its inverted signal are supplied to its gate via an inverter 12. When the enable signal ENA goes "H", the switch circuit M4 is in a conductive state, and when the enable signal ENA goes "L", the switch circuit M4 is in a non-conductive state.

[0019] Next, the operation of the semiconductor device 1 of the first embodiment will be described. This semiconductor device 1 can realize three modes ((1) LDO enable mode, (2) LDO disable mode, and (3) external voltage application mode) by controlling the transistors M2 to M4 in the LDO regulator 10 as follows. Fig. 2 shows the control (on / off) of the transistors M2 and M3 (switches) and the switch circuit M4 when each mode is executed. Fig. 3 shows various currents flowing through the LDO regulator 10 and the load circuit 20 during operation.

[0020] (1) LDO enable mode The LDO enable mode is the normal operating mode in which the LDO regulator 10 is in an operating state, and the power supply voltage VDD is stepped down by the LDO regulator 10 to generate an output voltage Vo, which is supplied to the load circuit 20. In the LDO enable mode, the enable signal ENA is set to "H" and the clamp enable signal CLAMP_ENA is set to "L," which turns transistor M2 OFF, switch circuit M4 ON, and transistor M3 OFF. This causes the LDO regulator 10 to enter an operating state, generating a voltage Vo of a desired value from the output terminal of the LDO regulator 10 and supplying the voltage Vo to the load circuit.

[0021] (2) LDO disable mode The LDO disable mode is a mode in which the LDO regulator 10 is set to an inactive state to reduce power consumption. In the LDO disable mode, the enable signal ENA is set to "L" and the clamp enable signal CLAMP_ENA is set to "H," which turns transistor M2 ON, switch circuit M4 OFF, and transistor M3 ON. The LDO regulator 10 is set to an inactive state and transistor M1 is also set to OFF, but a small off-leakage current Ioff_ido flows (see FIG. 3). However, if this off-leakage current Ioff_ido is smaller than the leakage current Ioff_load on the load circuit 20 side, the leakage current is absorbed on the load circuit 20 side, and the output voltage Vo does not increase.

[0022] However, if the off-leakage current Ioff_ido of the transistor M1 exceeds the leakage current Ioff_load on the load circuit 20 side, the difference in leakage current flows into the capacitor 30 connected to the output terminal of the LDO regulator 10, charging the capacitor 30 and causing the output voltage Vo to rise over time. Such an increase in the output voltage Vo may lead to damage to the low-voltage transistors in the load circuit 20.

[0023] To address this issue, the first embodiment includes transistor M3, which is turned on as appropriate in the LDO disable mode to allow the difference in leakage current to flow. Therefore, even if the off-leakage current Ioff_ido exceeds the leakage current Ioff_load, the difference in leakage current is prevented from flowing into capacitor 30, thereby suppressing an increase in output voltage Vo.

[0024] Specifically, in the LDO disable mode, the enable signal ENA is set to "L" and the clamp enable signal CLAMP_ENA is set to "H," which turns on the transistor M2, turns off the switch circuit M4, and puts the transistor M3 into standby (it switches on as appropriate when the voltage at the output terminal rises). The transistor M3 is a P-channel MOS transistor, and turns on when its gate-source voltage exceeds the threshold voltage, allowing excess current to flow on the load circuit 20 side.

[0025] When the current flowing to the transistor M3 side is Ioff_sw and the circuit stop time during which the LDO regulator 10 is stopped is T, the output voltage Vo is expressed by the following equation.

[0026] [Number 1] Vo=[{Ioff_ido-(Ioff_load+Ioff_sw)}×T] / C

[0027] According to this [Equation 1], until the output voltage Vo becomes equal to the threshold voltage Vth3 of transistor M3, Ioff_sw = 0, so the output voltage Vo rises due to the difference current between Ioff_ldo and Ioff_load. However, when the output voltage Vo exceeds the threshold voltage of transistor M3, the current Ioff_sw flows, and the output voltage Vo can be clamped.

[0028] (3) External voltage application mode The external voltage application mode is a mode in which an external voltage from an external power supply (not shown) is applied to the load circuit 20, rather than from the LDO regulator 10. In the external voltage application mode, the enable signal ENA and the clamp enable signal CLAMP_ENA are both set to "L", The second transistor M2 is turned ON, the switch circuit M4 is turned OFF, and the third clamp transistor M3 is also turned OFF. The output terminal of the LDO regulator 10 is in a high impedance state (Hiz). By applying an external voltage from outside without using the LDO regulator 10, the power supply can be adjusted arbitrarily during testing to check the characteristics of the load circuit connected to the LDO regulator 10.

[0029] Next, the effects of the semiconductor device 1 of the first embodiment will be described. By providing the transistor M3 in the LDO regulator 10 as in the first embodiment, even if the off-leakage current Ioff_ido of the transistor M1 exceeds the leakage current Ioff_load on the load circuit 20 side when the LDO regulator 10 is disabled, the difference in leakage current flows through the transistor M3, and the leakage current flowing through the capacitor 30 is limited. This limits the increase in the output voltage Vo and prevents damage to the low-voltage transistor connected to the LDO regulator 10.

[0030] FIG. 7 shows a semiconductor device according to a comparative example of the first embodiment. Unlike the first embodiment, this semiconductor device does not include transistor M3. Without transistor M3, as in this comparative example, the LDO regulator 10 repeatedly switches between enabled and disabled states, as shown by curve C1 in FIG. 4, which can cause the output voltage Vo to continue to rise and exceed the target voltage Vtgt. In contrast, in the semiconductor device 1 according to the first embodiment, when the LDO regulator 10 is disabled, transistor M3 conducts appropriately, reducing the potential at the output terminal of the LDO regulator 10 to the threshold voltage Vth3 (curve C2 in FIG. 4), thereby suppressing the rise in the potential at the output terminal.

[0031] One method for suppressing the rise in the potential at the output terminal of the LDO regulator 10 is to use a comparator to compare the potential at the output terminal with a reference potential and discharge the charge at the output terminal as appropriate, but providing such a comparator leads to an increase in the size of the device.In this regard, the first embodiment described above makes it possible to monitor the voltage at the output terminal using a single PMOS transistor, eliminating the need for a comparator and enabling a more compact device.

[0032] [Second embodiment]

[0033] Next, a semiconductor device 1 according to a second embodiment will be described with reference to FIG. 5. The overall configuration and basic operation of this semiconductor device 1 are the same as those of the first embodiment (FIGS. 1 and 2), so a duplicated description will be omitted. As shown in FIG. 5, the second embodiment differs from the first embodiment in that a back-gate adjustment unit 15 that adjusts the back-gate voltage of transistor M3 is further added. The threshold voltage of transistor M3 (a PMOS transistor) can be changed by adjusting the back-gate voltage of transistor M3. Changing the threshold voltage of transistor M3 makes it possible to change the clamp voltage of the output terminal of the LDO regulator.

[0034] For example, if the back gate voltage of transistor M3 is set higher than the source terminal, the back bias effect increases the threshold voltage Vth3 of the PMOS transistor of transistor M3, thereby increasing the clamp voltage level of the voltage Vo at the output terminal of the LDO regulator 10 (see curves C3 to C5 in Figure 6). Conversely, if the back gate voltage is brought closer to the source voltage, the threshold voltage of the PMOS transistor of transistor M3 decreases, thereby lowering the clamp voltage level at the output terminal (see Figure 6). Therefore, by adjusting the clamp voltage level, it is possible to adjust the recovery time from disable to enable. The recovery time refers to the time it takes to achieve the desired voltage. Shortening the recovery time makes it possible to suppress the large current (rush current) that occurs during the recovery time. Suppressing the rush current also helps to prevent a drop in the power supply voltage of the LDO regulator 10.

[0035] [others] The present invention is not limited to the above-described embodiments and includes various modifications. For example, the above-described embodiments have been described in detail to clearly explain the present invention, and the present invention is not necessarily limited to those including all of the described configurations. Furthermore, it is possible to replace part of the configuration of one embodiment with the configuration of another embodiment, or to add the configuration of another embodiment to the configuration of one embodiment. Furthermore, it is possible to add, delete, or replace part of the configuration of each embodiment with other configurations. [Explanation of symbols]

[0036] 1...Semiconductor device 11...OP amp 12, 13...Inverter 14...Voltage dividing resistor M1 to M3: Transistors 14...Switch circuit 15...Back gate voltage adjustment section 10...LDO regulator 20...Load circuit 30...Capacitor

Claims

1. a differential amplifier that differentially amplifies a reference voltage and a detection voltage related to the output voltage and outputs a differentially amplified signal; an output transistor whose gate is supplied with the differentially amplified signal to control conduction, whose one end is supplied with an input voltage, and whose output terminal outputs the output voltage to a load circuit; a clamp transistor connected in parallel with the load circuit, which is rendered conductive when the output transistor is in a non-conductive state, and which is rendered conductive when the output voltage exceeds a predetermined value; An LDO regulator comprising:

2. 2. The LDO regulator according to claim 1, further comprising: a disable transistor having one end supplied with the input voltage and the other end connected to the gate of the output transistor, the disable transistor being non-conductive when an enable signal has a first logic level and being conductive when the enable signal has a second logic level.

3. A voltage dividing resistor, 3. The LDO regulator according to claim 2, further comprising: a switch circuit connected between the voltage dividing resistor and the output terminal, the switch circuit being made conductive when the enable signal is at the first logic level and being made non-conductive when the enable signal is at the second logic level.

4. 4. The LDO regulator according to claim 3, wherein an output voltage of the voltage dividing resistor is used as the detection voltage.

5. the clamp transistor is switched between a conductive state and a non-conductive state in response to a clamp enable signal being supplied to a gate thereof; 5. The LDO regulator according to claim 2, wherein the clamp enable signal is set to a second logic when the enable signal is set to a first logic to put the LDO regulator into an operating state, and is set to a first logic when the enable signal is set to a second logic to put the LDO regulator into a non-operating state.

6. 6. The LDO regulator according to claim 5, wherein when a voltage is supplied to the load circuit from an external power supply separate from the LDO regulator, the enable signal and the clamp enable signal are both set to the second logic level.

7. The LDO regulator according to claim 1 , further comprising a back-gate voltage adjusting unit that adjusts a back-gate voltage of the clamp transistor.

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