Semiconductor device

Abstract

To provide a semiconductor device having a resistance connection structure with high characteristic fluctuation resistance.SOLUTION: The semiconductor element comprises a substrate 1, an insulating layer 2 formed on the substrate 1 and having a groove side 2G, a tungsten layer 3 buried in the groove side 2G, a resistance layer R formed on a first region 31 of the tungsten layer 3 and containing a chromium compound or a metallic nitride, and a metallic layer EC formed on a second region 32 of the tungsten layer 3.SELECTED DRAWING: Figure 4

Description

[Technical Field]

[0001] The present disclosure relates to semiconductor devices. [Background technology]

[0002] Patent Document 1 discloses a semiconductor device including a plurality of resistance elements. [Prior art documents] [Patent documents]

[0003] [Patent Document 1] International Publication No. 2023 / 085026

[0004] [overview] A semiconductor device having a resistor connection structure with high resistance to characteristic fluctuations is provided.

[0005] The semiconductor device disclosed herein includes a semiconductor substrate, an insulating layer formed on the semiconductor substrate and having a groove on its surface, a tungsten electrode embedded in the groove, a resistive layer including a chromium compound or a metal nitride formed on a first region of the tungsten electrode, and a metal electrode formed on a second region of the tungsten electrode. [Brief explanation of the drawings]

[0006] [Figure 1] FIG. 1 is a diagram showing the planar configuration of a high voltage detection device. [Figure 2] FIG. 2 is a circuit diagram of the resistor section. [Figure 3] FIG. 3 is a plan view of a partial region of the resistor portion. [Figure 4] FIG. 4 is a diagram showing a vertical cross-sectional configuration of the region shown in FIG. 3 taken along line AA. [Figure 5] FIG. 5 is a diagram showing a vertical cross-sectional configuration of the region shown in FIG. 3 taken along line BB. [Figure 6] FIG. 6 is a diagram showing a vertical cross-sectional configuration of the area near the tungsten electrode.

[0007] [Detailed explanation] Various exemplary embodiments will be described in detail below with reference to the drawings. Note that the same or equivalent parts in the drawings will be denoted by the same reference numerals, and redundant explanations will be omitted.

[0008] FIG. 1 is a diagram showing the planar configuration of a high voltage detection device.

[0009] The high-voltage detection device 100 is a semiconductor device including a resistor device 10 and an amplifier device 20. The resistor device 10 and the amplifier device 20 may be formed on the same semiconductor chip, or may be formed on separate semiconductor chips. When the resistor device 10 is formed on a resistor chip and the amplifier device 20 is formed on an amplifier chip, they can be housed in the same package. The package case may have a recess, and one or more semiconductor chips can be housed in the recess. The recess may be filled with an insulating material such as gas or resin, if necessary, and the space within the recess is made into a sealed space. In either structure, the potential output of the resistor device 10 is input to the amplifier device 20.

[0010] When a structure in which the resistor device 10 and the amplifier device 20 are formed on the same semiconductor chip is adopted, the overall size of the package can be reduced, resulting in reduced area and cost. When the semiconductor chip is housed in a case, the semiconductor chip can be fixed on a die pad of a lead frame. Multiple leads extend from the die pad.

[0011] The resistance device 10 has a resistor between the first electrode E1 and the second electrode E2. When detecting the battery voltage, the positive terminal of the battery is electrically connected to the first electrode E1. The negative terminal of the battery is electrically connected to the second electrode E2. The amplifier 20 functions as a voltage detection device. That is, by extracting the potential at two or more appropriate positions in the resistor in the resistance device 10 and inputting it to the amplifier 20, the amplifier 20 can amplify the detected voltage and output it to the outside. In other words, the semiconductor device includes resistors (RP, RPS, RND, RN) formed by electrically connecting multiple resistance layers, and multiple terminals (EP, EG, EN) for potential detection connected to multiple nodes in the resistor.

[0012] The resistance device 10 includes a first high resistance section RP (first resistor), a first low resistance section RPS, a second low resistance section RNS, and a second high resistance section RN (second resistor). The first high resistance section RP, the first low resistance section RPS, the second low resistance section RNS, and the second high resistance section RN are connected in series in this order between the first electrode E1 and the second electrode E2. The first high resistance section RP and the second high resistance section RN have a function for reducing high voltages and each have a high resistance value. The first low resistance section RPS and the second low resistance section RNS have a function for detecting voltages and each have a relatively low resistance value compared to the high resistance sections.

[0013] An exemplary resistance value of one high resistance section is 500 MΩ, but it can also be 1 MΩ or more and 1000 MΩ or less. The resistance value of the high resistance section can also be 100 MΩ or more and 800 MΩ or less. The resistance value of the high resistance section can also be 300 MΩ or more and 600 MΩ or less. This resistance value should be a resistance value that can withstand high voltages and allows voltage detection.

[0014] The resistance value of one low resistance section (RPS or RNS) is equal to or less than K% of the resistance value of the high resistance section. Exemplary values ​​of K% are 5%, 3%, 1%, 0.5%, 0.3%, 0.1%, 0.05%, or 0.01%, and the resistance value of the low resistance section can be, for example, 0.01 MΩ to 10 MΩ.

[0015] A first output electrode EP (electrode pad or terminal) is electrically connected to the connection point between the first high resistance section RP and the first low resistance section RPS. A second output electrode EN (electrode pad or terminal) is electrically connected to the connection point between the second high resistance section RN and the second low resistance section RNS. A reference electrode EG (electrode pad or terminal) is electrically connected between the first low resistance section RPS and the second low resistance section RNS.

[0016] Since the resistance device 10 is a voltage divider circuit, it is possible to obtain a voltage corresponding to the resistance value between two selected points within the resistance device 10. The first output electrode EP is electrically connected to the first input terminal INP of the amplifier device 20. The second output electrode EN is electrically connected to the second input terminal INN of the amplifier device 20. The reference electrode EG is electrically connected to the reference terminal VC of the amplifier device 20. The potential of the reference terminal VC can be set to, for example, ground potential. The amplifier device 20 can output an output voltage Vout. The output voltage Vout can be the sum of a first potential difference between the first input terminal INP and the reference terminal VC and a second potential difference between the second input terminal INN and the reference terminal VC. The amplifier device 20 can include a source follower (amplifier) ​​that amplifies the voltage input from the input terminals and a differential amplifier circuit that obtains the sum of the input voltages. The amplifier device 20 includes an input terminal for a power supply voltage Vcc for operating the internal circuit and an input terminal for setting the ground potential GND.

[0017] The resistance device 10 may include a dummy resistor. The dummy resistor is a resistor through which no current flows, and is provided to maintain electrical equivalence in the resistance device 10, maintain electrical stability, or reduce error factors that may occur during resistor manufacturing in the manufacturing process. The circuit configuration of the high voltage detection device is not limited to these, and the shape and arrangement of the resistor may be changed as long as the basic voltage detection function is achieved.

[0018] Furthermore, the reference electrode EG in the resistance device 10 can be divided into two. The terminal of the first low resistance section RPS opposite to the first high resistance section RP is set as the first reference electrode, and the terminal of the second low resistance section RNS opposite to the second high resistance section RN is set as the second reference electrode, and the potentials of the first reference electrode and the second reference electrode are respectively input to the amplifier device 20. The potential of the reference electrode EG is the potential of the connection point between the first reference electrode and the second reference electrode, so this potential can be obtained within the amplifier device 20.

[0019] FIG. 2 is a circuit diagram of the resistor section.

[0020] A first high resistance section RP, a first low resistance section RPS, a second low resistance section RNS, and a second high resistance section RN are connected in series between the first electrode E1 and the second electrode E2. Each resistance section includes a resistance layer R (resistor, resistance element). In this example, a plurality (two) of resistance layers R are arranged per row and connected in series. A first output electrode EP is electrically connected to the node between the first high resistance section RP and the first low resistance section RPS. A reference electrode EG is electrically connected to the node between the first low resistance section RPS and the second low resistance section RNS. A second output electrode EN is electrically connected between the second low resistance section RNS and the second high resistance section RN.

[0021] FIG. 3 is a plan view of a partial region of the resistor portion.

[0022] Each resistive layer R extends in the X-axis direction. The width direction of the resistive layer R is defined as the Y-axis direction. The thickness direction of the resistive layer R is defined as the Z-axis direction. The X-axis, Y-axis, and Z-axis form a three-dimensional Cartesian coordinate system. Two resistive layers R are arranged in one row. One end region of one resistive layer R in the X-axis direction and the other end region are defined as first regions 31. The first region 31 at the end of the first resistive layer (R) in one row and the first region 31 at the end of the adjacent second resistive layer (R) are electrically and physically connected by one or more tungsten electrodes 3 extending in the X-axis direction. The first region 31 at the end of the resistive layer R in one row and the first region 31 at the end of the resistive layer R in the adjacent row are electrically and physically connected by one or more tungsten electrodes 3 extending in the Y-axis direction.

[0023] When the resistive layer R is located at the end in the Y-axis direction, the end (first region 31) of this resistive layer R and the second region 32 directly below the metal electrode EC are connected by one or more tungsten electrodes 3 extending in the X-axis direction. In other words, the resistive layer R is formed on the first region 31 of the tungsten electrode 3, and the metal electrode EC is formed on the second region 32 of the tungsten electrode 3.

[0024] The resistive layer R is made of a material with high precision and high resistivity. The resistive layer R is made of a chromium compound or a metal nitride. The tungsten electrode 3 is an electrode whose main component is tungsten metal, and is embedded in the groove in which the tungsten electrode 3 is disposed.

[0025] FIG. 4 is a diagram showing a vertical cross-sectional configuration of the region shown in FIG. 3 taken along line AA.

[0026] The semiconductor device includes an insulating layer 2 provided on a semiconductor substrate 1, and a plurality of resistive layers R (resistors, resistive elements) provided on the insulating layer 2.

[0027] The insulating layer 2 includes a plurality of laminated dielectric layers (first dielectric layer 2A, second dielectric layer 2B). At least one of the plurality of dielectric layers (first dielectric layer 2A) is made of a material containing silicon oxide. At least one of the plurality of dielectric layers (second dielectric layer 2B) is made of a material containing silicon nitride. In this example, the first dielectric layer 2A and the second dielectric layer 2B are alternately laminated. The silicon oxide in this example is SiO2, but the elemental composition ratio may be changed or other elements may be included as necessary. The silicon nitride in this example is Si3N4, but the elemental composition ratio may be changed or other elements may be included as necessary. The thickness of the insulating layer 2 may be, for example, 5 μm or more and 50 μm or less.

[0028] A protective film 4 is provided on the resistive layer R formed on the insulating layer 2.

[0029] The protective film 4 includes a first protective film 4A, a second protective film 4B, a third protective film 4C, and a fourth protective film 4D, which are laminated in this order on the insulating layer 2.

[0030] The first protective film 4A may be made of an inorganic insulating material such as silicon oxide or silicon nitride, for example, SiO 2. The first protective film 4A covers the resistive layer R.

[0031] A second protective film 4B is formed on the first protective film 4A. The material of the second protective film 4B is an inorganic insulator such as silicon oxide or silicon nitride, and may be the same as or different from the material of the first protective film 4A, but is, for example, made of SiO2.

[0032] The material of the third protective film 4C is made of an inorganic insulating material such as silicon oxide or silicon nitride, and may be the same as or different from the material of the first protective film 4A, but is made of silicon nitride, for example.

[0033] The fourth protective film 4D is made of a resin (insulating material) such as polyimide. The thickness of the fourth protective film 4D may be greater than the thickness of the third protective film 4C. The second to fourth protective films 4B to 4D are formed on the first protective film 4A and cover the metal electrodes EC.

[0034] A tungsten electrode 3 is disposed directly below one end region (31) of the resistive layer R in the X-axis direction. The resistive layer R and the tungsten electrode 3 are electrically connected. Note that, because a physical connection of conductive elements involves an electrical connection, in the explanation, the term "connected" may be used simply when the state of connection is clear.

[0035] The lower end of the metal electrode EC is in contact with the other end region (32) in the X-axis direction of the tungsten electrode 3, and the metal electrode EC is electrically connected to the tungsten electrode 3. The material of the metal electrode EC illustratively includes aluminum (Al), but it is also possible to use a conductive material with low resistivity such as copper (Cu).

[0036] The tungsten electrode 3 is formed in one or more grooves 2G formed on the surface of the insulating layer 2 (the surface of the upper first dielectric layer 2A). If an aluminum buried electrode is disposed directly below the resistive layer R, aluminum has a high tendency to diffuse due to an electric field, etc., and this can cause characteristic fluctuations. On the other hand, in the resistive connection structure of this embodiment, a tungsten electrode 3 with low diffusibility is disposed directly below the resistive layer R, which can increase resistance to characteristic fluctuations. Furthermore, because the resistive connection structure does not include a columnar via electrode, the dimension in the thickness direction can be reduced.

[0037] FIG. 5 is a diagram showing a vertical cross-sectional configuration of the region shown in FIG. 3 taken along line BB.

[0038] The second protective film 4B to the fourth protective film 4D are formed on the first protective film 4A and cover the metal electrodes EC. When connecting a contact conductor (PAD) such as a wiring or an electrode pad to the metal electrodes EC, the second protective film 4B to the fourth protective film 4D in the corresponding region are removed.

[0039] The number of grooves 2G formed on the surface of the insulating layer 2 is four (plural). The number of grooves 2G provided to connect the resistive layer R and the metal electrode EC is multiple, and multiple tungsten electrodes 3 are embedded in each of the multiple grooves 2G. Regarding the width of each tungsten electrode 3, if the depth is approximately half the width, the larger the width, the higher the material cost, and the narrower the width, the lower the material cost. A small number of tungsten electrodes 3 increases resistance and reduces precision and reliability. The width YW of the tungsten electrode 3 in the Y-axis direction, whose longitudinal direction is the X-axis direction, may satisfy the following relationship: 0.20 μm≦YW≦0.60 μm. By providing multiple tungsten electrodes 3 with relatively narrow widths, the semiconductor device can increase its precision and reduce its resistance. The number N of tungsten electrodes 3 forming a single inter-region connection can be, for example, 2≦N≦20.

[0040] The grooves 2G can be formed by patterning a resist on the surface of the insulating layer 2 and then etching the surface of the insulating layer 2 using the resist. This etching can be performed using wet etching or dry etching. When etching SiO2, an acidic etchant such as hydrofluoric acid can be used. For dry etching, anisotropic etching such as reactive ion etching (RIE) can be used. Examples of etching gases for dry etching include fluorine-containing gases such as CF4 and CHF3. Fluorocarbon gases can efficiently etch SiO2. If necessary, an etching stop layer such as a silicon nitride film may be disposed on the bottom of the grooves 2G. Plasma etching can also be used as an alternative etching method. After depositing tungsten (W) in the grooves 2G, a tungsten electrode 3 can be formed in the grooves 2G by chemical mechanical polishing (CMP) of the substrate surface. Tungsten deposition can be performed using sputtering or plating.

[0041] FIG. 6 is a diagram showing a vertical cross-sectional configuration of the area near the tungsten electrode 3.

[0042] The longitudinal dimension XL of the tungsten electrode 3 (X-axis direction) can be, for example, 2 μm≦XL≦20 μm. If the dimension XL is too short, the contact area with the resistive layer will be small, and if it is too long, the device dimensions will be large. The range of the dimension XL can be changed. The thickness Z3 of the tungsten electrode 3 can be, for example, 0.4 μm≦Z3≦1 μm. The thickness Z3 of the tungsten electrode 3 can be larger than the thickness of the resistive layer R. The above range of thickness Z3 is within the range usable in recent processes, but can be changed. The dimension XC in the X-axis direction of the overlapping region between the tungsten electrode 3 and the resistive layer R can be, for example, 1 μm≦XC≦10 μm. A more specific range for the dimension XC can be 2 μm to 4 μm. If the dimension XC is too short, the contact area between them will be small, and if it is too long, the region in which the resistive layer effectively functions will be small. The thickness Z4A of the first protective film 4A can be set to, for example, 10 nm≦Z4A≦100 nm. A specific example of the thickness Z4A is 50 nm. The thickness Z4A is set to a value that can protect the resistance layer R.

[0043] The metal electrode EC may be composed of two or more layers of metal material. The metal electrode EC includes a base electrode layer EC1 in contact with the second region 32 of the tungsten electrode 3 and an upper electrode layer EC2. To form the base electrode layer EC1 on the second region 32 of the tungsten electrode 3, the resistive layer R is etched and patterned, followed by the formation of a first protective film 4A made of silicon oxide (SiO2), an etching stop layer 4E made of silicon nitride (Si3N4) or the like, and an interlayer film 4F made of silicon oxide (SiO2) or the like. Next, the interlayer film 4F is etched until the etching stop layer 4E is exposed. Note that the etching rate of the etching stop layer 4E is lower than the etching rate of the interlayer film 4F. Next, the etching stop layer 4E and the first protective film 4A are etched to expose the surface of the tungsten electrode 3. Dry etching such as the RIE described above can be used for these etching processes.

[0044] Gases that can be used for dry etching of SiO2 include perfluorocarbon gases (CF4, C2F6, C3F8, C4F8, C5F 12 , C2F4, C3F6, C5F8), hydrofluorocarbon gases (CHF3, CH2F2, CH3F, C2H2F4, C2H4F2, C2HF5, C3H3F5, C4H3F), and fluorocarbon gases ((CF3CO)2, (CF3)2O, CBrF3, (CBrF2)2, C2F5I). If necessary, a gas selected from O2 and H2 may be mixed with these etching gases. Si3N4 can be etched using an etching gas containing a fluorine-containing gas, such as perfluorocarbon gas or hydrofluorocarbon gas. For example, when the etching stop layer 4E is a silicon nitride film, a dry etching gas for the silicon nitride film can be, for example, a mixed gas of fluorine, oxygen, and nitrogen, or a mixed gas of hydrofluorocarbon with oxygen and chlorine.

[0045] Known methods for forming the above-mentioned SiO2 include thermal oxidation of silicon, CVD (chemical vapor deposition), and sputtering. An example of a raw material for the CVD method is TEOS (((Si(OC2H5)4):tetraethoxysilane)). An example of a method for forming the above-mentioned Si3N4 is CVD or sputtering.

[0046] On the surface of the tungsten electrode 3, a base electrode layer EC1 and an upper electrode layer EC2 are formed in this order by using a sputtering method or the like.

[0047] The base electrode layer EC1 may contain tantalum (Ta) or titanium nitride (TiN). The top electrode layer EC2 is formed on the base electrode layer EC1 and contains aluminum. In the semiconductor device of this example, aluminum is used for the top electrode layer EC2 of the metal electrode EC, but not for the tungsten electrode 3 or the base electrode layer EC1. Aluminum has a high tendency to diffuse due to electric fields, etc., and can be a cause of characteristic fluctuations. Because the tungsten electrode 3 and the base electrode layer EC1 are not made of aluminum, the cause of characteristic fluctuations due to aluminum can be suppressed.

[0048] The materials of each element will be explained.

[0049] The semiconductor substrate 1 may have conductivity. For example, the impurity concentration of the semiconductor substrate 1 may be 5×10 13 (cm -3 ) or more 5 x 10 14 (cm -3 ) or less. The thickness of the semiconductor substrate 1 may be 50 μm or more and 800 μm or less. The material of the semiconductor substrate 1 can be silicon (Si), but it is also possible to use a compound semiconductor such as SiC or SiGe.

[0050] The material of the resistive layer (wire resistor) constituting the resistive layer R is a resistive material with a higher resistivity than polysilicon. It includes a chromium compound or a metal nitride. The resistive layer R includes a chromium compound, which includes chromium (Cr) and silicon (Si). The chromium compound can include at least one chromium compound selected from the group consisting of CrSi, CrSiO, CrSiC, and CrSiN. When the resistive layer R includes a metal compound, the metal nitride can include at least one metal nitride selected from the group consisting of tantalum nitride and titanium nitride. These materials can be in good direct contact with the tungsten electrode 3. Other materials can also be used. Specifically, the material of the resistive layer constituting the resistor can include at least one metal compound selected from the group consisting of CrSi, CrSiN, CrSiO, CrSiC, TaN, and TiN. The resistive layer constituting the resistor can be formed using a sputtering method using a target containing a resistive material. Depending on the type of material of the resistive layer R, a plating method can also be used. The resistive layer R can be composed of a single resistive material or a combination of multiple resistive materials. The thickness Rd of each resistive layer constituting the resistive layer R can be set to 1 nm≦Rd≦5 nm. When the thickness Rd is equal to or less than the upper limit, the resistance value can be sufficiently increased, and when the thickness Rd is equal to or greater than the lower limit, the resistance and strength of the resistive layer can be maintained.

[0051] The first electrode E1 and the second electrode E2 may be made of a metal material such as Al (aluminum) or Cu (copper).

[0052] In addition, in the range of various parameters, the range of an arbitrary parameter P is P min ≦P≦P max If given by (P min +ΔP)≦P≦(P max -ΔP), ΔP=(P max -P min )×R%, R may be set to 10, or R may be set to 20, R may be set to 30, or R may be set to 40. (Supplementary Note) As described above, various embodiments of the present disclosure can be defined as the following supplementary notes.

[0053] [A1] A semiconductor device comprising: a semiconductor substrate 1; an insulating layer 2 formed on the semiconductor substrate 1 and having a groove 2G on its surface; a tungsten electrode 3 embedded in the groove 2G; a resistive layer R containing a chromium compound or a metal nitride formed on a first region 31 of the tungsten electrode 3; and a metal electrode EC formed on a second region 32 of the tungsten electrode 3.

[0054] [A2] The semiconductor device according to [A1], wherein the resistive layer R contains a chromium compound, and the chromium compound contains chromium and silicon.

[0055] [A3] The semiconductor device according to [A2], wherein the chromium compound includes at least one chromium compound selected from the group consisting of CrSi, CrSiO, CrSiC, and CrSiN.

[0056] [A4] The semiconductor device according to [A1], wherein the resistive layer R contains a metal compound, and the metal nitride contains at least one metal nitride selected from the group consisting of tantalum nitride and titanium nitride.

[0057] [A5] A semiconductor device described in any one of [A1] to [A4], wherein the number of the grooves 2G provided to connect the resistive layer R and the metal electrode EC is plural, and a plurality of the tungsten electrodes 3 are embedded in each of the plurality of grooves 2G.

[0058] [A6] A semiconductor device described in any one of [A1] to [A4], wherein the metal electrode EC is in contact with the second region 32 of the tungsten electrode 3 and includes a base electrode layer EC1 containing tantalum or titanium nitride, and an upper electrode layer EC2 formed on the base electrode layer EC1 and containing aluminum.

[0059] [A7] A semiconductor device according to any one of [A1] to [A4], comprising a resistor formed by electrically connecting a plurality of the resistive layers R, and a plurality of terminals (EP, EG, EN) for detecting potential connected to a plurality of nodes in the resistor.

[0060] Although various exemplary embodiments have been described above, various omissions, substitutions, and modifications may be made without being limited to the above-described exemplary embodiments. Furthermore, elements from different embodiments may be combined to form other embodiments. It will be understood from the above description that various embodiments of the present disclosure have been described herein for illustrative purposes, and that various modifications may be made without departing from the scope and spirit of the present disclosure. Accordingly, the various embodiments disclosed herein are not intended to be limiting, with the true scope and spirit being indicated by the appended claims. [Explanation of symbols]

[0061] 1...Semiconductor substrate 2...Insulating layer 2G…Groove 3...Tungsten electrode 2A...First dielectric layer 2B: Second dielectric layer 4…Protective film 4A…First protective film 4B…Second protective film 4C…Third protective film 4D…Fourth protective film 4E…Etch stop layer 4F...Interlayer film 10...Resistance device 20...Amplification device 31...First area 32…Second area 100...High voltage detection device E1…1st electrode E2…Second electrode EC…metal electrode EC1…base electrode layer EC2…electrode layer EG…Reference electrode EN: Second output electrode EP…1st output electrode GND: Ground potential INP...First input terminal INN: Second input terminal R…Resistance layer RP…1st high resistance part RPS...1st low resistance section RN…Second high resistance section RNS…Second low resistance section VC…Reference terminal Vcc: power supply voltage Vout: Output voltage

Claims

1. a semiconductor substrate; an insulating layer formed on the semiconductor substrate and having a groove on its surface; a tungsten electrode embedded in the groove; a resistive layer including a chromium compound or a metal nitride formed on a first region of the tungsten electrode; a metal electrode formed on a second region of the tungsten electrode; A semiconductor device comprising:

2. the resistive layer contains a chromium compound; The chromium compound includes chromium and silicon. The semiconductor device according to claim 1 .

3. The chromium compound includes at least one chromium compound selected from the group consisting of CrSi, CrSiO, CrSiC, and CrSiN. The semiconductor device according to claim 2 .

4. the resistive layer includes a metal compound; The metal nitride includes at least one metal nitride selected from the group consisting of tantalum nitride and titanium nitride. The semiconductor device according to claim 1 .

5. the number of the grooves provided to connect the resistance layer and the metal electrode is plural, A plurality of the tungsten electrodes are embedded in the plurality of grooves, respectively. The semiconductor device according to any one of claims 1 to 4.

6. The metal electrode is a base electrode layer contacting the second region of the tungsten electrode and including tantalum or titanium nitride; an upper electrode layer formed on the base electrode layer and containing aluminum; Including, The semiconductor device according to any one of claims 1 to 4.

7. a resistor formed by electrically connecting a plurality of the resistive layers; a plurality of electrodes for detecting potential connected to a plurality of nodes of the resistor; Equipped with The semiconductor device according to any one of claims 1 to 4.

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