Design support system and design support method

Abstract

To reduce time and labor required for designing a semiconductor.SOLUTION: A code-generating language model processing unit that generates a code necessary for designing a wafer or a package by natural language processing using a language model based on an input specification, a transmission / reception unit that transmits, to an external server, concealed data-excluded learning data obtained by excluding data that needs to be concealed from learning data used in the natural language processing and an input and an output of the code-generating language model processing unit, and receives a natural language processing result in the server, and a verification unit that verifies the code as the natural language processing result in the server. When the verification unit determines that the code is appropriate, the verified code is output as design data of the wafer or the package.SELECTED DRAWING: Figure 5

Description

[Technical Field]

[0001] The present invention relates to a design support system and a design support method suitable for application to semiconductor design. [Background technology]

[0002] Conventionally, general-purpose semiconductors that can be installed in a variety of products have been mass-produced. Examples of general-purpose semiconductors include the central processing units (CPUs) installed in personal computers. Conventional general-purpose semiconductors based on the von Neumann architecture were designed to have high performance in sequential processing.

[0003] According to Moore's Law, semiconductor production costs can be reduced by increasing integration density. Therefore, the main goal of conventional semiconductors has been to increase the production volume of general-purpose semiconductors and reduce production costs. However, increasing the production volume of semiconductors requires a large investment in equipment. For this reason, the fabless production method, in which a company that primarily designs semiconductors outsources the production of semiconductors to an external company, has become mainstream.

[0004] Patent Document 1 discloses a technique relating to lithography-based pattern optimization. [Prior art documents] [Patent documents]

[0005] [Patent Document 1] U.S. Patent No. 1,144,9659 Summary of the Invention [Problem to be solved by the invention]

[0006] As semiconductors become increasingly miniaturized, not only are there issues with turnaround time (TAT) in semiconductor manufacturing, but the rules and constraints for semiconductor design have become more complex, lengthening the time required for design. As a result, if a problem is discovered in the semiconductor development process, it takes a huge amount of time and money to redo the design and manufacturing (prototype). Therefore, there was a need for a design methodology that would reduce the number of redoes required when designing semiconductors.

[0007] In the current semiconductor manufacturing system, businesses that design semiconductors and businesses that manufacture semiconductors exist separately. Therefore, optimal manufacturing conditions and causes of failures, which can only be determined by the semiconductor manufacturing businesses manufacturing semiconductors based on design information from the semiconductor design businesses, are not shared with the semiconductor design businesses. Even if optimal manufacturing conditions and causes of failures are shared among businesses, semiconductor design businesses simply repeat trial and error, not knowing how to optimally design semiconductors. Therefore, conventional semiconductors require a long time to design. Furthermore, even when the technology disclosed in Patent Document 1 is used, the time required for semiconductor design remains the same.

[0008] The present invention has been made in view of the above circumstances, and has as its object to provide a design support system and a design support method that can reduce the time and effort required for semiconductor design. [Means for solving the problem]

[0009] The design support system of the present invention is a design support system for designing either or both of a wafer process for manufacturing wafers and a packaging process for manufacturing packages from wafers, and includes: a specification input unit for acquiring specifications of the wafer and / or package; a code-generation language model processing unit for generating code required for designing the wafer and / or package through natural language processing using a language model based on the specifications input to the specification input unit; a transceiver unit for transmitting confidential data-excluded learning data, which is obtained by excluding data that needs to be kept confidential from the learning data used in the natural language processing in the code-generation language model processing unit, and the input and output of the code-generation language model processing unit to an external server that performs natural language processing and receives the natural language processing results from the server; a verification unit for verifying the code obtained by the transceiver unit as the result of the natural language processing on the server; and if the verification unit determines that the verified code is appropriate, outputting the verified code as design data for the wafer and / or package.

[0010] Furthermore, the design support method of the present invention is a design support system that designs either or both of a wafer process for manufacturing wafers and a packaging process for manufacturing packages from wafers through computational processing by a computer, and the computational processing executed by the computer includes a specification input process for acquiring specifications for the wafer and / or package, a code generation language model process for generating code required for designing the wafer and / or package through natural language processing using a language model based on the specifications input by the specification input process, a transmission and reception process for transmitting confidential data-excluded learning data that excludes data that needs to be kept confidential from the learning data used in the natural language processing by the code generation language model processing, and the input and output when performing the code generation language model processing to an external server that performs natural language processing, and receiving the natural language processing results at the server, and a verification process for verifying the code as a result of the natural language processing at the server obtained by the transmission and reception process, and if the verification process determines that the code is appropriate, the verified code is output as design data for the wafer and / or package. [Effects of the Invention]

[0011] According to the present invention, the time required for semiconductor design can be significantly reduced by coordinating the generation of design code in an on-premise environment that can be used by the design department and the generation of design code in a cloud environment using an external server. [Brief explanation of the drawings]

[0012] [Figure 1] 1 is an overall configuration diagram showing an example of a semiconductor manufacturing process according to a first embodiment of the present invention. [Figure 2] FIG. 4 is a diagram showing an example of a post-process in a packaging process according to the first embodiment of the present invention. [Figure 3] 1 is a block diagram showing an example of the overall configuration of a design support system according to a first embodiment of the present invention; [Figure 4] 1 is a block diagram showing an example of the configuration of a commanding device according to a first embodiment of the present invention; [Figure 5] 1 is a block diagram showing an example of the configuration of a design unit of a design support system according to a first embodiment of the present invention; [Figure 6] 5 is a flowchart showing an example of a program language generation process of a design unit of a design support system according to a first embodiment of the present invention. [Figure 7] 1 is a flowchart illustrating an example of processing in an on-premise environment and processing in a cloud environment during design in a design support system according to a first embodiment of the present invention. [Figure 8] FIG. 10 is a block diagram showing an example of the configuration of a design unit of a design support system according to a second embodiment of the present invention. [Figure 9] 10 is a flowchart showing an example (example 1) of a program language generation process of a design unit of a design support system according to a second embodiment of the present invention. [Figure 10] 10 is a flowchart showing an example (example 2: example of generating an intermediate language) of a program language generation process of a design unit of a design support system according to a second embodiment of the present invention. [Figure 11]FIG. 10 is a diagram illustrating an example of a processing configuration of a code generated by a design support system according to a second embodiment of the present invention. [Figure 12] FIG. 10 is a diagram illustrating an example of code generated by a code generation LLM processing unit according to a second embodiment of the present invention. [Figure 13] FIG. 10 is a diagram illustrating an example of an operation performed by a code generation LLM processing unit according to each embodiment of the present invention. [Figure 14] 10A-10C illustrate examples of additional prompts according to exemplary embodiments of the present invention. DETAILED DESCRIPTION OF THE INVENTION

[0013] <First embodiment> A design support system and a design support method according to a first embodiment of the present invention will be described below with reference to FIGS.

[0014] [An example of the semiconductor manufacturing process] FIG. 1 is a diagram showing an overall configuration of an example of a semiconductor manufacturing process according to a first embodiment.

[0015] The semiconductor manufacturing process is roughly divided into the design process, the wafer process for manufacturing wafers, and the packaging process for manufacturing packages from wafers. In this embodiment, the manufacturing technology for design is called MFD (Manufacturing for Design) to distinguish it from DFM (Design for Manufacturing), which is a conventional design technology for manufacturing. MFD is a methodology that supports design based on data obtained in the wafer process and packaging process. In the design support system 10 according to the first embodiment (see FIG. 3 described later), repeating MFD and DFM enables Design-Manufacturing Co-Optimization (DMCO), which represents the coordination and optimization of semiconductor design and manufacturing. As a result, the design support system 10 according to the first embodiment makes it possible to reduce the total cycle time from semiconductor design to packaging compared to conventional methods.

[0016] In the design process, semiconductors and circuit layouts are designed. In this embodiment, a new design methodology supported by an AI (Artificial Intelligence) model is provided to semiconductor customers. For example, the AI ​​model learns from silicon big data measured by various measuring devices in the wafer process and packaging process, thereby training each AI model shown in FIG. 4 (described later) and improving the performance of the PDK (Process Design Kit). Then, in this embodiment, the trained AI model is used in the design process to assist the customer's designer in their design, thereby automating semiconductor design.

[0017] The PDK contains technology information necessary for semiconductor design, such as what device models are available, what design rules should be used, and what regulatory components should be extracted. Designers import this information into the PDK tool to design semiconductors. The MFD, in which the AI ​​model learns from silicon big data (Figure 1), and the MFD, in which the AI ​​model assists the designer by navigating the design, are configured in a hierarchical structure.

[0018] [General wafer process and packaging process] The wafer and packaging processes are divided into front-end and back-end processes. The front-end process includes the front-end line (FEOL) where device formation is performed, the back-end line (BEOL) where wiring formation is performed, and wafer characteristic inspection.

[0019] FEOL includes, for example, a cleaning process, a film deposition process, a photolithography process, an etching process, an ion implantation process, and a wafer inspection process, and these processes are repeated. BEOL includes, for example, a cleaning process, a film deposition process, a photolithography process, an etching process, a planarization process, and a wafer inspection process, and these processes are repeated for wafers manufactured through FEOL. In the wafer inspection process, electrical characteristics of wafers manufactured through BEOL are inspected. Once the wafer characteristic inspection is completed, the wafer is completed.

[0020] Post-processing includes assembly and inspection. The assembly process includes dicing, die bonding, wire bonding, and molding for wafers that are determined to be non-defective as a result of wafer characteristic inspection. The inspection process includes a final inspection process for semiconductors produced in the molding process. This post-processing consisting of assembly and inspection is carried out in simple packaging processes using wire bonding of a single chip and complex packaging processes in which multiple chips are stacked. Once the final inspection process is completed, the packaged semiconductor (also called a chip) is completed.

[0021] [Wafer Process and Packaging Process According to the Present Embodiment] Generally, wafer processes are divided into batch processes, in which all wafers in a lot undergo the same process, and single-wafer processes, in which wafers in a lot are processed one by one and the process for each wafer can be changed. Usually, both processes are mixed. In the wafer process according to this embodiment, all processes are performed using the single-wafer process. As a result, in this embodiment, the time required to complete one lot can be reduced to less than the time required to complete batch-based processing. Furthermore, in this embodiment, by prototyping each wafer under different conditions, a larger amount of data can be accumulated in the same time period compared to processes that include batch processing, and silicon big data is generated. Silicon big data contributes to improving wafer yield in the wafer process. Silicon big data is also used to train AI models in the design process (MFD). In addition, in the wafer process, the single-wafer process can reduce the processing time (x) per wafer to less than half of the conventional process.

[0022] The packaging process involves bonding wafers together, wafers together, chips together, and chips together to form multi-chips, which are then mounted on a substrate, and the combinations are extremely diverse and complex. The post-processing described below conceptually involves chipping the wafer completed in the pre-processing, mounting the chips on a substrate (such as a silicon substrate) with a different redistribution line, and then mounting the resulting substrate on a final packaging substrate. Because a substrate with a different redistribution line is mounted on the packaging substrate, multiple chips with different functions are integrated and connected in the post-processing. Therefore, according to this embodiment, even if not all functions are integrated on a single chip, equivalent functionality can be achieved by a packaging substrate product in which multiple chips with different functions are integrated.

[0023] FIG. 2 is a diagram showing an example of a post-process in a packaging process that corresponds to multi-chip. In the back-end process, for example, a bump formation process and a dicing process are performed on the wafer manufactured in the above-mentioned front-end process. In the back-end process, a TSV process, a rewiring layer formation process, and a bump formation process are performed on the rewiring substrate. Then, in the back-end process, a chip mounting process is performed in which the chips separated by the dicing process are combined with the rewiring substrate. After the sealing process and the bump formation process, a substrate mounting process is performed on the packaging substrate. Furthermore, in the back-end process, after the sealing process, a final inspection process is performed.

[0024] During the design process, heterogeneous (heterogeneous integration) design is possible using chiplet technology based on design support information received from a chiplet technology platform containing multiple IPs. In the semiconductor field, the functional blocks that make up LSIs, such as CPUs, image processing circuits, and memories, are considered design assets and are called IP (Intellectual Property) cores or simply IP. In this specification, IP is described as a circuit element in semiconductor design. Circuit elements can be anything, such as simple standard cells, interface functional blocks, or CPU cores.

[0025] [Example of design support system configuration] 3 is a block diagram showing an example of the overall configuration of a design support system 10 according to this embodiment. The design support system 10 includes a control device 1, a design section 2, a wafer process section 3, and a packaging section 4.

[0026] The control device 1 provides a platform that can be arbitrarily accessed by the design department 2, wafer process department 3, and packaging department 4. To this end, the control device 1 acquires wafer process information measured in the wafer process for manufacturing wafers from the wafer process department 3, acquires packaging process information measured in the packaging process from the packaging department 4, and provides design support information calculated based on the wafer process information and packaging process information to the design department 2.

[0027] The supervisory device 1 uses the wafer process information as silicon big data and the packaging process information as packaging big data to perform analysis using a design AI model (described below) to create design support information. The analysis using the design AI model determines correlations between various types of parameters based on the silicon big data and the packaging big data. The design AI model provides the design support information, including optimal parameter combinations and values, to the design department 2.

[0028] The design unit 2 designs the wafer process and the wafer packaging process. The design support information provided by the control device 1 and the design support function of the AI ​​model enable optimal semiconductor design, so the design unit 2 can increase the convergence speed of the design. Note that the design unit 2 may incorporate information on semiconductor design by a designer using the design support function of the AI ​​model, or it may incorporate information on semiconductor design by the AI ​​model itself.

[0029] The wafer process section 3 has a function of managing the wafer process, and manufactures wafers based on the design information designed by the design section 2. The wafer process section 3 transmits data measured by various measuring devices in the wafer process to the control device 1 as wafer process information.

[0030] The packaging unit 4 has a function of managing the packaging process for wafers manufactured by the wafer process unit 3. The packaging unit 4 performs a packaging process for wafers manufactured by the wafer process unit 3, in which various chips are placed on a substrate and wiring is performed between the multiple chips based on the placement information designed by the design unit 2. The packaging unit 4 also transmits data measured by various measuring devices in the packaging process to the control device 1 as packaging process information.

[0031] 4 is a block diagram showing an example of the internal configuration of the supervising device 1. The supervising device 1 operates as a platform that provides the functions of each section of the design section 2. The supervising device 1 includes a wafer process information collecting section 50, a packaging process information collecting section 60, a design process learning section 70, and a separating section 73.

[0032] The wafer process information collecting unit 50 accumulates wafer process information acquired for each wafer manufactured in the wafer process, and outputs the wafer process information to the design process learning unit 70. The wafer process information collecting unit 50 includes a data acquiring unit 51, a feedback unit 52, and a wafer process database (hereinafter referred to as DB) 53.

[0033] The data acquisition unit 51 acquires a large amount of data for each wafer in the wafer process as wafer process information. The data acquired by the data acquisition unit 51 is stored in the wafer process DB 53.

[0034] The feedback unit 52 outputs the data (wafer process information) read from the wafer process DB 53 to the design process learning unit .

[0035] The packaging process information collecting unit 60 accumulates packaging process information acquired each time a chip cut out from a wafer manufactured in the packaging process is packaged, and outputs the packaging process information to the design process learning unit 70. This packaging process information collecting unit 60 includes a data acquiring unit 61, a feedback unit 62, and a packaging process DB 63.

[0036] The data acquisition unit 61 acquires a large amount of data measured for each packaged product in the packaging process as packaging process information. The data acquired by the data acquisition unit 61 is stored in the packaging process DB 63. The feedback unit 62 outputs the data (packaging process information) read from the packaging process DB 63 to the design process learning unit .

[0037] The design process learning unit 70 obtains design support information that supports the design of the wafer process based on the wafer process information, and obtains design support information that supports the design of the packaging process based on the packaging process information. The design process learning unit 70 creates a design AI model based on this design support information and supplies it to the design unit 2. The design process learning unit 70 includes a design DB 71 and a design learning unit 72.

[0038] The design DB 71 stores wafer process information provided by the wafer process information collection unit 50 and stores packaging process information provided by the packaging process information collection unit 60 . The design DB 71 also stores design AI models used in the design process. The design AI models have functions to support various designs in the design process. Machine learning in the design AI model can be unsupervised, supervised, or reinforcement learning, depending on the DMCO application. The design learning unit 72 performs machine learning or the like based on the wafer process information and packaging process information to update the design AI model. The updated design AI model is stored in the design DB 71.

[0039] The dividing unit 73 can set the dividing range between the process of the designer who is the customer and the process of the manufacturer who manufactures wafers based on that design.

[0040] The design department 2 designs wafer specifications and package specifications using a design AI model provided by the design process learning department 70. The wafer specifications designed by the design department 2 are transmitted to the wafer process department 3. The package specifications designed by the design department 2 are transmitted to the package department 4.

[0041] The design unit 2 performs design using a design AI model in a so-called on-premise environment prepared within a company that has the design support system 10 according to this embodiment. However, the design unit 2 of this embodiment transfers data to a cloud server 90 prepared in a cloud environment, and performs part of the design using the cloud server 90. Details of the processing performed by this design unit 2 using the cloud server 90 will be described in Figure 5 and subsequent figures.

[0042] [Design Department Structure] FIG. 5 shows an example of the configuration of the design unit 2. The design unit 2 includes a specification input unit 101. The specification input unit 101 performs specification input processing to acquire and input specifications (such as a specification sheet) of a semiconductor to be designed from a user company or the like. The specification data input to the specification input unit 101 is supplied to the code generation LLM processing unit 110. The specification input to the specification input unit 101 is written in a natural language.

[0043] The code generation LLM processing unit 110 is a code generation language model processing unit that generates code, which is a design specification in a design language required for designing wafers and packages, through natural language processing using a large-scale language model (LLM). The code generation LLM processing unit 110 uses the design AI model provided by the design process learning unit 70 as the large-scale language model.

[0044] The code generated by the code generation LLM processing unit 110 is written in, for example, C++, a language used in semiconductor design. The code is written at, for example, the RTL (Register Transfer Level) level. At the RTL level, details of hardware resources, details of data transfer registers, etc. are written.

[0045] When generating code, the code generation LLM processor 110 obtains additional information about the semiconductor design from a Retrieval-Augmented Generation (RAG) processor 140 for performing an augmentation process called RAG. The additional information obtained from the RAG processing unit 140 is used together with the design AI model when the code generation LLM processing unit 110 performs natural language processing using a large-scale language model.

[0046] The code generation LLM processing unit 110 is also configured to be able to transfer data to and from an external cloud server 90 via a transmission / reception unit 111. The transmission / reception unit 111 executes transmission / reception processing between the code generation LLM processing unit 110 and the cloud server 90 via a predetermined network.

[0047] Cloud server 90 is a general-purpose server that is provided on a network such as the Internet and performs natural language processing using large-scale language models. Cloud server 90 is used by various users and has extremely large-scale language models that are AI models that have been accumulated through repeated learning based on the use by these various users.

[0048] Therefore, the large-scale language model possessed by the cloud server 90 is likely to be larger in scale than the code generation LLM processing unit 110 of the design unit 2 prepared in the on-premise environment. The cloud server 90 may be one that has a design AI model specialized for semiconductor design, but it may also be a general-purpose cloud server that is not specialized for semiconductor design.

[0049] The code generation LLM processing unit 110 uses the cloud server 90 to generate code that meets appropriate design specifications through the interaction of the large-scale language models that both parties possess. In other words, the transmitting / receiving unit 111 sends the code generated by the code generation LLM processing unit 110 and training data from the AI ​​model to the cloud server 90 as data d1, and receives the code that has been further processed by the cloud server 90 as data d2.

[0050] The code included in the data d2 received by the transmitting / receiving unit 111 is supplied to the code generation LLM processing unit 110, and is output as the code generated by the code generation LLM processing unit 110. The process in which the code generation LLM processing unit 110 generates code using the cloud server 90 will be described later with reference to the flowchart of FIG.

[0051] The code generated by the code generation LLM processing unit 110 is verified by the C++ verification unit 120 and the RTL verification unit 130 to determine whether it is correct. At this time, the C++ verification unit 120 and the RTL verification unit 130 perform equivalence verification to determine whether they have been mutually verified correctly. As the C++ verification unit 120 and the RTL verification unit 130, commercially available tools (software) for semiconductor design can be used.

[0052] After the verification by the C++ verification unit 120 and the RTL verification unit 130 is completed, the code generated by the code generation LLM processing unit 110 and the cloud server 90 is output to the wafer process unit 3 and the packaging unit 4 shown in Figure 4.

[0053] [Code generation processing in the code generation LLM processing unit] FIG. 6 is a flowchart showing the flow of the code generation process performed by the code generation LLM processing unit 110. First, the specification input unit 101 of the design unit 2 acquires the specifications of the semiconductor to be designed (step S11). The acquired specifications are written in natural language, for example, in a specification table provided by a semiconductor user company.

[0054] The specification data acquired by the specification input unit 101 is supplied to the code generation LLM processing unit 110, which generates code as wafer and package design data using a large-scale language model as a design AI model (step S12). In the LLM processing at this time, the specification data acquired by the specification input unit 101 becomes a prompt.

[0055] When generating the code in step S12, the code generation LLM processing unit 110 obtains additional conditions for performing the extension processing from the RAG processing unit 140, and performs the code generation processing after taking into consideration, for example, information specific to the design of the current software or package (step S18). Furthermore, the code generation process in step S12 is performed both in an on-premise environment by the code generation LLM processing unit 110 provided in the design unit 2, and in a cloud environment by the cloud server 90, as will be described in the following Figure 7.

[0056] Next, the design unit 2 acquires the program language based on the code obtained by the generation process in step S12 (step S13). When the programming language is acquired in step S13, the C++ verification unit 120 and the RTL verification unit 130 of the design unit 2 execute verification of the acquired programming language (step S14). When the verification in step S14 is completed, the design unit 2 determines whether the verification result is OK or not (step S15).

[0057] If it is determined in step S15 that the programming language is not appropriate (No in step S15), the user of the design support system 10 performs specification correction (step S16), returns to step S11, and the corrected specifications are input into the specification input unit 101.

[0058] If it is determined in step S15 that the programming language is appropriate (Yes in step S15), the design unit 2 performs processing such as high-level synthesis for the programming language acquired in step S13 (step S17), and ends the processing for acquiring the programming language. The high-level synthesis in step S17 is performed using, for example, an existing high-level synthesis tool.

[0059] [Code generation process in on-premise and cloud environments] FIG. 7 is a flowchart showing the flow of processing performed by the code generation LLM processing unit 110 using the cloud server 90 when generating code. First, the design unit 2 executes the code generation process in the code generation LLM processing unit 110 on-premise (step S101).

[0060] During the code generation process in step S101, the code generation LLM processing unit 110 performs code generation through natural language processing using a design AI model obtained from the design DB 71 (FIG. 4). Then, the code generation LLM processing unit 110 acquires learning data from the used design AI model (step S102).

[0061] Next, the design unit 2 receives input of information (confidential data) that cannot be disclosed, as instructed by the user of the design support system 10 (step S103). This confidential data that cannot be disclosed may be held in advance by the design unit 2 or the like. The confidential data that cannot be disclosed is input, for example, as a list of keywords. Specifically, as a semiconductor manufacturer, keywords related to design matters that the manufacturer wants to keep confidential as know-how become confidential data that cannot be disclosed.

[0062] When the secret data is input in step S103, the transmitting / receiving unit 111 of the design unit 2 excludes the secret data specified in step S103 from the learning data acquired in step S102 (step S104). Then, the transmitting / receiving unit 111 transmits the learning data from which the secret data has been removed and the code generated in step S101 to the cloud server 90.

[0063] The cloud server 90 uses the transmitted learning data and learning data already stored in the cloud server 90 to further convert the transmitted code into an appropriate code through natural language processing (step S105). Note that the learning data stored in the cloud server 90 is learning data resulting from the code generation process executed by multiple users in the past.

[0064] Then, the transmitting / receiving unit 111 acquires the program language using the code obtained in the code generation process in step S105 from the cloud server 90 (step S106). The programming language obtained in step S106 corresponds to the programming language obtained in step S13 in FIG.

[0065] As described above, according to this embodiment, by coordinating the generation of design code in an on-premise environment prepared by the semiconductor design company and the generation of design code in a cloud environment using an external server, it becomes possible to design appropriate semiconductors in a short amount of time. In other words, according to this embodiment, the design code generation process is performed using natural language processing in both the on-premise environment and the cloud environment, so that appropriate semiconductor design code can be generated in a short period of time by taking advantage of the capabilities of each processing function.

[0066] In this embodiment, data that should be kept confidential is removed from the training data used in the on-premise environment before the training data is sent to the cloud environment. Therefore, according to this embodiment, the confidentiality of data that a semiconductor design company does not want to be made public is ensured, and natural language processing is executed in the cloud environment, thereby achieving both ensuring the confidentiality of the training data and reducing the design time.

[0067] <Second embodiment> Next, a design support system and a design support method according to a second embodiment of the present invention will be described with reference to Figures 8 to 11. In Figures 8 to 11 which are used to describe the second embodiment, the same parts as those in Figures 1 to 7 which are used to describe the first embodiment are given the same reference numerals, and duplicated explanations will be omitted.

[0068] In this embodiment, the configuration and processing of the design unit 2 are different from those of the first embodiment. The overall configuration and processing of the design support system 10 excluding the design unit 2 are the same as those described with reference to FIG. 3 and the like as the first embodiment.

[0069] [Design Department Structure] FIG. 8 shows the configuration of the design unit 2 of the design support system 10 according to this embodiment. The design unit 2 of this embodiment differs from the design unit 2 shown in FIG. 5 in that it includes a language LLM processing unit 150. The linguistic LLM processing unit 150 is supplied with the semiconductor specifications (specifications, etc.) input to the specification input unit 101 in natural language.

[0070] The language LLM processing unit 150 is a language model processing unit for language generation that uses natural language processing with a large-scale language model (LLM) to generate natural language with specifications that match code generation from input specifications such as specifications. The linguistic LLM processing unit 150 uses the design AI model provided by the design process learning unit 70 as a large-scale language model. When generating the specifications, the linguistic LLM processing unit 150 also acquires additional information about the semiconductor design from the RAG processing unit 140 and generates specifications that reflect the additional information. A specific example of how the linguistic LLM processing unit 150 generates natural language with specifications that match the code generation from data such as a specification table will be described later.

[0071] The specifications generated by the language LLM processing unit 150 are supplied to the code generation LLM processing unit 110. The code generation LLM processing unit 110 generates code, which is a design specification in a design language required for wafer and package design, from the specifications that match the code generation supplied from the language LLM processing unit 150, by natural language processing using a large-scale language model (LLM). This code generation LLM processing unit 110 is the same as the code generation LLM processing unit 110 of the first embodiment in that it uses the design AI model provided by the design process learning unit 70 as a large-scale language model.

[0072] In addition, in this embodiment, when the code generation LLM processing unit 110 generates code, it obtains and uses additional information regarding the semiconductor design from the RAG processing unit 140, which is the same as the code generation LLM processing unit 110 in the first embodiment.

[0073] Furthermore, in this embodiment, the code generation LLM processing unit 110 is configured to be able to transfer data to and from an external cloud server 90 via the transmitting / receiving unit 111, and performs code generation using the cloud server 90. Here, the process in which the code generation LLM processing unit 110 uses the cloud server 90 is the same as the process described in the flowchart of FIG. 7 of the first embodiment. Furthermore, in this embodiment, the design unit 2 is provided with a C++ verification unit 120 and an RTL verification unit 130, and verifies whether the generated code is proper code, just like the first embodiment. The design unit 2 also includes an additional prompt creation unit 112, which creates an additional prompt and supplies it to the code generation LLM processing unit 110 and the language LLM processing unit 150 when the code or specifications generated by the code generation LLM processing unit 110 or the language LLM processing unit 150 are inappropriate.

[0074] [Processing in the language LLM processor and code generation LLM processor (Example 1)] FIG. 9 is a flowchart showing an example (example 1) of the flow of processing performed by the language LLM processing unit 150 and the code generation LLM processing unit 110. First, the specification input unit 101 of the design unit 2 acquires the specifications of the semiconductor to be designed (step S21). The acquired semiconductor specifications are, for example, a specification table provided by a semiconductor user company, and are written in natural language.

[0075] The specification data acquired by the specification input unit 101 is supplied to the language LLM processing unit 150. The language LLM processing unit 150 uses a large-scale language model as a design AI model to generate specifications suitable for generating design code for wafers and packages (step S22). In the LLM processing at this time, the specification data acquired by the specification input unit 101 becomes a prompt. When generating specifications suitable for code generation in step S22, the language LLM processing unit 150 acquires additional conditions for performing extension processing from the RAG processing unit 140 and executes code generation processing (step S30).

[0076] Then, the design unit 2 acquires the specifications obtained by the generation process in step S22 and supplies the acquired specifications as a prompt to the code generation LLM processing unit 110 (step S23).The code generation LLM processing unit 110 then uses a large-scale language model as a design AI model to generate code as design data for the wafer and package (step S24).

[0077] When generating code in step S24, the code generation LLM processing unit 110 also acquires the additional status for performing the extension processing from the RAG processing unit 140 and executes the code generation processing (step S30). The code generation process in step S24 is performed both in an on-premise environment by the code generation LLM processing unit 110 provided in the design unit 2 and in a cloud environment by the cloud server 90, as described in Figure 7 of the first embodiment.

[0078] Next, the design unit 2 acquires the program language based on the code obtained in the generation process in step S24 (step S25). When the programming language is acquired in step S25, the C++ verification unit 120 and the RTL verification unit 130 execute verification of the acquired programming language (step S26). When the verification in step S26 is completed, the design section 2 determines whether the verification result is OK or not (step S27).

[0079] If it is determined in step S27 that the programming language is not appropriate (No in step S27), the user of the design support system 10 performs a process of creating an additional prompt to instruct the language LLM processing unit 150 (step S28a). Furthermore, the user of the design support system 10 performs a process of creating an additional prompt to instruct the code generation LLM processing unit 110 (step S28b). The generated additional prompt is input to the language LLM processing unit 150 or the code generation LLM processing unit 110 and used to generate specifications in step S22 or to generate code in step S24.

[0080] The process of creating these additional prompts is performed by the user after reviewing the verification results. Alternatively, the design unit 2 may automatically create prompts to supplement the specifications of inappropriate parts based on the verification results. Also, in FIG. 9, both the creation of an additional prompt for the language LLM processing unit 150 in step S28a and the creation of an additional prompt for the code generation LLM processing unit 110 in step S28b are performed. Alternatively, the design unit 2 of this embodiment may only create an additional prompt for the code generation LLM processing unit 110 in step S28b, for example.

[0081] Then, if it is determined in step S27 that the programming language is appropriate (Yes in step S27), the design unit 2 performs processing such as high-level synthesis for the programming language obtained in step S25 (step S29), and ends the processing of obtaining the programming language.

[0082] [Processing in the language LLM processor and code generation LLM processor (Example 2)] Fig. 10 is a flowchart showing an example (example 2) of the flow of processing performed by the language LLM processing unit 150 and the code generation LLM processing unit 110. Example 2 shown in Fig. 10 differs from example 1 shown in Fig. 9 in that, during code generation in the code generation LLM processing unit 110, an intermediate language is generated and then a final program language is obtained from the intermediate language.

[0083] First, the specification input unit 101 of the design unit 2 acquires the specifications of the semiconductor to be designed (step S31). The acquired specifications are, for example, a specification table provided by a semiconductor user company, and are written in natural language. The specification data acquired by the specification input unit 101 is supplied as a prompt to the language LLM processing unit 150. The language LLM processing unit 150 uses a large-scale language model as a design AI model to generate specifications suitable for generating design code for wafers and packages (step S32). When generating specifications suitable for code generation in step S32, the language LLM processing unit 150 acquires additional conditions for performing extension processing from the RAG processing unit 140 and executes generation processing (step S44).

[0084] Then, the design unit 2 acquires the specifications obtained by the generation process in step S22, and supplies the acquired specifications to the code generation LLM processing unit 110 as a prompt (step S33). The code generation LLM processing unit 110 generates code for wafer and package design using a large-scale language model as a design AI model (step S34). The code generated here is code in a programming language that serves as an intermediate language for wafer and package design. Also, when generating the code in step S34, the code generation LLM processing unit 110 obtains the addition status for performing extension processing from the RAG processing unit 140 and executes the code generation processing in step S44.

[0085] Furthermore, the code generation process in step S44 is performed both in an on-premise environment by the code generation LLM processing unit 110 provided in the design unit 2, and in a cloud environment by the cloud server 90, as described in Figure 7 of the first embodiment. However, the design unit 2 generates the code in both an on-premise environment using the code generation LLM processing unit 110 provided in the design unit 2 and in a cloud environment using the cloud server 90 only when reprocessing step S34 described below, and the generation in the cloud environment using the cloud server 90 may be omitted when processing step S34 for the first time.

[0086] The design unit 2 acquires the program language of the intermediate language obtained by the generation process in step S24 (step S35). When the intermediate language programming language is acquired in step S35, the C++ verification unit 120 and the RTL verification unit 130 of the design unit 2 execute verification of the acquired programming language (step S36). When the verification in step S36 is completed, the design unit 2 determines whether the verification result is OK or not (step S37).

[0087] If it is determined in step S37 that the programming language is not appropriate (No in step S37), the user of the design support system 10 performs a process of creating an additional prompt to be instructed to the language LLM processing unit 150 (step S38a). Also, the user of the design support system 10 performs a process of creating an additional prompt to be instructed to the code generation LLM processing unit 110 (step S38b).

[0088] Each of the generated additional prompts is input to the language LLM processor 150 or the code generation LLM processor 110, where specification generation in step S32 or code generation in step S34 is performed. The process of creating these additional prompts may be performed by a user after viewing the verification results, or may be performed automatically by the design unit 2. Also, only one of the creation of the additional prompt for the language LLM processing unit 150 in step S38a and the creation of the additional prompt for the code generation LLM processing unit 110 in step S38b may be performed.

[0089] Then, if it is determined in step S37 that the programming language is appropriate (Yes in step S37), the design unit 2 inputs the intermediate programming language acquired in step S35 to the code generation LLM processing unit 110. As a result, the code generation LLM processing unit 110 performs processing to generate code as a programming language for manufacturing wafers and packages (re-executing step S34), and the design unit 2 acquires the generated programming language (step S39).

[0090] When the programming language for manufacturing is acquired by re-executing step S34, the C++ verification unit 120 and the RTL verification unit 130 of the design unit 2 execute verification of the acquired programming language (step S40). When the verification in step S40 is completed, the design section 2 determines whether the verification result is OK or not (step S41).

[0091] If the verification in step S41 determines that the programming language is not appropriate (No in step S41), the user of the design support system 10 performs a process of creating an additional prompt to instruct the code generation LLM processing unit 110 (step S42). Then, the code generation LLM processing unit 110 adds the prompt obtained in step S42 and performs a process of generating code again as a programming language for manufacturing wafers and packages.

[0092] Furthermore, if the verification in step S41 determines that the programming language is appropriate (Yes in step S41), the design unit 2 executes processing such as high-level synthesis (step S43), and ends the processing for obtaining the programming language.

[0093] [Processing configuration of the code generated by the code generation LLM processing unit] Fig. 11 shows a processing configuration for obtaining design data based on the code generated by the code generation LLM processing unit 110. The configuration shown in Fig. 11 corresponds to a configuration for performing, for example, the processing in step S20 of the flowchart in Fig. 9 and the processing in step S43 of the flowchart in Fig. 10.

[0094] 8, the code generated by the code generation LLM processing unit 110 is supplied to an EDA (Electronic Design Automation) tool 5. The EDA tool 5 is a tool that supports circuit design for semiconductors, etc. Note that the use of an EDA tool by the design support system of this embodiment is just an example, and other circuit support design tools may also be used.

[0095] The EDA tool 5 includes a high-level synthesis unit 51, an RTL netlist processing unit 52, and a placement and routing unit 53. The design data obtained by the EDA tool 5 is output from a design data output unit . The high-level synthesis unit 51 generates RTL level data, which is semiconductor circuit data, using as input the code in C++ or the like generated by the code generation LLM processing unit 110. The circuit data generated by the high-level synthesis unit 51 is supplied to the RTL netlist processing unit 52.

[0096] The RTL netlist processing unit 52 generates a netlist describing the wiring of each element from semiconductor circuit data (RTL level data). The netlist generated by the RTL netlist processing unit 52 is supplied to the layout and wiring unit 53. The placement and wiring unit 53 executes processing to place on the device the wiring and elements indicated in the netlist generated by the RTL netlist processing unit 52. The semiconductor placement and wiring data obtained by the placement and wiring unit 53 is supplied to the design data output unit 54.

[0097] The design data output unit 54 outputs the layout and wiring data, which is the design data of the semiconductor obtained by the layout and wiring unit 53. As described above, according to this embodiment, semiconductor design data can be generated based on the code generated by the code generation LLM processing unit 110. The EDA tool 5 shown in FIG. 11 may also perform similar processing on the code generated by the code generation LLM processing unit 110 shown in FIG. 5 to obtain semiconductor design data.

[0098] As explained above, in this embodiment, as in the first embodiment, by linking the generation of design code in an on-premise environment prepared by the semiconductor design company with the generation of design code in a cloud environment using an external server, it becomes possible to design an appropriate semiconductor in a short time.

[0099] In this embodiment, specifications suitable for code generation are generated by the language LLM processing unit 150 from specifications such as a specification sheet provided by a semiconductor user company, and the generated specifications are then supplied to the code generation LLM processing unit 110, which generates a programming language for semiconductor manufacturing. Therefore, according to this embodiment, code generation by the code generation LLM processing unit 110 is performed with appropriate prompts, enabling appropriate code generation in a shorter time. Furthermore, according to this embodiment, semiconductor circuit design data can be obtained based on the generated code, as shown in FIG. 11 , contributing to appropriate semiconductor design in a shorter time.

[0100] Furthermore, according to this embodiment, as shown in the flowchart of Fig. 10, the code generation LLM processing unit 110 first generates an intermediate language, and then the final program language is obtained from that intermediate language, thereby making it possible to verify whether there are any errors at the intermediate language stage. Therefore, according to this embodiment, there is a high possibility that the corrections required will be smaller than correcting the final program language, and the time required for designing wafers and packages can be shortened.

[0101] [Specific examples of processing in the language LLM processing unit] Next, a specific example will be described in which the language LLM processing unit 150 generates a natural language with specifications that match code generation from data such as a specification table. Here, an example is shown that is unrelated to code generation for programming languages ​​used in semiconductor manufacturing, but the principles of generating specifications that match code generation are the same as those for code generation for programming languages ​​used in semiconductor manufacturing.

[0102] For example, the specifications input to the linguistic LLM processing unit 150 are the following natural language sentences: Specifications as input: We would like you to create a specification for the problem of using a Naive Bayes learner to predict whether approximately 100 different animals, given 16 attributes, are classified as "Mammals," "Birds," "Fish," "Reptiles," "Amphibians," "Insects," or "Invertebrates."

[0103] In this case, the specifications that match the code generated by the language LLM processing unit 150 are as follows: Output specifications: 1. Problem definition: This learning device classifies over 100 types of animals into seven categories (mammals, corvids, fish, reptiles, amphibians, insects, and invertebrates). 2. Model: We use a Naive Bayes learner and use fold cross-validation to evaluate accuracy. 3. Data: The dataset contains 16 attributes for each animal (e.g., body temperature, breathing pattern, skin type, etc.). The data is labeled, and each animal must already be classified into one of the categories mentioned above. 4. Feature extraction: The 16 attributes are the features for the model. If necessary, we engineer these attributes (e.g., combine or transform some attributes). 5. Training: The dataset is split into training and test data, and the training data is used to train a Naive Bayesian learner. During this training process, the probability of each animal classification occurring based on the given attributes is determined. 6. Testing: After learning is complete, the model's predictive accuracy is verified using unknown data (test data). 7. Evaluation: To evaluate the performance of the model, we use a confusion matrix and statistical metrics such as accuracy, precision, recall, and F-measure, which allow us to evaluate how accurately each classification is predicted. 8. Optimization: If the model is not accurate enough, we improve it by performing feature engineering and tuning hyperparameters. 9. Prediction: When the user inputs new animal attributes, the trained model is used to predict which category those animals belong to and the result is output.

[0104] As shown in this specific example, the language LLM processing unit 150 generates a detailed analysis of the input specifications by dividing them into items such as problem definition, model, data, feature extraction, learning, testing, optimization, and prediction. Here, if the design AI model supplied to the language LLM processing unit 150 is appropriate, the language LLM processing unit 150 can generate specifications having optimal items for obtaining a programming language for manufacturing wafers and packages. In particular, if the specifications are itemized as described above, the code generation LLM processing unit 110 can easily generate code in a hierarchical structure when generating code, making it possible to generate optimal code.

[0105] [Example of code generated by the code LLM processing unit and its operation] FIG. 12 shows an example of the code generated by the code generating LLM processing unit 110. As shown in Figure 12, the code generation LLM processing unit 110 generates a predetermined programming language such as C++, and the generated programming language can be supplied as is to the wafer processing unit 3 or packaging unit 4 shown in Figure 3 to instruct manufacturing.

[0106] 13 shows an example of how the code generation LLM processor 110 operates based on the design AI model. That is, the example in Fig. 13 shows operations such as implementing a Naive Bayes learner, reading data and dividing it into training and test sets, training the model, evaluating accuracy on the test set, and making predictions on new input data. The output of this operating status is referred to, for example, during the process of creating an additional prompt, allowing the user of the design support system 10 to input an appropriate additional prompt.

[0107] FIG. 14 shows a specific example of an additional prompt generated in steps S28a and S28b of FIG. 9 and steps S38a and S38b of FIG. For example, as shown in Figure 14, we ask participants to enter sentences such as, "Could you please explain the detailed code for the steps to train the model on the training data?" and "Here is a more detailed code for implementing training the Naive Bayes model on the training data..." as additional prompts. In this way, in this embodiment, it is possible to issue an instruction to inquire about inappropriate or omitted parts of the code generated by the code generation LLM processing unit 110.

[0108] <Modification> In the above-described embodiments, the process of generating a programming language consisting of codes for designing both the wafer process and the packaging process has been described. However, the design support system of the present invention may be configured to generate a programming language consisting of codes for designing either the wafer process or the packaging process.

[0109] In addition, in each of the above-described embodiments, the design unit 2 in the design support system 10 shown in Fig. 3 is equipped with a code generation LLM processing unit 110, a language LLM processing unit 150, etc. Alternatively, the design support system 10 may be configured by installing a program as a design support method in an existing computer that designs the wafer process and the packaging process, the program executing the processing shown in the flowcharts of Figs. 6 and 7 in the first embodiment, or the processing procedures shown in the flowcharts of Figs. 8, 9, and 10 in the second embodiment. In this case, the program can be installed in the computer via various recording media. [Explanation of symbols]

[0110] 1...control device, 2...design unit, 3...wafer process unit, 4...packaging unit, 10...design support system, 50...wafer process information collection unit, 51...data acquisition unit, 52...feedback unit, 53...wafer process database, 60...packaging process information collection unit, 61...data acquisition unit, 62...feedback unit, 63...packaging process database, 70...design process learning unit, 72...design learning unit, 73...isolation unit, 90...cloud server, 101...specification input unit, 110...code generation LLM processing unit, 111...transmission / reception unit, 112...additional prompt creation unit, 120...verification unit, 130...RTL verification unit, 140...RAG processing unit, 150...language LLM processing unit

Claims

1. A design support system for designing either or both of a wafer process for manufacturing wafers and a packaging process for manufacturing packages from the wafers, comprising: a specification input unit for acquiring specifications of the wafer and / or the package; a code generation language model processing unit that generates code required for designing the wafer and / or the package by natural language processing using a language model based on the specifications input to the specification input unit; a transceiver that transmits confidential data-excluded training data obtained by excluding data that needs to be kept confidential from training data used in the natural language processing in the code-generation language model processing unit, as well as inputs and outputs from the code-generation language model processing unit, to an external server that performs natural language processing, and receives the results of the natural language processing in the server; a verification unit that verifies a code obtained by the transmission / reception unit as a result of the natural language processing at the server, If the verification unit determines that the code is correct, the verified code is output as design data for the wafer and / or package. Design support system.

2. The language generation language model processing unit processes the specifications input to the specification input unit into specifications suitable for code generation by natural language processing using a language model, The specifications obtained by the language generation language model processing unit are supplied to the code generation language model processing unit. The design support system according to claim 1 .

3. further comprising a search expansion generator; When performing natural language processing in the code generation language model processing unit and natural language processing in the language generation language model processing unit, the external information searched by the search extension generation unit is referenced. The design support system according to claim 2 .

4. Further, an additional prompt creating unit is provided, If the code is found to be inappropriate by the verification unit, the additional prompt creation unit creates an additional prompt related to the inappropriate code, and supplies the created additional prompt to the code generation language model processing unit and / or the language generation language model processing unit, thereby generating code and / or specifications through natural language processing using a language model. The design support system according to claim 2 .

5. The code generation language model processing unit generates a code in an intermediate language, and when the verification unit verifies that the generated code in the intermediate language is correct, the code generation language model processing unit generates a code necessary for designing the wafer and / or the package. The design support system according to claim 2 .

6. A design support method for designing, by computer processing, either one or both of a wafer process for manufacturing a wafer and a packaging process for manufacturing a package from the wafer, the method comprising: The arithmetic processing executed by the computer is a specification input process for acquiring specifications of the wafer and / or the package; a code generation language model process that generates code required for designing the wafer and / or the package by natural language processing using a language model based on the specifications input by the specification input process; a transmission / reception process of transmitting confidential data-excluded training data obtained by excluding data that needs to be kept confidential from the training data used in the natural language processing by the code generation language model processing, and inputs and outputs used in the code generation language model processing, to an external server that performs natural language processing, and receiving the natural language processing results from the server; a verification process of verifying a code obtained by the transmission and reception process as a result of the natural language processing performed by the server, If the verification process determines that the code is correct, the verified code is output as design data for the wafer and / or package. Design support method.

Images