Multi-level ferromagnetic memory device, method of fabricating the same, and semiconductor device including the same

Abstract

To provide a ferromagnetic memory device operating at a multi-level, a method of manufacturing the same, and a semiconductor device including the ferromagnetic memory device.SOLUTION: The ferromagnetic memory device of the present invention comprises a memory cell, wherein the memory cell comprises a magnetic free layer comprising a magnetic material layer, wherein the magnetic free layer comprises a magnetic anisotropy energy gradient induced inside the magnetic material layer by plasma ion irradiation.SELECTED DRAWING: Figure 2

Description

[Technical Field]

[0001] The present invention relates to a ferromagnetic memory device, and more particularly to a ferromagnetic memory device that operates at multiple levels by creating a magnetic anisotropy energy gradient within a memory cell of the ferromagnetic memory device and controlling the magnetization state within the memory cell by region by adjusting the magnitude and pulse of an input current supplied to the ferromagnetic memory device, a method for manufacturing the same, and a semiconductor device including the ferromagnetic memory device. [Background technology]

[0002] A ferromagnetic memory device is a memory device that uses a ferromagnetic material. A ferromagnetic material is a material that can be easily magnetized and retains its magnetized state even after an external magnetic field is removed. This property makes ferromagnetic memory suitable for data storage.

[0003] Ferromagnetic memory is generally associated with spintronics technology, which is a technology that uses the spin and charge of electrons to process information.

[0004] A ferromagnetic memory includes ferromagnetic elements that record information by changing the magnetization state to store data, and switching elements that control the magnetization state of the ferromagnetic elements to enable data reading and writing.

[0005] Ferromagnetic memory includes a magnetic tunnel junction (MTJ) formed by inserting a thin insulating layer between two ferromagnetic layers. The magnetization direction of one of the two ferromagnetic layers, called the reference layer or pinned layer, is fixed, while the magnetization direction of the other, called the magnetic free layer, is variable. [Prior art documents] [Patent documents]

[0006] [Patent Document 1] Japanese Patent Application Laid-Open No. 2015-88669 Summary of the Invention [Problem to be solved by the invention]

[0007] The present invention has been made in view of the above-mentioned conventional techniques, and an object of the present invention is to provide a ferromagnetic memory device that operates at multiple levels, a method for manufacturing the same, and a semiconductor device including the ferromagnetic memory device.

[0008] The present invention has been devised to overcome the drawback that it is difficult to implement multilevel memory in spin-transfer torque magnetoresistive random access memory (STT-MRAM), which stores only one bit using a transistor and a magnetic tunnel junction (MTJ). The present invention provides a ferromagnetic memory device that operates in multilevel mode by creating a magnetic anisotropy energy gradient within a memory cell of the ferromagnetic memory device and controlling the magnetization direction within the memory cell by region by adjusting the magnitude and pulse of the input current supplied to the ferromagnetic memory device, a manufacturing method thereof, and a semiconductor device including the ferromagnetic memory device. [Means for solving the problem]

[0009] In order to achieve the above object, one aspect of the present invention provides a ferromagnetic memory device comprising a memory cell, the memory cell including a magnetic free layer including a magnetic layer, the magnetic free layer including a magnetic anisotropy energy gradient induced within the magnetic layer by plasma ion irradiation.

[0010] The magnetic layer includes a plurality of magnetic domains formed by the magnetic anisotropy energy gradient induced by the plasma ion irradiation, and the magnetic anisotropy energy gradient can be induced by the magnetization states of each of the plurality of magnetic domains and the magnetization states formed by chemical inhomogeneities and physical defects formed within each of the plurality of magnetic domains during the plasma ion irradiation.

[0011] In order to achieve the above object, one aspect of the present invention provides a semiconductor device comprising a ferromagnetic memory device, the ferromagnetic memory device including a memory cell including a plurality of magnetic domains generated in a magnetic free layer, and a magnetic anisotropy energy gradient is induced in the magnetic free layer by injecting ions into the magnetic free layer, and the plurality of magnetic domains are formed by the induced magnetic anisotropy energy gradient.

[0012] The semiconductor device may further include a current control circuit that supplies current pulses to the ferromagnetic memory device to induce a number of different magnetization states greater than the number of the plurality of magnetic domains. The magnetization states may include magnetization states of each of the plurality of magnetic domains and magnetization states formed by chemical inhomogeneities and physical defects within the plurality of magnetic domains. Each of the magnetization states may be determined by the direction of the current pulse, the number of times the current pulse toggles, the pulse width of the current pulse, or the amplitude of the current pulse.

[0013] In order to achieve the above object, a method for manufacturing a ferromagnetic memory device according to one aspect of the present invention includes the steps of providing a memory device having a memory cell including a magnetic free layer having a magnetic material layer, and forming a magnetic anisotropy energy gradient within the memory cell.

[0014] Forming the magnetic anisotropy energy gradient may include implanting ions into the memory cell to form the magnetic anisotropy energy gradient. The step of forming the magnetic anisotropy energy gradient may include the step of injecting ions accelerated at an acceleration voltage corresponding to each of the regions included in the magnetic layer using different mask patterns at different times into each of the regions, thereby generating each of the ferromagnetic regions in the magnetic layer so that the magnetic layer has the magnetic anisotropy energy gradient. [Effects of the Invention]

[0015] According to the ferromagnetic memory device of the present invention, since the memory cell of the ferromagnetic memory device includes a plurality of magnetic domains generated by the formation of a magnetic anisotropy energy gradient by ions irradiated or injected into the memory cell of the ferromagnetic memory device, it is possible to control the magnetization state of each of the plurality of magnetic domains and / or the magnetization state generated by the interaction between the plurality of magnetic domains by adjusting the direction, number of togglings, pulse width, or amplitude of the current pulse supplied to the ferromagnetic memory device.

[0016] In addition, according to the ferromagnetic memory device of the present invention, it is possible to define each of the magnetization states of multiple magnetic domains and / or multiple levels of the magnetization state formed by the interaction of multiple magnetic domains, thereby allowing multi-bit data to be stored. [Brief explanation of the drawings]

[0017] [Figure 1] 1 is a schematic diagram of a semiconductor system including a ferromagnetic memory device having memory cells including magnetic layers with a magnetic anisotropy energy gradient according to an embodiment of the present invention; [Figure 2] FIG. 2 is a schematic diagram of the ferromagnetic memory device shown in FIG. 1 cut in the AA direction. [Figure 3] FIG. 2 is an enlarged view of a memory cell of the ferromagnetic memory device shown in FIG. [Figure 4] 1 is a schematic diagram of various magnetic hysteresis loops showing the magnitude of magnetization versus the strength of the magnetic field of a ferromagnetic material formed under various conditions. [Figure 5] 2A and 2B are an enlarged view and a schematic view of the memory cell shown in FIG. 1 taken along the BB direction, respectively, at a stage before a magnetic anisotropy energy gradient is formed in the memory cell. [Figure 6] 6 is a schematic diagram illustrating a method of generating a first magnetic domain by irradiating ions accelerated by a first acceleration voltage onto a first region of the memory cell region shown in FIG. 5(A) through a first mask pattern. FIG. [Figure 7] 6 is a schematic diagram illustrating a method of generating a second magnetic domain by irradiating ions accelerated by a second acceleration voltage onto a second region of the memory cell region shown in FIG. 5(A) through a second mask pattern. FIG. [Figure 8] FIG. 6 is a schematic diagram illustrating a method of generating a third magnetic domain by irradiating ions accelerated by a third acceleration voltage onto a third region of the memory cell region shown in FIG. 5(A) through a third mask pattern. [Figure 9] FIG. 9 is a conceptual diagram illustrating a method for controlling the magnetization direction of each of the first to third magnetic domains generated by FIGS. 6 to 8 by the number of times an input current is toggled. [Figure 10A] 10 is a schematic graph showing Hall resistance gradually changing depending on the number of times the input pulse current shown in FIG. 9 is toggled; [Figure 10B] 2 is a conceptual diagram illustrating a magnetization state that changes depending on the number of times an input pulse current supplied to the ferromagnetic memory device shown in FIG. 1 is toggled. [Figure 11] FIG. 9 is a conceptual diagram illustrating a method for controlling the magnetization direction of each of the first to third magnetic domains generated by FIGS. 6 to 8 using the pulse width of an input current. [Figure 12] 10 is a schematic graph illustrating the relationship between a change in the pulse width of an input current and a change in Hall resistance when the input current is a first directional input current. [Figure 13] 10 is a schematic graph illustrating the relationship between a change in the pulse width of an input current and a change in Hall resistance when the input current is a second directional input current. [Figure 14] FIG. 9 is a conceptual diagram illustrating a method for controlling the magnetization directions of the first to third magnetic domains generated by the methods of FIGS. 6 to 8 by varying the amplitude of an input current. [Figure 15] 10 is a schematic graph illustrating an example of the relationship between the amplitude of an input current and the change in Hall resistance when the pulse width of the input current is fixed. [Figure 16] 10 is a schematic graph illustrating another example of the relationship between the variable amplitude of the input current and the change in Hall resistance when the pulse width of the input current is fixed. [Figure 17] 2 is a flowchart illustrating a method for fabricating a ferromagnetic memory device having the magnetic anisotropy energy gradient shown in FIG. 1 and a method for using an input current to control the movement of each of the magnetic domains or magnetization states contained in the ferromagnetic memory device. [Figure 18] 2 is a schematic diagram of a process-in-memory including a ferromagnetic memory device with magnetic anisotropy energy gradient shown in FIG. 1. DETAILED DESCRIPTION OF THE INVENTION

[0018] Hereinafter, specific examples of embodiments of the present invention will be described in detail with reference to the drawings.

[0019] FIG. 1 is a schematic diagram of a semiconductor system including a ferromagnetic memory device having memory cells including magnetic layers with a magnetic anisotropy energy gradient according to one embodiment of the present invention, and FIG. 2 is a schematic diagram of the ferromagnetic memory device shown in FIG. 1 cut in the AA direction.

[0020] 1 includes a ferromagnetic memory device 110 and an input current control circuit 130. The semiconductor system 100 refers to a semiconductor device, a semiconductor integrated circuit, a system on chip (SoC), a process-in-memory (PIM), a computing-in-memory (CIM), a processor, or the like.

[0021] The ferromagnetic memory device 110 according to this embodiment is a device that stores two or more bits of data using the properties of a ferromagnetic material. The ferromagnetic memory device 110 has a magnetic anisotropy energy gradient formed inside the memory cell (MC) by reducing each of a plurality of regions (RG1, RG2, and RG3) included in the magnetic layer (hereinafter referred to as the first magnetic layer 103c') of the memory cell (MC) shown in Figure 5A through plasma ion irradiation.

[0022] For example, the first magnetic layer 103c' includes a magnetic material, and the magnetic material includes at least one of a ferromagnetic material, a paramagnetic material, and an antiferromagnetic material. According to this embodiment, the magnetic material included in the first magnetic layer 103c' includes, but is not limited to, (i) a paramagnetic material, or (ii) both a paramagnetic material and a ferromagnetic material.

[0023] Ions accelerated at different acceleration voltages are irradiated or injected into each of the memory cells (MC), for example, regions (RG1, RG2, and RG3), at different times, resulting in different magnetic anisotropy energies of the memory cells (MC), which in turn results in the formation of a magnetic anisotropy energy gradient within the memory cells (MC), and the formation of the magnetic anisotropy energy gradient generates magnetic domains.

[0024] Referring to Figures 1 and 2, a ferromagnetic memory device 110 includes a memory cell (MC) including an electric conductive layer 111 that includes current electrodes (EL1 and EL2) and supplies an input current or input voltage, and a magnetic free layer 115.

[0025] The electrically conductive layer 111 is a layer of good electrical conductor including at least one of palladium (Pd), tantalum (Ta), gold (Au), copper (Cu), and aluminum (Al), and for example, the magnetic free layer 115 includes at least one of palladium (Pd), tantalum (Ta), gold (Au), copper (Cu), and aluminum (Al), but is not limited to these.

[0026] The magnetic free layer 115 includes a plurality of magnetic domains (MD1, MD2, and MD3) formed by a magnetic anisotropy energy gradient or a plurality of patterns (magnetic domains (MD1, MD2, and MD3)) having different magnetization states. For example, each of the magnetic domains (MD1, MD2, and MD3) formed in a magnetic layer (hereinafter referred to as the second magnetic layer 103c) included in the magnetic free layer 115 represents a ferromagnetic region (or ferromagnetic material). For example, reference numeral 113 in the drawing indicates a portion etched by an etching process, and the etched portion is filled with a material, for example, an insulating material. The magnetic free layer 115 is the same as or includes the second magnetic layer 103c.

[0027] Magnetic anisotropy energy gradient is a concept in which the magnitude of energy changes along the magnetization direction in a magnetic material, and the change in magnitude appears along a physical direction. In magnetic materials, magnetic anisotropy refers to the phenomenon in which the properties of a material change along the magnetization direction, and magnetic anisotropy energy describes how magnetic energy changes along the magnetization direction.

[0028] 2, a memory cell (MC) including a magnetic free layer 115 includes a tantalum (Ta) layer 101a, a palladium (Pd) layer 101b formed on the tantalum layer 101a, and a second magnetic layer 103c including a plurality of magnetic domains (MD1, MD2, and MD3) formed on the palladium (Pd) layer 101b. According to one embodiment, the positions of the tantalum (Ta) layer 101a and the palladium (Pd) layer 101b are interchangeable.

[0029] For example, the palladium (Pd) layer 101b inside the memory cell (MC) absorbs and stores hydrogen (or hydrogen ions) generated from each of the multiple magnetic domains (MD1, MD2, and MD3) formed by irradiation with hydrogen ions.

[0030] The second magnetic layer 103c included in the magnetic free layer 115 includes ferromagnetic regions (first to third magnetic domains (MD1, MD2, and MD3)) associated with the magnetic anisotropy energy gradient.

[0031] For example, the second magnetic layer 103c includes a magnetic material, and the magnetic material includes at least one of a ferromagnetic material, a paramagnetic material, and an antiferromagnetic material. According to this embodiment, the magnetic material included in the second magnetic layer 103c includes, but is not limited to, (i) a paramagnetic material, or (ii) both a paramagnetic material and a ferromagnetic material.

[0032] The plurality of magnetic domains (MD1, MD2, and MD3) generated by the formation of the magnetic anisotropy energy gradient will be described in detail with reference to FIGS.

[0033] In Figures 1 and 3, in order to explain that multiple magnetic domains (MD1, MD2, and MD3) are formed within the memory cell (MC) due to the formation of a magnetic anisotropy energy gradient, the multiple magnetic domains (MD1, MD2, and MD3) formed within the ferromagnetic memory device 110 are also illustrated in a plan view of the memory cell (MC) of the ferromagnetic memory device 110.

[0034] Referring to FIG. 2, the thickness of the tantalum layer 101a inside the memory cell (MC) is 4 nm, the thickness of the palladium layer 101b is 3 nm, and the thickness of the second magnetic layer 103c in which multiple magnetic domains (MD1, MD2, and MD3) are formed is 0.7 nm, but is not limited to these.

[0035] The input current control circuit 130 generates an input current (also referred to as an "input pulse current") Ix whose characteristics change in response to a current control signal (CTL), and transmits it to the current electrode (EL1 or EL2).

[0036] Here, the above characteristics include the number of pulses (or the number of togglings) contained in the input current (Ix) described with reference to FIG. 9, the pulse width of the input current (Ix) described with reference to FIG. 11, or the amplitude of the input current (Ix) described with reference to FIG. 14.

[0037] 1 and 2, the input current control circuit 130 controls the direction of the input current (Ix) using the current control signal (CTL). As illustrated in Fig. 1 and Fig. 2, the input current (Ix) flowing from the first current electrode (EL1) to the second current electrode (EL2) is referred to as the first directional input current (Ix_CD1), and the input current (Ix) flowing from the second current electrode (EL2) to the first current electrode (EL1) is referred to as the second directional input current (Ix_CD2).

[0038] 2, each current electrode (EL1, EL2) is formed of a conductive metal such as titanium (Ti), gold (Au), copper, or aluminum, and is deposited to measure a current flowing through the ferromagnetic memory device 110 or to supply a current to the ferromagnetic memory device 110. In this case, physical vapor deposition (PVD) or chemical vapor deposition (CVD) is used as a deposition method.

[0039] A first directional input current (Ix_CD1) input to the first current electrode (EL1) or a second directional input current (Ix_CD2) input to the second current electrode (EL2) flows through the electrical conduction layer 111 as shown in FIG. 2 to form a current path.

[0040] FIG. 3 is an enlarged view of a memory cell of the ferromagnetic memory device shown in FIG.

[0041] 1 to 3, the second magnetic layer 103c of the memory cell (MC) includes n magnetic domains (MD1, MD2, and MD3) formed by forming a magnetic anisotropy energy gradient, where n is a natural number of 1 or more.

[0042] For convenience of explanation, the present specification will be described with an example in which n is 3, but in order to realize multilevels, one or more magnetic domains may be formed by a magnetic anisotropy energy gradient formed in the second magnetic layer 103c or a magnetization state formed by non-uniform chemical states and physical defects such as vacancies.

[0043] FIG. 4 is a schematic diagram of various magnetic hysteresis loops showing the magnitude of magnetization versus magnetic field strength of a ferromagnetic material formed under various conditions, and FIG. 5 is an enlarged view of the memory cell shown in FIG. 1 at a stage before a magnetic anisotropy energy gradient is formed in the memory cell, and a schematic diagram of the memory cell cut in the BB direction.

[0044] 4, the x-axis represents the strength of a magnetic field (e.g., an external magnetic field) in Oersted (Oe), and the y-axis represents the size of magnetization (Mz) or the magnitude of magnetization (Mz).

[0045] "HL1" ​​shown in Figure 4 is a magnetic hysteresis loop showing the magnitude of magnetization (Mz) versus the strength of the magnetic field (Hz) at a stage before the first magnetic layer 103c' including the multiple regions (RG1, RG2, and RG3) shown in Figure 5(B) is converted into the second magnetic layer 103c including the magnetic domains (MD1, MD2, and MD3) shown in Figure 2 by irradiation with ions (e.g., hydrogen ions).

[0046] Figure 5(A) is a plan view of the memory cell (MC) at a stage before a magnetic anisotropy energy gradient is formed therein, and Figure 5(B) is a cross-sectional view of the memory cell (MC) of Figure 5(A) cut in the BB direction.

[0047] In Figure 5(A), to explain the stage before a magnetic anisotropy energy gradient is formed within the memory cell (MC), a plan view of the memory cell (MC) is shown together with multiple regions (RG1, RG2, and RG3).

[0048] Here, each region (RG1, RG2, and RG3) means a region of a memory cell (MC), means an internal region included in the first magnetic layer 103c', and means an internal region of the first magnetic layer 103c' that matches the surface region of the memory cell (MC).

[0049] 5A and 5B, the memory cell (MC) includes a non-magnetic first magnetic material layer 103c', such as a magnetic free layer including a cobalt oxide (Co3O4) layer (e.g., the first magnetic material layer 103c' including regions (RG1, RG2, and RG3)). As described above, the first magnetic material layer 103c' includes a mixture of paramagnetic and ferromagnetic materials, but is not limited thereto.

[0050] "HL2" shown in FIG. 4 is a magnetic hysteresis loop of the magnitude of magnetization (Mz) versus the strength (Hz) of the magnetic field when the first magnetic layer 103c' shown in FIG. 5B is a cobalt layer.

[0051] That is, "HL2" is a reference magnetic hysteresis loop for comparison with the other magnetic hysteresis loops (HL3 to HL6).

[0052] FIG. 6 is a schematic diagram illustrating a method of generating a first magnetic domain by irradiating ions accelerated by a first acceleration voltage onto a first region of the memory cell region shown in FIG. 5(A) through a first mask pattern.

[0053] Referring to Figures 4, 5, and 6, "HL3" shown in Figure 4 is a magnetic hysteresis loop showing the magnetization size (Mz) versus the magnetic field strength (Hz) when the first region (RG1) of the memory cell region (MC) (or the first magnetic layer 103c') is converted into the first magnetic domain (MD1) by irradiating the first region (RG1) of the memory cell region (MC) (or the first magnetic layer 103c') with first ions (200_IV1) accelerated at a first acceleration voltage (IV1, for example, 100V) through the first opening (OP1) of the first mask pattern (MASK1).

[0054] FIG. 7 is a schematic diagram illustrating a method of generating a second magnetic domain by irradiating ions accelerated by a second acceleration voltage onto the second region of the memory cell region shown in FIG. 5(A) through a second mask pattern.

[0055] Referring to Figures 4 and 7, "HL6" shown in Figure 4 is a magnetic hysteresis loop showing the magnitude of magnetization (Mz) versus the magnetic field strength (Hz) for the second region (RG2) when the second region (RG2) of the memory cell region (MC) (or the first magnetic layer 103c') is converted into a second magnetic domain (MD2) by irradiating the second region (RG2) with second ions (200_IV2) accelerated at a second acceleration voltage (IV2, for example, 500V) through the second opening (OP2) of the second mask pattern (MASK2) onto the second region (RG2).

[0056] FIG. 8 is a schematic diagram illustrating a method of generating a third magnetic domain by irradiating ions accelerated by a third acceleration voltage onto the third region of the memory cell region shown in FIG. 5(A) through a third mask pattern.

[0057] 4 and 8, "HL4" shown in FIG. 4 is a magnetic hysteresis loop showing the magnitude of magnetization (Mz) versus the magnetic field strength (Hz) for the third region (RG3) when the third region (RG3) of the memory cell region (MC, or first magnetic layer 103c') is converted into a third magnetic domain (MD3) by irradiating the third region (RG3) with third ions (200_IV3) accelerated at a third acceleration voltage (IV3, for example, 200V) through the third opening (OP3) of the third mask pattern (MASK3). In this case, the first to third ions (200_IV1, 200_IV2, and 200_IV3) are the same type of ions (for example, hydrogen ions).

[0058] Referring to Figures 4 to 8, "HL5" shown in Figure 4 is a magnetic hysteresis loop showing the magnetization size (Mz) versus magnetic field strength (Hz) when any one region (RG1, RG2, or RG3) of the memory cell region (MC) is converted into any one of the magnetic domains (MD1, MD2, or MD3) by irradiating any one region (RG1, RG2, or RG3) of the memory cell region (MC) with fourth ions accelerated at a fourth acceleration voltage (e.g., 300V) through the first opening (OP1) of the first mask pattern (MASK1), the second opening (OP2) of the second mask pattern (MASK2), or the third opening (OP3) of the third mask pattern (MASK3).

[0059] That is, each region (RG1, RG2, or RG3) is a region that is changed into each magnetic domain (MD1, MD2, or MD3) depending on the acceleration voltage of the irradiated ions.

[0060] Referring to each magnetic hysteresis loop (HL1 to HL6) in FIG. 4, when the acceleration energy (or acceleration voltage) of ions irradiated to each region (RG1, RG2, or RG3) is changed by an ion irradiation method, different magnetic properties and / or magnetic anisotropy energy gradients are induced in each magnetic domain (MD1, MD2, and MD3) corresponding to each region (RG1, RG2, or RG3), and thus a magnetic pattern can be embodied in each of the magnetic domains (MD1, MD2, and MD3).

[0061] For example, the magnetic anisotropy energy gradient is induced not only by the magnetization states of the magnetic domains (MD1, MD2, and MD3), but also by the magnetization states formed by chemical inhomogeneities and physical defects such as vacancies formed within the magnetic domains (MD1, MD2, and MD3) during ion irradiation.

[0062] The inhomogeneity of the chemical state occurs due to local differences in chemical concentration (or density) or composition within each magnetic domain (MD1, MD2, and MD3), and there is a risk that the inhomogeneity will occur as a result of ion irradiation, either by concentrating more of the compounds or specific substances that occur within each magnetic domain (MD1, MD2, and MD3) or by escaping due to defects.

[0063] Within each magnetic domain (MD1, MD2, and MD3), the magnetic properties of that region change as the concentration of a particular material increases or decreases, or as physical defects occur.

[0064] Furthermore, chemical inhomogeneities and physical defects strengthen or weaken the anisotropy within each magnetic domain (MD1, MD2, and MD3), causing the domain walls of each magnetic domain (MD1, MD2, and MD3) to move in stages rather than in a single stage. This stepwise movement corresponds to the phenomenon of a gradual change in Hall resistance, which will be described later with reference to FIGS. 10A and 10B.

[0065] For example, hydrogen ions collide with oxygen atoms or oxygen ions of the magnetic material contained in each region (RG1, RG2, or RG3), such as cobalt oxide, to convert each region (RG1, RG2, or RG3) into the respective magnetic domains (MD1, MD2, and MD3). Cobalt oxide is a Co oxide such as Co3O4 or CoO. x O 1-x It has various compositions in the form of, but becomes cobalt (Co) when reduced regardless of the composition.

[0066] For example, cobalt oxide (Co3O4) reacts with hydrogen ions (H + ) to form cobalt (Co). During the reduction process, oxygen is removed from cobalt oxide (Co3O4), changing its oxidation state, forming cobalt.

[0067] For example, cobalt oxide (Co3O4) is a compound in which cobalt is 2 + and 3 + When cobalt oxide (Co3O4) is reduced, the cobalt changes to its metallic state with an oxidation number of 0.

[0068] An example of the reduction reaction of cobalt oxide (Co3O4) is shown in Chemical Formula 1 below.

[0069] [ka]

[0070] When each region (RG1, RG2, or RG3) contains a paramagnetic material (e.g., cobalt oxide (Co3O4)), the hydrogen ions irradiated (or implanted) into each region (RG1, RG2, or RG3) reduce the paramagnetic material (e.g., cobalt oxide (Co3O4)) contained in each region (RG1, RG2, or RG3) using a mechanism such as that shown in Chemical Formula 1 above, thereby converting each region (RG1, RG2, or RG3) into each magnetic domain (MD1, MD2, and MD3), although the conversion method is not limited to Chemical Formula 1.

[0071] In another embodiment, when each region (RG1, RG2, or RG3) contains both a paramagnetic material (e.g., cobalt oxide (Co3O4)) and a ferromagnetic material, hydrogen ions irradiated (or injected) into each region (RG1, RG2, or RG3) reduce the paramagnetic material (e.g., cobalt oxide (Co3O4)) contained in each region (RG1, RG2, or RG3) using a mechanism such as that shown in Chemical Formula 1, thereby converting each region (RG1, RG2, or RG3) into each magnetic domain (MD1, MD2, and MD3), although the conversion method is not limited to Chemical Formula 1.

[0072] FIG. 9 is a conceptual diagram illustrating a method for controlling the magnetization direction of each of the first to third magnetic domains generated by the methods of FIGS. 6 to 8 by the number of times the input current is toggled.

[0073] 1 and 6 to 9, the input current control circuit 130 controls the number of pulses included in the first directional input current (Ix_CD1) or the second directional input current (Ix_CD2) in response to the current control signal (CTL). Hereinafter, for convenience of explanation, the first directional input current (Ix_CD1) or the second directional input current (Ix_CD2) will be collectively referred to as the input current (Ix).

[0074] Referring to (A) of Figure 9, when the input current control circuit 130 supplies an input current (Ix) having a low level (L) to the ferromagnetic memory device 110 in response to the current control signal (CTL), the magnetization directions of the magnetic domains (MD1, MD2, and MD3) are all the first magnetization direction (MTD1).

[0075] It is assumed that the memory cell (MC) of the ferromagnetic memory device 110 when the magnetization directions of the magnetic domains (MD1, MD2, and MD3) are all the first magnetization direction (MTD1) represents or stores the first level (

[00] ) of the multilevel data. Hereinafter, for convenience of explanation, it is assumed that the multilevel data includes four levels, and in a read operation, the first level (

[00] ) is defined or interpreted as 2b'00 of 2-bit data. Here, a level represents a method of expressing a signal, information, or data.

[0076] Referring to Figures 9(A) and 9(B), when the input current control circuit 130 supplies an input current (Ix) having one pulse or an input current (Ix) toggling once to the ferromagnetic memory device 110 in response to the current control signal (CTL), only the magnetization direction of the first magnetic domain (MD1) among the magnetic domains (MD1, MD2, and MD3) is converted from the first magnetization direction (MTD1) to the second magnetization direction (MTD2), and the magnetization directions of the remaining magnetic domains (MD2 and MD3) maintain the first magnetization direction (MTD1).

[0077] In this case, assuming that the memory cell (MC) of the ferromagnetic memory device 110 means or stores the second level (

[01] ) among the four levels, during a read operation, the second level (

[01] ) is defined or interpreted as 2b'01 among the two-bit data.

[0078] Referring to Figures 9(B) and 9(C), when the input current control circuit 130 supplies an input current (Ix) having two pulses or an input current (Ix) toggling twice to the ferromagnetic memory device 110 in response to the current control signal (CTL), only the magnetization direction of the second magnetic domain (MD2) among the magnetic domains (MD1, MD2, and MD3) is converted from the first magnetization direction (MTD1) to the second magnetization direction (MTD2), the magnetization direction of the first magnetic domain (MD1) remains the second magnetization direction (MTD2), and the magnetization direction of the third magnetic domain (MD3) remains the first magnetization direction (MTD1).

[0079] In this case, assuming that the memory cell (MC) of the ferromagnetic memory device 110 represents or stores the third level (

[10] ) among the four levels, during a read operation, the third level (

[10] ) is defined or interpreted as 2b'10 in the 2-bit data.

[0080] Referring to Figures 9(C) and 9(D), when the input current control circuit 130 supplies an input current (Ix) having three pulses or an input current (Ix) toggling three times to the ferromagnetic memory device 110 in response to the current control signal (CTL), only the magnetization direction of the third magnetic domain (MD3) among the magnetic domains (MD1, MD2, and MD3) is converted from the first magnetization direction (MTD1) to the second magnetization direction (MTD2), and the magnetization directions of the first magnetic domain (MD1) and the second magnetic domain (MD2) remain the second magnetization direction (MTD2).

[0081] In this case, assuming that the memory cell (MC) of the ferromagnetic memory device 110 means or stores the fourth level (

[11] ) among the four levels, during a read operation, the fourth level (

[11] ) is defined or interpreted as 2b'11 among the two-bit data.

[0082] Referring to (E) of Figure 9, the second level (

[01] ) is higher than the first level (

[00] ), the third level (

[10] ) is higher than the second level (

[01] ), and the fourth level (

[11] ) is higher than the third level (

[10] ).

[0083] FIG. 9 shows an embodiment in which the level increases as the number of pulses included in one of the first directional input current (Ix_CD1) and the second directional input current (Ix_CD2) increases, but in one embodiment, the level may decrease as the number of pulses included in the other of the first directional input current (Ix_CD1) and the second directional input current (Ix_CD2) increases.

[0084] In this embodiment, the magnetization directions of two magnetic domains (MD1 and MD2, MD2 and MD3, or MD1 and MD3) among the magnetic domains (MD1, MD2, and MD3) are simultaneously switched between a first magnetization direction (MTD1) and a second magnetization direction (MTD2) by changing the number of pulses contained in the input current (Ix).

[0085] In this embodiment, the magnetization directions of the magnetic domains (MD1, MD2, and MD3) are simultaneously switched between a first magnetization direction (MTD1) and a second magnetization direction (MTD2) by changing the number of pulses contained in the input current (Ix).

[0086] The number of pulses included in the variable input current (Ix) can be used to change the magnetization direction of any of the magnetic domains (MD1, MD2, and MD3) or to change the magnetization directions of several domains simultaneously, which can be varied in various ways depending on the embodiment.

[0087] FIG. 10A is a schematic graph of Hall resistance gradually changing with the number of toggling of the input pulse current shown in FIG.

[0088] Referring to Figures 9 and 10A, "HL" is a magnetic hysteresis loop showing the size of magnetization (Mz) versus the strength of the magnetic field (Hz), and "HL_NOP" is a schematic graph showing that the Hall resistance (RH) increases gradually or analogously as the number of pulses contained in an appropriate input current (Ix) increases.

[0089] This indicates that as the number of pulses contained in the appropriate input current (Ix) is changed, the magnetization (or magnetization state) does not change across magnetic domains (MD1, MD2, and MD3), but rather changes gradually or stepwise within each region (RG1, RG2, or RG3).

[0090] Such changes are due to the magnetic anisotropy energy gradient formed by the magnetization state affected not only by each magnetic domain (MD1, MD2, and MD3) but also by the chemical inhomogeneity and physical defects such as vacancies formed within the magnetic domains (MD1, MD2, and MD3) during ion irradiation.

[0091] As shown in Figure 10A, a number of different magnetization states corresponding to the analog signal are induced. That is, the number of magnetic domains and the number of magnetization states are different. The points shown in Figure 10A are only examples of the illustrated magnetization states for convenience of explanation.

[0092] 'HL_UP' is the part of the magnetic hysteresis loop (HL) that changes depending on the first direction input current (Ix_CD1), and 'HL_DOWN' is the part of the magnetic hysteresis loop (HL) that changes depending on the second direction input current (Ix_CD2).

[0093] Therefore, by appropriately adjusting the input current (Ix) to the ferromagnetic memory device 110 according to the present invention, various fine multi-levels can be implemented in the ferromagnetic memory device 110 like an analog device.

[0094] FIG. 10B is a conceptual diagram illustrating the magnetization state that changes depending on the number of toggling of the input pulse current supplied to the ferromagnetic memory device shown in FIG.

[0095] Referring to FIGS. 10A and 10B, as the input pulse current (Ix) changes, magnetic domains move and multiple magnetization states are generated or determined in the memory cell (MC).

[0096] For example, the magnetization state is determined by the magnetization direction and the magnetization magnitude.

[0097] The magnetization direction refers to the alignment direction of magnetic particles within an object. The magnetization direction is determined when the spins of magnetic atoms or molecules within a magnetized material are aligned in a specific direction. The magnitude of magnetization indicates the magnitude of the magnetic moment possessed by the magnetized material. The forward magnetic moment possessed by magnetic particles per unit volume within an object corresponds to the magnitude of magnetization.

[0098] In the present invention, the magnetization direction and magnitude are determined by the number of times the current pulse is toggled, the pulse width of the current pulse, or the amplitude of the current pulse.

[0099] 10B, for convenience of explanation regarding the magnetization state in each magnetic domain (MD1, MD2, and MD3), the magnetization state is represented by three magnetization directions for each magnetic domain (MD1, MD2, and MD3), but this is not limiting. Therefore, the magnetization state is represented by two or four or more magnetization directions for each magnetic domain (MD1, MD2, and MD3).

[0100] As the input pulse current (Ix) changes, for example, as the number of toggling cycles increases, the magnetic domains move and the magnetization state changes.

[0101] For example, as the number of times the input pulse current (Ix) toggles increases, the magnetization state of the first magnetic domain (MD1) changes sequentially from (A) in FIG. 10B to (D) in FIG. 10B, and as the number of times the input pulse current (Ix) toggles further increases, the magnetization state of the second magnetic domain (MD2) changes sequentially from (E) in FIG. 10B to (G) in FIG. 10B, and as the number of times the input pulse current (Ix) toggles further increases, the magnetization state of the third magnetic domain (MD3) changes sequentially from (H) in FIG. 10B to (J) in FIG. 10B.

[0102] For example, each of the magnetization states of (A) in FIG. 10B to (J) in FIG. 10B corresponds to a corresponding level (or a level that is one-to-one mapped) in the multilevel structure.

[0103] Also, the magnetization state of (A) in Figure 10B corresponds to 3b'000, the magnetization state of (B) in Figure 10B corresponds to 3b'001, the magnetization state of (C) in Figure 10B corresponds to 3b'010, the magnetization state of (D) in Figure 10B corresponds to 3b'011, the magnetization state of (E) in Figure 10B corresponds to 3b'100, the magnetization state of (F) in Figure 10B corresponds to 3b'101, the magnetization state of (G) in Figure 10B corresponds to 3b'110, and the magnetization state of (H) in Figure 10B corresponds to 3b'111, but these may be defined differently depending on the embodiment.

[0104] (A) of Figure 10B corresponds to (A) of Figure 9, (D) of Figure 10B corresponds to (B) of Figure 9, (G) of Figure 10B corresponds to (C) of Figure 9, and (J) of Figure 10B corresponds to (D) of Figure 9. To explain in more detail, (A) of Figure 9 conceptually shows the magnitude of the forward magnetization of (A) of Figure 10B, (B) of Figure 9 conceptually shows the magnitude of the forward magnetization of (D) of Figure 10B, (C) of Figure 9 conceptually shows the magnitude of the forward magnetization of (G) of Figure 10B, and (D) of Figure 9 conceptually shows the magnitude of the forward magnetization of (J) of Figure 10B.

[0105] From the viewpoint of the first magnetic domain (MD1), the magnitude of the forward magnetization in (A) of Figure 10B is larger than that in (B) of Figure 10B, and the magnetization direction in (B) of Figure 10B is opposite to that in (C) of Figure 10B, and the magnitude of the magnetization in (B) of Figure 10B is the same as that in (C) of Figure 10B.

[0106] The concept shown in FIG. 10B can also be applied as it is to a method of controlling the magnetization state by changing the pulse width of the input pulse current (Ix), which will be described with reference to FIG. 11, and a method of controlling the magnetization state by changing the pulse amplitude of the input pulse current (Ix), which will be described with reference to FIG. 14.

[0107] FIG. 11 is a conceptual diagram illustrating a method for controlling the magnetization direction of each of the first to third magnetic domains generated by the methods of FIGS. 6 to 8 using the pulse width of the input current.

[0108] 1, 6, 7, 8, and 11, the input current control circuit 130 controls the pulse width (width) included in the first directional input current (Ix_CD1) or the second directional input current (Ix_CD2) in response to the current control signal (CTL). For convenience of explanation, the first directional input current (Ix_CD1) or the second directional input current (Ix_CD2) will be collectively referred to as the input current (Ix) hereinafter.

[0109] 11A, when the input current control circuit 130 supplies an input current (Ix) having a low level (L) to the ferromagnetic memory device 110 in response to the current control signal (CTL), the magnetization directions of the magnetic domains (MD1, MD2, and MD3) are all the first magnetization direction (MTD1). Assuming that the multi-level memory device 110 includes four levels as described with reference to FIG. 9, during a read operation, the first level (

[00] ) is defined or interpreted as 2b'00 in the two-bit data.

[0110] 11A and 11B, when the input current control circuit 130 supplies an input current (Ix) having a first pulse width (W1) to the ferromagnetic memory device 110 in response to the current control signal (CTL), the magnetization direction of only the first magnetic domain (MD1) among the magnetic domains (MD1, MD2, and MD3) is converted from the first magnetization direction (MTD1) to the second magnetization direction (MTD2), and the magnetization directions of the remaining magnetic domains (MD2 and MD3) remain the first magnetization direction (MTD1). As described with reference to FIG. 9, during a read operation, the second level (

[01] ) is defined or interpreted as 2b'01 in the 2-bit data.

[0111] 11B and 11C, when the input current control circuit 130 supplies the input current (Ix) having a second pulse width (W2) to the ferromagnetic memory device 110 in response to the current control signal (CTL), the magnetization direction of only the second magnetic domain (MD2) among the magnetic domains (MD1, MD2, and MD3) is changed from the first magnetization direction (MTD1) to the second magnetization direction (MTD2), the magnetization direction of the first magnetic domain (MD1) remains the second magnetization direction (MTD2), and the magnetization direction of the third magnetic domain (MD3) remains the first magnetization direction (MTD1). In this case, the second pulse width (W2) is greater than the first pulse width (W1).

[0112] As described with reference to FIG. 9, during a read operation, the third level (

[10] ) is defined or interpreted as 2b'10 in the 2-bit data.

[0113] 11(C) and 11(D), when the input current control circuit 130 supplies the input current (Ix) having a third pulse width (W3) to the ferromagnetic memory device 110 in response to the current control signal (CTL), the magnetization direction of only the third magnetic domain (MD3) among the magnetic domains (MD1, MD2, and MD3) is changed from the first magnetization direction (MTD1) to the second magnetization direction (MTD2), and the magnetization directions of the first magnetic domain (MD1) and the second magnetic domain (MD2) remain the second magnetization direction (MTD2). In this case, the third pulse width (W3) is greater than the second pulse width (W2).

[0114] As described with reference to FIG. 9, during a read operation, the fourth level (

[11] ) is defined or interpreted as 2b'11 in the 2-bit data.

[0115] Referring to (E) of Figure 11, the second level (

[01] ) is higher than the first level (

[00] ), the third level (

[10] ) is higher than the second level (

[01] ), and the fourth level (

[11] ) is higher than the third level (

[10] ).

[0116] FIG. 11 shows an embodiment in which the level increases as the pulse width of one of the first directional input current (Ix_CD1) and the second directional input current (Ix_CD2) increases, but depending on the embodiment, the level may decrease as the pulse width of the other of the first directional input current (Ix_CD1) and the second directional input current (Ix_CD2) increases.

[0117] In this embodiment, the magnetization directions of two magnetic domains (MD1 and MD2, MD2 and MD3, or MD1 and MD3) among the magnetic domains (MD1, MD2, and MD3) are simultaneously switched between a first magnetization direction (MTD1) and a second magnetization direction (MTD2) by changing the pulse width contained in the input current (Ix).

[0118] In this embodiment, the magnetization directions of the magnetic domains (MD1, MD2, and MD3) are simultaneously switched between a first magnetization direction (MTD1) and a second magnetization direction (MTD2) by changing the pulse width contained in the input current (Ix).

[0119] The pulse width of the variable input current (Ix) can be varied to change the magnetization direction of any of the magnetic domains (MD1, MD2, and MD3) or to change the magnetization direction of several domains simultaneously, depending on the embodiment.

[0120] FIG. 12 is a schematic graph illustrating the relationship between the change in pulse width of the input current and the change in Hall resistance when the input current is a first directional input current, and FIG. 13 is a schematic graph illustrating the relationship between the change in pulse width of the input current and the change in Hall resistance when the input current is a second directional input current.

[0121] Referring to FIG. 1 and FIGS. 10 to 13, “HL_UP” in FIG. 12 indicates that the Hall resistance (R H) increases as the pulse width of the second direction input current (Ix=Ix_CD2) increases. H 1 is a schematic graph showing that the

[0122] FIG. 14 is a conceptual diagram illustrating a method for controlling the magnetization direction of each of the first to third magnetic domains generated by the methods of FIGS. 6 to 8 by varying the amplitude of the input current.

[0123] 1, 6, 7, 8, and 14, the input current control circuit 130 controls the amplitude of pulses included in the first directional input current (Ix_CD1) or the second directional input current (Ix_CD2) in response to the current control signal (CTL). Hereinafter, for convenience of explanation, the first directional input current (Ix_CD1) or the second directional input current (Ix_CD2) will be collectively referred to as the input current (Ix).

[0124] 14A, when the input current control circuit 130 supplies an input current (Ix) having a low level (L) to the ferromagnetic memory device 110 in response to the current control signal (CTL), the magnetization directions of the magnetic domains (MD1, MD2, and MD3) are all the first magnetization direction (MTD1). Assuming that the multi-level memory device 110 includes four levels as described with reference to FIG. 9, during a read operation, the first level (

[00] ) is defined or interpreted as 2b'00 in the two-bit data.

[0125] 14A and 14B, when the input current control circuit 130 supplies an input current (Ix) having a first amplitude (AT1) to the ferromagnetic memory device 110 in response to the current control signal (CTL), the magnetization direction of only the first magnetic domain (MD1) among the magnetic domains (MD1, MD2, and MD3) is converted from the first magnetization direction (MTD1) to the second magnetization direction (MTD2), and the magnetization directions of the remaining magnetic domains (MD2 and MD3) remain the first magnetization direction (MTD1). As described with reference to FIG. 9, during a read operation, the second level (

[01] ) is defined or interpreted as 2b'01 in the 2-bit data.

[0126] 14B and 14C, when the input current control circuit 130 supplies an input current (Ix) having a second amplitude (AT2) to the ferromagnetic memory device 110 in response to the current control signal (CTL), the magnetization direction of only the second magnetic domain (MD2) among the magnetic domains (MD1, MD2, and MD3) is changed from the first magnetization direction (MTD1) to the second magnetization direction (MTD2), the magnetization direction of the first magnetic domain (MD1) remains the second magnetization direction (MTD2), and the magnetization direction of the third magnetic domain (MD3) remains the first magnetization direction (MTD1). In this case, the second amplitude (AT2) is greater than the first amplitude (AT1).

[0127] As described with reference to FIG. 9, during a read operation, the third level (

[10] ) is defined or interpreted as 2b'10 in the 2-bit data.

[0128] 14(C) and 14(D), when the input current control circuit 130 supplies an input current (Ix) having a third amplitude (AT3) to the ferromagnetic memory device 110 in response to the current control signal (CTL), the magnetization direction of only the third magnetic domain (MD3) among the magnetic domains (MD1, MD2, and MD3) is converted from the first magnetization direction (MTD1) to the second magnetization direction (MTD2), and the magnetization directions of the first magnetic domain (MD1) and the second magnetic domain (MD2) remain the second magnetization direction (MTD2). In this case, the third amplitude (AT3) is greater than the second amplitude (AT2).

[0129] As described with reference to FIG. 9, during a read operation, the fourth level (

[11] ) is defined or interpreted as 2b'11 in the 2-bit data.

[0130] Referring to (E) of Figure 14, the second level (

[01] ) is higher than the first level (

[00] ), the third level (

[10] ) is higher than the second level (

[01] ), and the fourth level (

[11] ) is higher than the third level (

[10] ).

[0131] FIG. 14 shows an embodiment in which the level increases as the amplitude of one of the first directional input current (Ix_CD1) and the second directional input current (Ix_CD2) increases, but depending on the embodiment, the level may decrease as the amplitude of the other of the first directional input current (Ix_CD1) and the second directional input current (Ix_CD2) increases.

[0132] In this embodiment, the magnetization directions of two magnetic domains (MD1 and MD2, MD2 and MD3, or MD1 and MD3) among the magnetic domains (MD1, MD2, and MD3) are simultaneously switched between a first magnetization direction (MTD1) and a second magnetization direction (MTD2) by changing the amplitude of the input current (Ix).

[0133] In this embodiment, the magnetization directions of the magnetic domains (MD1, MD2, and MD3) are simultaneously switched between a first magnetization direction (MTD1) and a second magnetization direction (MTD2) by changing the amplitude of the input current (Ix).

[0134] The amplitude of the variable input current (Ix) can be varied to change the magnetization direction of any of the magnetic domains (MD1, MD2, and MD3) or to change the magnetization direction of several domains simultaneously, depending on the embodiment.

[0135] FIG. 15 is a schematic graph illustrating an example of the relationship between the variable amplitude of the input current and the change in Hall resistance when the pulse width of the input current is fixed, and FIG. 16 is a schematic graph illustrating another example of the relationship between the variable amplitude of the input current and the change in Hall resistance when the pulse width of the input current is fixed.

[0136] 10, 14, 15, and 16, "HL_DOWN" in FIG. 15 indicates that the Hall resistance (R H 1 is a schematic graph showing that the

[0137] "HL_UP" in FIG. 16 indicates that the Hall resistance (R H 1 is a schematic graph showing that the

[0138] The graphs shown in Figures 10, 12, 13, 15, and 16 are schematic graphs illustrating that multi-levels are realized without changing the shape of the memory cell (MC) as a result of a change in the Hall resistance of the second magnetic layer 103c of the memory cell (MC) due to the magnetic anisotropy energy gradient formed by the magnetic domains (MD1, MD2, and MD3).

[0139] FIG. 17 is a flowchart illustrating a method for fabricating a ferromagnetic memory device having the magnetic anisotropy energy gradient shown in FIG. 1 and a method for using an input current to control the motion of each of the magnetic domains or magnetization states contained in the ferromagnetic memory device.

[0140] Referring to Figure 5 (B) and Figure 17, a memory device is manufactured or formed having memory cells (MC) formed in the magnetic free layer and including regions (RG1, RG2, and RG3) that correspond one-to-one to each magnetic domain (MD1, MD2, and MD3) (step S110).

[0141] Referring to Figures 5(B), 6, and 17, when the first ions (200_IV1) accelerated by the first acceleration voltage are irradiated onto the first region (RG1) through the first opening (OP1) of the first mask pattern (MASK1), the first region (RG1) is changed into a first magnetic domain (MD1), and a magnetic anisotropy energy gradient is formed in the memory cell (MC) including the first magnetic domain (MD1) (step S120).

[0142] Referring to Figures 5(B), 7, and 17, when the second ions (200_IV2) accelerated by the second acceleration voltage are irradiated onto the second region (RG2) through the second opening (OP2) of the second mask pattern (MASK2), the second region (RG2) is changed into a second magnetic domain (MD2), and a magnetic anisotropy energy gradient is formed in the memory cell (MC) including the magnetic domains (MD1 and MD2) (step S130).

[0143] Referring to Figures 5(B), 8, and 17, when the third ions (200_IV3) accelerated by the third acceleration voltage are irradiated onto the third region (RG3) through the third opening (OP3) of the third mask pattern (MASK3), the third region (RG3) is changed into a third magnetic domain (MD3), and a magnetic anisotropy energy gradient is formed in the memory cell (MC) including the magnetic domains (MD1, MD2, and MD3) (step S140).

[0144] After the ferromagnetic memory device 110 having the second magnetic layer 103c including magnetic domains (MD1, MD2, and MD3) corresponding to the magnetic anisotropy energy gradient is manufactured through steps S110 to S140, in order to embody or define multi-levels, the input current control circuit 130 controls the number of pulses of the input current (Ix), the pulse width of the input current (Ix), or the amplitude of the input current (Ix) in response to the control signal (CTL), as described with reference to Figure 9, Figure 11, or Figure 14, to control the magnetization state of each of the magnetic domains (MD1, MD2, and MD3) (step S150).

[0145] The magnetization state of each of the magnetic domains (MD1, MD2, and MD3) defines a corresponding level in the multilevel structure.

[0146] FIG. 18 is a schematic diagram of a process-in-memory including a ferromagnetic memory device with magnetic anisotropy energy gradient shown in FIG.

[0147] 1 and 18, the process-in-memory 200 includes a processor 210 and a memory device 220. The processor 210 is a central processing unit (CPU), a graphics processing unit (GPU), or a neural processing unit (NPU), and the memory device 220 includes a memory cell array 222 and an arithmetic unit (also referred to as an "arithmetic unit circuit") 224.

[0148] The process-in-memory 200 is used in autonomous vehicles, Internet of Things (IoT), health informatics, or systems-on-chips (SoCs).

[0149] The ferromagnetic memory device 110 is used in a domain wall-based magnetic memory.

[0150] The memory cell array 222 includes a plurality of multi-level ferromagnetic memory devices 110, and the arithmetic unit 224 performs an operation using data stored in the memory cell array 222 within the memory device 220 based on an instruction output from the processor 210, and simply transmits the result to the processor 210. This improves the arithmetic performance of the process-in-memory 200 and reduces power consumption.

[0151] The ferromagnetic memory device 110 according to the present invention, which can define or store any one of multiple levels, is different from conventional STT-MRAM, which can define or store only single-bit data, and is used in process-in-memory 200 or computing-in-memory for artificial intelligence (AI) or intelligent semiconductors for deep learning, etc.

[0152] Although the embodiments of the present invention have been described in detail above with reference to the drawings, the present invention is not limited to the above-described embodiments and can be modified in various ways without departing from the technical concept of the present invention. [Explanation of symbols]

[0153] 100 Semiconductor Systems 101a Tantalum (Ta) layer 101b Palladium (Pd) layer 103c Second magnetic layer 103c' First magnetic layer 110 Ferromagnetic memory device 111 Electrically Conductive Layer 115 Magnetic free layer 130 Input current control circuit 200 Process In Memory 200_IV1, 200_IV2, 200_IV3 1st to 3rd ions 210 processor 220 Memory Device 222 memory cell array 224 arithmetic units AT1~AT3 1st~3rd amplitude CTL Current control signal EL1, EL2 1st, 2nd current electrode HL magnetic hysteresis loop Ix Input current (input pulse current) Ix_CD1, Ix_CD2 1st and 2nd direction input current MASK1~MASK3 1st~3rd mask patterns MC memory cell MD1~MD3 1st~3rd magnetic domains MTD1, MTD2 1st and 2nd magnetization direction OP1~OP3 1st~3rd opening RG1~RG3 1st~3rd area W1~W3 1st~3rd pulse width

Claims

1. 1. A ferromagnetic memory device comprising memory cells, the memory cell includes a magnetic free layer including a magnetic layer; The ferromagnetic memory device, wherein the magnetic free layer includes a magnetic anisotropy energy gradient induced inside the magnetic layer by plasma ion irradiation.

2. the magnetic layer includes a plurality of magnetic domains formed by the magnetic anisotropy energy gradient induced by the plasma ion irradiation, 2. The ferromagnetic memory device of claim 1, wherein the magnetic anisotropy energy gradient is induced by the magnetization states of each of the plurality of magnetic domains and the magnetization states formed by chemical inhomogeneities and physical defects formed within each of the plurality of magnetic domains during the plasma ion irradiation.

3. 3. The ferromagnetic memory device according to claim 2, wherein each of the plurality of magnetic domains is formed by implanting ions accelerated by each of a plurality of different acceleration voltages in the plasma ion irradiation.

4. A semiconductor device including a ferromagnetic memory device, the ferromagnetic memory device includes a memory cell including a plurality of magnetic domains generated in a magnetic free layer; A semiconductor device characterized in that a magnetic anisotropy energy gradient is induced in the magnetic free layer by injecting ions into the magnetic free layer, and the plurality of magnetic domains are formed by the induced magnetic anisotropy energy gradient.

5. a first magnetic domain among the plurality of magnetic domains is generated by injecting first ions accelerated by a first acceleration voltage into a first region among a plurality of regions included in the magnetic free layer; a second magnetic domain among the plurality of magnetic domains is generated by injecting second ions accelerated by a second acceleration voltage into a second region among the plurality of regions included in the magnetic free layer; 5. The semiconductor device of claim 4, wherein the magnetic anisotropy energy gradient is induced by the magnetic anisotropy energy formed in the first region by the first ions and the anisotropy energy formed in the second region by the second ions being mutually interchangeable.

6. the first region includes a first cobalt oxide; the second region includes cobalt dioxide; the first magnetic domain includes cobalt reduced from the first cobalt oxide by the first accelerating voltage; 6. The semiconductor device according to claim 5, wherein the second magnetic domain contains cobalt reduced from the second cobalt oxide by the second acceleration voltage.

7. 5. The semiconductor device according to claim 4, further comprising a current control circuit that supplies current pulses to the ferromagnetic memory device to induce a number of different magnetization states greater than the number of the plurality of magnetic domains.

8. The magnetization state is a magnetization state of each of the plurality of magnetic domains; 8. The semiconductor device according to claim 7, further comprising: a magnetization state formed by inhomogeneity of chemical states and physical defects within the plurality of magnetic domains.

9. 8. The semiconductor device according to claim 7, wherein the magnetization states define corresponding levels from among multiple levels including different levels.

10. 8. The semiconductor device according to claim 7, wherein each of the magnetization states is determined by the direction of the current pulse, the number of times the current pulse toggles, the pulse width of the current pulse, or the amplitude of the current pulse.

11. 5. The semiconductor device according to claim 4, wherein the semiconductor device is a process-in-memory or a computing-in-memory.

12. 1. A method of manufacturing a ferromagnetic memory device, comprising: providing a memory device having memory cells including a magnetic free layer having a magnetic layer; forming a magnetic anisotropy energy gradient within the memory cell.

13. 13. The method of claim 12, wherein forming the magnetic anisotropy energy gradient comprises implanting ions into the memory cell to form the magnetic anisotropy energy gradient.

14. 13. The method of claim 12, wherein forming the magnetic anisotropy energy gradient comprises injecting ions accelerated at an acceleration voltage corresponding to each of the regions included in the magnetic layer using different mask patterns at different times into each of the regions, thereby generating each of the ferromagnetic regions in the magnetic layer such that the magnetic layer has the magnetic anisotropy energy gradient.

15. each of the regions comprises cobalt oxide; each of the ferromagnetic regions contains cobalt reduced from the cobalt oxide by the ions; The method of claim 14, wherein the magnetic anisotropy energy of each of the ferromagnetic regions is formed differently by implanting ions accelerated at the corresponding acceleration voltage into each of the regions included in the magnetic layer.

16. A ferromagnetic memory device manufactured by the method of manufacturing a ferromagnetic memory device according to claim 12; an input current control circuit for supplying a current pulse to the ferromagnetic memory device to gradually change the magnetization state of the memory cell.

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