Scan driver, display device, and electronic device

Abstract

To provide a highly reliable scan driver.SOLUTION: The scan driver includes a plurality of stages. At least one stage of the plurality of stages includes a logic circuit configured to control a voltage of a first node and a voltage of a second node based on an input signal, a first clock signal, and a second clock signal in a sequential driving period, an output circuit configured to receive the first clock signal and a simultaneous driving signal and to output a scan signal in response to the voltage of the first node and the voltage of the second node, and a simultaneous driving circuit configured to control the voltage of the first node and the voltage of the second node in response to an inverted simultaneous driving signal such that the output circuit outputs the simultaneous driving signal as the scan signal in a simultaneous driving period.SELECTED DRAWING: Figure 4

Description

[Technical Field]

[0001] The present invention relates to a display device, and more particularly to a scan driver, a display device, and an electronic device. [Background technology]

[0002] A scan driver of a display device sequentially provides scan signals to a plurality of pixels of a display panel in a row-by-row manner. To provide the scan signals sequentially in a row-by-row manner, the scan driver is implemented in the form of a shift register including a plurality of stages.

[0003] When the pixel of the display device includes an NMOS (N-type Metal-Oxide-Semiconductor) transistor, the scan driver is implemented to generate an active-high scan signal to turn on the NMOS transistor of the pixel. However, when the scan driver includes an NMOS transistor, leakage current occurs due to the NMOS transistor, which may cause the scan driver to malfunction. Summary of the Invention [Problem to be solved by the invention]

[0004] An object of the present invention is to provide a highly reliable scan driver.

[0005] Another object of the present invention is to provide a display device including the above scan driver.

[0006] However, the object of the present invention is not limited to the above-mentioned problems, and can be expanded in various ways without departing from the spirit and scope of the present invention. [Means for solving the problem]

[0007] A driver according to one embodiment of the present invention is a scan driver including a plurality of stages, wherein at least one of the plurality of stages includes: a logic circuit that controls the voltage of a first node and the voltage of a second node based on an input signal, a first clock signal, and a second clock signal during a sequential drive period; an output circuit that receives the first clock signal and a simultaneous drive signal and outputs a scan signal in response to the voltage of the first node and the voltage of the second node; and a simultaneous drive circuit that controls the voltage of the first node and the voltage of the second node in response to an inverted simultaneous drive signal so that the output circuit outputs the simultaneous drive signal as the scan signal during a simultaneous drive period.

[0008] The simultaneous drive signal may have a first low gate voltage in the sequential drive period and a high gate voltage in the simultaneous drive period, and the inverted simultaneous drive signal may have the high gate voltage in the sequential drive period and a second low gate voltage lower than the first low gate voltage in the simultaneous drive period.

[0009] The simultaneous drive signal may change from the high gate voltage to the first low gate voltage at the start of the sequential drive period, and the inverted simultaneous drive signal may change from the second low gate voltage to the high gate voltage after changing to the first low gate voltage of the simultaneous drive signal within the sequential drive period.

[0010] During the simultaneous drive period, the simultaneous drive circuit may apply a first low gate voltage to the first node and a high gate voltage to the second node in response to the inverted simultaneous drive signal, and the output circuit may output the simultaneous drive signal having the high gate voltage as the scan signal.

[0011] During the sequential driving period, when the first clock signal has a low level and the input signal has a high level, the logic circuit may control the voltage of the first node to the high level and the voltage of the second node to the low level, and the output circuit may output the first clock signal as the scan signal in response to the voltage of the first node having the high level and the voltage of the second node having the low level.

[0012] All transistors included in the at least one stage may be PMOS transistors.

[0013] The simultaneous drive circuit may include a first transistor including a gate that receives the inverted simultaneous drive signal, a first terminal that receives a first low gate voltage, and a second terminal connected to the first node.

[0014] The simultaneous drive circuit may further include a second transistor including a gate that receives the inverted simultaneous drive signal, a first terminal that receives a high gate voltage, and a second terminal connected to the second node.

[0015] The simultaneous drive circuit may further include a fourth capacitor having a first electrode connected to the second node and a second electrode receiving the simultaneous drive signal.

[0016] The output circuit may include a third transistor having a gate connected to the second node, a first terminal for receiving the first clock signal, and a second terminal connected to an output node from which the scan signal is output, and a fourth transistor having a gate connected to the first node, a first terminal connected to the output node, and a second terminal for receiving the simultaneous drive signal.

[0017] The logic circuit may include an input circuit that transmits the input signal to a third node in response to the first clock signal, a node isolation circuit connected between the third node and the first node, a boost circuit that boosts the voltage of the first node based on the second clock signal, and a node control circuit that controls the voltage of the second node based on the first clock signal, the second clock signal, the voltage of the first node, and the simultaneous drive signal.

[0018] The input circuit may include a fifth transistor including a gate that receives the first clock signal, a first terminal that receives the input signal, and a second terminal connected to the third node.

[0019] The node isolation circuit may include a sixth transistor having a gate that receives the simultaneous drive signal, a first terminal connected to the third node, and a second terminal connected to the first node.

[0020] The boost circuit may include a seventh transistor having a gate connected to the first node, a first terminal, and a second terminal for receiving the second clock signal, and a first capacitor having a first electrode connected to the first terminal of the seventh transistor and a second electrode connected to the first node.

[0021] The node control circuit includes an eighth transistor having a gate receiving the first clock signal, a first terminal receiving the simultaneous drive signal, and a second terminal connected to a fourth node; a ninth transistor having a gate connected to the first node, a first terminal receiving the first clock signal, and a second terminal connected to the fourth node; a tenth transistor having a gate receiving a first low gate voltage, a first terminal connected to the fourth node, and a second terminal connected to a fifth node; a second capacitor having a first electrode connected to the fifth node and a second electrode connected to a sixth node; a gate connected to the fifth node, a first terminal connected to the sixth node, and a second terminal connected to the sixth node; a 11th transistor including a gate connected to the fifth node, a first terminal connected to the second terminal of the 11th transistor, and a second terminal for receiving the second clock signal; a 13th transistor including a gate for receiving the second clock signal, a first terminal connected to the sixth node, and a second terminal connected to the second node; a third capacitor including a first electrode for receiving the first clock signal and a second electrode connected to the second node; and a 14th transistor including a gate connected to the first node, a first terminal for receiving the first clock signal, and a second terminal connected to the second node.

[0022] The at least one stage may further include a reset circuit that transmits the first clock signal to the first node in response to a reset signal and transmits the simultaneous drive signal to the second node in response to the reset signal.

[0023] The reset circuit may include a fifteenth transistor having a gate for receiving the reset signal, a first terminal for receiving the first clock signal, and a second terminal connected to a third node, and a sixteenth transistor having a gate for receiving the reset signal, a first terminal connected to the second node, and a second terminal for receiving the simultaneous drive signal.

[0024] A scan driver according to one embodiment of the present invention includes a plurality of stages, at least one of which includes: a logic circuit receiving an input signal, a first clock signal, a second clock signal, and a simultaneous drive signal and connected to a first node and a second node; a first transistor having a gate receiving an inverted simultaneous drive signal, a first terminal receiving a first low gate voltage, and a second terminal connected to the first node; a second transistor having a gate receiving the inverted simultaneous drive signal, a first terminal receiving a high gate voltage, and a second terminal connected to the second node; a third transistor having a gate connected to the second node, a first terminal receiving the first clock signal, and a second terminal connected to an output node at which a scan signal is output; and a fourth transistor having a gate connected to the first node, a first terminal connected to the output node, and a second terminal receiving the simultaneous drive signal.

[0025] the logic circuit includes a fifth transistor including a gate receiving the first clock signal, a first terminal receiving the input signal, and a second terminal connected to a third node; a sixth transistor including a gate receiving the simultaneous drive signal, a first terminal connected to the third node, and a second terminal connected to the first node; a seventh transistor including a gate connected to the first node, a first terminal, and a second terminal receiving the second clock signal; a first capacitor including a first electrode connected to the first terminal of the seventh transistor and a second electrode connected to the first node; an eighth transistor including a gate receiving the first clock signal, a first terminal receiving the simultaneous drive signal, and a second terminal connected to a fourth node; a ninth transistor including a gate connected to the first node, a first terminal receiving the first clock signal, and a second terminal connected to the fourth node; a tenth transistor including a first terminal connected to the fifth node and a second terminal connected to the fifth node; a second capacitor including a first electrode connected to the fifth node and a second electrode connected to a sixth node; an eleventh transistor including a gate connected to the fifth node, a first terminal connected to the sixth node, and a second terminal; a twelfth transistor including a gate connected to the fifth node, a first terminal connected to the second terminal of the eleventh transistor, and a second terminal for receiving the second clock signal; a thirteenth transistor including a gate for receiving the second clock signal, a first terminal connected to the sixth node, and a second terminal connected to the second node; a third capacitor including a first electrode for receiving the first clock signal and a second electrode connected to the second node; and a fourteenth transistor including a gate connected to the first node, a first terminal for receiving the first clock signal, and a second terminal connected to the second node.

[0026] A display device according to one embodiment of the present invention includes a display panel including a plurality of pixels, a data driver that provides data signals to the plurality of pixels, a scan driver including a plurality of stages that provides scan signals to the plurality of pixels, an emission driver that provides emission signals to the plurality of pixels, and a controller that controls the data driver, the scan driver, and the emission driver, wherein at least one of the plurality of stages includes: a logic circuit that controls a voltage of a first node and a voltage of a second node based on an input signal, a first clock signal, and a second clock signal in a sequential drive period; an output circuit that receives the first clock signal and a simultaneous drive signal and outputs a scan signal in response to the voltage of the first node and the voltage of the second node; and a simultaneous drive circuit that controls the voltage of the first node and the voltage of the second node in response to an inverted simultaneous drive signal so that the output circuit outputs the simultaneous drive signal as the scan signal in a simultaneous drive period.

[0027] An electronic device according to one embodiment of the present invention includes a processor that provides input image data, and a display device that receives the input image data from the processor and displays an image based on the input image data, the display device including a display panel having a plurality of pixels, a data driver that provides data signals to the plurality of pixels, a scan driver including a plurality of stages that provide scan signals to the plurality of pixels, an emission driver that provides emission signals to the plurality of pixels, and a controller that controls the data driver, the scan driver, and the emission driver, and at least one of the plurality of stages includes: a logic circuit that controls a voltage of a first node and a voltage of a second node based on an input signal, a first clock signal, and a second clock signal in a sequential drive period; an output circuit that receives the first clock signal and a simultaneous drive signal, and outputs a scan signal in response to the voltage of the first node and the voltage of the second node; and a simultaneous drive circuit that controls the voltage of the first node and the voltage of the second node in response to an inverted simultaneous drive signal, so that the output circuit outputs the simultaneous drive signal as the scan signal in a simultaneous drive period. [Effects of the Invention]

[0028] In a scan driver, a display device, and an electronic device according to an embodiment of the present invention, the scan driver may generate a scan signal for turning on an NMOS transistor of a pixel of the display device using a PMOS (P-type Metal-Oxide-Semiconductor) transistor.

[0029] In addition, in the scan driver, display device, and electronic device according to the present invention, the scan driver may sequentially provide scan signals to a plurality of pixels in row units in a sequential driving period, and may substantially simultaneously provide the scan signals to the plurality of pixels in a simultaneous driving period.

[0030] However, the effects of the present invention are not limited to the effects mentioned above, and can be expanded in various ways without departing from the spirit and scope of the present invention. [Brief explanation of the drawings]

[0031] [Figure 1] FIG. 1 is a block diagram showing a scan driver according to an embodiment of the present invention. [Figure 2] FIG. 2 is a timing diagram for explaining an example of the operation of the scan driver in the sequential drive period. [Figure 3] FIG. 3 is a timing diagram for explaining an example of the operation of the scan driver in the simultaneous drive period. [Figure 4] FIG. 4 is a circuit diagram showing a stage of a scan driver according to an embodiment of the present invention. [Figure 5] FIG. 5 is a timing chart for explaining an example of the operation of the stage of FIG. 4 in the sequential driving section. [Figure 6] FIG. 6 is a circuit diagram for explaining an example of the operation of the stage of FIG. 4 in the first time interval. [Figure 7] FIG. 7 is a circuit diagram for explaining an example of the operation of the stage of FIG. 4 in the second time interval. [Figure 8] FIG. 8 is a circuit diagram for explaining an example of the operation of the stage of FIG. 4 in the third time interval. [Figure 9] FIG. 9 is a timing chart for explaining an example of the operation of the stage of FIG. 4 in the simultaneous drive section. [Figure 10] FIG. 10 is a circuit diagram for explaining an example of the operation of the stage of FIG. 4 in the simultaneous drive section. [Figure 11] FIG. 11 is a timing diagram for explaining an example of a scan signal at the time when the simultaneous driving section ends and the sequential driving section starts. [Figure 12] FIG. 12 is a circuit diagram showing a stage of a scan driver according to another embodiment of the present invention. [Figure 13] FIG. 13 is a circuit diagram showing a stage of a scan driver according to yet another embodiment of the present invention. [Figure 14] FIG. 14 is a circuit diagram showing a stage of a scan driver according to yet another embodiment of the present invention. [Figure 15] FIG. 15 is a block diagram showing a display device according to one embodiment of the present invention. [Figure 16] FIG. 16 is a circuit diagram showing an example of a pixel included in a display device according to an embodiment of the present invention. [Figure 17] FIG. 17 is a timing chart showing an example of a frame period of a display device. [Figure 18] FIG. 18 is a block diagram showing an electronic device including a display device according to an embodiment of the present invention. [Figure 19] FIG. 19 is a block diagram illustrating an example of an electronic device according to an embodiment of the present invention. DETAILED DESCRIPTION OF THE INVENTION

[0032] Hereinafter, preferred embodiments of the present invention will be described in more detail with reference to the accompanying drawings. The same reference numerals are used to designate the same components in the drawings, and redundant description of the same components will be omitted.

[0033] FIG. 1 is a block diagram showing a scan driver according to one embodiment of the present invention, FIG. 2 is a timing diagram illustrating an example of the operation of the scan driver in a sequential drive period, and FIG. 3 is a timing diagram illustrating an example of the operation of the scan driver in a simultaneous drive period.

[0034] 1, a scan driver 100 according to an embodiment of the present invention includes a plurality of stages (STG1, STG2, STG3, STG4, STG5, ...). The scan driver 100 is implemented in the form of a shift register, in which the plurality of stages (STG1, STG2, STG3, STG4, STG5, ...) sequentially output scan signals (GW[1], GW[2], GW[3], GW[4], GW[5], ...).

[0035] Among the multiple stages (STG1, STG2, STG3, STG4, STG5, ...), the first stage (STG1) receives a start signal (FLM) as an input signal, and each of the subsequent stages (STG2, STG3, STG4, STG5, ...) receives the scan signal of the previous stage as an input signal. For example, the second stage (STG2) receives the first scan signal (GW[1]) of the first stage (STG1) as an input signal, the third stage (STG3) receives the second scan signal (GW[2]) of the second stage (STG2) as an input signal, the fourth stage (STG4) receives the third scan signal (GW[3]) of the third stage (STG3) as an input signal, and the fifth stage (STG5) receives the fourth scan signal (GW[4]) of the fourth stage (STG4) as an input signal.

[0036] The stages (STG1, STG2, STG3, STG4, STG5, ...) receive a first clock signal (CLK1), a second clock signal (CLK2), a third clock signal (CLK3), and a fourth clock signal (CLK4) having different phases from one another. In one embodiment of the present invention, each of the first to fourth clock signals (CLK1 to CLK4) has a clock period corresponding to, but not limited to, four horizontal periods. Here, one horizontal period is a time allocated to each pixel row of a display panel and is determined by dividing one frame period by the number of pixel rows of the display panel, but is not limited to this. Also, in one embodiment, as shown in FIG. 2, the second clock signal (CLK2) is delayed or shifted by one horizontal time from the first clock signal (CLK1), the third clock signal (CLK3) is delayed or shifted by one horizontal time from the second clock signal (CLK2), the fourth clock signal (CLK4) is delayed or shifted by one horizontal time from the third clock signal (CLK3), and the first clock signal (CLK1) is delayed or shifted by one horizontal time from the fourth clock signal (CLK4), but this is not limited to this.

[0037] In one embodiment of the present invention, each stage (STG1, STG2, STG3, STG4, STG5, ...) receives two adjacent clock signals from among the first to fourth clock signals (CLK1 to CLK4). For example, as shown in FIG. 1, the fourth N+1 stage (STG1, STG5, ...) (N is an integer equal to or greater than 0) receives the first clock signal (CLK1) and the second clock signal (CLK2), the fourth N+2 stage (STG2, ...) receives the second clock signal (CLK2) and the third clock signal (CLK3), the fourth N+3 stage (STG3, ...) receives the third clock signal (CLK3) and the fourth clock signal (CLK4), and the fourth N+4 stage (STG4, ...) receives the fourth clock signal (CLK4) and the first clock signal (CLK1).

[0038] The scan driver 100 according to an embodiment of the present invention sequentially outputs scan signals (GW[1], GW[2], GW[3], GW[4], GW[5], ...) in a sequential driving period, and outputs scan signals (GW[1], GW[2], GW[3], GW[4], GW[5], ...) substantially simultaneously in a simultaneous driving period. To perform such operations in the sequential driving period and the simultaneous driving period, the multiple stages (STG1, STG2, STG3, STG4, STG5, ...) further receive a simultaneous driving signal (GCK) and an inverted simultaneous driving signal (GCKB).

[0039] 2, in the sequential driving period (PDP), the first to fourth clock signals (CLK1 to CLK4) periodically toggle between high and low levels, the simultaneous driving signal (GCK) has a low level, and the inverted simultaneous driving signal (GCKB) has a high level. In one embodiment, in the sequential driving period (PDP), the simultaneous driving signal (GCK) has a first low gate voltage (VGL), and the inverted simultaneous driving signal (GCKB) has a high gate voltage (VGH). Based on the first to fourth clock signals (CLK1 to CLK4), the simultaneous drive signal (GCK), and the inverted simultaneous drive signal (GCKB), the first stage (STG1) delays or shifts the start signal (FLM) by one horizontal time to output a first scan signal (GW[1]), the second stage (STG2) delays or shifts the first scan signal (GW[1]) by one horizontal time to output a second scan signal (GW[2]), and the third stage The fourth stage (STG4) delays or shifts the third scan signal (GW[3]) by one horizontal time and outputs a fourth scan signal (GW[4]), and the fifth stage (STG5) delays or shifts the fourth scan signal (GW[4]) by one horizontal time and outputs a fifth scan signal (GW[5]).

[0040] 3, in the simultaneous drive period (SDP), the first to fourth clock signals (CLK1 to CLK4) are maintained at a high level or a high gate voltage (VGH), the simultaneous drive signal (GCK) has a high level, and the inverted simultaneous drive signal (GCKB) has a low level. In one embodiment, in the simultaneous drive period (SDP), the simultaneous drive signal (GCK) has a high gate voltage (VGH), and the inverted simultaneous drive signal (GCKB) has a second low gate voltage (VGL2) lower than the first low gate voltage (VGL). Furthermore, based on such first to fourth clock signals (CLK1 to CLK4), simultaneous drive signal (GCK), and inverted simultaneous drive signal (GCKB), multiple stages (STG1, STG2, STG3, STG4, STG5, ...) output scan signals (GW[1], GW[2], GW[3], GW[4], GW[5], ...) having a high level or high gate voltage (VGH) substantially simultaneously.

[0041] As described above, the scan driver 100 according to one embodiment of the present invention not only sequentially outputs scan signals (GW[1], GW[2], GW[3], GW[4], GW[5], ...) having a high level or high gate voltage (VGH) in the sequential driving period (PDP), but also outputs scan signals (GW[1], GW[2], GW[3], GW[4], GW[5], ...) having a high level or high gate voltage (VGH) substantially simultaneously in the simultaneous driving period (SDP).

[0042] FIG. 4 is a circuit diagram showing a stage of a scan driver according to an embodiment of the present invention.

[0043] As shown in FIG. 4, a stage 200 of a scan driver according to one embodiment of the present invention includes a logic circuit 210 that controls the voltage of a first node (N1) and the voltage of a second node (N2) during a sequential driving period, an output circuit 260 that outputs a scan signal (GW) in response to the voltage of the first node (N1) and the voltage of the second node (N2), and a simultaneous driving circuit 270 that controls the voltage of the first node (N1) and the voltage of the second node (N2) during a simultaneous driving period.

[0044] The logic circuit 210 controls the voltage of the first node (N1) and the voltage of the second node (N2) based on an input signal (SIN), a first clock signal (CLK1), and a second clock signal (CLK2). In one embodiment, the logic circuit 210 includes an input circuit 220, a node isolation circuit 230, a boost circuit 240, and a node control circuit 250.

[0045] The input circuit 220 transmits an input signal (SIN) to the third node (N3) in response to the first clock signal (CLK1). The input signal (SIN) is a start signal (FLM) if the stage 200 is the first stage, and is a scan signal (PGW) of the previous stage if the stage 200 is the subsequent stage. Also, Figure 4 shows an example in which stage 200 is the fourth N+1 stage and input circuit 220 receives a first clock signal (CLK1), but input circuit 220 of the fourth N+2 stage receives a second clock signal (CLK2) instead of the first clock signal (CLK1), input circuit 220 of the fourth N+3 stage receives the third clock signal (CLK3) in Figure 1 instead of the first clock signal (CLK1), and input circuit 220 of the fourth N+4 stage receives the fourth clock signal (CLK4) in Figure 1 instead of the first clock signal (CLK1).

[0046] In one embodiment of the present invention, the input circuit 220 includes a fifth transistor (T5) having a gate receiving the first clock signal (CLK1), a first terminal receiving the input signal (SIN), and a second terminal connected to the third node (N3).

[0047] The node isolation circuit 230 is connected between the third node (N3) and the first node (N1). The node isolation circuit 230 connects the third node (N3) and the first node (N1) to each other, but when the voltage of the first node (N1) is boosted by the boost circuit 240, the third node (N3) and the first node (N1) can be isolated from each other.

[0048] In one embodiment of the present invention, the node isolation circuit 230 includes a sixth transistor (T6) that is turned on in response to the simultaneous drive signal (GCK). The sixth transistor (T6) includes a gate that receives the simultaneous drive signal (GCK), a first terminal connected to the third node (N3), and a second terminal connected to the first node (N1).

[0049] The boost circuit 240 boosts the voltage of the first node (N1) based on the second clock signal (CLK2). For example, when the voltage of the first node (N1) has a low level and the second clock signal (CLK2) changes from a high level to a low level, the boost circuit 240 boosts the voltage of the first node (N1) to a boosted low level. Also, FIG. 4 shows an example in which stage 200 is the fourth N+1 stage and boost circuit 240 receives the second clock signal (CLK2), but the boost circuit 240 of the fourth N+2 stage receives the third clock signal (CLK3) in FIG. 1 instead of the second clock signal (CLK2), the boost circuit 240 of the fourth N+3 stage receives the fourth clock signal (CLK4) in FIG. 1 instead of the second clock signal (CLK2), and the boost circuit 240 of the fourth N+4 stage receives the first clock signal (CLK1) instead of the second clock signal (CLK2).

[0050] In one embodiment of the present invention, the boost circuit 240 includes a seventh transistor (T7) and a first capacitor (C1). The seventh transistor (T7) includes a gate connected to a first node (N1), a first terminal, and a second terminal for receiving a second clock signal (CLK2). The first capacitor (C1) includes a first electrode connected to the first terminal of the seventh transistor (T7) and a second electrode connected to the first node (N1).

[0051] The node control circuit 250 controls the voltage of the second node (N2) based on a first clock signal (CLK1), a second clock signal (CLK2), the voltage of the first node (N1), and a simultaneous drive signal (GCK). In one embodiment, the node control circuit 250 includes an eighth transistor (T8), a ninth transistor (T9), a tenth transistor (T10), a second capacitor (C2), an eleventh transistor (T11), a twelfth transistor (T12), a thirteenth transistor (T13), a third capacitor (C3), and a fourteenth transistor (T14).

[0052] The eighth transistor (T8) transmits the simultaneous drive signal (GCK) to the fourth node (N4) in response to the first clock signal (CLK1). For example, the eighth transistor (T8) includes a gate that receives the first clock signal (CLK1), a first terminal that receives the simultaneous drive signal (GCK), and a second terminal that is connected to the fourth node (N4).

[0053] The ninth transistor (T9) transmits the first clock signal (CLK1) to the fourth node (N4) in response to the voltage of the first node (N1). For example, the ninth transistor (T9) includes a gate connected to the first node (N1), a first terminal for receiving the first clock signal (CLK1), and a second terminal connected to the fourth node (N4).

[0054] The tenth transistor (T10) is turned on in response to the first low gate voltage (VGL) and connects the fourth node (N4) and the fifth node (N5) to each other. For example, the tenth transistor (T10) includes a gate that receives the first low gate voltage (VGL), a first terminal connected to the fourth node (N4), and a second terminal connected to the fifth node (N5).

[0055] The second capacitor (C2) is connected between the fifth node (N5) and the sixth node (N6). For example, the second capacitor (C2) includes a first electrode connected to the fifth node (N5) and a second electrode connected to the sixth node (N6).

[0056] The eleventh and twelfth transistors (T11, T12) transmit the second clock signal (CLK2) to the sixth node (N6) in response to the voltage of the fifth node (N5). For example, the eleventh transistor (T11) includes a gate connected to the fifth node (N5), a first terminal connected to the sixth node (N6), and a second terminal, and the twelfth transistor (T12) includes a gate connected to the fifth node (N5), a first terminal connected to the second terminal of the eleventh transistor (T11), and a second terminal that receives the second clock signal (CLK2).

[0057] The thirteenth transistor (T13) connects the sixth node (N6) and the second node (N2) to each other in response to the second clock signal (CLK2). For example, the thirteenth transistor (T13) includes a gate that receives the second clock signal (CLK2), a first terminal connected to the sixth node (N6), and a second terminal connected to the second node (N2).

[0058] The third capacitor (C3) is connected between the line transmitting the first clock signal (CLK1) and the second node (N2). For example, the third capacitor (C3) includes a first electrode that receives the first clock signal (CLK1) and a second electrode that is connected to the second node (N2).

[0059] The fourteenth transistor (T14) transmits the first clock signal (CLK1) to the second node (N2) in response to the voltage of the first node (N1). For example, the fourteenth transistor (T14) includes a gate connected to the first node (N1), a first terminal for receiving the first clock signal (CLK1), and a second terminal connected to the second node (N2).

[0060] The output circuit 260 receives a first clock signal (CLK1) and a simultaneous drive signal (GCK), and outputs a scan signal (GW) in response to the voltage of the first node (N1) and the voltage of the second node (N2). For example, when the voltage of the first node (N1) has a low level, the output circuit 260 outputs the simultaneous drive signal (GCK) as the scan signal (GW), and when the voltage of the second node (N2) has a low level, the output circuit 260 outputs the first clock signal (CLK1) as the scan signal (GW).

[0061] In one embodiment of the present invention, the output circuit 260 includes a third transistor (T3) and a fourth transistor (T4). The third transistor (T3) includes a gate connected to the second node (N2), a first terminal for receiving the first clock signal (CLK1), and a second terminal connected to an output node (NO) from which the scan signal (GW) is output. The fourth transistor (T4) includes a gate connected to the first node (N1), a first terminal connected to the output node (NO), and a second terminal for receiving the simultaneous drive signal (GCK).

[0062] The simultaneous drive circuit 270 controls the voltage of the first node (N1) and the voltage of the second node (N2) in response to an inverted simultaneous drive signal (GCKB) (e.g., an inverted signal of the simultaneous drive signal (GCK)) so that the output circuit 260 outputs the simultaneous drive signal (GCK) as the scan signal (GW) during the simultaneous drive period. For example, during the simultaneous drive period, the simultaneous drive circuit 270 applies a first low gate voltage (VGL) to the first node (N1) to control the voltage of the first node (N1) to a low level, and applies a high gate voltage (VGH) to the second node (N2) to control the voltage of the second node (N2) to a high level.

[0063] In one embodiment of the present invention, the simultaneous drive circuit 270 includes a first transistor (T1) that applies a first low gate voltage (VGL) to a first node (N1). The first transistor (T1) includes a gate that receives an inverted simultaneous drive signal (GCKB), a first terminal that receives the first low gate voltage (VGL), and a second terminal that is connected to the first node (N1). In one embodiment, the simultaneous drive circuit 270 further includes a second transistor (T2) that applies a high gate voltage (VGH) to a second node (N2). The second transistor (T2) includes a gate that receives the inverted simultaneous drive signal (GCKB), a first terminal that receives the high gate voltage (VGH), and a second terminal that is connected to the second node (N2).

[0064] In one embodiment of the present invention, all of the transistors included in stage 200, i.e., the first through fourteenth transistors (T1 through T14), are PMOS transistors. Also, as shown in Figures 5 and 9, stage 200 outputs a scan signal (GW) having a high level or high gate voltage (VGH) for turning on the NMOS transistor of the pixel. That is, stage 200 can generate an active-high scan signal (GW) for turning on the NMOS transistor using the PMOS transistor.

[0065] In addition, stage 200 delays or shifts the input signal (SIN) in the sequential driving period to generate a scan signal (GW) having a high level or high gate voltage (VGH), and generates a scan signal (GW) having a high level or high gate voltage (VGH) regardless of the input signal (SIN) in the simultaneous driving period. The operation of stage 200 in the sequential driving period will be described later with reference to Figures 4 to 8, and the operation of stage 200 in the simultaneous driving period will be described later with reference to Figures 4 and 9 to 11.

[0066] Figure 5 is a timing diagram for explaining an example of the operation of the stage of Figure 4 in a sequential drive interval, Figure 6 is a circuit diagram for explaining an example of the operation of the stage of Figure 4 in a first time interval, Figure 7 is a circuit diagram for explaining an example of the operation of the stage of Figure 4 in a second time interval, and Figure 8 is a circuit diagram for explaining an example of the operation of the stage of Figure 4 in a third time interval.

[0067] 4 and 5, during the sequential driving period (PDP), the first and second clock signals (CLK1, CLK2) periodically toggle between a high level (H) and a low level (L), the simultaneous driving signal (GCK) has a first low gate voltage (VGL) at a low level (L), and the inverted simultaneous driving signal (GCKB) has a high gate voltage (VGH) at a high level (H). Therefore, as shown in FIGS. 6 to 8, the first transistor (T1) and the second transistor (T2) are turned off in response to the inverted simultaneous driving signal (GCKB) having a high level (H) during the sequential driving period (PDP), and therefore the simultaneous driving circuit 270 does not control the voltages of the first node (N1) and the second node (N2) during the sequential driving period (PDP).

[0068] Furthermore, during the sequential driving period (PDP), the stage 200 delays or shifts the input signal (SIN) having a high level (H) based on the first and second clock signals (CLK1, CLK2), the simultaneous driving signal (GCK), and the inverted simultaneous driving signal (GCKB), and outputs a scan signal (GW) having a high level (H). For example, when the first clock signal (CLK1) has a low level (L) and the input signal (SIN) has a high level (H), the logic circuit 210 controls the voltage of the first node (N1) to a high level (H) and the voltage of the second node (N2) to a low level (L). Furthermore, the output circuit 260 outputs the first clock signal (CLK1) as the scan signal (GW) in response to the voltage of the first node (N1) having a high level (H) and the voltage of the second node (N2) having a low level (L). Therefore, the stage 200 can output a scan signal (GW) having a high level (H) or a high gate voltage (VGH) while the voltage of the first node (N1) has a high level (H), the voltage of the second node (N2) has a low level (L), and the first clock signal (CLK1) has a high level (H).

[0069] For example, as shown in Figures 5 and 6, during a first time period (TP1) when the input signal (SIN) has a high level (H), the first clock signal (CLK1) has a low level (L), and the second clock signal (CLK2) has a high level (H), the fifth transistor (T5) turns on in response to the first clock signal (CLK1) and transmits the input signal (SIN) having a high level (H) to the third node (N3). Therefore, the voltage of the third node (N3) can have a high level (H). The sixth transistor (T6) turns on in response to the simultaneous drive signal (GCK) and transmits the voltage of the third node (N3) to the first node (N1). Therefore, the voltage of the first node (N1) can have a high level (H). The eighth transistor T8 transmits a simultaneous drive signal (GCK) to the fourth node N4 in response to the first clock signal CLK1, and the tenth transistor T10 transmits the voltage of the fourth node N4 to the fifth node N5 in response to the first low gate voltage VGL. Thus, the voltages of the fourth and fifth nodes N4 and N5 can have a low level (L). The eleventh and twelfth transistors T11 and T12 transmit a second clock signal (CLK2) having a high level (H) to the sixth node N6 in response to the voltage of the fifth node N5, and the voltage of the sixth node N6 has a high level (H). The seventh, ninth, and fourteenth transistors (T7, T9, T14) are turned off in response to the voltage of the first node (N1), and the thirteenth transistor (T13) is turned off in response to the second clock signal (CLK2). Thus, the voltage of the first node (N1) has a high level (H), and the voltage of the second node (N2) can be maintained at its previous level, a low level (L). The fourth transistor (T4) is turned off in response to the voltage of the first node (N1) having a high level (H). The third transistor (T3) is turned on in response to the voltage of the second node (N2) having a low level (L), and outputs the first clock signal (CLK1) having a low level (L) as the scan signal (GW).As a result, in the first time period (TP1), the stage 200 can output a scan signal (GW) having a low level (L).

[0070] As shown in Figures 5 and 7, during a second time period (TP2) when the input signal (SIN) has a high level (H), the first clock signal (CLK1) has a high level (H), and the second clock signal (CLK2) has a low level (L), the fifth transistor (T5) is turned off in response to the first clock signal (CLK1), the sixth transistor (T6) is turned on in response to the simultaneous drive signal (GCK), and the voltage of the third node (N3) and the voltage of the first node (N1) have a high level (H). The eighth transistor (T8) is turned off in response to the first clock signal (CLK1), the seventh, ninth, and fourteenth transistors (T7, T9, T14) are turned off in response to the voltage of the first node (N1), the tenth transistor (T10) is turned on in response to the first low gate voltage (VGL), the voltages of the fourth node (N4) and the fifth node (N5) have a low level (L), the eleventh and twelfth transistors (T11, T12) transmit the second clock signal (CLK2) having a low level (L) to the sixth node (N6) in response to the voltage of the fifth node (N5), and the voltage of the sixth node (N6) has a low level (L). The thirteenth transistor (T13) is turned on in response to the second clock signal (CLK2) and transmits the voltage of the sixth node (N6) to the second node (N2). Therefore, the voltage of the first node (N1) may have a high level (H) and the voltage of the second node (N2) may have a low level (L). The fourth transistor (T4) is turned off in response to the voltage of the first node (N1) having a high level (H). The third transistor (T3) is turned on in response to the voltage of the second node (N2) having a low level (L) and outputs the first clock signal (CLK1) having a high level (H) as the scan signal (GW). This allows the stage 200 to output the scan signal (GW) having a high level (H) during the second time period (TP2).

[0071] 5 and 8, during a third time period (TP3) when the input signal (SIN) has a low level (L), the first clock signal (CLK1) has a low level (L), and the second clock signal (CLK2) has a high level (H), the fifth transistor (T5) turns on in response to the first clock signal (CLK1) and transmits the input signal (SIN) having a low level (L) to the third node (N3). Therefore, the voltage at the third node (N3) can have a low level (L). The sixth transistor (T6) turns on in response to the simultaneous drive signal (GCK) and transmits the voltage at the third node (N3) to the first node (N1). Therefore, the voltage at the first node (N1) can have a low level (L). The eighth transistor (T8) turns on in response to a first clock signal (CLK1), the seventh, ninth and fourteenth transistors (T7, T9, T14) turn on in response to the voltage of the first node (N1), the tenth transistor (T10) turns on in response to a first low gate voltage (VGL), the eleventh and twelfth transistors (T11, T12) turn on in response to the voltage of the fifth node (N5), and the thirteenth transistor (T13) turns off in response to a second clock signal (CLK2). Thus, the voltage of the fourth node (N4) has a low level (L) based on the simultaneous drive signal (GCK) and the first clock signal (CLK1), the voltage of the fifth node (N5) has a low level (L) based on the voltage of the fourth node (N4), the voltage of the sixth node (N6) has a high level (H) based on the second clock signal (CLK2), and the voltage of the second node (N2) has a low level (L) based on the first clock signal (CLK1). In one embodiment, when the first clock signal (CLK1) applied to the first electrode of the third capacitor (C3) decreases from a high level (H) to a low level (L), the voltage of the second node (N2) connected to the second electrode of the third capacitor (C3) is boosted. The third transistor (T3) turns on in response to the voltage of the second node (N2) having a low level (L), and outputs the first clock signal (CLK1) having a low level (L) as the scan signal (GW).In addition, the fourth transistor (T4) is turned on in response to the voltage of the first node (N1) having a low level (L) and outputs the simultaneous driving signal (GCK) having a low level (L) as the scan signal (GW), so that in the third time period (TP3), the stage 200 can output the scan signal (GW) having a low level (L).

[0072] In this manner, in the sequential driving period (PDP), the stage 200 or the fourth N+1 stage (STG1, STG5, ...) in FIG. 1 outputs scan signals (GW, GW[1], GW[5], ...) synchronized with the first clock signal (CLK1), the fourth N+2 stage (STG2, ...) in FIG. 1 outputs scan signals (GW[2], ...) synchronized with the second clock signal (CLK2), the fourth N+3 stage (STG3, ...) in FIG. 1 outputs scan signals (GW[3], ...) synchronized with the third clock signal (CLK3), and the fourth N+4 stage (STG4, ...) in FIG. 1 outputs scan signals (GW[4], ...) synchronized with the fourth clock signal (CLK4). Therefore, the scan driver according to an embodiment of the present invention can sequentially output scan signals (GW, GW[1], GW[2], GW[3], GW[4], GW[5], ...) having a high level (H) using PMOS transistors in the sequential driving period (PDP).

[0073] 9 is a timing diagram illustrating an example of the operation of the stage of FIG. 4 in the simultaneous driving section, FIG. 10 is a circuit diagram illustrating an example of the operation of the stage of FIG. 4 in the simultaneous driving section, and FIG. 11 is a timing diagram illustrating an example of the scan signal at the time when the simultaneous driving section ends and the sequential driving section starts.

[0074] 4 and 9, in the simultaneous drive period (SDP), the first and second clock signals (CLK1, CLK2) are maintained at a high level (H), the simultaneous drive signal (GCK) has a high gate voltage (VGH) as a high level (H), and the inverted simultaneous drive signal (GCKB) has a second low gate voltage (VGL2) lower than the first low gate voltage (VGL) as a low level (L'). During the simultaneous drive period (SDP), all stages of the scan driver, including the stage 200, substantially simultaneously output scan signals (GW) having a high level (H) based on the simultaneous drive signal (GCK) having a high level (H) or a high gate voltage (VGH) and the inverted simultaneous drive signal (GCKB) having a low level (L') or a second low gate voltage (VGL2). For example, the simultaneous drive circuit 270 of the stage 200 applies a first low gate voltage (VGL) to the first node (N1) and a high gate voltage (VGH) to the second node (N2) in response to the inverted simultaneous drive signal (GCKB). Also, the output circuit 260 of the stage 200 outputs a simultaneous drive signal (GCK) having a high level (H) or a high gate voltage (VGH) as the scan signal (GW) in response to the voltage of the first node (N1) having a low level (L) and the voltage of the second node (N2) having a high level (H).

[0075] 9 and 10, the sixth transistor (T6) is turned off in response to the simultaneous drive signal (GCK), and the thirteenth transistor (T13) is turned off in response to the second clock signal (CLK2), so the voltage of the third node (N3) does not affect the voltage of the first node (N1), and the voltage of the sixth node (N6) does not affect the voltage of the second node (N2). On the other hand, the fifth and eighth transistors (T5, T8) are turned off in response to the first clock signal (CLK1), the seventh, ninth and fourteenth transistors (T7, T9, T14) are turned on in response to the voltage of the first node (N1), the tenth transistor (T10) is turned on in response to the first low gate voltage (VGL), and the eleventh and twelfth transistors (T11, T12) are turned off in response to the voltage of the fifth node (N5).

[0076] The first transistor (T1) is turned on in response to the inverted simultaneous drive signal (GCKB) having a low level (L') or a second low gate voltage (VGL2) and transmits a first low gate voltage (VGL) to the first node (N1). The voltage at the first node (N1) can have a low level (L). The second transistor (T2) is turned on in response to the inverted simultaneous drive signal (GCKB) having a low level (L') or a second low gate voltage (VGL2) and transmits a high gate voltage (VGH) to the second node (N2). The voltage at the second node (N2) can have a high level (H). The third transistor (T3) is turned off in response to the voltage at the second node (N2) having a high level (H), and the fourth transistor (T4) is turned on in response to the voltage at the first node (N1) having a low level (L). Furthermore, the fourth transistor T4 outputs a simultaneous driving signal GCK having a high level (H) or a high gate voltage (VGH) as the scan signal GW, so that the stage 200 can output a scan signal GW having a high level (H) during the simultaneous driving period SDP.

[0077] In one embodiment of the present invention, at the end of the simultaneous driving period (SDP), i.e., at the start of the sequential driving period (PDP), the simultaneous driving signal (GCK) changes from the high gate voltage (VGH) to the first low gate voltage (VGL), and the inverted simultaneous driving signal (GCKB) changes from the second low gate voltage (VGL2) to the high gate voltage (VGH).

[0078] 11, the simultaneous driving signal (GCK) changes from a high gate voltage (VGH) to a first low gate voltage (VGL) at the end of the simultaneous driving period (SDP), i.e., at the start of the sequential driving period (PDP), and the inverted simultaneous driving signal (GCKB) changes from a second low gate voltage (VGL2) to a high gate voltage (VGH) a certain time after the simultaneous driving signal (GCK) changes to the first low gate voltage (VGL) within the sequential driving period (PDP). As a result, the scan signal (GW) can suddenly drop from a high level (H) to a low level (L) at the end of the simultaneous driving period (SDP), i.e., at the start of the sequential driving period (PDP). Also, when the inverted simultaneous driving signal (GCKB) has the first low gate voltage (VGL) during the simultaneous driving period (SDP), the voltage of the first node (N1) does not have a sufficiently low low level (L), the fourth transistor (T4) does not turn on sufficiently in the initial part of the sequential driving period (PDP), and the voltage level 320 of the scan signal (GW) does not reach the voltage level of the first low gate voltage (VGL) in the initial part of the sequential driving period (PDP). However, in the scan driver according to an embodiment of the present invention, the inverted simultaneous driving signal (GCKB) has a second low gate voltage (VGL2) lower than the first low gate voltage (VGL) during the simultaneous driving period (SDP), the voltage of the first node (N1) has a sufficiently low low level (L), the fourth transistor (T4) is fully or completely turned on, and the voltage level 340 of the scan signal (GW) can quickly reach the voltage level of the first low gate voltage (VGL) in the initial part of the sequential driving period (PDP).

[0079] FIG. 12 is a circuit diagram showing a stage of a scan driver according to another embodiment of the present invention.

[0080] 12, a stage 400 of a scan driver according to another embodiment of the present invention includes a logic circuit 210, an output circuit 260, and a simultaneous drive circuit 470. The logic circuit 210 includes an input circuit 220, a node isolation circuit 230, a boost circuit 240, and a node control circuit 250. The stage 400 of FIG. 12 may have substantially the same configuration and operation as the stage 200 of FIG. 4, except that the simultaneous drive circuit 470 does not include the second transistor (T2) in FIG. 4, but only includes the first transistor (T1).

[0081] During the simultaneous driving period, the first transistor T1 is turned on in response to the inverted simultaneous driving signal GCKB having a second low gate voltage and transmits the first low gate voltage VGL to the first node N1. Therefore, the voltage of the first node N1 may have a low level. Also, during the simultaneous driving period, the fourteenth transistor T14 is turned on in response to the voltage of the first node N1 having the low level and transmits the first clock signal CLK1 having a high level to the second node N2. Therefore, the voltage of the second node N2 may have a high level. As a result, even if the simultaneous driving circuit 470 does not include the second transistor (T2) in FIG. 4, during the simultaneous driving period, the simultaneous driving circuit 470 can control the voltage of the first node (N1) to the low level and, together with the fourteenth transistor (T14), control the voltage of the second node (N2) to the high level.

[0082] FIG. 13 is a circuit diagram showing a stage of a scan driver according to yet another embodiment of the present invention.

[0083] 13, a stage 500 of a scan driver according to another embodiment of the present invention includes a logic circuit 210, an output circuit 260, and a simultaneous drive circuit 570. The logic circuit 210 includes an input circuit 220, a node isolation circuit 230, a boost circuit 240, and a node control circuit 250. The stage 500 in FIG. 13 may have substantially the same configuration and operation as the stage 400 in FIG. 12, except that the simultaneous drive circuit 570 further includes a fourth capacitor (C4).

[0084] The fourth capacitor C4 is connected between the second node N2 and a line transmitting the simultaneous drive signal GCK. In one embodiment, the fourth capacitor C4 includes a first electrode connected to the second node N2 and a second electrode receiving the simultaneous drive signal GCK. Therefore, when the simultaneous drive signal GCK applied to the second electrode of the fourth capacitor C4 increases from the first low gate voltage VGL to the high gate voltage VGH at the start of the simultaneous drive period, the voltage of the second node N2 connected to the first electrode of the fourth capacitor C4 also increases due to coupling of the fourth capacitor C4. Thus, during the simultaneous drive period, the simultaneous drive circuit 570 can control the voltage of the first node N1 to a low level and quickly control the voltage of the second node N2 to a high level.

[0085] FIG. 14 is a circuit diagram showing a stage of a scan driver according to yet another embodiment of the present invention.

[0086] 14, a stage 600 of a scan driver according to yet another embodiment of the present invention includes a logic circuit 210, an output circuit 260, a simultaneous drive circuit 270, and a reset circuit 690. The logic circuit 210 includes an input circuit 220, a node isolation circuit 230, a boost circuit 240, and a node control circuit 250. The stage 600 of FIG. 14 may have substantially the same configuration and operation as the stage 200 of FIG. 4, except that it further includes the reset circuit 690.

[0087] The reset circuit 690 transmits a first clock signal (CLK1) to a first node (N1) in response to a reset signal (ESR) and transmits a simultaneous drive signal (GCK) to a second node (N2) in response to the reset signal (ESR). In one embodiment, when the display device is powered on, the reset signal (ESR) has a low level. Therefore, when the display device is powered on, the reset circuit 690 resets the voltage of the first node (N1) based on the first clock signal (CLK1) and resets the voltage of the second node (N2) based on the simultaneous drive signal (GCK) in response to the reset signal (ESR) having the low level.

[0088] In one embodiment of the present invention, the reset circuit 690 includes a fifteenth transistor (T15) that transmits (through the sixth transistor (T6)) the first clock signal (CLK1) to the first node (N1) in response to the reset signal (ESR), and a sixteenth transistor (T16) that transmits the simultaneous drive signal (GCK) to the second node (N2) in response to the reset signal (ESR). For example, the fifteenth transistor (T15) includes a gate that receives the reset signal (ESR), a first terminal that receives the first clock signal (CLK1), and a second terminal connected to the third node (N3). 14 shows an example in which the second terminal of the fifteenth transistor (T15) is connected to the third node (N3) and the first clock signal (CLK1) is transmitted to the first node (N1) by the sixth transistor (T6), but in other embodiments, the second terminal of the fifteenth transistor (T15) is connected to the first node (N1). Also, the sixteenth transistor (T16) includes a gate that receives a reset signal (ESR), a first terminal that is connected to the second node (N2), and a second terminal that receives a simultaneous drive signal (GCK).

[0089] FIG. 15 is a block diagram showing a display device according to an embodiment of the present invention, FIG. 16 is a circuit diagram showing an example of a pixel included in a display device according to an embodiment of the present invention, and FIG. 17 is a timing diagram showing an example of a frame period of the display device.

[0090] As shown in FIG. 15, a display device 700 according to one embodiment of the present invention includes a display panel 710 including a plurality of pixels (PX), a data driver 720 that provides data signals (DS) to the plurality of pixels (PX), a scan driver 730 that provides scan signals (GW) to the plurality of pixels (PX), an emission driver 740 that provides emission signals (EM) to the plurality of pixels (PX), and a controller 750 that controls the data driver 720, the scan driver 730, and the emission driver 740.

[0091] The display panel 710 includes data lines, scan lines, emission lines, and a plurality of pixels (PX) connected thereto. In one embodiment of the present invention, each pixel (PX) includes a light-emitting element, and the display panel 710 is an emissive display panel. However, the display panel 710 is not limited to the emissive display panel and may be any suitable display panel.

[0092] For example, as shown in FIG. 16, each pixel (PX) includes a first transistor (PXT1), a second transistor (PXT2), a third transistor (PXT3), a fourth transistor (PXT4), a storage capacitor (CST), and a light-emitting element (EL).

[0093] The first transistor (PXT1) generates a drive current based on the voltage stored in the storage capacitor (CST). The first transistor (PXT1) is a drive transistor for driving the light-emitting element (EL). In one embodiment, the first transistor (PXT1) includes a gate connected to a gate node, a first terminal receiving a first power supply voltage (ELVDD) (e.g., a high power supply voltage), and a second terminal connected to a source node.

[0094] The storage capacitor (CST) stores the data signal (DS) transmitted through the second transistor (PXT2). In one embodiment, the storage capacitor (CST) includes a first electrode connected to the second and fourth transistors (PXT2, PXT4) and a second electrode connected to the source node.

[0095] The second transistor (PXT2) connects the data line (DL) to the storage capacitor (CST) in response to the scan signal (GW[n]). In one embodiment, the second transistor (PXT2) includes a gate that receives the scan signal (GW[n]), a first terminal connected to the data line (DL), and a second terminal connected to the storage capacitor (CST).

[0096] The third transistor (PXT3) transmits a reference voltage (VREF) to the gate node in response to a scan signal (GW[n]). In one embodiment, the reference voltage (VREF) has a voltage level for turning on the first transistor (PXT1). Also in one embodiment, the third transistor (PXT3) includes a gate that receives the scan signal (GW[n]), a first terminal that receives the reference voltage (VREF), and a second terminal connected to the gate node.

[0097] A fourth transistor (PXT4) connects a storage capacitor (CST) to the gate node in response to a light emission signal (EM). In one embodiment, the fourth transistor (PXT4) includes a gate that receives the light emission signal (EM), a first terminal connected to the gate node, and a second terminal connected to the storage capacitor (CST).

[0098] The light-emitting element (EL) emits light based on the drive current generated by the first transistor (PXT1). In one embodiment, the light-emitting element (EL) is, but is not limited to, an organic light-emitting diode (OLED). In other embodiments, the light-emitting element (EL) is a micro light-emitting diode, a nano light-emitting diode (NED), a quantum dot (QD) light-emitting diode, an inorganic light-emitting diode, or any other suitable light-emitting element. Also, in one embodiment, the light-emitting element (EL) includes an anode connected to the first transistor (PXT1) and a cathode receiving a second power supply voltage (ELVSS) (e.g., a low power supply voltage).

[0099] In one embodiment of the present invention, the first, second, third, and fourth transistors (PXT1, PXT2, PXT3, PXT4) are, but are not limited to, NMOS transistors, as shown in Fig. 16. Also, Fig. 16 shows an example in which the pixel (PX) has a 4T1C structure, but the pixel (PX) of the display device 700 according to the embodiment of the present invention is not limited to the example shown in Fig. 16.

[0100] The data driver 720 generates data signals (DS) based on the data control signals (DCTRL) and output image data (ODAT) received from the controller 750, and provides the data signals (DS) to the pixels (PX) via the data lines. In one embodiment, the data control signals (DCTRL) include, but are not limited to, an output data enable signal, a horizontal start signal, and a load signal. In one embodiment, the data driver 720 and the controller 750 are implemented in a single integrated circuit, and such an integrated circuit is referred to as a timing controller embedded data driver (TED) integrated circuit. In other embodiments, the data driver 720 and the controller 750 may be implemented in separate integrated circuits.

[0101] The scan driver 730 generates a scan signal (GW) based on a scan control signal (SCTRL) received from the controller 750 and provides the scan signal (GW) to the pixels (PX) via the scan lines. In one embodiment, the scan control signal (SCTRL) includes, but is not limited to, the start signal (FLM), the first clock signal (CLK1), the second clock signal (CLK2), the third clock signal (CLK3), the fourth clock signal (CLK4), the simultaneous drive signal (GCK), and the inverted simultaneous drive signal (GCKB) in FIG. 1. The scan driver 730 is the scan driver 100 of FIG. 1 including stage 200 of FIG. 4, stage 400 of FIG. 12, stage 500 of FIG. 13, stage 600 of FIG. 14, or a similar stage. Therefore, the scan driver 730 generates a scan signal (GW) using a PMOS transistor to turn on the second and third transistors (PXT2, PXT3), i.e., the NMOS transistors, of the pixel (PX). The scan driver 730 sequentially provides the scan signal (GW) to the pixels (PX) row by row in a sequential driving period, and provides the scan signal (GW) to the pixels (PX) substantially simultaneously in a simultaneous driving period. In one embodiment, the scan driver 730 is integrated or formed in the display panel 710. In another embodiment, the scan driver 730 may be embodied in one or more integrated circuits.

[0102] The light emitting driver 740 generates a light emitting signal (EM) based on a light emitting control signal (EMCTRL) received from the controller 750 and provides the light emitting signal (EM) to the plurality of pixels (PX) via the light emitting lines. In one embodiment, the light emitting driver 740 provides the light emitting signal (EM) to the plurality of pixels (PX) substantially simultaneously. In another embodiment, the light emitting driver 740 provides the light emitting signal (EM) to the plurality of pixels (PX) sequentially in rows. Also, in one embodiment, the light emitting driver 740 is integrated into or formed on the display panel 710. In another embodiment, the light emitting driver 740 may be embodied in one or more integrated circuits.

[0103] The controller 750 (e.g., a timing controller) receives input image data (IDAT) and control signals (CTRL) from an external host processor (e.g., a graphics processing unit (GPU), an application processor (AP), or a graphics card). In one embodiment, the input image data (IDAT) is RGB image data including red image data, green image data, and blue image data. In one embodiment, the control signals (CTRL) further include, but are not limited to, a vertical synchronization signal, a horizontal synchronization signal, an input data enable signal, a master clock signal, etc. The controller 750 generates output image data (ODAT), a data control signal (DCTRL), a scan control signal (SCTRL), and an emission control signal (EMCTRL) based on the input image data (IDAT) and the control signal (CTRL). The controller 750 provides output image data (ODAT) and a data control signal (DCTRL) to the data driver 720 to control the operation of the data driver 720, provides a scan control signal (SCTRL) to the scan driver 730 to control the operation of the scan driver 730, and provides an emission control signal (EMCTRL) to the emission driver 740 to control the operation of the emission driver 740.

[0104] In a display device 700 according to an embodiment of the present invention, a frame period includes a simultaneous driving period in which a scan driver 730 provides a scan signal (GW) to a plurality of pixels (PX) substantially simultaneously, and a sequential driving period in which the scan driver 730 provides a scan signal (GW) to a plurality of pixels (PX) sequentially in row units. For example, as shown in Fig. 17, the frame period (FP) includes an initialization period (INIP) in which gate nodes and source nodes of a plurality of pixels (PX) are initialized, a data write period (DWP) in which data signals (DS) are written to a plurality of pixels (PX) sequentially in row units, and an emission period (EMP) in which a plurality of pixels (PX) emit light substantially simultaneously. Also, the initialization period (INIP) is a simultaneous driving period (SDP) in which the scan driver 730 provides scan signals (GW[1], ..., GW[M]) to a plurality of pixels (PX) substantially simultaneously, and the data write period (DWP) is a sequential driving period (PDP) in which the scan driver 730 provides scan signals (GW[1], ..., GW[M]) to a plurality of pixels (PX) sequentially in row units. Meanwhile, in FIG. 17, the emission signal (EM) is a global signal that is applied to a plurality of pixels (PX) substantially simultaneously.

[0105] For example, during the initialization period (INIP), the emission signal (EM) has a low level, the simultaneous drive signal (GCK) has a high gate voltage (VGH), and the inverted simultaneous drive signal (GCKB) has a second low gate voltage (VGL2). Therefore, the scan driver 730 can provide scan signals (GW[1], ..., GW[M]) having a high level to multiple pixels (PX) substantially simultaneously based on the simultaneous drive signal (GCK) and the inverted simultaneous drive signal (GCKB). In each pixel (PX), the second and third transistors (PXT2, PXT3) are turned on in response to the scan signal (GW[n]) having the high level, and the first transistor (PXT1) is turned on based on the reference voltage (VREF) transmitted to the gate node via the third transistor (PXT3). Therefore, the gate node is initialized based on the reference voltage (VREF), and the source node is initialized based on the first power supply voltage (ELVDD).

[0106] Also, during the data write period (DWP), the light emission signal (EM) has a low level, the simultaneous drive signal (GCK) has a first low gate voltage (VGL), and the inverted simultaneous drive signal (GCKB) has a high gate voltage (VGH). The scan driver 730 sequentially provides scan signals (GW[1], ..., GW[M]) having a high level to the plurality of pixels (PX) row by row based on the simultaneous drive signal (GCK) and the inverted simultaneous drive signal (GCKB). For example, if the display panel 710 has first to Mth pixel rows (M is an integer equal to or greater than 2), the scan driver 730 sequentially outputs the first to Mth scan signals (GW[1], ..., GW[M]) in the order of a first scan signal (GW[1]) for the first pixel row to an Mth scan signal (GW[M]) for the Mth pixel row. When a pixel (PX) is included in the nth pixel row (n is an integer greater than or equal to 1 and less than or equal to M), when an nth scan signal (GW[n]) having a high level is applied, the third transistor (PXT3) transmits the reference voltage (VREF) to the gate node, the first transistor (PXT1) is turned on until the voltage of the source node becomes the reference voltage (VREF) minus the threshold voltage of the first transistor (PXT1), and the second transistor (PXT2) applies a data signal (DS) to the first electrode of the storage capacitor (CST). Thus, the storage capacitor (CST) can store the data signal (DS) that reflects or compensates for the threshold voltage of the first transistor (PXT1).

[0107] In addition, during the light emitting period (EMP), the light emitting signal (EM) has a high level. In each pixel (PX), the fourth transistor (PXT4) connects the storage capacitor (CST) to the gate node, the first transistor (PXT1) generates a driving current based on the data signal (DS) stored in the storage capacitor (CST), and the light emitting element (EL) emits light based on the driving current.

[0108] As described above, in the display device 700 according to an embodiment of the present invention, the scan driver 730 generates the scan signal (GW) using a PMOS transistor to turn on the NMOS transistor of each pixel (PX). Also, in the display device 700 according to an embodiment of the present invention, the scan driver 730 sequentially provides the scan signal (GW) to the plurality of pixels (PX) row by row in the sequential driving period (PDP), and provides the scan signal (GW) to the plurality of pixels (PX) substantially simultaneously in the simultaneous driving period (SDP).

[0109] FIG. 18 is a block diagram showing an electronic device including a display device according to an embodiment of the present invention.

[0110] 18, electronic device 1100 includes a processor 1110, a memory device 1120, a storage device 1130, an input / output device 1140, a power supply 1150, and a display device 1160. Electronic device 1100 further includes a number of ports for communicating with a video card, a sound card, a memory card, a USB device, etc., or for communicating with other systems.

[0111] The processor 1110 performs specific calculations or tasks. The processor 1110 may be a microprocessor, a central processing unit (CPU), or the like. The processor 1110 is connected to other components via an address bus, a control bus, a data bus, or the like. Depending on the embodiment, the processor 1110 may also be connected to an expansion bus such as a Peripheral Component Interconnect (PCI) bus.

[0112] The memory device 1020 stores data necessary for the operation of the electronic device 1000. For example, the memory device 1020 may include a non-volatile memory device such as an erasable programmable read-only memory (ERPOM), an electrically erasable programmable read-only memory (EERPOM), a flash memory, a phase change random access memory (PRAM), a resistance random access memory (RRAM), a nano floating gate memory (NFGM), a polymer random access memory (PoRAM), a magnetic random access memory (MRAM), a ferroelectric random access memory (FRAM), etc., and / or a volatile memory device such as a dynamic random access memory (DRAM), a static random access memory (SRAM), a mobile DRAM device, etc.

[0113] The storage device 1130 may include a solid state drive (SSD), a hard disk drive (HDD), a CD-ROM, etc. The input / output device 1040 may include input means such as a keyboard, a keypad, a touchpad, a touch screen, a mouse, etc., and output means such as a speaker, a printer, etc. The power supply 1050 may provide power necessary for the operation of the electronic device 1000. The display device 1060 may be connected to other components via the bus or other communication link.

[0114] In the display device 1160, the scan driver generates a scan signal using a PMOS transistor to turn on an NMOS transistor of each pixel. In addition, in the display device 1160, the scan driver sequentially provides scan signals to a plurality of pixels row by row in a sequential driving period, and provides the scan signals to the plurality of pixels substantially simultaneously in a simultaneous driving period.

[0115] The electronic device 1100 may be any electronic device including a display device 1160 such as a digital TV, a 3D TV, a mobile phone, a smartphone, a virtual reality (VR) device, a personal computer (PC) (e.g., a tablet computer, a laptop computer, etc.), a home electronic device, a personal digital assistant (PDA), a portable multimedia player (PMP), a digital camera, a music player, a portable game console, a navigation system, etc.

[0116] FIG. 19 is a block diagram illustrating an example of an electronic device according to an embodiment of the present invention.

[0117] In an operating system, the electronic device 2101 outputs various information through the display module 2140. When the processor 2110 executes an application stored in the memory 2120, the display module 2140 provides application information to the user through the display panel 2141.

[0118] The processor 2110 acquires an external input through the input module 2130 or the sensor module 2161, and executes an application corresponding to the external input. For example, when a user selects a camera icon displayed on the display panel 2141, the processor 2110 acquires the user input through the input sensor 2161-2 and activates the camera module 2171. The processor 2110 transmits image data corresponding to the captured image acquired through the camera module 2171 to the display module 2140. The display module 2140 displays an image corresponding to the captured image on the display panel 2141.

[0119] As another example, when personal information authentication is performed by the display module 2140, the fingerprint sensor 2161-1 acquires input fingerprint information as input data. The processor 2110 compares the input data acquired by the fingerprint sensor 2161-1 with authentication data stored in the memory 2120 and executes an application based on the comparison result. The display module 2140 displays information generated by the logic of the application on the display panel 2141.

[0120] As another example, when a music streaming icon displayed on the display module 2140 is selected, the processor 2110 obtains a user input through the input sensor 2161-2 and activates a music streaming application stored in the memory 2120. When a music execution command is input in the music streaming application, the processor 2110 activates the audio output module 2163 to provide the user with audio information corresponding to the music execution command.

[0121] The above is a brief description of the operation of the electronic device 2101. Below, a detailed description will be given of the configuration of the electronic device 2101. Some of the components of the electronic device 2101 described below may be integrated into one component, or one component may be divided into two or more components.

[0122] 19 , electronic device 2101 communicates with external electronic device 2102 via a network (e.g., a short-range wireless communication network or a long-range wireless communication network). In one embodiment, electronic device 2101 includes processor 2110, memory 2120, input module 2130, display module 2140, power module 2150, internal module 2160, and external module 2170. In one embodiment, electronic device 2101 may omit at least one of the aforementioned components or may include one or more additional components. In one embodiment, some of the aforementioned components (e.g., sensor module 2161, antenna module 2162, or acoustic output module 2163) may be integrated into another component (e.g., display module 2140).

[0123] The processor 2110 may execute software to control at least one other component (e.g., a hardware or software component) of the electronic device 2101 connected to the processor 2110, and may perform various data processing or calculations. According to one embodiment, as at least part of the data processing or calculations, the processor 2110 stores instructions or data received from other components (e.g., the input module 2130, the sensor module 2161, or the communication module 2173) in the volatile memory 2121, processes the instructions or data stored in the volatile memory 2121, and the resulting data is stored in the non-volatile memory 2122.

[0124] The processor 2110 includes a main processor 2111 and an auxiliary processor 2112. The main processor 2111 includes one or more of a central processing unit 2111-1 (CPU) or an application processor (AP). The main processor 2111 may further include one or more of a graphics processing unit 2111-2 (GPU), a communication processor (CP), and an image signal processor (ISP). The main processor 2111 further includes a neural processing unit 2111-3 (NPU). The neural processing unit 2111-3 is a processor specialized in processing artificial intelligence models, which are generated by machine learning. The artificial intelligence models include multiple artificial neural layers. The artificial neural network may be, but is not limited to, a deep neural network (DNN), a convolutional neural network (CNN), a recurrent neural network (RNN), a restricted Boltzmann machine (RBM), a deep belief network (DBN), a bidirectional recurrent deep neural network (BRDNN), a deep Q-network, or a combination of two or more thereof. The artificial intelligence model may include a software structure in addition to a hardware structure. At least two of the processing unit and processor may be embodied in an integrated structure (e.g., a single chip) or each may be embodied in an independent structure (e.g., multiple chips).

[0125] The auxiliary processor 2112 includes a controller. The controller included in the auxiliary processor 2112 corresponds to the controller 750 in FIG. 15. The controller includes an interface switching circuit and a timing control circuit. The controller receives image signals from the main processor 2111, switches the data format of the image signals to match the interface specifications with the display module 2140, and outputs image data. The controller outputs various control signals required to drive the display module 2140.

[0126] The auxiliary processor 2112 further includes a data switching circuit 2112-2, a gamma correction circuit 2112-3, a rendering circuit 2112-4, etc. The data switching circuit 2112-2 receives image data from the controller and compensates for the image data so that an image is displayed at a desired brightness, or switches the image data to reduce power consumption or compensate for image retention, depending on the characteristics of the electronic device 2101 or user settings. The gamma correction circuit 2112-3 switches the image data or a gamma reference voltage, etc., so that an image displayed on the electronic device 2101 has a desired gamma characteristic. The rendering circuit 2112-4 receives image data from the controller and renders the image data, taking into account the pixel arrangement of a display panel 2141 applied to the electronic device 2101, etc. At least one of the data switching circuit 2112-2, the gamma correction circuit 2112-3, and the rendering circuit 2112-4 is integrated into another component (e.g., the main processor 2111 or the controller). At least one of the data switching circuit 2112-2, the gamma correction circuit 2112-3, and the rendering circuit 2112-4 can also be integrated into the data driver 2143, which will be described later.

[0127] The memory 2120 stores various data used by at least one component (e.g., the processor 2110 or the sensor module 2161) of the electronic device 2101 and input or output data for instructions associated therewith. The memory 2120 includes at least one of a volatile memory 2121 and a non-volatile memory 2122.

[0128] The input module 2130 receives commands or data from outside the electronic device 2101 (e.g., from a user or an external electronic device 2102) for use by components of the electronic device 2101 (e.g., the processor 2110, the sensor module 2161, or the acoustic output module 2163).

[0129] The input module 2130 includes a first input module 2131 through which commands or data are input from a user, and a second input module 2132 through which commands or data are input from the external electronic device 2102. The first input module 2131 includes a microphone, a mouse, a keyboard, keys (e.g., buttons), or a pen (e.g., a passive pen or an active pen). The second input module 2132 can support a specified protocol that can be connected to the external electronic device 2102 via a wired or wireless connection. According to one embodiment, the second input module 2132 includes a high definition multimedia interface (HDMI), a universal serial bus (USB), an SD card interface, or an audio interface. The second input module 2132 includes a connector that can be physically connected to the external electronic device 2102, such as an HDMI connector, a USB connector, an SD card connector, or an audio connector (e.g., a headphone connector).

[0130] The display module 2140 provides visual information to the user and includes a display panel 2141, a scan driver 2142, and a data driver 2143. The display module 2140 further includes a window, a chassis, and a bracket for protecting the display panel 2141.

[0131] The display panel 2141 may be a liquid crystal display panel, an organic light emitting display panel, or an inorganic light emitting display panel, and the type of the display panel 2141 is not particularly limited. The display panel 2141 may be a rigid type or a rollable or foldable flexible type. The display module 2140 may further include a supporter, bracket, or heat dissipation member for supporting the display panel 2141.

[0132] The scan driver 2142 is a driver chip and is mounted on the display panel 2141. Alternatively, the scan driver 2142 may be integrated into the display panel 2141. For example, the scan driver 2142 includes an ASG (Amorphous Silicon TFT Gate driver circuit), an LTPS (Low Temperature Polycrystalline Silicon TFT Gate driver circuit), or an OSG (Oxide Semiconductor TFT Gate driver circuit) internalized in the display panel 2141. The scan driver 2142 receives control signals from the controller and outputs scan signals to the display panel 2141 in response to the control signals.

[0133] In one embodiment of the present invention, the scan driver 2142 uses a PMOS transistor to generate a scan signal for turning on an NMOS transistor of each pixel, and provides the scan signal to a plurality of pixels row by row in a sequential driving period, and provides the scan signal to the plurality of pixels substantially simultaneously in a simultaneous driving period.

[0134] The display panel 2141 further includes a light emitting driver, which outputs a light emitting signal to the display panel 2141 in response to a control signal received from the controller. The light emitting driver can be formed separately from the scan driver 2142 or can be integrated into the scan driver 2142.

[0135] The data driver 2143 receives a control signal from the controller, converts image data into an analog voltage (for example, a data voltage) in response to the control signal, and then outputs the data voltage to the display panel 2141 .

[0136] The data driver 2143 can be integrated into other components (for example, the controller). The functions of the interface switching circuit and timing control circuit of the controller can also be integrated into the data driver 2143.

[0137] The display module 2140 further includes a voltage generating circuit, etc. The voltage generating circuit outputs various voltages required to drive the display panel 2141.

[0138] The power supply module 2150 supplies power to the components of the electronic device 2101. The power supply module 2150 includes a battery that charges the power supply voltage. The battery may be a non-rechargeable primary battery, a rechargeable secondary battery, or a fuel cell. The power supply module 2150 includes a power management integrated circuit (PMIC). The PMIC supplies optimized power to each of the modules described above and below. The power supply module 2150 includes a wireless power transmitting and receiving component electrically connected to the battery. The wireless power transmitting and receiving component includes multiple coil-shaped antenna radiators.

[0139] The electronic device 2101 further includes an internal module 2160 and an external module 2170. The internal module 2160 includes a sensor module 2161, an antenna module 2162, and an acoustic output module 2163. The external module 2170 includes a camera module 2171, a light module 2172, and a communication module 2173.

[0140] The sensor module 2161 senses input from the user's body or input from the pen of the first input module 2131, and generates an electrical signal or data value corresponding to the input. The sensor module 2161 includes at least one of a fingerprint sensor 2161-1, an input sensor 2161-2, and a digitizer 2161-3.

[0141] Fingerprint sensor 2161-1 generates a data value corresponding to a user's fingerprint and includes either an optical or capacitive fingerprint sensor.

[0142] The input sensor 2161-2 generates a data value corresponding to coordinate information of an input by the user's body or a pen. The input sensor 2161-2 generates a data value representing the amount of capacitance change due to the input. The input sensor 2161-2 senses an input by a passive pen or transmits and receives data to and from an active pen.

[0143] The input sensor 2161-2 can also measure biological signals such as blood pressure, water content, or body fat. For example, when a user touches a part of their body to the sensor layer or sensing panel and does not move for a certain period of time, the input sensor 2161-2 senses the biological signal based on the electric field change caused by the part of their body and outputs information desired by the user to the display module 2140.

[0144] The digitizer 2161-3 generates data values ​​corresponding to the coordinate information of the input by the pen. The digitizer 2161-3 generates data values ​​representing the amount of electromagnetic change caused by the input. The digitizer 2161-3 senses input by a passive pen or transmits and receives data to and from an active pen.

[0145] At least one of the fingerprint sensor 2161-1, the input sensor 2161-2, and the digitizer 2161-3 may be implemented in a sensor layer formed on the display panel 2141 by a continuous process. The fingerprint sensor 2161-1, the input sensor 2161-2, and the digitizer 2161-3 are disposed on the upper side of the display panel 2141, and one of the fingerprint sensor 2161-1, the input sensor 2161-2, and the digitizer 2161-3, for example, the digitizer 2161-3, is disposed on the lower side of the display panel 2141.

[0146] At least two of the fingerprint sensor 2161-1, the input sensor 2161-2, and the digitizer 2161-3 are formed by the same process to be integrated into one sensing panel. When integrated into one sensing panel, the sensing panel is disposed between the display panel 2141 and a window disposed above the display panel 2141. According to one embodiment, the sensing panel may also be disposed on the window, and the position of the sensing panel is not particularly limited.

[0147] At least one of the fingerprint sensor 2161-1, the input sensor 2161-2, and the digitizer 2161-3 is built into the display panel 2141. That is, at least one of the fingerprint sensor 2161-1, the input sensor 2161-2, and the digitizer 2161-3 can be formed simultaneously in the process of forming elements (e.g., light-emitting elements, transistors, etc.) included in the display panel 2141.

[0148] Additionally, the sensor module 2161 may generate an electrical signal or a data value corresponding to an internal or external state of the electronic device 2101. The sensor module 2161 may further include, for example, a gesture sensor, a gyro sensor, a barometric pressure sensor, a magnetic sensor, an acceleration sensor, a grip sensor, a proximity sensor, a color sensor, an IR (infrared) sensor, a biometric sensor, a temperature sensor, a humidity sensor, or an illuminance sensor.

[0149] The antenna module 2162 includes one or more antennas for transmitting or receiving signals or power to or from the outside. According to one embodiment, the communication module 2173 transmits or receives signals to or from the external electronic device 2102 via an antenna suitable for the communication method. The antenna pattern of the antenna module 2162 may be integrated into one component of the display module 2140 (e.g., the display panel 2141) or the input sensor 2161-2.

[0150] The audio output module 2163 is a device for outputting audio signals to the outside of the electronic device 2101, and includes, for example, a speaker used for general purposes such as multimedia playback or recording playback, and a receiver used exclusively for receiving telephone calls. According to one embodiment, the receiver is formed integrally with or separately from the speaker. The audio output pattern of the audio output module 2163 may also be integrated into the display module 2140.

[0151] The camera module 2171 captures still and video images. In one embodiment, the camera module 2171 includes one or more lenses, image sensors, or image signal processors. The camera module 2171 further includes an infrared camera to measure the presence or absence of a user, the user's position, the user's line of sight, etc.

[0152] The light module 2172 provides light. The light module 2172 includes a light emitting diode or a xenon lamp. The light module 2172 operates in conjunction with the camera module 2171 or independently.

[0153] The communication module 2173 supports the establishment of a wired or wireless communication channel between the electronic device 2101 and the external electronic device 2102 and the execution of communication through the established communication channel. The communication module 2173 includes one or all of a wireless communication module, such as a cellular communication module, a short-range wireless communication module, or a global navigation satellite system (GNSS) communication module, and a wired communication module, such as a local area network (LAN) communication module or a power line communication module. The communication module 2173 communicates with the external electronic device 2102 through a short-range communication network, such as Bluetooth, WiFi Direct, or Infrared Data Association (IrDA), or a long-range communication network, such as a cellular network, the Internet, or a computer network (e.g., LAN or WAN). The above-mentioned various types of communication modules 2173 may be implemented on a single chip or on separate chips.

[0154] The input module 2130 , the sensor module 2161 , the camera module 2171 , and the like are used in conjunction with the processor 2110 to control the operation of the display module 2140 .

[0155] The processor 2110 outputs commands or data to the display module 2140, the audio output module 2163, the camera module 2171, or the light module 2172 based on input data received from the input module 2130. For example, the processor 2110 generates image data corresponding to input data applied by a mouse, an active pen, or the like, and outputs the image data to the display module 2140, or generates command data corresponding to the input data and outputs the command data to the camera module 2171 or the light module 2172. If no input data is received from the input module 2130 for a certain period of time, the processor 2110 can switch the operation mode of the electronic device 2101 to a low power mode or a sleep mode to reduce power consumption by the electronic device 2101.

[0156] The processor 2110 outputs a command or data to the display module 2140, the audio output module 2163, the camera module 2171, or the light module 2172 based on the sensory data received from the sensor module 2161. For example, the processor 2110 compares authentication data applied by the fingerprint sensor 2161-1 with authentication data stored in the memory 2120, and then performs an application based on the comparison result. The processor 2110 issues a command or outputs corresponding image data to the display module 2140 based on the sensory data sensed by the input sensor 2161-2 or the digitizer 2161-3. If the sensor module 2161 includes a temperature sensor, the processor 2110 can receive temperature data on the measured temperature from the sensor module 2161 and further perform brightness correction on the image data based on the temperature data.

[0157] The processor 2110 receives measurement data on the presence or absence of a user, the user's position, the user's line of sight, etc. from the camera module 2171. The processor 2110 further performs brightness correction on the image data based on the measurement data. For example, the processor 2110, having determined the presence or absence of a user from the input from the camera module 2171, outputs image data whose brightness has been corrected by the data switching circuit 2112-2 or the gamma correction circuit 2112-3 to the display module 2140.

[0158] Some of the components are connected to each other via a peripheral communication method, such as a bus, a general purpose input / output (GPIO), a serial peripheral interface (SPI), a mobile industry processor interface (MIPI), or an ultrapath interconnect (UPI) link, and exchange signals (e.g., commands or data) with each other. The processor 2110 communicates with the display module 2140 via a mutually agreed-upon interface, and may use, for example, any one of the communication methods described above, but is not limited to the above communication methods.

[0159] The electronic device 2101 according to various embodiments disclosed herein may be a device in various forms, including, for example, at least one of a portable communication device (e.g., a smartphone), a computing device, a portable multimedia device, a portable medical device, a camera, a wearable device, or a consumer electronic device. The electronic device 2101 according to embodiments disclosed herein is not limited to the above devices. [Industrial Applicability]

[0160] The present invention can be applied to any display device and electronic device including the same, such as a digital TV, a 3D TV, a mobile phone, a smartphone, a VR device, a PC, a tablet computer, a laptop computer, a home electronic device, a PDA, a PMP, a digital camera, a music player, a portable game console, a navigation system, etc.

[0161] Although the present invention has been described with reference to various embodiments, those skilled in the art will understand that various modifications and variations can be made to the present invention without departing from the spirit and scope of the present invention as defined in the claims below. [Explanation of symbols]

[0162] 100, 730: Scan driver 200, 400, 500, 600: Stage 210: Logic circuit 220: Input circuit 230: Node isolation circuit 240: Boost circuit 250: Node control circuit 260: Output circuit 270: Simultaneous drive circuit 700:Display device 710: Display panel 720: Data driver 740: Light emitting driver 750: Controller

Claims

1. A scan driver including a plurality of stages, At least one stage of the plurality of stages comprises: a logic circuit that controls a voltage of the first node and a voltage of the second node based on an input signal, a first clock signal, and a second clock signal during a sequential driving period; an output circuit that receives the first clock signal and the simultaneous drive signal and outputs a scan signal in response to a voltage at the first node and a voltage at the second node; a simultaneous drive circuit that controls the voltage of the first node and the voltage of the second node in response to an inverted simultaneous drive signal so that the output circuit outputs the simultaneous drive signal as the scan signal during a simultaneous drive period.

2. the simultaneous driving signal has a first low gate voltage in the sequential driving period and a high gate voltage in the simultaneous driving period; 2. The scan driver according to claim 1, wherein the inverted simultaneous drive signal has the high gate voltage in the sequential drive period and has a second low gate voltage lower than the first low gate voltage in the simultaneous drive period.

3. the simultaneous driving signal changes from the high gate voltage to the first low gate voltage at the start of the sequential driving period; 3. The scan driver of claim 2, wherein the inverted simultaneous driving signal changes to the first low gate voltage of the simultaneous driving signal and then changes from the second low gate voltage to the high gate voltage during the sequential driving period.

4. In the simultaneous driving section, the simultaneous drive circuit applies a first low gate voltage to the first node and a high gate voltage to the second node in response to the inverted simultaneous drive signal; 2. The scan driver according to claim 1, wherein the output circuit outputs the simultaneous drive signal having the high gate voltage as the scan signal.

5. In the sequential driving section, the logic circuit controls the voltage of the first node to the high level and the voltage of the second node to the low level when the first clock signal has a low level and the input signal has a high level; 2. The scan driver according to claim 1, wherein the output circuit outputs the first clock signal as the scan signal in response to the voltage of the first node having the high level and the voltage of the second node having the low level.

6. 2. The scan driver according to claim 1, wherein all transistors included in the at least one stage are PMOS transistors.

7. The simultaneous drive circuit includes:

2. The scan driver of claim 1, further comprising a first transistor including a gate receiving the inverted simultaneous drive signal, a first terminal receiving a first low gate voltage, and a second terminal connected to the first node.

8. The simultaneous drive circuit includes:

8. The scan driver of claim 7, further comprising a second transistor having a gate receiving the inverted simultaneous drive signal, a first terminal receiving a high gate voltage, and a second terminal connected to the second node.

9. The simultaneous drive circuit includes:

8. The scan driver of claim 7, further comprising a fourth capacitor having a first electrode connected to the second node and a second electrode receiving the simultaneous drive signal.

10. The output circuit a third transistor including a gate connected to the second node, a first terminal for receiving the first clock signal, and a second terminal connected to an output node at which the scan signal is output; a fourth transistor having a gate connected to the first node, a first terminal connected to the output node, and a second terminal for receiving the simultaneous drive signal.

11. The logic circuit an input circuit responsive to the first clock signal to transmit the input signal to a third node; a node isolation circuit connected between the third node and the first node; a boost circuit that boosts the voltage of the first node based on the second clock signal; a node control circuit that controls the voltage of the second node based on the first clock signal, the second clock signal, the voltage of the first node, and the simultaneous drive signal.

12. The input circuit 12. The scan driver of claim 11, further comprising a fifth transistor including a gate receiving the first clock signal, a first terminal receiving the input signal, and a second terminal connected to the third node.

13. The node isolation circuit 12. The scan driver of claim 11, further comprising a sixth transistor including a gate receiving the simultaneous drive signal, a first terminal connected to the third node, and a second terminal connected to the first node.

14. The boost circuit comprises: a seventh transistor including a gate connected to the first node, a first terminal, and a second terminal for receiving the second clock signal; a first capacitor having a first electrode connected to the first terminal of the seventh transistor and a second electrode connected to the first node.

15. The node control circuit an eighth transistor including a gate receiving the first clock signal, a first terminal receiving the simultaneous drive signal, and a second terminal connected to a fourth node; a ninth transistor including a gate connected to the first node, a first terminal for receiving the first clock signal, and a second terminal connected to the fourth node; a tenth transistor including a gate receiving a first low gate voltage, a first terminal connected to the fourth node, and a second terminal connected to a fifth node; a second capacitor including a first electrode connected to the fifth node and a second electrode connected to a sixth node; an eleventh transistor including a gate connected to the fifth node, a first terminal connected to the sixth node, and a second terminal; a twelfth transistor including a gate connected to the fifth node, a first terminal connected to the second terminal of the eleventh transistor, and a second terminal receiving the second clock signal; a thirteenth transistor including a gate receiving the second clock signal, a first terminal connected to the sixth node, and a second terminal connected to the second node; a third capacitor including a first electrode receiving the first clock signal and a second electrode connected to the second node; a fourteenth transistor including a gate connected to the first node, a first terminal for receiving the first clock signal, and a second terminal connected to the second node.

16. The at least one stage comprises:

2. The scan driver according to claim 1, further comprising a reset circuit that transmits the first clock signal to the first node in response to a reset signal, and transmits the simultaneous drive signal to the second node in response to the reset signal.

17. The reset circuit a fifteenth transistor including a gate for receiving the reset signal, a first terminal for receiving the first clock signal, and a second terminal connected to a third node; a sixteenth transistor including a gate receiving the reset signal, a first terminal connected to the second node, and a second terminal receiving the simultaneous drive signal.

18. A scan driver including a plurality of stages, At least one stage of the plurality of stages comprises: a logic circuit that receives the input signal, the first clock signal, the second clock signal, and the simultaneous drive signal and is coupled to the first node and the second node; a first transistor including a gate receiving an inverted simultaneous drive signal, a first terminal receiving a first low gate voltage, and a second terminal connected to the first node; a second transistor having a gate receiving the inverted simultaneous drive signal, a first terminal receiving a high gate voltage, and a second terminal connected to the second node; a third transistor including a gate connected to the second node, a first terminal for receiving the first clock signal, and a second terminal connected to an output node at which a scan signal is output; a fourth transistor having a gate connected to the first node, a first terminal connected to the output node, and a second terminal for receiving the simultaneous drive signal.

19. The logic circuit a fifth transistor including a gate receiving the first clock signal, a first terminal receiving the input signal, and a second terminal connected to a third node; a sixth transistor including a gate receiving the simultaneous drive signal, a first terminal connected to the third node, and a second terminal connected to the first node; a seventh transistor including a gate connected to the first node, a first terminal, and a second terminal for receiving the second clock signal; a first capacitor including a first electrode connected to the first terminal of the seventh transistor and a second electrode connected to the first node; an eighth transistor including a gate receiving the first clock signal, a first terminal receiving the simultaneous drive signal, and a second terminal connected to a fourth node; a ninth transistor including a gate connected to the first node, a first terminal for receiving the first clock signal, and a second terminal connected to the fourth node; a tenth transistor including a gate receiving the first low gate voltage, a first terminal connected to the fourth node, and a second terminal connected to a fifth node; a second capacitor including a first electrode connected to the fifth node and a second electrode connected to a sixth node; an eleventh transistor including a gate connected to the fifth node, a first terminal connected to the sixth node, and a second terminal; a twelfth transistor including a gate connected to the fifth node, a first terminal connected to the second terminal of the eleventh transistor, and a second terminal receiving the second clock signal; a thirteenth transistor including a gate receiving the second clock signal, a first terminal connected to the sixth node, and a second terminal connected to the second node; a third capacitor including a first electrode receiving the first clock signal and a second electrode connected to the second node; a fourteenth transistor including a gate connected to the first node, a first terminal for receiving the first clock signal, and a second terminal connected to the second node.

20. a display panel including a plurality of pixels; a data driver for providing data signals to the plurality of pixels; a scan driver including a plurality of stages for providing scan signals to the plurality of pixels; an emission driver that provides emission signals to the plurality of pixels; a controller for controlling the data driver, the scan driver, and the light emission driver; At least one stage of the plurality of stages comprises: a logic circuit that controls a voltage of the first node and a voltage of the second node based on an input signal, a first clock signal, and a second clock signal during a sequential driving period; an output circuit that receives the first clock signal and the simultaneous drive signal and outputs a scan signal in response to a voltage at the first node and a voltage at the second node; a simultaneous drive circuit that controls the voltage of the first node and the voltage of the second node in response to an inverted simultaneous drive signal so that the output circuit outputs the simultaneous drive signal as the scan signal during a simultaneous drive period.

21. a processor for providing input image data; a display device that receives the input image data from the processor and displays an image based on the input image data; The display device includes: a display panel including a plurality of pixels; a data driver for providing data signals to the plurality of pixels; a scan driver including a plurality of stages for providing scan signals to the plurality of pixels; an emission driver that provides emission signals to the plurality of pixels; a controller for controlling the data driver, the scan driver, and the light emission driver; At least one stage of the plurality of stages comprises: a logic circuit that controls a voltage of the first node and a voltage of the second node based on an input signal, a first clock signal, and a second clock signal during a sequential driving period; an output circuit that receives the first clock signal and the simultaneous drive signal and outputs a scan signal in response to a voltage at the first node and a voltage at the second node; a simultaneous drive circuit that controls the voltage of the first node and the voltage of the second node in response to an inverted simultaneous drive signal so that the output circuit outputs the simultaneous drive signal as the scan signal during a simultaneous drive period.

Images