Automated mapping of event-based simulation data to cycle-based simulation in a hybrid hardware debugging platform

Abstract

For example, while an event based simulation may provide a highly accurate simulation environment, the speed of execution is dependent on the size of the design associated with the simulation and the level of activity within the simulation.SOLUTION: A computer-implemented method is provided. Aspects include receiving first waveform data in a first format, the first waveform data including event-based simulation data. Aspects include generating second waveform data in a second format based on the first waveform data, wherein the second waveform data conforms to a cycle-based simulation environment. Aspects include performing one or more debug operations by processing the second waveform data in the cycle-based simulation environment.SELECTED DRAWING: Figure 5

Description

[Technical Field]

[0001] The present disclosure relates generally to event-based simulation data, and more particularly to automatic mapping of event-based simulation data to cycle-based simulation in a hybrid hardware debug platform. [Background technology]

[0002] A variety of feature-rich tools are available for simulating integrated circuit (IC) designs (e.g., application specific integrated circuit (ASIC) designs) in conjunction with the verification of the IC design before manufacturing. For example, some approaches may use cycle-based simulation or event-based simulation in conjunction with the verification of the IC design.

[0003] Cycle-based simulation (also referred to herein as cycle simulation) is a technique for digital circuit simulation that calculates the steady-state response of a circuit at each clock cycle. Cycle-based simulation does not simulate detailed circuit timing. Rather, for example, cycle-based simulation provides circuit signals for each clock cycle. Cycle-based simulation evaluates logic between state elements and / or ports every cycle. For example, each logic element is evaluated once per cycle, which can support increased simulation speed. Cycle-based simulators are suitable for simulating synchronous logic designs. Summary of the Invention [Problem to be solved by the invention]

[0004] Event-based simulation (also referred to herein as event simulation) is a technique for simulating digital circuits based on events in the logic. In event-based simulation, outputs are evaluated in response to input events when the input events change. For example, an event-based simulator may operate by propagating events through the design. Event-based simulation is relatively slow compared to cycle-based simulation. For example, event-based simulation may provide a highly accurate simulation environment, but execution speed depends on the size of the design associated with the simulation and the level of activity within the simulation. Verilog-XL is an example of an event-based simulator. [Means for solving the problem]

[0005] Embodiments of the present disclosure are directed to a computer-implemented method for automatically mapping event-based simulation data to cycle-based simulation in a hybrid hardware debug platform.

[0006] An exemplary embodiment of the present disclosure is directed to a computer-implemented method comprising: receiving first waveform data of a first format, wherein the first waveform data includes event-based simulation data; generating second waveform data of a second format based on the first waveform data, wherein the second waveform data is compatible with a cycle-based simulation environment; and performing one or more debug operations by processing the second waveform data within the cycle-based simulation environment.

[0007] An exemplary embodiment of the present disclosure includes a computing system comprising a memory having computer-readable instructions and one or more processors for executing the computer-readable instructions, the computer-readable instructions controlling the one or more processors to perform operations including receiving first waveform data in a first format, where the first waveform data comprises event-based simulation data; generating second waveform data in a second format based on the first waveform data, where the second waveform data is compatible with a cycle-based simulation environment; and performing one or more debug operations by processing the second waveform data within the cycle-based simulation environment.

[0008] An exemplary embodiment of the present disclosure includes a computer program product comprising a computer-readable storage medium having program instructions embodied thereon, the program instructions being executable by a processor to cause the processor to perform operations including receiving first waveform data in a first format, where the first waveform data includes event-based simulation data; generating second waveform data in a second format based on the first waveform data, where the second waveform data is compatible with a cycle-based simulation environment; and performing one or more debug operations by processing the second waveform data within the cycle-based simulation environment.

[0009] Other embodiments of the present disclosure implement features of the above-described methods in computer systems and computer program products.

[0010] Additional technical features and advantages are realized through the techniques of the present disclosure. Embodiments and aspects of the present disclosure are described in detail herein and are considered a part of the claimed subject matter. For a better understanding, please refer to the detailed description and drawings. [Brief explanation of the drawings]

[0011] The particulars of the exclusive rights set forth herein are particularly pointed out and distinctly claimed in the claims at the end of the specification. The foregoing and other features and advantages of embodiments of the present disclosure will become apparent from the following detailed description taken in conjunction with the accompanying drawings.

[0012] [Figure 1] FIG. 1 shows a block diagram of an exemplary computer system for use in conjunction with one or more embodiments of the present disclosure.

[0013] [Figure 2] 1 shows an example timing diagram illustrating the difference between cycle-based simulation and event-based simulation.

[0014] [Figure 3] 1 illustrates a flow diagram for supporting hardware logic design and debugging in accordance with one or more embodiments of the present disclosure.

[0015] [Figure 4] FIG. 1 illustrates a flow diagram illustrating a platform that supports automatically mapping event-based simulation data to cycle-based simulation, in accordance with one or more embodiments of the present disclosure.

[0016] [Figure 5] 1 illustrates an example flowchart of a method for supporting automatic mapping of event-based simulation data to cycle-based simulation in a hybrid hardware debug platform, in accordance with one or more embodiments of the present disclosure.

[0017] [Figure 6] 1 illustrates an example timing diagram associated with automatically mapping event-based simulation data to cycle-based simulation in a hybrid hardware debug platform, in accordance with one or more embodiments of the present disclosure.

[0018] [Figure 7] 1 illustrates an example workflow associated with designing and debugging an IC design in accordance with one or more embodiments of the present disclosure.

[0019] [Figure 8] 1 illustrates an exemplary hybrid hardware debug platform in accordance with one or more embodiments of the present disclosure.

[0020] [Figure 9] 1 illustrates an example flowchart of a method for supporting automatic mapping of event-based simulation data to cycle-based simulation in a hybrid hardware debug platform, in accordance with one or more embodiments of the present disclosure. DETAILED DESCRIPTION OF THE INVENTION

[0021] Embodiments of the present disclosure are directed to a computer-implemented method for automatically mapping event-based simulation data to cycle-based simulation in a hybrid hardware debug platform.

[0022] An exemplary embodiment of the present disclosure is directed to a computer-implemented method comprising: receiving first waveform data of a first format, where the first waveform data includes event-based simulation data; generating second waveform data of a second format based on the first waveform data, where the second waveform data is compatible with a cycle-based simulation environment; and performing one or more debug operations by processing the second waveform data within the cycle-based simulation environment. The computer-implemented method provides the advantage of effective debugging through technical improvements including converting event-based simulation data (i.e., events are time-granular and data does not fit into a cycle-based simulation environment) into equivalent cycle-based simulation data for debugging.

[0023] An exemplary embodiment of the present disclosure includes a computing system including a memory having computer-readable instructions and one or more processors for executing the computer-readable instructions. The computer-readable instructions control the one or more processors to perform operations including receiving first waveform data in a first format, where the first waveform data includes event-based simulation data; generating second waveform data in a second format based on the first waveform data, where the second waveform data is compatible with a cycle-based simulation environment; and performing one or more debug operations by processing the second waveform data within the cycle-based simulation environment. These operations provide the advantage of effective debugging through technical improvements including converting event-based simulation data (i.e., events are time-granular and data does not fit into a cycle-based simulation environment) into equivalent cycle-based simulation data for debugging.

[0024] An exemplary embodiment of the present disclosure includes a computer program product comprising a computer-readable storage medium having program instructions embodied thereon. The program instructions are executable by a processor to cause the processor to perform operations including receiving first waveform data in a first format, where the first waveform data includes event-based simulation data; generating second waveform data in a second format based on the first waveform data, where the second waveform data is compatible with a cycle-based simulation environment; and performing one or more debug operations by processing the second waveform data within the cycle-based simulation environment. These operations provide an advantage of effective debugging through technical improvements including converting event-based simulation data (i.e., events are time-granular and data does not fit into a cycle-based simulation environment) into equivalent cycle-based simulation data for debugging.

[0025] In addition to one or more of the features described herein, generating the second waveform data includes transforming the first waveform data into the second waveform data by sampling signal waveforms included in the first waveform data according to a sampling rate. The sampling operation provides advantages and technical improvements in supporting effective mapping between the first waveform data (i.e., events have time granularity and data does not fit into a cycle-based simulation environment) and the second waveform data (i.e., events occur on clock edges and fit into a cycle-based simulation environment), thus providing waveform data that designers are more familiar with and can use to effectively debug integrated circuit designs.

[0026] In addition to one or more of the features described herein, the method and operations include selecting a target abstraction level from among a set of candidate abstraction levels associated with transforming first waveform data into second waveform data based on a parameter, where the parameter is selected from the group consisting of a time parameter associated with transforming the first waveform data into the second waveform data and a data preservation parameter associated with transforming the first waveform data into the second waveform data; and determining a sampling rate based on the target abstraction level. These operations provide advantages and technical improvements that support various levels of abstraction for determining the sampling rate. Determining the sampling rate based on a target abstraction level for transforming the event-based simulation data into cycle-based simulation data supports balancing the amount of time to complete the conversion from event-based simulation data to cycle-based simulation data and the data preservation associated with the conversion.

[0027] In addition to one or more of the features described herein, determining the sampling rate is based on a first abstraction level among the set of candidate abstraction levels, and includes: identifying, for at least two signal waveforms included in the first waveform data, a target amount of events associated with each of the at least two signal waveforms; calculating, for each of the at least two signal waveforms included in the first waveform data, a time duration between two consecutive events included in the target amount of events; and selecting a minimum time duration among the time durations as the sampling rate. Determining the sampling rate based on a target abstraction level for transforming the event-based simulation data to cycle-based simulation data supports striking a balance between the amount of time to complete the conversion from event-based simulation data to cycle-based simulation data and data preservation associated with the conversion.

[0028] In addition to one or more of the features described herein, determining the sampling rate is based on a first abstraction level among the set of candidate abstraction levels and includes an assumption that the fastest clock among the signal waveforms included in the first waveform data can be used as the sampling rate. These operations provide advantages and technical improvements in supporting adjusting the sampling rate in conjunction with transforming the first waveform data into the second waveform data.

[0029] In addition to one or more of the features described herein, determining the sampling rate is based on a second abstraction level from the set of candidate abstraction levels and includes: identifying, for at least two signal waveforms included in the first waveform data, all events associated with each of the at least two signal waveforms; calculating, for each of the at least two signal waveforms included in the first waveform data, a time duration between two consecutive events included in all the events; and selecting a minimum time duration from the time durations as the sampling rate. Determining the sampling rate based on a target abstraction level for transforming the event-based simulation data to cycle-based simulation data supports striking a balance between the amount of time to complete the conversion from event-based simulation data to cycle-based simulation data and data preservation associated with the conversion.

[0030] In addition to one or more of the features described herein, determining the sampling rate is based on a second abstraction level from the set of candidate abstraction levels and includes assuming there is no skew between events among the signal waveforms included in the first waveform data. This operation provides an advantage and technical improvement that supports trading off loss of skew information when transforming event-based simulation data into cycle-based simulation data for reduced processing time.

[0031] In addition to one or more of the features described herein, determining the sampling rate is based on a third abstraction level among the set of candidate abstraction levels, and includes, for at least two signal waveforms included in the first waveform data, identifying all events associated with each of the at least two signal waveforms; calculating a time duration between the events associated with each of the at least two signal waveforms; and selecting a minimum time duration among the time durations as the sampling rate, the minimum time duration being between a first event associated with the first signal waveform and a second event associated with the second signal waveform. Determining the sampling rate based on a target abstraction level for transforming the event-based simulation data to cycle-based simulation data supports striking a balance between the amount of time to complete the conversion from event-based simulation data to cycle-based simulation data and data preservation associated with the conversion.

[0032] In addition to one or more of the features described herein, the time parameter is a target time duration associated with transforming the first waveform data into the second waveform data. These operations provide advantages and technical improvements in support of adjusting the amount of time that occurs in conjunction with transforming the first waveform data into the second waveform data.

[0033] In addition to one or more of the features described herein, the data preservation parameter is associated with preserving skew information associated with the signal waveform included in the first waveform data. These operations provide advantages and technical improvements that support adjusting the amount of information (e.g., skew information) that is preserved or omitted in conjunction with transforming the first waveform data into the second waveform data.

[0034] Various aspects of the present disclosure are described through text, flowcharts, block diagrams of computer systems, and / or block diagrams of machine logic included in computer program product (CPP) embodiments. For any flowchart, depending on the technology involved, operations may be performed in an order different from that shown in a given flowchart. For example, again depending on the technology involved, two operations shown in successive flowchart blocks may be performed in the reverse order, as a single integrated step, simultaneously, or in an at least partially overlapping manner.

[0035] A computer program product embodiment ("CPP embodiment" or "CPP") is a term used in this disclosure to describe any set of one or more storage media (also referred to as "media") collectively included in a set of one or more storage devices that collectively contain machine-readable code corresponding to instructions and / or data for performing the computer operations specified in a given CPP claim. A "storage device" is any tangible device that can hold and store instructions for use by a computer processor. The computer-readable storage medium may be, but is not limited to, an electronic storage medium, a magnetic storage medium, an optical storage medium, an electromagnetic storage medium, a semiconductor storage medium, a mechanical storage medium, or any suitable combination of the foregoing. Some known types of storage devices that include these media include diskettes, hard disks, random access memory (RAM), read-only memory (ROM), erasable programmable read-only memory (EPROM or flash memory), static random access memory (SRAM), compact disk read-only memory (CD-ROM), digital versatile disk (DVD), memory stick, floppy disk, mechanically encoded device (such as pits / lands formed on the major surface of a punch card or disk), or any suitable combination of the foregoing. Computer-readable storage media, as the term is used in this disclosure, is not to be construed as storage in the form of a transient signal per se, such as radio waves or other freely propagating electromagnetic waves, electromagnetic waves propagating through a waveguide, light pulses passing through fiber optic cables, electrical signals communicated through wires, and / or other transmission media. As will be appreciated by those skilled in the art, data is typically moved at some infrequent time during the normal operation of the storage device, such as during access, defragmentation, or garbage collection, but the above does not qualify a storage device as transient because the data is not transient while it is stored.

[0036] 1 , computing environment 100 includes an example of an environment for executing at least a portion of computer code involved in performing the methodology of the present invention, such as automatically mapping event-based simulation data to a cycle-based simulation of a hybrid hardware debugging platform using a transformation engine 150. In addition to transformation engine 150, computing environment 100 includes, for example, computer 101, wide area network (WAN) 102, end user device (EUD) 103, remote server 104, public cloud 105, and private cloud 106. In this embodiment, computer 101 includes a set of processors 110 (including processing circuitry 120 and cache 121), communications fabric 111, volatile memory 112, persistent storage 113 (including operating system 122 and transformation engine 150 as identified above), a set of peripheral devices 114 (including a set of user interface (UI) devices 123, storage 124, and a set of Internet of Things (IoT) sensors 135), and network module 115. The remote server 104 includes a remote database 132. The public cloud 105 includes a gateway 130, a cloud orchestration module 131, a set of host physical machines 142, a set of virtual machines 143, and a set of containers 144.

[0037] Computer 101 may take the form of a desktop computer, a laptop computer, a tablet computer, a smartphone, a smartwatch or other wearable computer, a mainframe computer, a quantum computer, or any other form of computer or mobile device now known or later developed that is capable of executing programs, accessing a network, or querying a database, such as remote database 132. As is well understood in the field of computer technology, and depending on the technology, execution of a computer-implemented method may be distributed among multiple computers and / or among multiple locations. However, in this description of computing environment 100, for purposes of brevity, the detailed discussion focuses on a single computer, specifically computer 101. While computer 101 is not shown in FIG. 1 within the cloud, it may be located within the cloud. However, computer 101 is not required to reside within the cloud except to any extent that may be expressly indicated.

[0038] Processor set 110 includes one or more computer processors of any type now known or later developed. Processing circuitry 120 may be distributed across multiple packages, e.g., multiple linked integrated circuit chips. Processing circuitry 120 may implement multiple processor threads and / or multiple processor cores. Cache 121 is memory located within the processor chip package and is typically used for data or code that should be available for fast access by threads or cores executing on processor set 110. Cache memory is typically organized into multiple levels depending on relative proximity to the processing circuitry. Alternatively, some or all of the cache for a processor set may be located “off-chip.” In some computing environments, processor set 110 may be designed to operate with qubits and perform quantum computing.

[0039] Computer-readable program instructions are typically loaded onto computer 101 and cause processor set 110 of computer 101 to perform a series of operational steps, thereby realizing a computer-implemented method; the instructions so executed will thus instantiate the method set forth in the flowcharts and / or descriptions of the computer-implemented method contained herein (collectively referred to as the "methods of the present invention"). These computer-readable program instructions are stored in various types of computer-readable storage media, such as cache 121 and other storage media discussed below. The program instructions and associated data are accessed by processor set 110 to control and direct the execution of the methods of the present invention. In computing environment 100, at least a portion of the instructions for executing the methods of the present invention may be stored in transformation engine 150 in persistent storage 113.

[0040] Communications fabric 111 is the signal-conducting pathway that allows the various components of computer 101 to communicate with one another. Typically, this fabric is made up of switches and conductive pathways, such as those that make up buses, bridges, physical input / output ports, and the like. Other types of signal communication pathways may be used, such as fiber optic and / or wireless communication pathways.

[0041] Volatile memory 112 may be any type of volatile memory, now known or later developed. Examples include dynamic random access memory (RAM) or static RAM. Typically, volatile memory is characterized by random access, although this is not required unless expressly stated. In computer 101, volatile memory 112 is located in a single package and is internal to computer 101; however, alternatively or additionally, volatile memory may be distributed across multiple packages and / or located external to computer 101.

[0042] Persistent storage 113 is any form of non-volatile storage for a computer, now known or later developed. The non-volatility of this storage means that stored data is maintained regardless of whether power is supplied to computer 101 and / or directly to persistent storage 113. While persistent storage 113 may be read-only memory (ROM), typically at least a portion of persistent storage allows data to be written, data to be deleted, and data to be rewritten. Some well-known forms of persistent storage include magnetic disks and solid-state storage devices. Operating system 122 may take several forms, such as various known proprietary operating systems or open-source Portable Operating System Interface-type operating systems employing a kernel. The code contained in transformation engine 150 typically includes at least a portion of the computer code involved in performing the methods of the present invention.

[0043] Peripheral device set 114 includes a set of peripheral devices of computer 101. Data communication connections between peripheral devices and other components of computer 101 may be implemented in various ways, such as Bluetooth® connections, Near-Field Communication (NFC) connections, connections made by cable (such as a universal serial bus (USB)-type cable), insertion-type connections (e.g., a secure digital (SD) card), connections made over a local area communication network, and even connections made over a wide area network such as the Internet. In various embodiments, UI device set 123 may include components such as a display screen, speakers, microphones, wearable devices (such as goggles and smartwatches), keyboards, mice, printers, touchpads, game controllers, and haptic devices. Storage 124 may be external storage, such as an external hard drive, or insertable storage, such as an SD card. Storage 124 may be persistent and / or volatile. In some embodiments, storage 124 may take the form of a quantum computing storage device for storing data in the form of qubits. In embodiments where computer 101 is required to have a large amount of storage (e.g., where computer 101 stores and manages large databases locally), this storage may be provided by a peripheral storage device designed to store very large amounts of data, such as a storage area network (SAN) shared by multiple, geographically distributed computers. IoT sensor set 135 consists of sensors that can be used in Internet of Things applications. For example, one sensor may be a thermometer and another may be a motion detector.

[0044] Network module 115 is a collection of computer software, hardware, and firmware that enables computer 101 to communicate with other computers over WAN 102. Network module 115 may include hardware such as a modem or Wi-Fi® signal transceiver, software for packetizing and / or de-packetizing data for communication network transmission, and / or web browser software for communicating data over the Internet. In some embodiments, the network control and network forwarding functions of network module 115 are performed on the same physical hardware device. In other embodiments (e.g., embodiments utilizing software-defined networking (SDN)), the control and forwarding functions of network module 115 are performed on physically separate devices, such that the control function manages multiple different network hardware devices. Computer-readable program instructions for implementing the methods of the present invention may be downloaded to computer 101 from an external computer or external storage device, typically through a network adapter card or network interface included in network module 115.

[0045] WAN 102 is any now known or later developed wide area network (e.g., the Internet) capable of communicating computer data between remote locations using any technology for communicating computer data. In some embodiments, a WAN may be replaced and / or supplemented by a local area network (LAN) designed to communicate data between devices located in a local area, such as a Wi-Fi network. WANs and / or LANs typically include copper transmission cables, optical fiber transmissions, wireless transmissions, and computer hardware such as routers, firewalls, switches, gateway computers, and edge servers.

[0046] End-user device (EUD) 103 is any computer system used and controlled by an end user (e.g., a customer of the enterprise that operates computer 101) and may take any of the forms discussed above in connection with computer 101. EUD 103 typically receives useful and useful data from the operation of computer 101. For example, in the hypothetical case where computer 101 is designed to provide recommendations to the end user, the recommendations would typically be communicated from network module 115 of computer 101 over WAN 102 to EUD 103. In this manner, EUD 103 can display or otherwise present the recommendations to the end user. In some embodiments, EUD 103 may be a client device such as a thin client, a heavy client, a mainframe computer, a desktop computer, and the like.

[0047] Remote server 104 is any computer system that provides at least some data and / or functionality to computer 101. Remote server 104 may be controlled and used by the same entity that operates computer 101. Remote server 104 represents a machine that collects and stores useful and useful data for use by other computers, such as computer 101. For example, in the hypothetical case where computer 101 is designed and programmed to provide recommendations based on historical data, then this historical data may be provided to computer 101 from remote database 132 of remote server 104.

[0048] A public cloud 105 is any computer system available for use by multiple entities that provides on-demand availability of computer system resources and / or other computer functionality, particularly data storage (cloud storage) and computing power, without direct active management by users. Cloud computing typically leverages resource sharing to achieve consistency and economies of scale. Direct active management of the computing resources of the public cloud 105 is performed by the computer hardware and / or software of a cloud orchestration module 131. The computing resources provided by the public cloud 105 are typically implemented by virtual computing environments running on various computers comprising a host physical machine set 142, which is the universe of physical computers within and / or available to the public cloud 105. The virtual computing environments (VCEs) typically take the form of virtual machines from a virtual machine set 143 and / or containers from a container set 144. It is understood that these VCEs may be stored as images and may be transferred among and between various physical machine hosts, either as images or after instantiation of the VCEs. Cloud orchestration module 131 manages the transfer and storage of images, deploys new instantiations of VCE, and manages active instantiations of VCE deployments. Gateway 130 is a collection of computer software, hardware, and firmware that enables public cloud 105 to communicate over WAN 102.

[0049] We now provide some further explanation of virtual computing environments (VCEs). A VCE can be stored as an "image." A new, active instance of a VCE can be instantiated from the image. Two well-known types of VCEs are virtual machines and containers. A container is a VCE that uses operating system-level virtualization. This refers to an operating system feature where the kernel allows the existence of multiple isolated user space instances called containers. These isolated user space instances typically behave as actual computers from the perspective of programs running in them. A computer program running on a normal operating system can utilize all of the computer's resources, such as connected devices, files and folders, network shares, CPU power, and quantifiable hardware capabilities. However, a program running inside a container can only use the contents of the container and of the devices assigned to the container; this feature is known as containerization.

[0050] Private cloud 106 is similar to public cloud 105, except that computing resources are available only for use by a single enterprise. While private cloud 106 is shown in communication with WAN 102, in other embodiments, the private cloud may be completely disconnected from the Internet and accessible only through a local / private network. A hybrid cloud is a composite of multiple clouds of different types (e.g., private, community, or public cloud types), often implemented by different vendors. While each of the multiple clouds remains a separate, discrete entity, the larger hybrid cloud architecture is bound together by standardized or proprietary technologies that enable orchestration, management, and / or data / application portability between the constituent clouds. In this embodiment, both public cloud 105 and private cloud 106 are part of a larger hybrid cloud.

[0051] A container is a VCE that uses operating system-level virtualization. This refers to an operating system feature where the kernel allows the existence of multiple isolated user space instances, called containers. These isolated user space instances typically behave as actual computers from the perspective of programs running in them. A computer program running on a normal operating system can utilize all of the computer's resources, such as connected devices, files and folders, network shares, CPU power, and quantifiable hardware capabilities. However, a program running inside a container can only use the contents of the container and of the devices assigned to the container; this feature is known as containerization.

[0052] FIG. 2 shows an example timing diagram 200 illustrating some of the differences between cycle-based simulation and event-based simulation.

[0053] Timing diagram 200 shows waveforms of a clock signal 205 (“clk”), a data signal 210 (“d”), an output signal 215 (“I1(Event-Sim)”) associated with an event-based simulation, and an output signal 220 (“I1(Cycle-Sim)”) associated with a cycle-based simulation.

[0054] With respect to event-based simulation, time advances in specific steps (e.g., steps of variable width). In event-based simulation, events (also referred to herein as transitions) can occur at any time and are not limited to being aligned with a clock signal 205. Event-based simulation supports the time granularity at which events occur. For example, with reference to timing diagram 200 of FIG. 2, events associated with event-based simulation occur every 20 picoseconds (ps), although the time granularity is not limited thereto.

[0055] For cycle-based simulation, time advances on clock edges of clock signal 205. In cycle-based simulation, events occur on clock edges of clock signal 205. In cycle-based simulation, delays with respect to specific times (clock skew) are ignored. For example, with reference to output signal 220 and timing diagram 200 of FIG. 2, events associated with output signal 220 and cycle-based simulation occur on rising clock edges (also referred to herein as upticks) or falling clock edges (also referred to herein as downticks) of clock signal 205. Upticks and downticks are sometimes collectively referred to as "simticks." Data generated by cycle-based simulation has transitions at a "simtick" granularity.

[0056] Described herein are systems and techniques, example embodiments of which are described herein, that support the effective conversion of event-based simulation data (i.e., events are at time granularity) to equivalent cycle-based simulation data (i.e., events are at clock edges). For example, described herein are systems and techniques, example embodiments of which are described herein, that support the effective conversion of event-based waveform data (i.e., events are at time granularity) to equivalent cycle-based waveform data (i.e., events are at clock edges). The systems and techniques described herein support the conversion of event-based simulation data to cycle-based simulation data by determining a sampling rate at which to sample the event-based simulation data and further sampling the event-based simulation data according to the sampling rate.

[0057] Aspects of the techniques described herein support various levels of abstraction for determining the sampling rate, including determining the sampling rate based on a target abstraction level for transforming event-based simulation data to cycle-based simulation data, which supports balancing the amount of time to complete the conversion from event-based simulation data to cycle-based simulation data and data preservation associated with the conversion.

[0058] As described herein, systems and techniques are provided that support transforming event-based simulation data (e.g., third-party simulation data) associated with an event-based simulation tool into cycle-based simulation data associated with a cycle-based simulation tool. The event-based simulation data includes waveforms in a first format compatible with the event-based simulation tool, and the cycle-based simulation data includes waveforms in a second format compatible with the cycle-based simulation tool. As used herein, descriptions of transforming event-based simulation data into cycle-based simulation data, converting event-based simulation data into cycle-based simulation data, converting event-based simulation data into cycle-based simulation data, and mapping event-based simulation data to cycle-based simulation data may be used interchangeably.

[0059] Exemplary aspects of determining a sampling rate and applying the sampling rate in connection with transforming event-based simulation data into cycle-based simulation data are described below with reference to Figures 4, 5, 6, and 9.

[0060] FIG. 3 illustrates a flow diagram 300 for supporting hardware logic design and debugging in accordance with one or more embodiments of the present disclosure.

[0061] Referring to flow diagram 300, a hardware design coded in mixed language source code 301 (e.g., VHDL / Verilog) is compiled using an HDL compiler 302 (e.g., PORTALS, IBM EDA RTL compiler) and then simulated at 305 using a logic simulator 3051 (e.g., MESA, IBM EDA logic simulator), which may be supplemented with hardware accelerated simulation 3052 (e.g., using AWAN, IBM EDA hardware accelerated simulation). The simulation generates waveform data 307. Waveform data 307 may include all event traces (AET), which are logic simulation waveforms suitable for hardware logic debug 308. The AET format is a binary format for logic simulation waveform output, such as Cadence SHM, Synopsys FSDB, and the like.

[0062] Flow diagram 300 is an example of cycle-based simulation and debugging of a cycle-based simulation.

[0063] In accordance with one or more embodiments of the present disclosure, the systems and techniques described herein support shortening time to market for next-generation systems by automatically mapping event-based simulation data to cycle-based simulation.

[0064] The systems and techniques described herein for automatically mapping event-based simulation data to cycle-based simulation overcome shortcomings due to the lack of "plug-ins" provided by vendor companies to convert or translate the simulation data provided by those companies (i.e., for faster joint debugging of hardware / firmware and / or for emulation engines, RISCV-based designs). As described herein, the systems and techniques supported by aspects of the present disclosure provide a flexible and extensible platform for a wider range of use cases, while enabling highly efficient debugging of system logic.

[0065] Exemplary aspects of automatically mapping event-based simulation data to cycle-based simulation in a hybrid hardware debug platform are described herein with reference to FIGS.

[0066] 4 illustrates a flow diagram 400 illustrating a platform (e.g., a hybrid hardware debug platform) that supports automatically mapping event-based simulation data to cycle-based simulation according to an exemplary aspect of the present disclosure. The platform and flow diagram 400 may include aspects of the flow diagram 300 described herein, with repeated descriptions of similar elements omitted for brevity.

[0067] 4, mixed-language source code 401 is combined and compiled in HDL compiler 402. HDL compiler 402 outputs a compiled design, which is sent to plug-in component 403 (HDLOUT), from which debug assist elements 404 are generated. Plug-in component 403 (HDLOUT) may generate hardware description language (HDL) code (e.g., Verilog) for the hardware design. The HDL code is sent to vendor emulation flow 405, which outputs vendor waveforms (contained in vendor waveform data 4053) for specific hardware / firmware co-debug use cases.

[0068] Vendor emulation flow 405 is vendor-specific and may include a vendor compiler 4051, a vendor emulator 4052 (also referred to herein as a vendor waveform generator), and vendor waveform data 4053 (also referred to herein as vendor-proprietary waveform data). Vendor waveform data 4053 is output to wave converter 406. Wave converter 406 may use debug assist element 404 to generate waveform data 407 for use in debug operation 408 based on vendor waveform data 4053.

[0069] Thus, for example, the wave converter 406 may use a set of plug-ins within the platform framework to generate the waveform data 407 with additional instrumentation assistance. The aspects of the waveform data 407 provided by the wave converter 406 support effective debugging of the AET from emulation failures.

[0070] In one example, vendor emulator 4052 may be an event-based simulator, and vendor waveform data 4053 may include waveforms of signals generated based on vendor emulator 4052. The waveforms may correspond to different signals associated with the event-based simulation performed by vendor emulator 4052. Wave converter 406 may transform vendor waveform data 4053 into waveform data 407 using mapping and conversion techniques described herein. Waveform data 407 may include waveforms corresponding to a cycle-based simulation format supported by debug operations 408. For example, waveform data 407 may be in a format compatible with the cycle-based simulation environment (e.g., AET format, binary format).

[0071] In a production scenario, the hardware RTL can be in a given VHDL, with significant portions of the design based on Verilog™. The main simulation framework can be complemented with a hardware-accelerated simulation function based on a given logic simulator to generate simulation waveforms. Because debug operations for selected complex and system-wide scenarios may require fast interoperation of hardware / firmware system components, an emulation platform from a vendor can be used as an additional engine to complement hardware verification. For example, Verilog™ code can be generated using plugin components 403 and sent to vendor emulation flow 405 for specific hardware / firmware co-debug use cases. The generated waveform in the vendor-proprietary format can be transformed into the original HDL-compatible waveform by wave converter 406 using a new set of plugins, along with additional measurement assistance from debug assist elements 404.

[0072] Aspects of wave converter 406 may be implemented, for example, by all or a subset of computing environment 100 of Figure 1. For example, wave converter 406 may be implemented by, or be an example of, conversion engine 150 of Figure 1.

[0073] FIG. 5 illustrates an example flowchart of a method 500 for supporting automatic mapping of event-based simulation data to cycle-based simulation in a hybrid hardware debug platform, in accordance with one or more embodiments of the present disclosure.

[0074] Aspects of method 500 may be implemented, for example, by all or a subset of the computing environment 100 of Figure 1 or the platform of Figure 4. For example, aspects of method 500 may be implemented by the conversion engine 150 of Figure 1 or the wave converter 406 of Figure 4.

[0075] At 505, method 500 includes receiving vendor waveform data 4053. Vendor waveform data 4053 may be event-based simulation data having events at specific timestamps. Vendor waveform data 4053 may include signal waveforms associated with an event-based simulation (e.g., signal waveforms 605-620, described below with reference to FIG. 6). Event-based simulation data differs from cycle-based simulation data in that transitions occur at a "cycle-tick" granularity in cycle-based simulation data.

[0076] At 510, method 500 includes processing bender waveform data 4053. The processing of bender waveform data 4053 may be based on a sampling rate associated with transforming bender waveform data 4053 into waveform data 407. Aspects of processing bender waveform data 4053 are described with reference to 515-525.

[0077] At 515, method 500 includes selecting, based on the target performance parameter(s), a level of abstraction associated with sampling vendor waveform data 4053. For example, method 500 may include determining the level of abstraction based on time and data preservation parameters (e.g., data loss, preservation of skew information) associated with transforming vendor waveform data 4053 into waveform data 407.

[0078] In one example, the time parameter may be a target time constraint (e.g., target time duration, threshold time duration) associated with transforming the bender waveform data 4053 into the waveform data 407. In one example, the data preservation parameter may be associated with preserving or omitting skew information between signal waveforms included in the bender waveform data 4053.

[0079] At 520, the method 500 includes determining a sampling rate based on the abstraction level. For example, the method 500 may include automatically determining a sampling rate based on processing the vendor waveform data 4053 according to the abstraction level.

[0080] In some aspects, processing the vendor waveform data 4053 according to the abstraction level may include implementing one or more processing operations specific to the abstraction level to calculate the sampling rate. The method 500 may support multiple candidate abstraction levels (e.g., Level 1, Level 2, Level 3). An example of determining the sampling rate based on the abstraction level is described later herein with reference to FIG. 6.

[0081] In some embodiments, the method 500 includes calculating a sampling rate that can be equated to a "simtick" in a cycle-based simulation environment.

[0082] At 525, method 500 includes transforming vendor waveform data 4053 into waveform data 407 (cycle-based simulation data) based on the sampling rate determined at 520. Transforming vendor waveform data 4053 may include transforming vendor waveforms (signal waveforms associated with event-based simulation) included in vendor waveform data 4053 into logic simulation waveforms compatible with a hardware design language (HDL) for hardware logic debug. For example, transforming vendor waveform data 4053 may include transforming vendor waveforms (signal waveforms) included in vendor waveform data 4053 into waveforms in a cycle-based simulation format (e.g., binary format, AET format) supported by debug operation 408 and the cycle-based simulation environment.

[0083] At 530, method 500 includes performing a debug operation (e.g., via debug operation 408) based on waveform data 407. For example, method 500 may include performing the debug operation by processing waveform data 407 within a cycle-based simulation environment.

[0084] 6 illustrates an example timing diagram 600 associated with automatically mapping event-based simulation data to cycle-based simulation in a hybrid hardware debug platform, in accordance with one or more embodiments of the present disclosure. In the example of FIG. 6, time is in picoseconds (ps). Aspects of determining a sampling rate based on an abstraction level (e.g., at 520 of method 500 of FIG. 5) will now be described with reference to timing diagram 600 of FIG. 6.

[0085] In one example, signal waveforms 605 through 620 correspond to signals (e.g., signals 1 through 4), respectively, associated with an event-based simulation (e.g., an event-based simulation performed by vendor emulator 4052). Signal waveforms 605 through 620 may be included in vendor waveform data 4053 described with reference to Figure 4. It should be understood that vendor waveform data 4053 is not limited to signal waveforms 605 through 620 shown in Figure 6, and vendor emulation flow 405 may include signal waveforms (not shown) in addition to or in place of signal waveforms 605 through 620.

[0086] Abstraction Level 1: Determining the sampling rate according to Abstraction Level 1 may include looking at the first few events of each signal (e.g., Signal 1, Signal 2, and the like) and using the smallest amount of time between two consecutive events of the same signal as the sampling rate. In some aspects, determining the sampling rate according to Abstraction Level 1 assumes (or includes) that the fastest clock among the signals can be used as the sampling rate.

[0087] 6 , in one example of determining a sampling rate according to abstraction level 1, the wave converter 406 may review the first three events (e.g., uptick, downtick, uptick) of each signal (e.g., signal 1 through signal 4) starting from 0 ps to a certain point (e.g., 400 ps) so that the time window includes the first three events of each signal waveform. The wave converter 406 determines that the minimum amount of time between two consecutive events of the same signal among signals 1 through 4 is 50 ps. For example, the wave converter 406 determines that the minimum amount of time between two consecutive events of the same signal is the 50 ps difference between an uptick at 50 ps of signal 2 and a downtick at 100 ps of signal 2, e.g., 100 ps−50 ps=50 ps.

[0088] It should be understood that a reference to processing or analyzing a signal (eg, signal 1) includes processing or analyzing a signal waveform (eg, signal waveform 605) corresponding to that signal.

[0089] In some aspects, the amount of time associated with determining a sampling rate (also referred to herein as a scale factor) according to abstraction level 1 may be the smallest of abstraction levels 1 through 3. Transforming vendor waveform data 4053 into waveform data 407 using a sampling rate determined according to abstraction level 1 may preserve most, but not all, of the transition data contained in vendor waveform data 4053. The amount of time associated with completing the transformation according to abstraction level 1 may be the smallest of abstraction levels 1 through 3.

[0090] Abstraction Level 2: Determining the sampling rate according to Abstraction Level 2 may include checking all events of each signal and using the minimum amount of time between two consecutive events of the same signal as the sampling rate. In some aspects, determining the sampling rate according to Abstraction Level 2 assumes (or includes) that there is no skew between events between different signals.

[0091] 6 , in one example of determining a sampling rate according to abstraction level 2, wave converter 406 may review all events (e.g., uptick, downtick, uptick, and the like) of each signal (e.g., signal 1 through signal 4) starting from 0 ps to the end of the event-based simulation. Wave converter 406 may determine that the minimum amount of time between two consecutive events of the same signal, among signals 1 through 4, is 50 ps. For example, wave converter 406 may determine that the minimum amount of time between two consecutive events of the same signal is the 50 ps difference between an uptick of signal 2 and a downtick of signal 2 (e.g., 50 ps and 100 ps, ​​respectively, 350 ps and 400 ps, ​​respectively), e.g., 100 ps−50 ps=50 ps.

[0092] In some aspects, the amount of time associated with determining a sampling rate (also referred to herein as a scale factor) according to abstraction level 3 may be longer than the amount of time for determining a sampling rate according to abstraction level 1, and may be shorter than the amount of time for determining a sampling rate according to abstraction level 3. Transforming bender waveform data 4053 into waveform data 407 using a sampling rate determined according to abstraction level 2 may preserve all transition data included in bender waveform data 4053, but may not preserve skew data included in bender waveform data 4053. The amount of time associated with completing a transformation according to abstraction level 1 may be longer than the amount of time associated with completing a transformation according to abstraction level 1, and may be shorter than the amount of time associated with completing a transformation according to abstraction level 3.

[0093] Abstraction Level 3: Determining the sampling rate may include checking all events across all signals and using the minimum amount of time between two events across different signals as the sampling rate. In some aspects, determining the sampling rate according to Abstraction Level 3 makes no assumptions and is the most general of Abstraction Levels 1 through 3. In some cases, determining the sampling rate according to Abstraction Level 3 may result in a lower sampling rate, which may increase or lengthen the overall time associated with transforming the vendor waveform data 4053 into waveform data 407.

[0094] 6 , in one example of determining a sampling rate according to abstraction level 3, wave converter 406 may review all events (e.g., upticks, downticks, upticks, and the like) in all signals (e.g., signals 1 through 4) starting from 0 ps to the end of the event-based simulation. Wave converter 406 determines that the minimum amount of time between two events across different signals among signals 1 through 4 is 10 ps. For example, wave converter 406 determines that the minimum amount of time between two events across different signals is a 10 ps difference between an uptick of signal 1 (e.g., at 50 ps, ​​350 ps) and an uptick of signal 4 (e.g., at 60 ps, ​​360 ps), e.g., 60 ps−50 ps=10 ps, ​​and 360 ps−350 ps=10 ps.

[0095] Additionally, or alternatively, wave converter 406 may determine that the minimum amount of time between two events across different signals among signals 1-4 is a 10 ps difference between an uptick of signal 1 (e.g., 50 ps, ​​350 ps), signal 2 (e.g., 50 ps, ​​350 ps), or signal 3 (e.g., 50 ps, ​​350 ps) and an uptick of signal 4 (e.g., 60 ps, ​​360 ps).

[0096] In some aspects, the amount of time associated with determining a sampling rate (also referred to herein as a scale factor) according to abstraction level 3 may be the greatest among abstraction levels 1 through 3. Transforming bender waveform data 4053 into waveform data 407 using a sampling rate determined according to abstraction level 3 may preserve all transition data and all skew data included in bender waveform data 4053. The amount of time associated with completing the transformation according to abstraction level 3 may be the greatest among abstraction levels 1 through 3.

[0097] In a comparative example, transforming the bender waveform data 4053 into waveform data 407 can be implemented such that 1 ps maps directly to 1 simtick for a simulation period of 1100 ps, ​​resulting in a cycle-based simulation equivalent of 1100 simticks.

[0098] In contrast, determining a sampling rate and converting bender waveform data 4053 to waveform data 407 according to, for example, the techniques described herein may result in a reduced amount of simtic signals. For example, converting bender waveform data 4053 to waveform data 407 using a sampling rate of 50 ps determined according to abstraction level 1 or abstraction level 2 results in the generation of 22 simtic signals, at the expense of losing skew information between signal 4 and other signals. In yet another example, converting bender waveform data 4053 to waveform data 407 using a sampling rate of 10 ps determined according to abstraction level 3 results in the generation of 110 simtic signals while preserving skew information between signal 4 and other signals.

[0099] The sampling described herein may support transforming vendor waveform data 4053 into waveform data 407 compatible with debug operations 408. That is, sampling supports mapping or converting vendor waveform data 4053 into waveform data 407 compatible with debug operations 408, and thus may support effective debugging of event-based simulation data in a cycle-based simulation environment. Aspects of the transformation (i.e., mapping, conversion) techniques described herein enable logic teams (e.g., logic hardware and firmware engineers) to obtain waveform data (e.g., waveform data 407) from event-based simulation data provided by a vendor platform (e.g., vendor waveform data 4053) in a format that is familiar to the logic team and that is mapped to the cycle-based simulation environment. Various levels of abstraction support effective transformation taking into account target performance parameters (e.g., amount of data storage, amount of time to complete transformation). Thus, for example, the transformation techniques described herein support effective debugging of IC designs when simulation results provided by the vendor (e.g., vendor waveform data 4053) are in a format that is incompatible with the debug tools (e.g., debug operations 408) used by the logic team.

[0100] 7 illustrates an example workflow 700 related to designing and debugging an IC design in accordance with one or more embodiments of the present disclosure. Aspects of the present disclosure support implementing techniques described herein for automatically mapping event-based simulation data to cycle-based simulation at any stage of the workflow 700, as shown in FIG.

[0101] The techniques described herein support providing logic designers with a consistent platform and touchpoint across a variety of debug use cases, including: (1) debug use cases that may include working with abbreviated VHDL and normalized RTL / simulation; (2) debug use cases that may include physical design (PD) VHDL simulation; (3) debug use cases that may include emulation (e.g., PD netlist); and (4) debug use cases that may include actual hardware data (e.g., post-silicon).

[0102] Thus, for example, the techniques described herein provide seamless integration of the workflow 700 framework with event-based simulation data generated by a vendor engine (e.g., Cadence), thus supporting consistent productivity and continuous debugging for logic designers at various stages of the workflow 700.

[0103] FIG. 8 illustrates an example of providing a hybrid hardware debug platform 800 with a translated AET 805 and VHDL-based instrumentation 810, in accordance with one or more embodiments of the present disclosure.

[0104] The converted AET 805 is an emulation Verilog-based AET. In general, the AET may have various types of information, as shown by the exemplary sub-blocks "Signal Data," "Alias ​​Data," "Stem Data," "Build Data," and "Type Data." Signal data refers to different signals in the model and their corresponding signal values ​​in different cycles. Alias ​​data includes IO port mapping information. Stem data includes hierarchy information and mapping to HDL source. Build data includes material build information. Type data includes some of the HDL language construct information, e.g., language-specific information such as VHDL types. The emulation AET is a Verilog-based AET generated by HDLOUT.

[0105] Hybrid hardware debug platform 800 supports combining transformed AET 805 and VHDL-based instrumentation 810. Hybrid hardware debug platform 800 and transformed AET 805 include aspects of debug operations 408 and waveform data 407, respectively, as described with reference to FIG.

[0106] In an exemplary implementation, if a designer is interested in signals and their values ​​from the actual emulation AET, the hybrid hardware debug platform 800 may enable the designer to look up the signals in the original VHDL that the designer wrote. The techniques described herein support the implementation of VHDL-based instrumentation 810 by importing the necessary information from the load assist 804 (debug assist AET), as shown by the right arrow. The debug assist AET is typically an AET from a logic simulation (e.g., MESA simulation) of the same HDL model. See Figure 8 for a link between the two, enabling the logic designer's experience.

[0107] As described herein, embodiments of the present disclosure provide a hybrid hardware debug platform that supports automatic mapping of event-based simulation data to cycle-based simulation in the hybrid hardware debug platform. The platform may support complementary environments (e.g., logic design, block simulation, element simulation, system simulation, emulation). The platform supports signal waveform debugging and source-level (e.g., mixed language, VHDL) annotation of given signal / cycle values, supporting effective debugging based on source-level code. The platform supports high-level type and state enumeration.

[0108] FIG. 9 illustrates an example flowchart of a method 900 for supporting automatic mapping of event-based simulation data to cycle-based simulation in a hybrid hardware debug platform, in accordance with one or more embodiments of the present disclosure.

[0109] At 905, the method 900 includes receiving first waveform data in a first format, the first waveform data including event-based simulation data.

[0110] In some aspects, the method 900 comprises selecting (at 910) a target abstraction level from among a set of candidate abstraction levels associated with transforming first waveform data into second waveform data based on a parameter, where the parameter is selected from the group consisting of: a time parameter associated with transforming the first waveform data into the second waveform data; and a data storage parameter associated with transforming the first waveform data into the second waveform data; and determining (at 915) a sampling rate based on the target abstraction level.

[0111] In some examples, the time parameter is a target time duration associated with transforming the first waveform data into the second waveform data.

[0112] In some examples, the data storage parameter is associated with storing skew information associated with a signal waveform included in the first waveform data.

[0113] In one example, determining the sampling rate is based on a first abstraction level from the set of candidate abstraction levels and includes: identifying, for at least two signal waveforms included in the first waveform data, a target amount of events associated with each of the at least two signal waveforms; calculating, for each of the at least two signal waveforms included in the first waveform data, a time duration between two consecutive events included in the target amount of events; and selecting a minimum time duration from the time durations as the sampling rate.

[0114] In one example, determining the sampling rate is based on a first abstraction level among a set of candidate abstraction levels and includes an assumption that the fastest clock among the signal waveforms included in the first waveform data can be used as the sampling rate.

[0115] In one example, determining the sampling rate is based on a second abstraction level from the set of candidate abstraction levels and includes: identifying, for at least two signal waveforms included in the first waveform data, all events associated with each of the at least two signal waveforms; calculating, for each of the at least two signal waveforms included in the first waveform data, a time duration between two consecutive events included among all the events; and selecting a minimum time duration among the time durations as the sampling rate.

[0116] In one example, determining the sampling rate is based on a second abstraction level among the set of candidate abstraction levels and includes an assumption that there is no skew between events between signal waveforms included in the first waveform data.

[0117] In one example, determining the sampling rate is based on a third abstraction level from the set of candidate abstraction levels and includes: identifying, for at least two signal waveforms included in the first waveform data, all events associated with each of the at least two signal waveforms; calculating a time duration between the events associated with each of the at least two signal waveforms; and selecting as the sampling rate a minimum time duration among the time durations, the minimum time duration being between a first event associated with the first signal waveform and a second event associated with the second signal waveform.

[0118] At 920, the method 900 includes generating second waveform data of a second format based on the first waveform data, the second waveform data being compatible with the cycle-based simulation environment.

[0119] In some aspects, generating the second waveform data includes transforming the first waveform data into the second waveform data by sampling a signal waveform included in the first waveform data according to a sampling rate.

[0120] At 925, the method 900 includes performing one or more debug operations by processing the second waveform data within the cycle-based simulation environment.

[0121] In the flowchart descriptions herein, operations may be performed in an order different from that shown, or may be performed in a different order or at a different time. Also, certain operations may be omitted from a flowchart, one or more operations may be repeated, or other operations may be added to a flowchart.

[0122] Various embodiments are described herein with reference to the associated drawings. Alternative embodiments may be devised without departing from the scope of the present disclosure. Various connection and positional relationships (e.g., above, below, adjacent, etc.) are described between elements in the following description and in the drawings. These connections and / or positions may be direct or indirect unless otherwise specified, and the present disclosure is not intended to be limiting in this respect. Thus, coupling between entities may refer to either direct or indirect coupling, and positional relationships between entities may be direct or indirect positions. Furthermore, various tasks and process steps described herein may be combined into a broader procedure or process having additional steps or functions not described in detail herein.

[0123] One or more of the methods described herein may be implemented using any or a combination of the following technologies: discrete logic circuitry having logic gates for performing logical functions on data signals, application specific integrated circuits (ASICs) having appropriate combinatorial logic gates, programmable gate arrays (PGAs), field programmable gate arrays (FPGAs), etc., each of which is well known in the art.

[0124] For purposes of brevity, conventional techniques associated with making and using aspects of the present disclosure may or may not be described in detail herein. In particular, various aspects of computing systems and specific computer programs for implementing various technical features described herein are well known. Thus, for purposes of brevity, many conventional implementation details are mentioned only briefly herein or omitted entirely without providing details of well-known systems and / or processes.

[0125] In some embodiments, various functions or operations may be performed at a given location and / or in conjunction with the operation of one or more devices or systems. In some embodiments, a portion of a given function or operation may be performed at a first device or location, and the remainder of the function or operation may be performed at one or more additional devices or locations.

[0126] The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting. As used herein, the singular forms "a," "an," and "the" are intended to include the plural forms as well, unless the context clearly dictates otherwise. It should be further understood that the terms "comprises" and / or "comprising," when used herein, specify the presence of stated features, integers, steps, operations, and / or components of an element, but do not exclude the presence or addition of one or more other features, integers, steps, operations, components of an element, and / or groups thereof.

[0127] In the following claims, corresponding structure, material, acts, and equivalents of any means-plus-function or step-plus-function element are intended to include any structure, material, or act for performing the function in combination with other claimed elements as specifically claimed. The present disclosure has been presented for purposes of illustration and description, but is not intended to be exhaustive or limited to the precise form disclosed. Many modifications and variations will be apparent to those skilled in the art without departing from the scope and spirit of the present disclosure. The embodiments were chosen and described to best explain the principles and practical applications of the disclosure and to enable those skilled in the art to understand the disclosure in various embodiments with various modifications suited to the particular uses contemplated.

[0128] The diagrams shown herein are exemplary. Many changes can be made to the diagrams or to the steps (or operations) described therein without departing from the spirit of this disclosure. For example, actions can be performed in a different order, or actions can be added, deleted, or modified. Also, the term "coupled" indicates that there is a signal path between two elements and does not imply a direct connection between elements with no intervening elements / connections between them. All of these variations are considered part of this disclosure.

[0129] The following definitions and abbreviations may be used for interpreting the claims and the specification. As used herein, the terms "comprises," "comprising," "includes," "including," "has," "having," "contains," or "containing," or any other variation thereof, are intended to cover a non-exclusive inclusion. For example, a composition, mixture, process, method, article, or device that includes a list of elements is not necessarily limited to only those elements but may include other elements not expressly listed or inherent in such composition, mixture, process, method, article, or device.

[0130] Moreover, the term "exemplary" is used herein to mean "serving as an example, instance, or illustration." Any embodiment or design described herein as "exemplary" is not necessarily to be construed as preferred or advantageous over other embodiments or designs. The terms "at least one" and "one or more" may be understood to include any integer greater than or equal to 1, i.e., 1, 2, 3, 4, etc. The term "plurality" may be understood to include any integer greater than or equal to 2, i.e., 2, 3, 4, 5, etc. The term "connected" may include both an indirect "connected" and a direct "connected."

[0131] The terms "about," "substantially," "approximately," and variations thereof are intended to include the degree of error associated with measurement of a particular quantity based on equipment available at the time of the filing of this application. For example, "about" can include a range of ±8%, or 5%, or 2% of a given value.

[0132] The present disclosure may be a system, method, and / or computer program product at any possible level of integration of technical details. The computer program product may include a computer-readable storage medium (or media) having computer-readable program instructions thereon for causing a processor to perform aspects of the present disclosure.

[0133] A computer-readable storage medium may be a tangible device that can hold and store instructions for use by an instruction execution device. The computer-readable storage medium may be, for example, but not limited to, an electronic storage device, a magnetic storage device, an optical storage device, an electromagnetic storage device, a semiconductor storage device, or any suitable combination of the foregoing. A non-exhaustive list of more specific examples of computer-readable storage media includes the following: portable computer diskettes, hard disks, random access memory (RAM), read-only memory (ROM), erasable programmable read-only memory (EPROM or flash memory), static random access memory (SRAM), portable compact disk read-only memory (CD-ROM), digital versatile disk (DVD), memory sticks, floppy disks, mechanically encoded devices such as punch cards or ridge structures in grooves in which instructions are recorded, and any suitable combination of the foregoing. Computer-readable storage medium, as used herein, should not be construed as a transitory signal per se, such as an electric wave or other freely propagating electromagnetic wave, an electromagnetic wave propagating through a waveguide or other transmission medium (e.g., a light pulse passing through a fiber optic cable), or an electrical signal transmitted over an electrical wire.

[0134] The computer-readable program instructions described herein may be downloaded from a computer-readable storage medium to each computing / processing device or to an external computer or external storage device via a network, such as the Internet, a local area network, a wide area network, and / or a wireless network. The network may comprise copper transmission cables, optical transmission fiber, wireless transmission, routers, firewalls, switches, gateway computers, and / or edge servers. A network adapter card or network interface in each computing / processing device receives the computer-readable program instructions from the network and transfers the computer-readable program instructions to a computer-readable storage medium in the respective computing / processing device for storage.

[0135] The computer-readable program instructions for carrying out the operations of the present disclosure may be either assembler instructions, instruction set architecture (ISA) instructions, machine instructions, machine-dependent instructions, microcode, firmware instructions, state setting data, configuration data for an integrated circuit, or source or object code written in any combination of one or more programming languages, including object-oriented programming languages ​​such as Smalltalk® or C++, and procedural programming languages ​​such as the “C” programming language or similar programming languages. The computer-readable program instructions may execute entirely on the user's computer, partially on the user's computer, as a standalone software package, partially on the user's computer and partially on a remote computer, or entirely on a remote computer or server. In the latter scenario, the remote computer may be connected to the user's computer through any type of network, including a local area network (LAN) or a wide area network (WAN), or the connection may be to an external computer (e.g., over the Internet using an Internet Service Provider). In some embodiments, electronic circuitry including, for example, a programmable logic circuit, a field programmable gate array (FPGA), or a programmable logic array (PLA) may execute computer-readable program instructions by utilizing state information of the computer-readable program instructions to personalize the electronic circuitry to perform aspects of the present disclosure.

[0136] Aspects of the present disclosure are described herein with reference to flowchart illustrations and / or block diagrams of methods, apparatus (systems), and computer program products according to embodiments of the present disclosure. It will be understood that each block of the flowchart illustrations and / or block diagrams, and combinations of blocks in the flowchart illustrations and / or block diagrams, can be implemented by computer-readable program instructions.

[0137] These computer-readable program instructions may be provided to a processor of a general-purpose computer, special-purpose computer, or other programmable data processing apparatus to produce a machine, such that the instructions, executed by the processor of the computer or other programmable data processing apparatus, create means for implementing the functions / acts specified in one or more blocks of the flowcharts and / or block diagrams. These computer-readable program instructions may also be stored on a computer-readable storage medium that can direct a computer, programmable data processing apparatus, and / or other device to function in a particular manner, such that the computer-readable storage medium on which the instructions are stored has an article of manufacture including instructions that implement aspects of the functions / acts specified in one or more blocks of the flowcharts and / or block diagrams.

[0138] Computer-readable program instructions may also be loaded into a computer, other programmable data processing apparatus, or other device and cause a series of operational steps to be executed on the computer, other programmable apparatus, or other device to generate a computer-implemented process, such that the instructions executing on the computer, other programmable apparatus, or other device implement the functions / acts specified in one or more blocks of the flowcharts and / or block diagrams.

[0139] The flowcharts and block diagrams in the figures illustrate the architecture, functionality, and operation of possible implementations of systems, methods, and computer program products according to various embodiments of the present disclosure. In this regard, each block in a flowchart or block diagram may represent a module, segment, or portion of instructions, including one or more executable instructions, that implements a specified logical function. In some alternative implementations, the functions noted in the blocks may occur out of the order noted in the figures. For example, two blocks shown in succession may, in fact, be executed substantially concurrently, or the blocks may possibly be executed in the reverse order, depending on the functionality involved. It should also be noted that each block in the block diagrams and / or flowchart diagrams, and combinations of blocks in the block diagrams and / or flowchart diagrams, may be implemented by a dedicated hardware-based system that performs the specified functions or operations, or that executes a combination of dedicated hardware and computer instructions.

[0140] The description of various embodiments of the present disclosure has been presented for illustrative purposes, but is not intended to be exhaustive or limited to the disclosed embodiments. Many modifications and variations will be apparent to those skilled in the art without departing from the spirit and scope of the described embodiments. The terms used herein have been selected to best explain the principles of the embodiments, practical applications, or technical improvements over technologies found in the market, or to enable others skilled in the art to understand the embodiments described herein.

Claims

1. receiving first waveform data in a first format, wherein the first waveform data comprises event-based simulation data; generating second waveform data of a second format based on the first waveform data, wherein the second waveform data is compatible with a cycle-based simulation environment; and performing one or more debug operations by processing the second waveform data within the cycle-based simulation environment; 1. A computer-implemented method comprising:

2. 2. The computer-implemented method of claim 1, wherein generating the second waveform data comprises transforming the first waveform data into the second waveform data by sampling a signal waveform included in the first waveform data according to a sampling rate.

3. selecting a target abstraction level from among a set of candidate abstraction levels associated with transforming the first waveform data into the second waveform data based on a parameter, wherein the parameter comprises: a time parameter associated with transforming the first waveform data into the second waveform data; and data storage parameters associated with transforming the first waveform data into the second waveform data; selected from the group consisting of: determining the sampling rate based on the target abstraction level The computer-implemented method of claim 2 further comprising:

4. determining the sampling rate is based on a first abstraction level in the set of candidate abstraction levels; identifying, for at least two signal waveforms included in the first waveform data, a target quantity of events associated with each of the at least two signal waveforms; Calculating a time duration between two consecutive events included in the target amount of events for each of the at least two signal waveforms included in the first waveform data; and selecting a minimum time duration from among the time durations as the sampling rate; The computer-implemented method of claim 3 , comprising:

5. 4. The computer-implemented method of claim 3, wherein determining the sampling rate is based on a first abstraction level in the set of candidate abstraction levels and includes an assumption that the fastest clock among the signal waveforms included in the first waveform data can be used as the sampling rate.

6. determining the sampling rate is based on a second abstraction level in the set of candidate abstraction levels; identifying, for at least two signal waveforms included in the first waveform data, all events associated with each of the at least two signal waveforms; calculating a time duration between two consecutive events included in all of the events for each of the at least two signal waveforms included in the first waveform data; and selecting a minimum time duration from among the time durations as the sampling rate; The computer-implemented method of claim 3 , comprising:

7. 4. The computer-implemented method of claim 3, wherein determining the sampling rate is based on a second abstraction level in the set of candidate abstraction levels and includes assuming no skew between events between signal waveforms included in the first waveform data.

8. determining the sampling rate is based on a third abstraction level in the set of candidate abstraction levels; identifying, for at least two signal waveforms included in the first waveform data, all events associated with each of the at least two signal waveforms; calculating a time duration between events associated with each of the at least two signal waveforms; selecting a minimum time duration among the time durations as the sampling rate, wherein the minimum time duration is between a first event associated with a first signal waveform and a second event associated with a second signal waveform. The computer-implemented method of claim 3 , comprising:

9. The computer-implemented method of claim 3 , wherein the time parameter is a target time duration associated with transforming the first waveform data into the second waveform data.

10. The computer-implemented method of claim 3 , wherein the data storage parameter is associated with storing skew information associated with a signal waveform included in the first waveform data.

11. 1. A computing system comprising: a memory having computer-readable instructions; and one or more processors for executing said computer-readable instructions, said computer-readable instructions controlling said one or more processors to: receiving first waveform data in a first format, wherein the first waveform data comprises event-based simulation data; generating second waveform data of a second format based on the first waveform data, wherein the second waveform data is compatible with a cycle-based simulation environment; and performing one or more debug operations by processing the second waveform data within the cycle-based simulation environment; 1. A computing system that performs operations including:

12. 12. The computing system of claim 11, wherein the step of generating the second waveform data includes the step of transforming the first waveform data into the second waveform data by sampling a signal waveform included in the first waveform data according to a sampling rate.

13. The computer readable instructions control the one or more processors to: selecting a target abstraction level from a set of candidate abstraction levels associated with transforming the first waveform data into the second waveform data based on a parameter, wherein the parameter comprises: a time parameter associated with transforming the first waveform data into the second waveform data; and data storage parameters associated with transforming the first waveform data into the second waveform data; selected from the group consisting of: determining the sampling rate based on the target abstraction level; The computing system of claim 12 , further comprising:

14. determining the sampling rate is based on a first abstraction level in the set of candidate abstraction levels; identifying, for at least two signal waveforms included in the first waveform data, a target quantity of events associated with each of the at least two signal waveforms; calculating a time duration between two consecutive events included in the target amount of events for each of the at least two signal waveforms included in the first waveform data; and selecting a minimum time duration among said time durations as said sampling rate; The computing system of claim 13 , comprising:

15. 14. The computing system of claim 13, wherein the procedure for determining the sampling rate is based on a first abstraction level in the set of candidate abstraction levels and includes an assumption that the fastest clock among the signal waveforms included in the first waveform data can be used as the sampling rate.

16. determining the sampling rate is based on a second abstraction level in the set of candidate abstraction levels; identifying, for at least two signal waveforms included in the first waveform data, all events associated with each of the at least two signal waveforms; calculating a time duration between two consecutive events included in all of the events for each of the at least two signal waveforms included in the first waveform data; and selecting a minimum time duration among said time durations as said sampling rate; The computing system of claim 13 , comprising:

17. 14. The computing system of claim 13, wherein the procedure for determining the sampling rate is based on a second abstraction level in the set of candidate abstraction levels and includes an assumption that there is no skew between events between signal waveforms included in the first waveform data.

18. determining the sampling rate is based on a third abstraction level in the set of candidate abstraction levels; identifying, for at least two signal waveforms included in the first waveform data, all events associated with each of the at least two signal waveforms; calculating a time duration between events associated with each of said at least two signal waveforms; selecting a minimum time duration among the time durations as the sampling rate, wherein the minimum time duration is between a first event associated with a first signal waveform and a second event associated with a second signal waveform. The computing system of claim 13 , comprising:

19. the time parameter is a target time duration associated with transforming the first waveform data into the second waveform data; and The computing system of claim 13 , wherein the data storage parameter is associated with storing skew information associated with a signal waveform included in the first waveform data.

20. The processor receiving first waveform data in a first format, wherein the first waveform data comprises event-based simulation data; generating second waveform data of a second format based on the first waveform data, wherein the second waveform data is compatible with a cycle-based simulation environment; and performing one or more debug operations by processing the second waveform data within the cycle-based simulation environment; A computer program for executing

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