Semiconductor device

Abstract

SOLUTION: A first conductivity-type drift region provided in a semiconductor substrate, a plurality of trench portions extending in a predetermined trench extending direction and arrayed in a predetermined trench array direction, a second conductivity-type base region provided above the drift region, a first conductivity-type emitter region having a doping concentration higher than that of the drift region, A contact region of the second conductivity type having a doping concentration higher than that of the base region, a well region of the second conductivity type provided above the drift region, and a front electrode portion provided above the semiconductor substrate. At least one trench portion of the plurality of trench portions may have a narrow portion provided extending in the trench extension direction and a wide portion having a trench width wider than that of the narrow portion. The well region may be provided below the wide portion.SELECTED DRAWING: Figure 2A

Description

[Technical Field]

[0001] The present invention relates to a semiconductor device. [Background technology]

[0002] BACKGROUND ART Semiconductor devices having a plurality of trenches provided on the upper surface of a semiconductor substrate have been disclosed (see, for example, Patent Documents 1 and 2). Patent Document 1: JP 2021-129020 A Patent Document 2: Japanese Patent Application Laid-Open No. 2000-200901 Summary of the Invention

[0003] A first aspect of the present invention provides a semiconductor device including: a first conductivity type drift region provided in a semiconductor substrate; a plurality of trenches extending in a predetermined trench extension direction and arranged in a predetermined trench arrangement direction on the front surface side of the semiconductor substrate; a second conductivity type base region provided above the drift region; a first conductivity type emitter region provided on the front surface of the semiconductor substrate and having a higher doping concentration than the drift region; a second conductivity type contact region provided above the drift region and having a higher doping concentration than the base region; a second conductivity type well region provided above the drift region; and a front surface electrode provided above the semiconductor substrate. At least one of the plurality of trenches may have a narrow portion extending in the trench extension direction and a wide portion whose trench width is wider than the narrow portion. The well region may be provided below the wide portion.

[0004] In the semiconductor device, the plurality of trenches may include gate trenches, and the gate trenches may have the wide portion and the narrow portion.

[0005] In any of the above semiconductor devices, the front surface electrode portion may include a gate pad provided above the semiconductor substrate, a gate metal layer electrically connected to the gate pad, and a gate runner portion including polysilicon for connecting the gate trench portion and the gate metal layer.

[0006] In any of the above semiconductor devices, the front surface electrode portion may include a gate pad provided above the semiconductor substrate. The front surface electrode portion may include a gate metal layer electrically connected to the gate pad. A gate trench contact hole for connecting the gate metal layer to the gate trench portion may be provided above the wide portion of the gate trench portion.

[0007] In any of the semiconductor devices described above, the plurality of trenches may include a dummy trench, and the dummy trench may have the wide portion and the narrow portion.

[0008] In any of the semiconductor devices described above, the front surface electrode portion may have an emitter electrode provided above the semiconductor substrate, and a dummy trench contact hole for connecting the emitter electrode and the dummy trench portion may be provided above the wide portion of the dummy trench portion.

[0009] In any of the above semiconductor devices, the distance between the dummy trench contact hole and the end of the emitter electrode in the trench extension direction may be 1 μm or more and 50 μm or less.

[0010] In any of the above semiconductor devices, the trench depth of the wide portion may be deeper than the trench depth of the narrow portion.

[0011] In any of the above semiconductor devices, the trench depth of the wide portion may be shallower than the trench depth of the narrow portion.

[0012] In any of the above semiconductor devices, a contact width in the trench arrangement direction of a gate trench contact hole provided above the wide portion of the gate trench portion may be smaller than a trench width of the narrow portion of the gate trench portion.

[0013] In any of the above semiconductor devices, a contact width in the trench arrangement direction of a dummy trench contact hole provided above the wide portion of the dummy trench portion may be smaller than a trench width of the narrow portion of the dummy trench portion.

[0014] In any of the above semiconductor devices, a contact width in the trench arrangement direction of the gate trench contact hole provided above the wide portion of the gate trench portion may be equal to or greater than the trench width of the narrow portion of the gate trench portion.

[0015] In any of the above semiconductor devices, a contact width in the trench arrangement direction of a dummy trench contact hole provided above the wide portion of the dummy trench portion may be equal to or greater than the trench width of the narrow portion of the dummy trench portion.

[0016] In any of the above semiconductor devices, the wide portion may be covered by the well region in a top view.

[0017] In any of the above semiconductor devices, the sidewalls and bottom surface of the wide portion may be covered with the well region.

[0018] In any of the above semiconductor devices, the wide portion may have a bridging portion where the trench width gradually increases from the narrow portion.

[0019] In any of the above semiconductor devices, the well region may be provided below the connecting portion.

[0020] In any of the above semiconductor devices, the connecting portion may have a structure in which only one side wall gradually widens.

[0021] In any of the above semiconductor devices, the radius of curvature R of the connecting portion may be not less than 0.1 μm and not more than 5.0 μm.

[0022] In any of the semiconductor devices described above, the plurality of trenches may include gate trenches and dummy trenches, and a difference between an end of the gate trench and an end of the dummy trench in the trench extension direction may be equal to or less than twice the pitch of the plurality of trenches.

[0023] In any of the semiconductor devices described above, the plurality of trenches may include gate trenches and dummy trenches, and a distance in the trench extension direction between a gate trench contact hole provided above the gate trench and a dummy trench contact hole provided above the dummy trench may be 8 μm or more and 20 μm or less.

[0024] In any of the semiconductor devices described above, the plurality of trench portions may have extension portions that extend in the trench extension direction, and the plurality of trench portions may have connection portions for connecting two of the extension portions.

[0025] In any of the semiconductor devices described above, the plurality of trenches may include a plurality of gate trenches and a plurality of dummy trenches, and at least one of the plurality of dummy trenches may be sandwiched between two of the extension portions connected by the connection portion.

[0026] In any of the above semiconductor devices, the plurality of gate trench portions may be configured such that two of the extension portions connected by the connection portion in the plurality of gate trench portions sandwich two of the extension portions connected by the connection portion in the plurality of dummy trench portions.

[0027] Any of the above semiconductor devices may have a contact hole above the connection portion, the contact hole extending in the trench arrangement direction.

[0028] In any of the above semiconductor devices, the connecting portion of the wide portion where the trench width gradually increases from the narrow portion may have a structure in which only the outer side wall of the U-shape formed by the connecting portion and the extending portion gradually widens.

[0029] In any of the above semiconductor devices, the plurality of trench portions may each have the wide portion, and adjacent wide portions may be connected to each other.

[0030] In any of the semiconductor devices described above, the plurality of trenches may include gate trenches and dummy trenches. The wide portion may be provided in the gate trenches but not in the dummy trenches. The well region may cover the wide portion of the gate trenches in a top view, but may not cover ends of the dummy trenches in a trench extension direction.

[0031] Any of the above semiconductor devices may include a transistor section and a diode section.

[0032] In a second aspect of the present invention, a semiconductor device may include a first-conductivity-type drift region provided in a semiconductor substrate, a plurality of trenches extending in a predetermined trench extension direction and arranged in a predetermined trench arrangement direction on the front surface side of the semiconductor substrate, a second-conductivity-type base region provided above the drift region, a first-conductivity-type emitter region provided on the front surface of the semiconductor substrate and having a doping concentration higher than that of the drift region, a second-conductivity-type contact region provided above the drift region and having a doping concentration higher than that of the base region, a second-conductivity-type well region provided above the drift region, and a front-surface electrode provided above the semiconductor substrate. At least one of the plurality of trenches may have a narrow portion extending in the trench extension direction and a wide portion whose trench width is wider than that of the narrow portion. The plurality of trenches may include gate trench portions and dummy trench portions. In the trench extension direction, a difference between an end of the gate trench portion and an end of the dummy trench portion may be equal to or less than twice the pitch of the plurality of trench portions.

[0033] In a third aspect of the present invention, a semiconductor device may include a first conductivity type drift region provided in a semiconductor substrate, a plurality of gate trenches extending in a predetermined trench extension direction on the front surface side of the semiconductor substrate, a second conductivity type base region provided above the drift region, a first conductivity type emitter region provided on the front surface of the semiconductor substrate and having a doping concentration higher than that of the drift region, a second conductivity type contact region provided above the drift region and having a doping concentration higher than that of the base region, a second conductivity type well region provided above the drift region, and a front surface electrode provided above the semiconductor substrate. At least one of the plurality of gate trenches may have a narrow portion extending in the trench extension direction and a wide portion whose trench width is wider than that of the narrow portion. The front surface electrode may include a gate pad provided above the semiconductor substrate. The front surface electrode may include a gate metal layer electrically connected to the gate pad. A gate trench contact hole for connecting the gate metal layer and the gate trench portion may be provided above the wide portion of the gate trench portion.

[0034] The above summary of the invention does not list all of the features of the present invention, and subcombinations of these features may also be inventions. [Brief explanation of the drawings]

[0035] [Figure 1] 1 shows an example of a top view of a semiconductor device 100. FIG. [Figure 2A] FIG. 2 is an enlarged view of an area A in FIG. [Figure 2B] FIG. 2B is a diagram showing an example of an XZ cross section including the aa' cross section in FIG. 2A. [Figure 2C] FIG. 2B is a diagram showing an example of an XZ cross section including the bb' cross section in FIG. 2A. [Figure 2D] 10 is an enlarged view of an XZ cross section passing through a mesa portion 71. FIG. [Figure 3A] FIG. 2B is an enlarged view of region B in FIG. 2A. [Figure 3B] FIG. 2B is an enlarged view of a modified example of region B in FIG. 2A. [Figure 3C] FIG. 3B is a diagram showing an example of an XZ cross section including the cc' cross section in FIG. 3A. [Figure 3D] FIG. 3B is a diagram showing an example of a YZ cross section including the dd' cross section in FIG. 3A. [Figure 3E] 3B is a diagram showing a modified example of the YZ cross section including the dd' cross section in FIG. 3A. FIG. [Figure 4A] FIG. 10 is a top view showing a modified example of the semiconductor device 100. [Figure 4B] FIG. 4B is an enlarged view of region C in FIG. 4A. [Figure 5] FIG. 10 is a top view showing a modified example of the semiconductor device 100. [Figure 6] FIG. 10 is a top view showing a modified example of the semiconductor device 100. [Figure 7A] FIG. 10 is a top view showing a modified example of the semiconductor device 100. [Figure 7B] FIG. 10 is a top view showing a modified example of the semiconductor device 100. [Figure 8] FIG. 10 is a top view showing a modified example of the semiconductor device 100. [Figure 9] FIG. 10 is a top view showing a modified example of the semiconductor device 100. [Figure 10] FIG. 10 is a top view showing a modified example of the semiconductor device 100. [Figure 11] FIG. 10 is a top view showing a modified example of the semiconductor device 100. [Figure 12] FIG. 10 is a top view showing a modified example of the semiconductor device 100. DETAILED DESCRIPTION OF THE INVENTION

[0036] The present invention will be described below through embodiments of the invention, but the following embodiments do not limit the scope of the invention according to the claims. Furthermore, not all of the combinations of features described in the embodiments are necessarily essential to the solution of the invention.

[0037] In this specification, one side in a direction parallel to the depth direction of a semiconductor substrate is referred to as "upper" and the other side as "lower." Of the two main surfaces of a substrate, layer, or other member, one surface is referred to as the upper surface and the other surface is referred to as the lower surface. The directions of "upper" and "lower" are not limited to the direction of gravity or the directions when the semiconductor device is mounted.

[0038] In this specification, technical matters may be explained using the Cartesian coordinate axes of the X-axis, Y-axis, and Z-axis. The Cartesian coordinate axes merely identify the relative positions of components and do not limit a specific direction. For example, the Z-axis does not limit the height direction relative to the ground. Note that the +Z-axis direction and the -Z-axis direction are opposite directions. When the Z-axis direction is written without specifying positive or negative, it means the direction parallel to the +Z-axis and -Z-axis.

[0039] In this specification, orthogonal axes parallel to the top and bottom surfaces of the semiconductor substrate are referred to as the X-axis and Y-axis. Furthermore, an axis perpendicular to the top and bottom surfaces of the semiconductor substrate is referred to as the Z-axis. In this specification, the direction of the Z-axis may be referred to as the depth direction. Furthermore, in this specification, the direction parallel to the top and bottom surfaces of the semiconductor substrate, including the X-axis and Y-axis, may be referred to as the horizontal direction.

[0040] In this specification, when we say "same" or "equal," it may include cases where there is an error due to manufacturing variations, etc. The error is, for example, within 10%.

[0041] In this specification, the conductivity type of a doped region doped with an impurity is described as P-type or N-type. In this specification, the impurity may particularly mean either an N-type donor or a P-type acceptor, and may be referred to as a dopant. In this specification, doping means introducing a donor or an acceptor into a semiconductor substrate to form a semiconductor exhibiting N-type conductivity or a semiconductor exhibiting P-type conductivity.

[0042] In this specification, the doping concentration refers to the concentration of donors or acceptors in a thermal equilibrium state. In this specification, the net doping concentration refers to the net concentration obtained by adding together the donor concentration as the concentration of positive ions and the acceptor concentration as the concentration of negative ions, taking into account the polarity of the charge. As an example, the donor concentration is N D , acceptor concentration N A Then, the net doping concentration at any point is N D -N A In this specification, the net doping concentration may be simply referred to as the doping concentration.

[0043] In this specification, when P+ type or N+ type is described, it means that the doping concentration is higher than that of P type or N type, and when P- type or N- type is described, it means that the doping concentration is lower than that of P type or N type. Also, when P++ type or N++ type is described in this specification, it means that the doping concentration is higher than that of P+ type or N+ type.

[0044] As used herein, chemical concentration refers to the atomic density of impurities measured regardless of their electrical activation state. Chemical concentration can be measured, for example, by secondary ion mass spectrometry (SIMS). The net doping concentration can be measured by voltage-capacitance (CV) measurement. The carrier concentration measured by spreading resistance (SR) measurement may also be used as the net doping concentration. Carriers refer to charge carriers, such as electrons or holes. The carrier concentration measured by CV or SR may be a value in a thermal equilibrium state. In addition, since the donor concentration in an N-type region is significantly greater than the acceptor concentration, the carrier concentration in that region may also be used as the donor concentration. Similarly, in a P-type region, the carrier concentration in that region may also be used as the acceptor concentration. In this specification, the doping concentration in an N-type region may also be referred to as the donor concentration, and the doping concentration in a P-type region may also be referred to as the acceptor concentration.

[0045] In addition, when the concentration distribution of the donor, acceptor, or net doping has a peak, the peak value may be taken as the donor, acceptor, or net doping concentration in the region. In cases where the donor, acceptor, or net doping concentration is approximately uniform, the average value of the donor, acceptor, or net doping concentration in the region may be taken as the donor, acceptor, or net doping concentration.

[0046] The carrier concentration measured by the SR method may be lower than the donor or acceptor concentration. In the range where current flows when measuring spreading resistance, the carrier mobility of the semiconductor substrate may be lower than the value in the crystalline state. A decrease in carrier mobility occurs when carriers are scattered due to disorder in the crystalline structure caused by lattice defects, etc. The reason for the decrease in carrier concentration is as follows: In the SR method, spreading resistance is measured and the carrier concentration is calculated from the measured spreading resistance. The carrier mobility used here is the mobility in the crystalline state. On the other hand, at locations where lattice defects are introduced, the carrier mobility is decreased, but the carrier concentration is calculated using the carrier mobility in the crystalline state. Therefore, the value obtained is lower than the actual carrier concentration, i.e., the donor or acceptor concentration.

[0047] The donor or acceptor concentration calculated from the carrier concentration measured by the CV method or the SR method may be lower than the chemical concentration of the element representing the donor or acceptor. As an example, the donor concentration of phosphorus or arsenic, which act as donors in silicon semiconductors, or the acceptor concentration of boron, which acts as an acceptor, is approximately 99% of their chemical concentrations. On the other hand, the donor concentration of hydrogen, which acts as a donor in silicon semiconductors, is approximately 0.1% to 10% of the chemical concentration of hydrogen. In this specification, the SI unit system is used. In this specification, distance and length may be expressed in centimeters (cm). In this case, various calculations may be performed by converting to meters (m). Regarding numerical representations of powers of 10, for example, 1E+16 is expressed as 1×10 16 The display of 1E-16 indicates 1 x 10-16 Shows.

[0048] FIG. 1 shows an example of a top view of a semiconductor device 100. In FIG. 1, the positions of each component projected onto the top surface of a semiconductor substrate 10 are shown. In FIG. 1, only some components of the semiconductor device 100 are shown, and some components are omitted. The semiconductor device 100 is a semiconductor chip including a transistor section 70 and a diode section 80.

[0049] The transistor section 70 includes a transistor such as an IGBT (Insulated Gate Bipolar Transistor). The diode section 80 includes a diode such as a free wheel diode (FWD). The semiconductor device 100 of this example is a reverse conducting IGBT (RC-IGBT) that has the transistor section 70 and the diode section 80 on the same chip.

[0050] The semiconductor substrate 10 is a substrate formed of a semiconductor material. The semiconductor substrate 10 may be a silicon substrate, a silicon carbide substrate, a diamond substrate, a nitride semiconductor substrate such as gallium nitride, an inorganic compound semiconductor substrate such as gallium oxide, or an organic compound semiconductor substrate. The semiconductor substrate 10 in this example is a silicon substrate. The semiconductor substrate 10 may be a wafer cut from a semiconductor ingot, or may be a chip obtained by dividing the wafer. The semiconductor ingot may be manufactured by any of the Czochralski method (CZ method), the magnetic field-applied Czochralski method (MCZ method), or the float zone method (FZ method).

[0051] The semiconductor substrate 10 has end edges 102 in a top view. In this specification, the term "top view" simply refers to a view from the top surface side of the semiconductor substrate 10. The semiconductor substrate 10 of this example has two pairs of end edges 102 that face each other in a top view. In FIG. 1 , the X-axis and Y-axis are parallel to one of the end edges 102. The Z-axis is perpendicular to the top surface of the semiconductor substrate 10. The semiconductor substrate 10 has an active region 160 and an edge termination structure 170.

[0052] The active region 160 is a region through which a main current flows in the depth direction between the upper and lower surfaces of the semiconductor substrate 10 during operation of the semiconductor device 100. An emitter electrode is provided above the active region 160, but is not shown in FIG.

[0053] At least one of a transistor section 70 including a transistor element such as an IGBT and a diode section 80 including a diode element such as a free wheel diode (FWD) is provided in the active region 160. In the example of Fig. 1, the transistor sections 70 and the diode sections 80 are alternately arranged along a predetermined arrangement direction (the X-axis direction in this example) on the upper surface of the semiconductor substrate 10.

[0054] In FIG. 1, the region where the transistor section 70 is arranged is marked with the symbol "I," and the region where the diode section 80 is arranged is marked with the symbol "F." In this specification, the direction perpendicular to the arrangement direction in a top view may be referred to as the extension direction (the Y-axis direction in FIG. 1). The transistor section 70 and the diode section 80 may each have a longitudinal direction in the extension direction. In other words, the length of the transistor section 70 in the Y-axis direction is greater than the width in the X-axis direction. Similarly, the length of the diode section 80 in the Y-axis direction is greater than the width in the X-axis direction. The extension direction of the transistor section 70 and the diode section 80 may be the same as the longitudinal direction of each trench section, which will be described later.

[0055] The diode section 80 has an N+ type cathode region in a region that contacts the lower surface of the semiconductor substrate 10. In this specification, the region in which the cathode region is provided is referred to as the diode section 80. In other words, the diode section 80 is a region that overlaps with the cathode region in a top view. A P+ type collector region may be provided in a region other than the cathode region on the lower surface of the semiconductor substrate 10.

[0056] The transistor section 70 has a P+ type collector region in a region in contact with the lower surface of the semiconductor substrate 10. In addition, the transistor section 70 has a gate structure periodically arranged on the upper surface side of the semiconductor substrate 10, the gate structure having an N type emitter region, a P type base region, a gate conductive portion, and a gate insulating film.

[0057] The semiconductor device 100 may have one or more pads above the semiconductor substrate 10. The semiconductor device 100 of this example has a gate pad 112 above the semiconductor substrate 10. The semiconductor device 100 may also have pads such as an anode pad, a cathode pad, and a current detection pad. Each pad is disposed near an edge 102. The vicinity of the edge 102 refers to the region between the edge 102 and the emitter electrode in a top view. When the semiconductor device 100 is mounted, each pad may be connected to an external circuit via wiring such as a wire.

[0058] A gate potential is applied to the gate pad 112. The gate pad 112 is electrically connected to a conductive portion of the gate trench portion of the active region 160. The semiconductor device 100 includes a gate wiring 130 that connects the gate pad 112 to the gate trench portion. The gate pad 112 is an example of a front surface electrode portion 200. The front surface electrode portion 200 may include the gate wiring 130 and the gate pad 112. The front surface electrode portion 200 may include an emitter electrode, which will be described later.

[0059] The gate wiring 130 is electrically connected to the gate conductive portion of the transistor portion 70 and applies a gate voltage to the transistor portion 70. The gate wiring 130 is provided so as to surround the outer periphery of the active region 160 in a top view. The gate wiring 130 is electrically connected to a gate pad 112 provided in the edge termination structure portion 170.

[0060] The semiconductor device 100 may also include a temperature sensing unit (not shown) which is a PN junction diode formed of polysilicon or the like, and a current detecting unit (not shown) which simulates the operation of a transistor unit provided in the active region 160.

[0061] In the present example, the semiconductor device 100 includes an edge termination structure 170 between the active region 160 and the edge 102 when viewed from above. The edge termination structure 170 in the present example is disposed between the gate wiring 130 and the edge 102. The edge termination structure 170 reduces electric field concentration on the top surface side of the semiconductor substrate 10. The edge termination structure 170 may include at least one of a guard ring, a field plate, and a resurf, which are arranged in an annular shape surrounding the active region 160.

[0062] 2A is an enlarged view of region A in Fig. 1. Region A is a region including the transistor section 70, the diode section 80, and the gate wiring 130. In this example, the gate wiring 130 includes a gate metal layer 50 and a gate runner section 51.

[0063] The transistor section 70 has a main region 75 and a boundary region 90. The boundary region 90 is provided on the front surface 21 of the semiconductor substrate 10 between the main region 75 of the transistor section 70 and the diode section 80. The front surface 21 of the semiconductor substrate 10 refers to one of two opposing main surfaces of the semiconductor substrate 10. The front surface 21 will be described later.

[0064] The semiconductor device 100 of this example includes a gate trench portion 40, a dummy trench portion 30, a well region 17, an emitter region 12, a base region 14, a contact region 15, and an anode region 19 formed inside the front surface 21 side of the semiconductor substrate 10. The semiconductor device 100 of this example also includes an emitter electrode 52 and a gate metal layer 50 provided above the semiconductor substrate 10. The emitter electrode 52 and the gate metal layer 50 are provided separately from each other.

[0065] An interlayer insulating film is formed between emitter electrode 52 and gate metal layer 50 and front surface 21 of semiconductor substrate 10, but the interlayer insulating film is omitted in Fig. 2A. In this example, contact holes 54, 55, and 56 are formed in the interlayer insulating film so as to penetrate the interlayer insulating film.

[0066] The emitter electrode 52 is electrically connected to the emitter region 12, contact region 15, base region 14, and anode region 19 on the front surface 21 of the semiconductor substrate 10 through a contact hole 54 opened in the interlayer insulating film. The emitter electrode 52 is also connected to a dummy conductive portion in the dummy trench portion 30 through a contact hole 56. The contact hole 56 that directly and electrically connects the emitter electrode 52 to the dummy conductive portion 34 in the dummy trench portion 30 may be referred to as a dummy trench contact hole 56. The dummy trench contact hole 56 may be a contact hole provided above the dummy conductive portion 34. The dummy conductive portion 34 will be described later.

[0067] The gate metal layer 50 contacts the gate runner 51 through a contact hole 55. The gate metal layer 50 and the gate runner 51 are electrically connected to the gate pad 112. The gate runner 51 is formed of a semiconductor such as polysilicon doped with impurities. In this example, the gate runner 51 includes polysilicon and connects the gate trench 40 and the gate metal layer 50. The gate runner 51 is connected to the gate conductive portion in the gate trench 40 on the front surface 21 of the semiconductor substrate 10. The gate runner 51 may be formed integrally with the gate conductive portion of the gate trench 40. In other words, the gate runner 51 and the gate conductive portion may be formed together in the same polysilicon formation process.

[0068] The emitter electrode 52 and the gate metal layer 50 are formed of a material containing metal. At least a portion of the emitter electrode 52 may be formed of a metal such as aluminum (Al), or a metal alloy such as aluminum-silicon alloy (AlSi) or aluminum-silicon-copper alloy (AlSiCu). At least a portion of the gate metal layer 50 may be formed of a metal such as aluminum (Al), or a metal alloy such as aluminum-silicon alloy (AlSi) or aluminum-silicon-copper alloy (AlSiCu). The emitter electrode 52 and the gate metal layer 50 may have a barrier metal made of titanium or a titanium compound below the region made of aluminum or the like. Each electrode may further have a plug formed by embedding tungsten or the like in a contact hole so as to contact the barrier metal and aluminum or the like.

[0069] The well region 17 is provided overlapping the gate metal layer 50 and the gate runner portion 51. The well region 17 is also provided extending by a predetermined width into an area where it does not overlap with the gate metal layer 50 and the gate runner portion 51. In this example, the well region 17 is provided away from the end of the contact hole 54 in the Y-axis direction toward the gate metal layer 50. The well region 17 is a region of a second conductivity type provided in the semiconductor substrate 10. The doping concentration of the well region 17 may be higher than the doping concentration of the base region 14. In this example, the base region 14 is P- type, and the well region 17 is P+ type.

[0070] Each of the transistor section 70 and the diode section 80 has a plurality of trench sections arranged in the trench arrangement direction on the front surface 21 of the semiconductor substrate 10. In the transistor section 70 of this example, one or more gate trench sections 40 and one or more dummy trench sections 30 are alternately arranged along the trench arrangement direction. In the diode section 80 of this example, a plurality of dummy trench sections 30 are arranged along the trench arrangement direction. In this example, the diode section 80 does not have a gate trench section 40. The trench arrangement direction may be the same as or different from the arrangement direction of the transistor section 70 and the diode section 80. In this example, the trench arrangement direction is the same as the arrangement direction of the transistor section 70 and the diode section 80.

[0071] In the transistor section 70, one or more gate trench sections 40 are arranged at predetermined intervals along the trench arrangement direction. The gate conductive section inside the gate trench section 40 is electrically connected to the gate metal layer 50, and a gate potential is applied thereto. In the transistor section 70, one or more dummy trench sections 30 may be arranged at predetermined intervals along the trench arrangement direction. A potential different from the gate potential is applied to the dummy conductive section inside the dummy trench section 30. In this example, the dummy conductive section is electrically connected to the emitter electrode 52, and an emitter potential is applied thereto.

[0072] In the transistor section 70, one or more gate trench sections 40 and one or more dummy trench sections 30 may be alternately formed along a predetermined trench arrangement direction. The dummy trench sections 30 are arranged at predetermined intervals along the predetermined trench arrangement direction in the diode section 80 and the boundary region 90. Note that the transistor section 70 may not be provided with dummy trench sections 30 and may be composed of only the gate trench sections 40.

[0073] The gate trench portion 40 in this example may have two extension portions 41 extending along a trench extension direction perpendicular to the trench arrangement direction, and a connection portion 43 connecting the two extension portions 41. The trench extension direction in FIG. 2A is the Y-axis direction. The trench extension direction may be the same as or different from the extension direction of the transistor portion 70 and the diode portion 80. The trench extension direction in this example is the same as the extension direction of the transistor portion 70 and the diode portion 80.

[0074] At least a part of the connecting portion 43 is preferably curved in a top view. By connecting the ends of the two extending portions 41 in the Y-axis direction with each other by the connecting portion 43, electric field concentration at the ends of the extending portions 41 can be alleviated.

[0075] In the transistor section 70, the dummy trench section 30 is provided between the extension portions 41 of the gate trench section 40. One or more dummy trench sections 30 may be provided between the extension portions 41. The dummy trench section 30 may have a linear shape extending in a predetermined trench extension direction, and may have an extension portion 31 and a connection portion 33, similar to the gate trench section 40. The semiconductor device 100 may include both linear dummy trench sections 30 without a connection portion 33 and dummy trench sections 30 with a connection portion 33. The direction in which the extension portion 41 of the gate trench section 40 or the extension portion 31 of the dummy trench section 30 extends long in the trench extension direction is defined as the longitudinal direction of the trench section. The longitudinal direction of the gate trench portion 40 or the dummy trench portion 30 may coincide with the extension direction of the transistor portion 70 and the diode portion 80. In this example, the extension direction of the transistor portion 70 and the diode portion 80 and the longitudinal direction of the trench portion are the Y-axis direction. The trench arrangement direction in which multiple gate trench portions 40 or dummy trench portions 30 are arranged is defined as the short-side direction of the trench portion. The short-side direction may coincide with the arrangement direction of the transistor portions 70 and the diode portions 80. The short-side direction may also be perpendicular to the longitudinal direction. In this example, the longitudinal direction and the short-side direction are perpendicular. In this example, the arrangement direction of the transistor portion 70 and the diode portion 80 and the short-side direction of the trench portion are the X-axis direction.

[0076] At a connection portion 43 at the tip of the gate trench portion 40, the gate conductive portion in the gate trench portion 40 and the gate runner portion 51 are connected. The gate trench portion 40 may be provided so as to protrude toward the gate runner portion 51 further than the dummy trench portion 30 in the trench extension direction (Y-axis direction). The protruding portion of the gate trench portion 40 is connected to the gate runner portion 51.

[0077] The diffusion depth of the well region 17 may be deeper than the depths of the gate trench portion 40 and the dummy trench portion 30. The ends of the gate trench portion 40 and the dummy trench portion 30 in the Y-axis direction are provided in the well region 17 when viewed from above. In other words, at the ends of each trench portion in the Y-axis direction, the bottom of each trench portion in the depth direction is covered by the well region 17. This makes it possible to alleviate electric field concentration at the bottom of each trench portion.

[0078] A mesa portion is provided between each trench portion in the arrangement direction. The mesa portion refers to a region inside the semiconductor substrate 10 that is sandwiched between two adjacent trench portions. As an example, the upper end of the mesa portion is the upper surface of the semiconductor substrate 10. The depth position of the lower end of the mesa portion is the same as the depth position of the lower end of the trench portion. In this example, the mesa portion is provided on the upper surface of the semiconductor substrate 10, extending along the trench portion in the trench extension direction (Y-axis direction).

[0079] The primary region 75 is a region in the transistor section 70 through which a primary current flows in the depth direction. The primary region 75 includes the emitter region 12 and the contact region 15. The area of ​​the primary region 75 may be larger than the area of ​​the boundary region 90.

[0080] The boundary region 90 is provided on the diode section 80 side of the transistor section 70. That is, the boundary region 90 is provided closer to the diode section 80 than the main region 75 is in the transistor section 70. The boundary region 90 may have a dummy trench portion 30 and may be a region in which a collector region 22 is provided on the back surface side of the semiconductor substrate 10. Both ends of the mesa portion of the boundary region 90 in the trench arrangement direction may contact the dummy trench portion 30. All of the trench portions in the boundary region 90 may be dummy trench portions 30. The boundary region 90 may also include a gate trench portion 40. In this example, the boundary region 90 does not have a first conductivity type emitter region 12 provided in the mesa portion on the front surface 21 side of the semiconductor substrate 10. The boundary region 90 may have a base region 14 on the front surface 21. The boundary region 90 may have an emitter region 12 or a contact region 15 on the front surface 21. Boundary region 90 in this example has base region 14 on front surface 21. Note that Fig. 2A shows the positions of collector region 22 and cathode region 82 provided on the back surface side of semiconductor substrate 10 when projected onto front surface 21.

[0081] The mesa portion 71 is a mesa portion provided in the main region 75 of the transistor portion 70. The mesa portion 81 is a mesa portion provided in the diode portion 80. The mesa portion 91 is a mesa portion provided in the boundary region 90. In this specification, when simply referred to as a mesa portion, it may refer to any of the mesa portion 71, the mesa portion 81, or the mesa portion 91. The extension portion of each trench portion may be considered as one trench portion. The region sandwiched between two extension portions may be considered as a mesa portion.

[0082] Each mesa may include a base region 14 or an anode region 19. Of the base regions 14 exposed on the front surface 21 of the semiconductor substrate 10 in the mesa, the region closest to the gate metal layer 50 is referred to as the base region 14-e. While FIG. 2A shows the base region 14-e at one end of each mesa in the trench extension direction, a base region 14-e may also be provided at the other end of each mesa. Each mesa may include at least one of a first-conductivity emitter region 12 and a second-conductivity contact region 15 in a region sandwiched between the base regions 14-e in a top view. In this example, the emitter region 12 is N+ type, and the contact region 15 is P+ type. The emitter region 12 and the contact region 15 may be provided between the base region 14 and the upper surface of the semiconductor substrate 10 in the depth direction.

[0083] The mesa portion 71 of the transistor portion 70 has an emitter region 12 exposed on the front surface 21 of the semiconductor substrate 10. The emitter region 12 is provided in contact with the gate trench portion 40. The mesa portion 71 may be provided with a contact region 15 exposed on the front surface 21 of the semiconductor substrate 10.

[0084] The emitter region 12 is provided on the front surface 21 of the semiconductor substrate 10 and is a region of the first conductivity type having a higher doping concentration than the drift region 18. The drift region 18 will be described later. The doping concentration of the emitter region 12 is 1E21 cm -3 Above, 1E22cm -3 The emitter region 12 in this example extends in the trench arrangement direction from one trench portion in contact with the mesa portion 71 to the other opposing trench portion.

[0085] An anode region 19 is provided in the mesa portion 81 of the diode portion 80. Contact regions 15 may be provided at both ends of the anode region 19 in the trench extension direction, and a base region 14-e may be provided. An emitter region 12 is not provided on the front surface 21 of the mesa portion 81, but an emitter region 12 may be provided thereon. A contact region 15 may be provided on the front surface 21 of the mesa portion 81.

[0086] The anode region 19 is a second conductivity type region provided in the mesa portion between the multiple trench portions. In this example, the anode region 19 is provided in the diode portion 80, but it may also be provided in the boundary region 90, or may be provided in both the diode portion 80 and the boundary region 90. The anode region 19 in this example is P-type, but is not limited to this. The doping concentration of the anode region 19 may be the same as or different from the doping concentration of the base region 14. The doping concentration of the anode region 19 may be greater or less than the doping concentration of the base region 14.

[0087] A contact hole 54 is provided above each mesa portion. The contact holes 54 are arranged in a region sandwiched between the base regions 14-e along the trench extension direction. In this example, the contact holes 54 are provided above the emitter region 12, the contact region 15, the base region 14, and the anode region 19. The contact holes 54 do not need to be provided in regions corresponding to the base region 14-e and the well region 17. The contact holes 54 may be arranged in the center of the mesa portion in the trench arrangement direction (X-axis direction).

[0088] In the diode section 80, an N+ type cathode region 82 is provided in a region adjacent to the lower surface of the semiconductor substrate 10. The doping concentration of the cathode region 82 is higher than the doping concentration of the drift region 18. A P+ type collector region 22 may be provided in a region of the lower surface of the semiconductor substrate 10 where the cathode region 82 is not provided. The cathode region 82 and the collector region 22 are provided between a rear surface 23 of the semiconductor substrate 10 and a buffer region 20, which will be described later. In FIG. 2A , a boundary 78 between the cathode region 82 and the collector region 22 is indicated by a dashed line. The rear surface 23 will be described later.

[0089] The cathode region 82 is disposed away from the well region 17 in the trench extension direction. This ensures a distance between the cathode region 82 and a P-type region (well region 17) that has a relatively high doping concentration and is formed deep, improving the breakdown voltage and suppressing hole injection from the well region 17. In this example, the end of the cathode region 82 in the trench extension direction is disposed farther from the well region 17 than the end of the contact hole 54 in the trench extension direction. In another example, the end of the cathode region 82 in the trench extension direction may be disposed between the well region 17 and the contact hole 54.

[0090] The base region 14 is provided in the mesa portion 91 of the boundary region 90. The boundary region 90 may have a plurality of mesa portions 91. The mesa portion 91 may be provided with a contact region 15. The mesa portion 91 in this example has the contact region 15 around the end of the contact hole 54 in the trench extension direction.

[0091] The trench contact portion 58 is provided in a mesa portion between two adjacent trench portions among the plurality of trench portions. The trench contact portion 58 extends from the front surface 21 of the semiconductor substrate 10 in the depth direction of the semiconductor substrate 10. The trench contact portion 58 may be provided extending from the upper end of the interlayer insulating film 38 to the inside of the semiconductor substrate 10. The trench contact portion 58 of this example is provided in the contact hole 54. By providing the trench contact portion 58, the semiconductor device 100 of this example can reduce the base resistance during turn-off and improve latch-up resistance.

[0092] At least one of the plurality of trench portions may have a narrow portion 60 and a wide portion 62. The narrow portion 60 and the wide portion 62 may be provided in the dummy trench portion 30, may be provided in the gate trench portion 40, or may be provided in both the dummy trench portion 30 and the gate trench portion 40.

[0093] The narrow width portion 60 is provided to extend in the trench extension direction. In this example, the narrow width portion 60 is provided in the extension portion 31 of the dummy trench portion 30. The narrow width portion 60 may be provided in the extension portion 41 of the gate trench portion 40. The narrow width portion 60 may be provided in the connection portion 33 of the dummy trench portion 30, or in the connection portion 43 of the gate trench portion 40.

[0094] The wide portion 62 is a region where the trench width is wider than the narrow portion 60. The wide portion 62 may be a region where the trench width is wider than the narrow portion 60. The trench width may be the width of the trench portion in the trench arrangement direction.

[0095] The wide portion 62 is provided so as to be connected to the narrow portion 60. The wide portion 62 may be provided so as to be connected to an end of the narrow portion 60 in the trench extension direction. In this example, the wide portion 62 is provided across the extension portion 31 and the connection portion 33 in the dummy trench portion 30. The wide portion 62 may be provided in either the extension portion 31 or the connection portion 33 in the dummy trench portion 30. The wide portion 62 may be provided across the extension portion 41 and the connection portion 43 in the gate trench portion 40, or may be provided in either the extension portion 41 or the connection portion 43. The wide portion 62 may have a bridging portion 63.

[0096] The connecting portion 63 is a region where the trench width gradually increases from the narrow portion 60. The trench width of the connecting portion 63 may gradually increase in a sloped shape that includes a straight line, or may gradually increase in a curved shape. The trench width of the connecting portion 63 gradually increasing in a sloped shape may mean that at least one end of the connecting portion 63 in the trench arrangement direction is sloped. The trench width of the connecting portion 63 gradually increasing in a curved shape may mean that at least one end of the connecting portion 63 in the trench arrangement direction is curved.

[0097] In this example, the connecting portion 63 is provided in the extending portion 31 in the dummy trench portion 30. The connecting portion 63 may be provided across the extending portion 31 and the connecting portion 33 in the dummy trench portion 30. The connecting portion 63 may be provided in either the extending portion 31 or the connecting portion 33 in the dummy trench portion 30. The connecting portion 63 may be provided across the extending portion 41 and the connecting portion 43 in the gate trench portion 40, or may be provided in either the extending portion 41 or the connecting portion 43.

[0098] In top view, the wide portion 62 is covered by the well region 17. In this case, the connecting portion 63 where the trench width increases from the narrow portion 60 is covered by the well region 17 in top view. This makes it possible to alleviate electric field concentration even in the region where the trench width changes.

[0099] The contact hole 56 in this example connects the emitter electrode 52 and the dummy trench portion 30. Specifically, the contact hole 56 connects the emitter electrode 52 and the dummy conductive portion of the dummy trench portion 30. The contact hole 56 in this example is provided above the wide portion 62 of the dummy trench portion 30. By providing the contact hole 56 above the wide portion 62 of the dummy trench portion 30, it becomes easier to connect the emitter electrode 52 to the dummy trench portion 30. This relaxes the required alignment accuracy and reduces the defect rate due to contact defects. The contact hole 56 may also be provided above the connecting portion 63.

[0100] The end position E30 is the end position of the dummy trench portion 30 in the trench extension direction. The end position E40 is the end position of the gate trench portion 40 in the trench extension direction. By reducing the difference D34 between the end of the gate trench portion 40 and the end of the dummy trench portion 30 in the trench extension direction, the electric field distribution at the end in the trench extension direction can be made more uniform. In the trench extension direction, the difference D34 between the end of the gate trench portion 40 and the end of the dummy trench portion 30 may be equal to or less than twice the pitch of the multiple trench portions, or may be equal to or less than 1 time. The pitch of the multiple trench portions may be the distance between the centers of adjacent trench portions in the trench arrangement direction. The pitch of the multiple trench portions may be equal to or greater than 1 μm and equal to or less than 5 μm. In the trench extension direction, the difference D34 between the end position E30 and the end position E40 may be equal to or greater than 0 μm and equal to or less than 4 μm.

[0101] 2B is a diagram showing an example of an XZ cross section including the a-a' cross section in FIG. 2A. The XZ cross section including the a-a' cross section is an XZ plane passing through the emitter region 12 in the main region 75. The semiconductor device 100 of this example has a semiconductor substrate 10, an interlayer insulating film 38, an emitter electrode 52, and a collector electrode 24 in the XZ cross section including the a-a' cross section. The emitter electrode 52 is provided above the semiconductor substrate 10 and the interlayer insulating film 38.

[0102] The drift region 18 is a region of a first conductivity type provided in the semiconductor substrate 10. In this example, the drift region 18 is, for example, an N-type. The drift region 18 may be a region remaining in the semiconductor substrate 10 without other doped regions being formed therein. That is, the doping concentration of the drift region 18 may be the same as the doping concentration of the semiconductor substrate 10.

[0103] The buffer region 20 is a region of the first conductivity type provided closer to the back surface 23 of the semiconductor substrate 10 than the drift region 18. In this example, the buffer region 20 is provided closer to the back surface 23 of the semiconductor substrate 10 than the center of the semiconductor substrate 10 in the depth direction. In this example, the buffer region 20 is, for example, N-type. The doping concentration of the buffer region 20 is higher than the doping concentration of the drift region 18. The buffer region 20 may function as a field stop layer that prevents a depletion layer spreading from the lower surface side of the base region 14 from reaching the collector region 22 of the second conductivity type and the cathode region 82 of the first conductivity type.

[0104] The collector region 22 and the cathode region 82 are provided on the back surface 23 of the semiconductor substrate 10. The collector region 22 is provided below the buffer region 20 in the transistor section 70. The cathode region 82 is provided below the buffer region 20 in the diode section 80. A boundary 78 between the collector region 22 and the cathode region 82 may be the boundary between the transistor section 70 and the diode section 80.

[0105] The collector electrode 24 is formed on the back surface 23 of the semiconductor substrate 10. The collector electrode 24 is formed of a conductive material such as a metal. At least a portion of the collector electrode 24 may be formed of a metal such as aluminum (Al), or a metal alloy such as an aluminum-silicon alloy (AlSi) or an aluminum-silicon-copper alloy (AlSiCu).

[0106] The base region 14 is a second conductivity type region provided above the drift region 18 in the mesa portion 71. The base region 14 may also be provided in the mesa portion 91. The base region 14 is provided in contact with the gate trench portion 40. The base region 14 may be provided in contact with the dummy trench portion 30.

[0107] The accumulation region 16 is provided above the drift region 18. That is, the accumulation region 16 is provided closer to the front surface 21 of the semiconductor substrate 10 than the drift region 18. The accumulation region 16 is a region of the first conductivity type having a higher doping concentration than the drift region 18. In this example, the accumulation region 16 is, for example, an N+ type. The doping concentration of the accumulation region 16 is 1E16 cm -3 Above, 1E18cm -3 The accumulation region 16 may be provided in the mesa portion 71. The accumulation region 16 may be provided in the mesa portion 81 and the mesa portion 91.

[0108] The accumulation region 16 is provided in contact with the gate trench portion 40. The accumulation region 16 may or may not be in contact with the dummy trench portion 30. The doping concentration of the accumulation region 16 is higher than the doping concentration of the drift region 18. By providing the accumulation region 16, the carrier injection enhancement effect (IE effect) can be enhanced, and the on-voltage of the transistor portion 70 can be reduced.

[0109] One or more gate trenches 40 and one or more dummy trenches 30 are provided on the front surface 21. Each trench extends from the front surface 21 to the drift region 18. In regions where at least one of the emitter region 12, the base region 14, the contact region 15, the accumulation region 16, and the anode region 19 is provided, each trench also penetrates these regions to reach the drift region 18. The trenches penetrating the doped regions are not limited to those formed in the order of forming the doped regions and then the trenches. The trenches penetrating the doped regions also include those formed after the trenches have been formed.

[0110] The gate trench portion 40 has a gate trench, a gate insulating film 42, and a gate conductive portion 44 formed on the front surface 21. The gate insulating film 42 is formed to cover the inner wall of the gate trench. The gate insulating film 42 may be formed by oxidizing or nitriding the semiconductor on the inner wall of the gate trench. The gate conductive portion 44 is formed inside the gate trench, further inward than the gate insulating film 42. The gate insulating film 42 insulates the gate conductive portion 44 from the semiconductor substrate 10. The gate conductive portion 44 is made of a conductive material such as polysilicon. The gate trench portion 40 is covered on the front surface 21 with an interlayer insulating film 38.

[0111] The gate conductive portion 44 includes a region facing the base region 14 across the gate insulating film 42. When a predetermined voltage is applied to the gate conductive portion 44, an electron channel is formed by an inversion layer in the surface layer of the base region 14 at the interface that contacts the gate trench.

[0112] The dummy trench portion 30 may have the same structure as the gate trench portion 40. The dummy trench portion 30 has a dummy trench, a dummy insulating film 32, and a dummy conductive portion 34 formed on the front surface 21 side. The dummy insulating film 32 is formed to cover the inner wall of the dummy trench. The dummy conductive portion 34 is formed inside the dummy trench and further inward than the dummy insulating film 32. The dummy insulating film 32 insulates the dummy conductive portion 34 from the semiconductor substrate 10. The dummy trench portion 30 may be covered on the front surface 21 with an interlayer insulating film 38.

[0113] The interlayer insulating film 38 is provided above the semiconductor substrate 10. In this example, the interlayer insulating film 38 is provided on the front surface 21. An emitter electrode 52 is provided above the interlayer insulating film 38. One or more contact holes 54 are provided in the interlayer insulating film 38 to electrically connect the emitter electrode 52 and the semiconductor substrate 10. Contact holes 55 and 56 may also be provided so as to penetrate the interlayer insulating film 38.

[0114] The front surface electrode portion 200 is provided above the front surface 21 of the semiconductor substrate 10. The front surface electrode portion 200 has an emitter electrode 52, a barrier metal portion 220, and a plug portion 230. The front surface electrode portion 200 may have a silicide layer 210, which will be described later. The front surface electrode portion 200 may have a trench contact portion 58. The front surface electrode portion 200 may be in ohmic contact with a plug region 13, which will be described later.

[0115] The barrier metal portion 220 is provided on the sidewall and bottom surface of the contact hole 54. The barrier metal portion 220 may be provided on the entire bottom surface of the contact hole 54. The material of the barrier metal portion 220 may be titanium (Ti) and / or a titanium compound. The barrier metal portion 220 may contain Ti or may contain TiN. Here, TiN is a compound of titanium and nitrogen.

[0116] The plug portion 230 is provided inside the barrier metal portion 220 in the contact hole 54. The material of the plug portion 230 may be tungsten. The material of the plug portion 230 may be the same as the material of the emitter electrode 52. In other words, the plug portion 230 may be the portion of the emitter electrode 52 that is embedded in the contact hole 54.

[0117] Although the semiconductor device 100 of this example does not include a lifetime control unit having a lifetime killer, it may include a lifetime control unit. The semiconductor device 100 may include a lifetime killer region closer to the front surface 21 than the center in the depth direction of the semiconductor substrate 10, or may include a lifetime killer region closer to the back surface 23 than the center in the depth direction of the semiconductor substrate 10.

[0118] The anode region 19 is a second conductivity type region provided above the drift region 18. The anode region 19 is provided in the mesa portion 81. The anode region 19 may be in contact with the dummy trench portion 30. In this example, the anode region 19 is provided in the mesa portion 81, extending in the trench arrangement direction from one adjacent dummy trench portion 30 to the other adjacent dummy trench portion 30. The anode region 19 may be provided in contact with the gate trench portion 40. The depth of the anode region 19 may be deeper, shallower, or equal to the depth of the base region 14 in the depth direction of the semiconductor substrate 10. In this example, the depth of the anode region 19 is equal to the depth of the base region 14.

[0119] The doping concentration of the anode region 19 may be the same as that of the base region 14, or may be lower or higher than that of the base region 14. The maximum doping concentration of the anode region 19 may be lower, higher, or equal to the maximum doping concentration of the base region 14. In this example, the maximum doping concentration of the anode region 19 is the same as the maximum doping concentration of the base region 14. The integral of the doping concentration of the anode region 19 along the depth direction of the semiconductor substrate 10 may be smaller, larger, or equal to the integral of the doping concentration of the base region 14. In this example, the integral of the doping concentration of the anode region 19 along the depth direction is the same as the integral of the doping concentration of the base region 14 along the depth direction. The depth direction is the direction from the front surface 21 toward the back surface 23, which in this example is the -Z-axis direction. The anode region 19 in this example is P-type.

[0120] The plug region 13 is a region of a second conductivity type provided above the drift region 18 and having a higher doping concentration than the base region 14 and the anode region 19. The plug region 13 may have a higher doping concentration than the contact region 15. In this example, the plug region 13 is of P++ type, but is not limited to this.

[0121] The plug region 13 may be provided in the semiconductor substrate 10 and in contact with the front surface electrode portion 200. The plug region 13 in this example is provided below the trench contact portion 58. The plug region 13 may be in contact with the trench contact portion 58. The plug region 13 in this example is in contact with the bottom surface of the trench contact portion 58. The plug region 13 may be in contact with a side surface of the trench contact portion 58. The emitter region 12 may be in contact with a side surface of the trench contact portion 58 on the front surface 21 side of the plug region 13.

[0122] The plug region 13 may be provided continuously on the bottom surface of the trench contact portion 58, extending in the trench extension direction. The plug region 13 may be provided over the entire bottom surface of the trench contact portion 58. The plug region 13 may be provided discretely on the bottom surface of the trench contact portion 58 in the trench extension direction. The plug region 13 may be provided in at least one of the main region 75, the diode portion 80, or the boundary region 90. In this example, the plug region 13 is provided in each of the main region 75, the diode portion 80, and the boundary region 90.

[0123] The plug region 13 may contact the anode region 19 at the mesa portion 81. The lower end of the plug region 13 may be shallower than the lower end of the anode region 19. The plug region 13 may contact the emitter region 12 and the base region 14 at the mesa portion 71. The lower end of the plug region 13 may be deeper than the lower end of the emitter region 12 and shallower than the lower end of the base region 14. The plug region 13 may contact the base region 14 at the mesa portion 91.

[0124] The bottom end of the trench contact portion 58 may be deeper than the bottom end of the emitter region 12. The bottom end of the trench contact portion 58 may be shallower than the bottom end of the base region 14. The bottom end of the trench contact portion 58 may be shallower than the top end of the accumulation region 16. The shape of the trench contact portion 58 may be the same or different in the main region 75, the diode portion 80, and the boundary region 90.

[0125] 2C is a diagram showing an example of an XZ cross section including the b-b' cross section in FIG. 2A. The XZ cross section including the b-b' cross section is an XZ plane that passes through the contact region 15 in the main region 75. In this example, differences from the a-a' cross section in FIG. 2B that passes through the emitter region 12 will be particularly described. Other points may be the same as the a-a' cross section in FIG. 2B.

[0126] The lower end of the contact region 15 may be deeper than the lower end of the emitter region 12. The contact region 15 may be in contact with the plug region 13 and the base region 14 in the mesa portion 71. The contact region 15 may be in contact with the side surface of the trench contact portion 58 on the front surface 21 side of the plug region 13.

[0127] The plug region 13 may contact the contact region 15 and the base region 14 at the mesa portion 71. The bottom end of the plug region 13 may be deeper than the bottom end of the contact region 15 and shallower than the bottom end of the base region 14.

[0128] The bottom end of the trench contact portion 58 may be deeper than the bottom end of the contact region 15. The bottom end of the trench contact portion 58 may be shallower than the bottom end of the base region 14. The bottom end of the trench contact portion 58 may be shallower than the top end of the accumulation region 16. The shape of the trench contact portion 58 in an XZ cross section passing through the contact region 15 may be the same as the shape of the trench contact portion 58 in an XZ cross section passing through the emitter region 12 in FIG. 2B, for example.

[0129] The mesa portion 81 may be the same as the mesa portion 81 in the aa' cross section of Figure 2B. The mesa portion 91 may be the same as the mesa portion 91 in the aa' cross section of Figure 2B.

[0130] 2D is an enlarged view of an XZ cross section passing through the mesa portion 71. This figure illustrates the mesa portion 71 sandwiched between two adjacent dummy trench portions 30. The front surface electrode portion 200 has a silicide layer 210, a barrier metal portion 220, a plug portion 230, and an emitter electrode 52.

[0131] The silicide layer 210 is in contact with the semiconductor substrate 10. If the semiconductor substrate 10 is silicon, the silicide layer 210 may be a layer formed by silicidation of the barrier metal portion 220 through reaction with the semiconductor substrate 10. The silicide layer 210 is provided on both the bottom and side surfaces of the trench contact portion 58. In this example, the silicide layer 210 is in contact with the emitter region 12 and the plug region 13. The silicide layer 210 does not need to be provided in a region that is not in contact with the semiconductor substrate 10. The material of the silicide layer 210 in this example is Ti, a compound of titanium (Ti) and silicon (Si). x Si y Here, x and y are values ​​that indicate the stoichiometry of a titanium-silicon compound. In this specification, the material of the silicide layer 210 may be simply referred to as TiSi.

[0132] The barrier metal portion 220 is in contact with the silicide layer 210. The barrier metal portion 220 may contain a material that reacts with Si of the semiconductor substrate 10 to form a silicide. The barrier metal portion 220 may contain Ti. The barrier metal portion 220 of this example has a first barrier metal layer 221 and a second barrier metal layer 222.

[0133] The first barrier metal layer 221 is provided on the side surface of the trench contact portion 58. The first barrier metal layer 221 may be in contact with the silicide layer 210 provided on the side surface and bottom surface of the trench contact portion 58. A part of the first barrier metal layer 221 may be in contact with the interlayer insulating film 38 on the side surface of the trench contact portion 58. The material of the first barrier metal layer 221 in this example is Ti.

[0134] The second barrier metal layer 222 is provided inside the first barrier metal layer 221 in the trench contact portion 58. The second barrier metal layer 222 is provided close to the bottom and side surfaces of the trench contact portion 58. The second barrier metal layer 222 may be in contact with the first barrier metal layer 221. In this example, the material of the second barrier metal layer 222 is TiN, a compound of titanium (Ti) and nitrogen (N). The stoichiometry of the compound of titanium and nitrogen is omitted.

[0135] The plug portion 230 is provided inside the barrier metal portion 220 in the trench contact portion 58. In this example, the plug portion 230 is provided inside the second barrier metal layer 222 in the trench contact portion 58. The plug portion 230 in this example is in contact with the second barrier metal layer 222. The plug portion 230 may be formed using a method and material that can fill the inside of the contact hole 54. The material of the plug portion 230 in this example is tungsten (W).

[0136] In this manner, the semiconductor device 100 may have a layered structure of the semiconductor substrate 10, the silicide layer 210, the first barrier metal layer 221, the second barrier metal layer 222, and the plug portion 230. In one example, the semiconductor device 100 has a layered structure of a Si substrate, a TiSi layer, a Ti layer, a TiN layer, and a W layer.

[0137] 2B, the emitter region 12 may be in contact with the side surface of the trench contact portion 58 on the front surface 21 side of the plug region 13. That is, the emitter region 12 may be in contact with the silicide layer 210 on the front surface 21 side of the plug region 13. This electrically connects the emitter region 12 to the emitter electrode 52 and prevents latch-up of the transistor portion 70.

[0138] Depth D58 indicates the distance from front surface 21 to the bottom end of trench contact portion 58 in the depth direction of semiconductor substrate 10. Increasing depth D58 suppresses the amount of holes injected from transistor portion 70 to diode portion 80, making it easier to reduce reverse recovery loss Err.

[0139] The mesa width Wm is the width of the mesa portion in the trench arrangement direction. In this example, the mesa width Wm indicates the mesa width of the mesa portion 71. The trench width Wt is the width of any one of the multiple trench portions in the trench arrangement direction. In this example, the trench width Wt indicates the trench width of the dummy trench portion 30. In this example, the mesa width Wm is larger than the trench width Wt, but may be smaller than or the same as the trench width Wt.

[0140] 3A is an enlarged view of region B in FIG. 2A. Region B is a region including narrow portions 60 and wide portions 62. The trench portion in this example is a dummy trench portion 30, but a similar structure may also be applied to the gate trench portion 40.

[0141] The contact width W56 is the contact width in the trench arrangement direction of the contact hole 56 provided above the wide portion 62. The contact width W56 may be the same as or different from the contact width W54 of the contact hole 54 in the trench arrangement direction. The contact width W56 may be larger or smaller than the contact width W54. The contact width W56 may be larger or smaller than the trench width W60 of the narrow portion 60. The contact width W56 may be the same as the trench width W60 of the narrow portion 60. In this example, the contact width W56 is smaller than the trench width W60 of the narrow portion 60. In this example, the contact width W56 in the trench arrangement direction of the dummy trench contact hole 56 provided above the wide portion 62 of the dummy trench portion 30 is smaller than the trench width W60 of the narrow portion 60 of the dummy trench portion 30. The contact width W56 may be 0.2 μm or more and 1.0 μm or less. By reducing the contact width W56 of the contact hole 56, it is possible to provide a margin for the trench width W62 of the wide portion 62. This makes it possible to suppress contact failures even when misalignment occurs, thereby improving the yield rate.

[0142] As will be described later, a contact hole 56 may be provided above the gate trench portion 40. In this case, the contact width W56 in the trench arrangement direction of the gate trench contact hole 56 provided above the wide portion 62 of the gate trench portion 40 may be smaller than the trench width W60 of the narrow portion 60 of the gate trench portion 40.

[0143] The trench width W60 is smaller than the trench width W62 of the wide portion 62. The trench width W60 and the trench width W62 are examples of the width Wt of the trench portion. The trench width W60 may be common to the dummy trench portion 30 and the gate trench portion 40, or may be different. Similarly, the trench width W62 may be common to the dummy trench portion 30 and the gate trench portion 40, or may be different.

[0144] The contact length L56 is the length of the contact hole 56 in the trench extension direction. In this example, the contact length L56 is greater than the contact width W56. That is, the longitudinal direction of the contact hole 56 is the trench extension direction. The contact length L56 may be 3.0 μm or more and 20.0 μm or less.

[0145] In this example, the wide portion 62 is provided inside the well region 17 when viewed from above. In this case, the connecting portion 63 is also provided inside the well region 17 when viewed from above. This makes it possible to alleviate electric field concentration around the connecting portion 63.

[0146] The distance Le indicates the distance in the trench extension direction between the contact hole 56 for connecting the emitter electrode 52 and the dummy trench portion 30 and the end of the emitter electrode 52. The distance Le may be 1 μm or more and 50 μm or less, or may be 5 μm or more and 20 μm or less.

[0147] Distance La indicates the distance in the trench extension direction between well region 17 and emitter region 12 that is closest to well region 17. Distance La may be 5.0 μm or more and 80 μm or less, or may be 10 μm or more and 50 μm or less.

[0148] Distance Lb indicates the distance in the trench extension direction between gate runner portion 51 and emitter region 12 that is closest to gate runner portion 51. Distance Lb may be 20 μm or more and 100 μm or less, or may be 30 μm or more and 80 μm or less.

[0149] The angle θ is the angle of the sidewall of the bridging portion 63 relative to the trench extension direction. The angle θ may be the angle of the slope at which the trench width Wt gradually increases from the narrow portion 60. The angle θ may be smaller than 90 degrees, or may be equal to or less than 60 degrees, or may be equal to or less than 45 degrees, or may be equal to or less than 30 degrees. By making the angle θ smaller, electric field concentration can be more easily alleviated. By making the angle θ larger, a region with a larger trench width Wt can be positioned closer to the narrow portion 60.

[0150] The connecting portion 63 has a structure in which only one side wall gradually widens. In this example, the connecting portion 63 has a structure in which only the outer side wall of the U-shaped trench portion gradually widens. The connecting portion 63 may have a structure in which only the inner side wall of the U-shaped trench portion gradually widens. In the case of the dummy trench portion 30, the U-shaped shape is composed of the extension portion 31 and the connection portion 33. The dummy trench portion 30 may have U-shaped shapes at both ends in the trench extension direction. In the case of the gate trench portion 40, the U-shaped shape is composed of the extension portion 41 and the connection portion 43. The gate trench portion 40 may have U-shaped shapes at both ends in the trench extension direction.

[0151] In a region where the trench width Wt changes, such as the connecting portion 63, the conditions for forming the oxide film in the trench may change, resulting in a change in the thickness of the oxide film. Even in such a case, by forming one sidewall of the trench in a straight line without widening it is possible to form a uniform oxide film on the straight sidewall. Note that the connecting portion 63 may have a structure in which it gradually widens on both sidewalls in the trench arrangement direction.

[0152] 3B is an enlarged view of a modified example of region B in FIG. 2A. In this figure, the shape of the contact hole 56 is different from that of the contact hole 56 in FIG. 3A. In this example, differences from the example in FIG. 3A will be particularly described, and other points may be the same as those in FIG. 3A. The trench portion in this example is a dummy trench portion 30, but a similar structure may also be applied to the case of a gate trench portion 40.

[0153] The contact width W56 is equal to or greater than the trench width W60 of the narrow portion 60. In this example, the contact width W56 in the trench arrangement direction of the dummy trench contact hole 56 provided above the wide portion 62 of the dummy trench portion 30 is equal to or greater than the trench width W60 of the narrow portion 60 of the dummy trench portion 30. In the semiconductor device 100 of this example, by providing the wide portion 62 whose trench width Wt is wider than that of the narrow portion 60, the contact width W56 of the contact hole 56 can be equal to or greater than the trench width W60 of the narrow portion 60. By increasing the contact width W56, contact breaks can be more easily suppressed even when defects due to foreign matter or the like occur. This improves the yield rate of the semiconductor device 100 and improves reliability.

[0154] As will be described later, contact holes 56 may be provided above the gate trench portions 40. In this case, the contact width W56 in the trench arrangement direction of the gate trench contact holes 56 provided above the wide portions 62 of the gate trench portions 40 may be equal to or greater than the trench width W60 of the narrow portions 60 of the gate trench portions 40. When the contact holes 56 are provided above the gate trench portions 40, increasing the contact width W56 makes it easier to prevent contact failures caused by foreign matter or the like and current imbalances caused by gate delays.

[0155] The contact width W56 is smaller than the trench width W62 of the wide portion 62. The contact width W56 in this example is larger than the contact width W54 in the trench arrangement direction of the contact hole 54. The contact length L56 in this example is larger than the contact width W56.

[0156] The connecting portion 63 in this example has a curved shape. The trench width of the connecting portion 63 may gradually increase in a curved shape. Increasing the radius of curvature R of the connecting portion 63 makes it easier to alleviate electric field concentration. The radius of curvature R of the connecting portion 63 may be 0.1 μm or more and 5.0 μm or less, or may be 0.1 μm or more and 1.0 μm or less. The radius of curvature R of the connecting portion 63 may be the radius of curvature of any curved portion included in the connecting portion 63.

[0157] 3C is a diagram showing an example of an XZ cross section including the c-c' cross section in FIG. 3A. The XZ cross section including the c-c' cross section is an XZ plane passing through the well region 17 and the dummy trench portion 30. In this example, the wide portion 62 of the dummy trench portion 30 is illustrated, but a similar structure may also be applied to the wide portion 62 of the gate trench portion 40.

[0158] The well region 17 is provided above the drift region 18. The well region 17 is provided below the wide portion 62. The bottom surface of the wide portion 62 may be shallower than the lower end of the well region 17. The well region 17 in this example is provided below the connecting portion 63. The bottom surface of the connecting portion 63 may be shallower than the lower end of the well region 17. The well region 17 in this example covers the sidewalls and bottom surface of the wide portion 62. The well region 17 in this example covers the sidewalls and bottom surface of the connecting portion 63. This makes it possible to alleviate electric field concentration in the wide portion 62.

[0159] The difference D1 is the difference in the depth direction of the semiconductor substrate 10 between the depth Dt of the lower end of the trench portion and the depth D17 of the lower end of the well region 17. The depth Dt of the lower end of the trench portion may be 1.0 μm or more and 10.0 μm or less. The depth D17 of the lower end of the well region 17 may be 4.0 μm or more and 15.0 μm or less. The difference D1 may be 0.5 μm or more, 1.0 μm or more, 1.5 μm or more, or 2.0 μm or less.

[0160] 3D is a diagram showing an example of a YZ cross section including the d-d' cross section in FIG. 3A. The YZ cross section including the d-d' cross section is a YZ plane passing through the dummy trench portion 30 and the well region 17. In this example, a cross section of the dummy trench portion 30 is illustrated, but a similar structure may also be applied to a cross section of the gate trench portion 40.

[0161] The trench depth of the wide portion 62 is deeper than the trench depth of the narrow portion 60. That is, the lower end of the connecting portion 63 gradually becomes deeper as it moves from the narrow portion 60 toward the wide portion 62 in the trench extension direction. The trench depths of the narrow portion 60 and the wide portion 62 can be adjusted by the etching conditions of the semiconductor substrate 10. Therefore, the trench depth of the narrow portion 60 can be made deeper or shallower than the trench depth of the wide portion 62.

[0162] The well region 17 is provided so as to cover the side surfaces and the bottom of the end portions in the trench extension direction of the dummy trench portion 30. The well region 17 is provided below the wide portion 62. In this case, the well region 17 is provided below the connecting portion 63. The well region 17 may also be provided below the narrow portion 60.

[0163] In the semiconductor device 100 of this embodiment, by providing the well region 17 in the connecting portion 63 where the trench depth changes, the electric field concentration in the connecting portion 63 is alleviated, making it easier to avoid overvoltage breakdown.

[0164] 3E is a diagram showing a modified example of the YZ cross section including the dd' cross section in FIG. 3A. In this example, the cross section of the dummy trench portion 30 is illustrated, but a similar structure may also be applied to the cross section of the gate trench portion 40.

[0165] The trench depth of the wide portion 62 is shallower than the trench depth of the narrow portion 60. The lower end of the connecting portion 63 gradually becomes shallower in the trench extension direction as it progresses from the narrow portion 60 toward the wide portion 62. That is, the trench depth of the connecting portion 63 is shallower than the trench depth of the narrow portion 60.

[0166] The semiconductor device 100 of this example can suppress a decrease in breakdown voltage by shallowing the trench depth of the wide portion 62 located at the end in the trench extension direction. Also, the semiconductor device 100 can suppress a decrease in breakdown voltage by shallowing the trench depth of the connecting portion 63 where the trench width Wt changes and there is a possibility of fluctuation in breakdown voltage.

[0167] 4A is a top view showing a modified example of the semiconductor device 100. The semiconductor device 100 of this example connects the gate trench portion 40 to the gate metal layer 50 in a different way than the semiconductor device 100 of FIG.

[0168] The gate trench portion 40 has a narrow portion 60 and a wide portion 62. The wide portion 62 of the gate trench portion 40 has a connecting portion 63. A contact hole 56 is provided above the wide portion 62 of the gate trench portion 40. The contact hole 56 connects the gate trench portion 40 and the gate metal layer 50. The contact hole 56 that directly and electrically connects the gate conductive portion 44 of the gate trench portion 40 and the gate metal layer 50 may be referred to as a gate trench contact hole 56. The gate trench contact hole 56 may be a contact hole provided above the gate conductive portion 44.

[0169] The contact hole 56 for connecting the gate metal layer 50 and the gate trench portion 40 is provided above the wide portion 62 of the gate trench portion 40. Therefore, the gate conductive portion 44 of the gate trench portion 40 is directly connected to the gate metal layer 50. The semiconductor device 100 of this example does not need to include a gate runner portion 51 for connecting the gate trench portion 40 and the gate metal layer 50. By providing the contact hole 56 above the wide portion 62 of the gate trench portion 40, it is easier to avoid the occurrence of a gate-emitter short circuit caused by the contact hole 56 protruding from the gate trench portion 40 due to misalignment.

[0170] In this example, the dummy trench portion 30 and the gate trench portion 40 have the same shape, but may have different shapes. The contact hole 56 in the dummy trench portion 30 may be provided at a different position in the trench extension direction from the contact hole 56 in the gate trench portion 40. The contact hole 56 in the dummy trench portion 30 and the contact hole 56 in the gate trench portion 40 may both be provided in the wide portion 62.

[0171] An emitter electrode 52 and a gate metal layer 50 are provided above the wide portion 62. The contact hole 56 of the dummy trench portion 30 is disposed in a region where the emitter electrode 52 is provided in a top view. The contact hole 56 of the gate trench portion 40 is disposed in a region where the gate metal layer 50 is provided in a top view.

[0172] In this example, the end position E30 is equal to the end position E40. That is, the difference D34 between the end of the gate trench portion 40 and the end of the dummy trench portion 30 in the trench extension direction is sufficiently small. For example, the difference D34 being sufficiently small may mean that the difference D34 does not exceed the width of the trench portion of the wide portion 62, or may be 10% or less of the width of the trench portion of the wide portion 62. This makes it possible to make the electric field distribution at the end in the trench extension direction more uniform.

[0173] The wide portions 62 of the dummy trench portion 30 and the gate trench portion 40 may be covered by the well region 17 in top view. Similarly, the connecting portions 63 of the dummy trench portion 30 and the gate trench portion 40 may be covered by the well region 17 in top view.

[0174] The semiconductor device 100 of this example does not include a gate runner 51 made of polysilicon. This allows for greater freedom in designing the shapes of the dummy trench 30 and the gate trench 40. As in this example, the dummy trench 30 and the gate trench 40 may have the same shape. Furthermore, this reduces the step in the resist after the polysilicon film formation process, improving manufacturing accuracy. This allows for narrower spacing between other components around the connection portion 43 of the gate trench 40, thereby increasing the area of ​​the active region 160.

[0175] In the semiconductor device 100 of this example, the contact holes 56 of the gate trench portions 40 are provided in the wide portions 62, thereby making it possible to suppress contact failure with the gate trench portions 40. This makes it easier to avoid gate defects in the semiconductor device 100.

[0176] 4B is an enlarged view of region C in FIG. 4A. Region C is a region that includes the dummy trench portion 30 and the wide portion 62 of the gate trench portion 40.

[0177] The distance D56 is the distance in the trench extension direction between the contact hole 56 provided above the gate trench portion 40 and the contact hole 56 provided above the dummy trench portion 30. The distance D56 may be 8 μm or more and 20 μm or less. The length L56 may be smaller than the distance D56.

[0178] Distance D52 is the distance in the trench extension direction between the contact hole 56 provided above the dummy trench portion 30 and the end of the emitter electrode 52. Distance D52 may be 1.0 μm or more and 10.0 μm or less.

[0179] Distance D50 is the distance in the trench extension direction between the contact hole 56 provided above the gate trench portion 40 and the end of the gate metal layer 50. Distance D50 may be 1.0 μm or more and 10.0 μm or less. Distance D50 may be length L56 or less.

[0180] FIG. 5 is a top view showing a modified example of the semiconductor device 100. The semiconductor device 100 of this example differs from the semiconductor device 100 of FIG. 2A in that the gate trench portion 40 does not have a wide portion 62. In this example, the differences from the semiconductor device 100 of FIG. 2A will be particularly described. The dummy trench portion 30 of this example has a narrow portion 60 and a wide portion 62. The wide portion 62 has a connecting portion 63. A contact hole 56 may be provided above the connecting portion 63.

[0181] The gate trench portion 40 in this example does not have a wide portion 62. The trench width Wt of the gate trench portion 40 may be uniform. The trench width Wt of the extension portion 41 may be the same as the trench width Wt of the connection portion 43. The trench width Wt of the gate trench portion 40 may be the same as the trench width Wt of the extension portion 31 of the dummy trench portion 30. The trench width Wt of the gate trench portion 40 may be the same as the trench width Wt of the narrow portion 60 of the dummy trench portion 30. The trench width Wt of the gate trench portion 40 may be smaller than the trench width W62 of the wide portion 62 of the dummy trench portion 30.

[0182] In the semiconductor device 100 of this example, the gate trench 40 and the gate metal layer 50 are connected to each other using the gate runner 51. However, the semiconductor device 100 may omit the gate runner 51 and directly connect the gate trench 40 to the gate metal layer 50 using a contact hole 56 above the gate trench 40.

[0183] 6 is a top view showing a modified example of the semiconductor device 100. The semiconductor device 100 of this example differs from the semiconductor device 100 of FIG. 2A in that dummy trench portions 30 are arranged between the gate trench portions 40. In this example, the differences from the semiconductor device 100 of FIG. 2A will be particularly described.

[0184] The multiple gate trenches 40 sandwich at least one of the multiple dummy trenches 30 between two extension portions 41 connected by a connection portion 43. In the present example, the multiple gate trenches 40 sandwich the multiple dummy trenches 30 between two extension portions 41 connected by a connection portion 43. That is, the multiple gate trenches 40 sandwich two extension portions 31 connected by a connection portion 33 in the multiple dummy trenches 30 between two extension portions 41 connected by a connection portion 43 in the multiple gate trenches 40.

[0185] Even when the dummy trench portion 30 is arranged inside the gate trench portion 40 as in this example, the difference D34 between the end of the gate trench portion 40 and the end of the dummy trench portion 30 in the trench extension direction may be less than twice the pitch of the multiple trench portions, or may be less than one time.

[0186] In this example, the gate trench portion 40 is connected to the gate metal layer 50 via the gate runner portion 51, but the gate runner portion 51 may be omitted and the gate trench portion 40 may be connected to the gate metal layer 50 using a contact hole 56. The gate trench portion 40 may have a narrow portion 60 and a wide portion 62.

[0187] 7A is a top view showing a modified example of the semiconductor device 100. The semiconductor device 100 of this example differs from the semiconductor device 100 of FIG. 6 in that the semiconductor device 100 of this example has a contact hole 57 in the wide portion 62 of the dummy trench portion 30. In this example, the differences from the semiconductor device 100 of FIG. 6 will be particularly described.

[0188] The contact holes 57 extend in the trench arrangement direction above the connection portions 33. Extending in the trench arrangement direction may mean that the longitudinal direction is the trench arrangement direction. The contact holes 57 may be provided in the same connection portions 33 as the contact holes 56. The contact holes 57 may be provided in portions of the connection portions 33 that extend in the trench arrangement direction. By providing multiple contact holes in the wide portions 62, it is possible to suppress a decrease in the yield rate even if poor contact occurs in any of the contact holes.

[0189] A single connection portion 33 may be provided with a plurality of contact holes 56. A single connection portion 33 may be provided with a plurality of contact holes 57. In this example, a single connection portion 33 is provided with two contact holes 56 and one contact hole 57.

[0190] In this example, the gate trench portion 40 is connected to the gate metal layer 50 via the gate runner portion 51, but the gate runner portion 51 may be omitted and the gate trench portion 40 may be connected to the gate metal layer 50 using a contact hole 56. In any embodiment, the contact hole 57 may be provided in the gate trench portion 40. That is, the contact hole 57 may be provided in the connection portion 43 of the gate trench portion 40, extending in the trench arrangement direction.

[0191] 7B is a top view showing a modified example of the semiconductor device 100. The semiconductor device 100 of this example differs from the semiconductor device 100 of FIG. 7A in that the wide portion 62 of the gate trench portion 40 is U-shaped, the width of the inside of the gate trench portion 40 is also widened, and the gate conductive portion 44 is directly connected to the gate metal layer 50 via the contact hole 56. In this example, the differences from the semiconductor device 100 of FIG. 7A will be particularly described.

[0192] The gate trench 40 of this example has a narrow portion 60 and a wide portion 62. The gate trench 40 may have a connecting portion 63. The wide portion 62 of the gate trench 40 has a U-shaped structure in which at least one of the inner and outer widths is widened. The gate trench 40 of this example has a U-shaped structure in which both the inner and outer widths are widened. By making the wide portion 62 of the gate trench 40 U-shaped, the radius of curvature R of the change in the sidewall of the gate trench 40 can be made larger. The radius of curvature R of the change in the sidewall of the gate trench 40 may be approximately 0.1 μm. This allows the thickness of the gate insulating film 42 to be maintained uniform, thereby suppressing dielectric breakdown. The radius of curvature R may be 0.05 μm or more and 0.2 μm or less.

[0193] 8 is a top view showing a modified example of the semiconductor device 100. The semiconductor device 100 of this example differs from the semiconductor device 100 of FIG. 2A in that the semiconductor device 100 has a wide portion 62 only in the gate trench portion 40. In this example, the differences from the semiconductor device 100 of FIG. 2A will be particularly described.

[0194] The gate trench portion 40 has a narrow portion 60 and a wide portion 62. The wide portion 62 of the gate trench portion 40 is connected to the gate metal layer 50 via a gate runner portion 51. The gate trench portion 40 may be connected to the gate metal layer 50 using a contact hole 56 above the gate trench portion 40, omitting the gate runner portion 51. The contact hole 56 may not be provided above the gate trench portion 40.

[0195] The dummy trench portion 30 does not have a wide portion 62. The dummy trench portion 30 of this example is connected to the gate metal layer 50 using a contact hole 56 provided above the dummy trench portion 30. The contact hole 56 of this example is provided above the extension portion 31 of the dummy trench portion 30.

[0196] 9 is a top view showing a modified example of the semiconductor device 100. In the semiconductor device 100 of this example, adjacent trench portions are connected to each other. The semiconductor device 100 of this example has only the gate trench portion 40 in the main region 75 of the transistor portion 70, but may also have a dummy trench portion 30.

[0197] Adjacent wide portions 62 are connected to each other. In this example, the wide portions 62 of adjacent gate trench portions 40 are connected to each other. However, the wide portions 62 of adjacent dummy trench portions 30 may also be connected to each other. A contact hole 56 may be formed above the connected wide portions 62. In this example, the gate trench portions 40 are connected to the gate metal layer 50 using the contact hole 56 provided above the connected wide portions 62. This makes it easier to avoid gate-emitter short circuits caused by the contact hole 56 protruding from the gate trench portion 40 due to misalignment. The connected wide portions 62 may be covered by the well region 17 in a top view. When adjacent gate trench portions 40 are connected to each other via the wide portions 62, the connecting ends may be rounded. This reduces electric field concentration and prevents insulation breakdown of the gate insulating film 42. The radius of curvature R2 of the end may be 0.01 μm or more and 0.2 μm or less.

[0198] The dummy trench portion 30 in this example has a wide portion 62 and is connected to the emitter electrode 52 using a contact hole 56 above the wide portion 62. The end positions of the dummy trench portion 30 and the gate trench portion 40 in the trench extension direction may be aligned. An end position E30 of the dummy trench portion 30 in the trench extension direction may be the same as an end position E40 of the gate trench portion 40 in the trench extension direction, and may be no more than twice the pitch of the multiple trench portions, or may be no more than one time.

[0199] Fig. 10 is a top view showing a modified example of the semiconductor device 100. The semiconductor device 100 of this example differs from the semiconductor device 100 of Fig. 9 in that it includes a gate runner portion 51. In this example, the differences from the semiconductor device 100 of Fig. 9 will be particularly described.

[0200] The gate trench portion 40 of this example is connected to the gate metal layer 50 via the gate runner portion 51. The gate trench portion 40 is connected to the gate runner portion 51 in a region where adjacent wide portions 62 are connected. The semiconductor device 100 of this example can increase the connection area between the gate runner portion 51 and the gate trench portion 40.

[0201] The gate runner 51 is connected to the wide portion 62 of the gate trench 40, but does not have to be connected to the connecting portion 63. In other words, the end of the gate runner 51 in the trench extension direction may terminate above the wide portion 62 other than the connecting portion 63.

[0202] The dummy trench portion 30 has a narrow portion 60 and a wide portion 62. The wide portion 62 of the dummy trench portion 30 is covered with the well region 17 in a top view. The dummy trench portion 30 is connected to the emitter electrode 52 using a contact hole 56 provided above the wide portion 62.

[0203] 11 is a top view showing a modified example of the semiconductor device 100. The semiconductor device 100 of this example differs from the semiconductor device 100 of FIG. 2A in the position where the well region 17 is provided. In this example, the differences from the semiconductor device 100 of FIG. 2A will be particularly described.

[0204] The well region 17 is disposed at a distance set back from the dummy trench portion 30 in a top view. That is, the well region 17 covers the end of the gate trench portion 40 in a top view, but does not cover the end of the dummy trench portion 30. In this example, the well region 17 covers the connection portion 43 of the gate trench portion 40 in a top view, but does not cover the connection portion 33 of the dummy trench portion 30.

[0205] The wide portion 62 may be provided in at least one of the dummy trench portion 30 or the gate trench portion 40. In this example, the wide portion 62 is provided in the gate trench portion 40, but is not provided in the dummy trench portion 30.

[0206] The well region 17 may be provided so as to cover the wide portion 62 in a top view. In this example, the well region 17 covers the end of the gate trench portion 40 having the wide portion 62 in a top view, but does not cover the end of the dummy trench portion 30. The well region 17 covers the wide portion 62 of the gate trench portion 40 in a top view, but does not have to cover the end of the dummy trench portion 30 in the trench extension direction. The end of the dummy trench portion 30 may be the connection portion 33 of the dummy trench portion 30.

[0207] 12 is a top view showing a modified example of the semiconductor device 100. The semiconductor device 100 of this example differs from the semiconductor device 100 of FIG. 4A in that the semiconductor device 100 of this example does not have a dummy trench portion 30 in the main region 75. In this example, the differences from the semiconductor device 100 of FIG. 4A will be particularly described.

[0208] The main region 75 has gate trench portions 40 arranged continuously in the trench arrangement direction. The main region 75 of this example does not have dummy trench portions 30. The dummy trench portions 30 may be provided in the diode portion 80 or in the boundary region 90.

[0209] The gate trench portion 40 has a narrow portion 60 and a wide portion 62. A contact hole 56 is provided above the gate trench portion 40. In this example, the contact hole 56 for connecting the gate metal layer 50 and the gate trench portion 40 is provided above the wide portion 62 of the gate trench portion 40. The contact holes 56 of the gate trench portion 40 may be arranged at the same position in the trench extension direction.

[0210] The dummy trench portion 30 has a narrow portion 60 and a wide portion 62. A contact hole 56 is provided above the dummy trench portion 30. In this example, the contact hole 56 for connecting the emitter electrode 52 and the dummy trench portion 30 is provided above the wide portion 62 of the dummy trench portion 30. The contact hole 56 of the dummy trench portion 30 may be provided at a different position from the contact hole 56 of the gate trench portion 40 in the trench extension direction. The contact hole 56 of the dummy trench portion 30 and the contact hole 56 of the gate trench portion 40 may both be provided in the wide portion 62.

[0211] Although the present invention has been described above using embodiments, the technical scope of the present invention is not limited to the scope described in the above embodiments. It will be apparent to those skilled in the art that various modifications and improvements can be made to the above embodiments. It is clear from the claims that such modifications and improvements can also be included within the technical scope of the present invention.

[0212] It should be noted that the execution order of each process, such as operations, procedures, steps, and stages, in the devices, systems, programs, and methods shown in the claims, specifications, and drawings is not specifically stated as "before," "prior to," etc., and that the processes can be performed in any order unless the output of a previous process is used in a subsequent process. Even if the operational flow in the claims, specifications, and drawings is described using "first," "next," etc. for convenience, this does not mean that the processes must be performed in this order. [Explanation of symbols]

[0213] 10 semiconductor substrate, 12 emitter region, 13 plug region, 14 base region, 15 contact region, 16 accumulation region, 17 well region, 18 drift region, 19 anode region, 20 buffer region, 21 front surface, 22 collector region, 23 back surface, 24 collector electrode, 30 dummy Trench portion, 31...extension portion, 32...dummy insulating film, 33...connection portion, 34...dummy conductive portion, 38...interlayer insulating film, 40...gate trench portion, 41...extension portion, 42...gate insulating film, 43...connection portion, 44...gate conductive portion, 50...gate metal layer, 51...gate runner portion, 52...emitter electrode, 54...contact hole 55 contact hole, 56 contact hole, 57 contact hole, 58 trench contact portion, 60 narrow portion, 62 wide portion, 63 connecting portion, 70 transistor portion, 71 mesa portion, 75 main region, 78 boundary, 80 diode portion, 81 mesa portion, 82 cathode region, 90 boundary Region, 91... mesa portion, 100... semiconductor device, 102... edge, 112... gate pad, 130... gate wiring, 160... active region, 170... edge termination structure portion, 200... front surface electrode portion, 210... silicide layer, 220... barrier metal portion, 221... first barrier metal layer, 222... second barrier metal layer, 230... plug portion

Claims

1. a first conductivity type drift region provided in a semiconductor substrate; a plurality of trench portions extending in a predetermined trench extension direction and arranged in a predetermined trench arrangement direction on the front surface side of the semiconductor substrate; a second conductivity type base region provided above the drift region; an emitter region of a first conductivity type provided on a front surface of the semiconductor substrate and having a doping concentration higher than that of the drift region; a second conductivity type contact region provided above the drift region and having a doping concentration higher than that of the base region; a well region of a second conductivity type provided above the drift region; a front surface electrode portion provided above the semiconductor substrate; Equipped with At least one of the plurality of trench portions comprises: a narrow portion extending in the trench extension direction; a wide portion having a trench width wider than the narrow portion; and The well region is provided below the wide portion. Semiconductor device.

2. the plurality of trench portions include gate trench portions, The gate trench portion has the wide portion and the narrow portion. The semiconductor device according to claim 1 .

3. The front surface electrode portion is a gate pad provided above the semiconductor substrate; a gate metal layer electrically connected to the gate pad; a gate runner portion including polysilicon for connecting the gate trench portion and the gate metal layer; have The semiconductor device according to claim 2 .

4. The front surface electrode portion is a gate pad provided above the semiconductor substrate; a gate metal layer electrically connected to the gate pad; and A gate trench contact hole for connecting the gate metal layer and the gate trench portion is provided above the wide portion of the gate trench portion. The semiconductor device according to claim 2 .

5. the plurality of trench portions include dummy trench portions, The dummy trench portion has the wide portion and the narrow portion. The semiconductor device according to claim 1 .

6. the front surface electrode portion has an emitter electrode provided above the semiconductor substrate, A dummy trench contact hole for connecting the emitter electrode and the dummy trench portion is provided above the wide portion of the dummy trench portion. The semiconductor device according to claim 5 .

7. The distance between the dummy trench contact hole and the end of the emitter electrode in the trench extension direction is 1 μm or more and 50 μm or less. The semiconductor device according to claim 6.

8. The trench depth of the wide portion is greater than the trench depth of the narrow portion. The semiconductor device according to claim 1 .

9. The trench depth of the wide portion is shallower than the trench depth of the narrow portion. The semiconductor device according to claim 1 .

10. The contact width in the trench arrangement direction of the gate trench contact hole provided above the wide portion of the gate trench portion is smaller than the trench width of the narrow portion of the gate trench portion. The semiconductor device according to claim 1 .

11. The contact width in the trench arrangement direction of the dummy trench contact hole provided above the wide portion of the dummy trench portion is smaller than the trench width of the narrow portion of the dummy trench portion. The semiconductor device according to claim 1 .

12. The contact width in the trench arrangement direction of the gate trench contact hole provided above the wide portion of the gate trench portion is equal to or greater than the trench width of the narrow portion of the gate trench portion. The semiconductor device according to claim 1 .

13. The contact width in the trench arrangement direction of the dummy trench contact hole provided above the wide portion of the dummy trench portion is equal to or greater than the trench width of the narrow portion of the dummy trench portion. The semiconductor device according to claim 1 .

14. The wide portion is covered by the well region in a top view. The semiconductor device according to claim 1 .

15. The sidewalls and bottom surface of the wide portion are covered by the well region. The semiconductor device according to claim 1 .

16. The wide portion has a connecting portion where the trench width gradually increases from the narrow portion. The semiconductor device according to claim 1 .

17. The well region is provided below the connecting portion. The semiconductor device according to claim 16.

18. The connecting portion has a structure in which only one side wall gradually widens. The semiconductor device according to claim 16.

19. The radius of curvature R of the connecting portion is 0.1 μm or more and 5.0 μm or less. The semiconductor device according to claim 16.

20. the plurality of trench portions include gate trench portions and dummy trench portions, In the trench extension direction, the difference between the end of the gate trench portion and the end of the dummy trench portion is equal to or less than twice the pitch of the plurality of trench portions. The semiconductor device according to claim 1 .

21. the plurality of trench portions include gate trench portions and dummy trench portions, The distance between the gate trench contact hole provided above the gate trench portion and the dummy trench contact hole provided above the dummy trench portion in the trench extension direction is 8 μm or more and 20 μm or less. The semiconductor device according to claim 1 .

22. The plurality of trench portions are an extension portion extending in the trench extension direction; a connecting portion for connecting the two extension portions; have The semiconductor device according to claim 1 .

23. the plurality of trench portions include a plurality of gate trench portions and a plurality of dummy trench portions; The plurality of gate trench portions sandwich at least one dummy trench portion of the plurality of dummy trench portions between the two extension portions connected by the connection portion.

23. The semiconductor device according to claim 22.

24. The plurality of gate trench portions sandwich the two extension portions connected by the connection portion in the plurality of dummy trench portions between the two extension portions connected by the connection portion in the plurality of gate trench portions.

24. The semiconductor device according to claim 23.

25. A contact hole extending in the trench arrangement direction is provided above the connection portion.

23. The semiconductor device according to claim 22.

26. The connecting portion of the wide portion where the trench width gradually increases from the narrow portion has a structure in which only the outer side wall of the U-shape formed by the connecting portion and the extending portion gradually widens.

23. The semiconductor device according to claim 22.

27. The plurality of trench portions each have the wide portion, and adjacent wide portions are connected to each other. The semiconductor device according to claim 1 .

28. the plurality of trench portions include gate trench portions and dummy trench portions, the wide portion is provided in the gate trench portion and not in the dummy trench portion, The well region covers the wide portion of the gate trench portion in a top view, but does not cover the end of the dummy trench portion in the trench extension direction. The semiconductor device according to claim 1 .

29. It has a transistor section and a diode section The semiconductor device according to claim 1 .

30. a first conductivity type drift region provided in a semiconductor substrate; a plurality of trench portions extending in a predetermined trench extension direction and arranged in a predetermined trench arrangement direction on the front surface side of the semiconductor substrate; a second conductivity type base region provided above the drift region; an emitter region of a first conductivity type provided on a front surface of the semiconductor substrate and having a doping concentration higher than that of the drift region; a second conductivity type contact region provided above the drift region and having a doping concentration higher than that of the base region; a well region of a second conductivity type provided above the drift region; a front surface electrode portion provided above the semiconductor substrate; Equipped with At least one of the plurality of trench portions comprises: a narrow portion extending in the trench extension direction; a wide portion having a trench width wider than the narrow portion; and the plurality of trench portions include gate trench portions and dummy trench portions, In the trench extension direction, the difference between the end of the gate trench portion and the end of the dummy trench portion is equal to or less than twice the pitch of the plurality of trench portions. Semiconductor device.

31. a first conductivity type drift region provided in a semiconductor substrate; a plurality of gate trench portions extending in a predetermined trench extension direction on the front surface side of the semiconductor substrate; a second conductivity type base region provided above the drift region; an emitter region of a first conductivity type provided on a front surface of the semiconductor substrate and having a doping concentration higher than that of the drift region; a second conductivity type contact region provided above the drift region and having a doping concentration higher than that of the base region; a well region of a second conductivity type provided above the drift region; a front surface electrode portion provided above the semiconductor substrate; Equipped with At least one of the plurality of gate trench portions includes: a narrow portion extending in the trench extension direction; a wide portion having a trench width wider than the narrow portion; and The front surface electrode portion is a gate pad provided above the semiconductor substrate; a gate metal layer electrically connected to the gate pad; and A gate trench contact hole for connecting the gate metal layer and the gate trench portion is provided above the wide portion of the gate trench portion. Semiconductor device.

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