Memory device

Abstract

To reduce a chip size while suppressing deterioration of an interface speed.SOLUTION: The memory according to the embodiment includes a substrate W1, a first circuit layer 100, a second circuit layer 200, and a wiring layer 300. The substrate has a first area AA and a second area DA. The first circuit layer includes a CMOS circuit. The wiring layer is provided above the second circuit layer and includes a pad electrically connected to the CMOS circuit via the second circuit layer. The second circuit layer includes a stacked body and a plurality of first pillars MP. The stacked body includes the first insulating layers 32 and the first conductive layers 22 alternately stacked in the first region, and includes the first insulating layers and the first members SM alternately stacked in the second region. The plurality of first pillars penetrate the stacked body in the first region and are electrically connected to the source line 21 above the stacked body. The pad includes a portion overlapping with the stack and does not include a portion overlapping with the source line.SELECTED DRAWING: Figure 11

Description

[Technical Field]

[0001] Embodiments relate to memory devices. [Background technology]

[0002] NAND flash memories capable of storing data in a nonvolatile manner are known. [Prior art documents] [Patent documents]

[0003] [Patent Document 1] Japanese Patent Application Publication No. 2019-057532 Summary of the Invention [Problem to be solved by the invention]

[0004] To reduce chip size while suppressing degradation of interface speed. [Means for solving the problem]

[0005] A memory device according to an embodiment has a junction surface. The memory device includes a substrate, a first circuit layer, a second circuit layer, and a wiring layer. The substrate has a first region and a second region aligned in a first direction. The first circuit layer is disposed between the substrate and the junction surface and includes a CMOS circuit. The second circuit layer is disposed above the junction surface. The wiring layer is disposed above the second circuit layer and includes a pad electrically connected to the CMOS circuit via the second circuit layer. The second circuit layer includes a stacked body, a plurality of first pillars, and a source line. The stacked body includes, within the first region, first insulating layers and first conductor layers alternately stacked in a second direction intersecting the first direction, and, within the second region, a first member made of a material different from each of the first insulating layers and first conductor layers alternately stacked in the second direction or the first insulating layers and first conductor layers alternately stacked in the second direction. The first pillars penetrate the stack in the second direction within the first region and are electrically connected to the source line above the stack, and the pad has a portion overlapping the stack in the second direction but does not have a portion overlapping the source line in the second direction. [Brief explanation of the drawings]

[0006] [Figure 1] 1 is a block diagram showing an example of the overall configuration of a memory system including a memory device according to a first embodiment. [Figure 2] FIG. 2 is a circuit diagram showing an example of the circuit configuration of a memory cell array included in the memory device according to the first embodiment. [Figure 3] FIG. 1 is a perspective view showing an example of the appearance of a memory device according to a first embodiment. [Figure 4] FIG. 2 is a plan view showing an example of a planar layout of the memory device according to the first embodiment. [Figure 5] FIG. 2 is a plan view showing an example of a planar layout in a core region of a memory cell array included in the memory device according to the first embodiment. [Figure 6] 6 is a cross-sectional view taken along line VI-VI in FIG. 5, showing an example of a cross-sectional structure in a storage region of a memory cell array included in the memory device according to the first embodiment. [Figure 7]7 is a cross-sectional view taken along line VII-VII in FIG. 6, showing an example of a cross-sectional structure of a memory pillar included in the memory device according to the first embodiment. [Figure 8] FIG. 2 is a cross-sectional view showing an example of the cross-sectional structure of the memory device according to the first embodiment. [Figure 9] FIG. 2 is a plan view showing an example of a planar layout of wiring layers in the memory device according to the first embodiment. [Figure 10] FIG. 2 is a plan view showing an example of a planar layout near a pad portion in the memory device according to the first embodiment. [Figure 11] 11 is a cross-sectional view taken along line XI-XI in FIG. 10, showing an example of a cross-sectional structure in the vicinity of a pad portion in the memory device according to the first embodiment. [Figure 12] 4 is a flowchart showing an example of a method for manufacturing a memory device according to the first embodiment. [Figure 13] 3A to 3C are cross-sectional views showing an example of a cross-sectional structure during the manufacturing process of the memory device according to the first embodiment. [Figure 14] 3A to 3C are cross-sectional views showing an example of a cross-sectional structure during the manufacturing process of the memory device according to the first embodiment. [Figure 15] 3A to 3C are cross-sectional views showing an example of a cross-sectional structure during the manufacturing process of the memory device according to the first embodiment. [Figure 16] 3A to 3C are cross-sectional views showing an example of a cross-sectional structure during the manufacturing process of the memory device according to the first embodiment. [Figure 17] 3A to 3C are cross-sectional views showing an example of a cross-sectional structure during the manufacturing process of the memory device according to the first embodiment. [Figure 18] FIG. 10 is a plan view showing an example of a planar layout near a pad portion in a memory device according to a first comparative example. [Figure 19] 19 is a cross-sectional view taken along line XIX-XIX in FIG. 18, showing an example of a cross-sectional structure in the vicinity of a pad portion in a memory device according to a first comparative example. [Figure 20] FIG. 10 is a plan view showing an example of a planar layout near a pad portion in a memory device according to a second comparative example. [Figure 21]21 is a cross-sectional view taken along line XXI-XXI in FIG. 20, showing an example of a cross-sectional structure in the vicinity of a pad portion in a memory device according to a second comparative example. [Figure 22] FIG. 10 is a plan view showing an example of a planar layout near a pad portion in a memory device according to a second embodiment. [Figure 23] 23 is a cross-sectional view taken along line XXIII-XXIII in FIG. 22, showing an example of a cross-sectional structure in the vicinity of a pad portion in a memory device according to a second embodiment. [Figure 24] 10 is a flowchart showing an example of a method for manufacturing a memory device according to the second embodiment. [Figure 25] 10A to 10C are cross-sectional views showing an example of a cross-sectional structure of a memory device according to a second embodiment during a manufacturing process. [Figure 26] 10A to 10C are cross-sectional views showing an example of a cross-sectional structure of a memory device according to a second embodiment during a manufacturing process. [Figure 27] 10A to 10C are cross-sectional views showing an example of a cross-sectional structure of a memory device according to a second embodiment during a manufacturing process. [Figure 28] FIG. 11 is a plan view showing an example of a planar layout near a pad portion in a memory device according to a third embodiment. [Figure 29] 29 is a cross-sectional view taken along line XXIX-XXIX in FIG. 28, showing an example of a cross-sectional structure in the vicinity of a pad portion in a memory device according to a third embodiment. [Figure 30] 10 is a flowchart showing an example of a method for manufacturing a memory device according to the third embodiment. [Figure 31] 10A to 10C are cross-sectional views showing an example of a cross-sectional structure of a memory device according to a third embodiment during a manufacturing process. [Figure 32] 10A to 10C are cross-sectional views showing an example of a cross-sectional structure of a memory device according to a third embodiment during a manufacturing process. [Figure 33] 10A to 10C are cross-sectional views showing an example of a cross-sectional structure of a memory device according to a third embodiment during a manufacturing process. [Figure 34] 10A to 10C are cross-sectional views showing an example of a cross-sectional structure of a memory device according to a third embodiment during a manufacturing process. [Figure 35]FIG. 10 is a plan view showing an example of a planar layout near a pad portion in a memory device according to a fourth embodiment. [Figure 36] 36 is a cross-sectional view taken along line XXXVI-XXXVI in FIG. 35, showing an example of a cross-sectional structure in the vicinity of a pad portion in a memory device according to a fourth embodiment. [Figure 37] FIG. 11 is a plan view showing an example of a planar layout near a pad portion in a memory device according to a fifth embodiment. [Figure 38] 38 is a cross-sectional view taken along line XXXVIII-XXXVIII in FIG. 37, showing an example of a cross-sectional structure in the vicinity of a pad portion in a memory device according to a fifth embodiment. [Figure 39] FIG. 13 is a cross-sectional view showing an example of the cross-sectional structure of a memory cell array included in a memory device according to a sixth embodiment. [Figure 40] FIG. 13 is a plan view showing an example of a planar layout in the vicinity of a pad portion in a memory device according to a sixth embodiment. [Figure 41] 41 is a cross-sectional view taken along line XLI-XLI in FIG. 40, showing an example of a cross-sectional structure in the vicinity of a pad portion in a memory device according to a sixth embodiment. [Figure 42] 13 is a flowchart showing an example of a method for manufacturing a memory device according to a sixth embodiment. [Figure 43] 13A to 13C are cross-sectional views showing an example of a cross-sectional structure of a memory device according to a sixth embodiment during a manufacturing process. [Figure 44] 13A to 13C are cross-sectional views showing an example of a cross-sectional structure of a memory device according to a sixth embodiment during a manufacturing process. [Figure 45] FIG. 13 is a plan view showing an example of a planar layout in the vicinity of a pad portion in a memory device according to a seventh embodiment. [Figure 46] 46 is a cross-sectional view taken along line XLVI-XLVI in FIG. 45, showing an example of a cross-sectional structure in the vicinity of a pad portion in a memory device according to a seventh embodiment. [Figure 47] FIG. 13 is a plan view showing an example of a planar layout in the vicinity of a pad portion in a memory device according to the eighth embodiment. [Figure 48]48 is a cross-sectional view taken along line XLVIII-XLVIII in FIG. 47, showing an example of a cross-sectional structure in the vicinity of a pad portion in a memory device according to the eighth embodiment. [Figure 49] FIG. 13 is a plan view showing an example of a planar layout in the vicinity of a pad portion in a memory device according to a ninth embodiment. [Figure 50] 49 along line LL in FIG. 49, showing an example of a cross-sectional structure in the vicinity of a pad portion in a memory device according to the ninth embodiment. [Figure 51] FIG. 23 is a plan view showing an example of a planar layout in the vicinity of a pad portion in a memory device according to a tenth embodiment. [Figure 52] 52 is a cross-sectional view taken along line LII-LII in FIG. 51, showing an example of a cross-sectional structure in the vicinity of a pad portion in a memory device according to a tenth embodiment. [Figure 53] FIG. 23 is a plan view showing an example of a planar layout in the vicinity of a pad portion in a memory device according to an eleventh embodiment. [Figure 54] 54 is a cross-sectional view taken along line LIV-LIV in FIG. 53, showing an example of a cross-sectional structure in the vicinity of a pad portion in a memory device according to an eleventh embodiment. [Figure 55] FIG. 3 is a cross-sectional view showing an example of a detailed cross-sectional structure of the vicinity of two bond pads arranged opposite to each other in the memory device according to the first embodiment. DETAILED DESCRIPTION OF THE INVENTION

[0007] Each embodiment will be described below with reference to the drawings. Each embodiment illustrates an apparatus or method for embodying the technical idea of ​​the invention. The drawings are schematic or conceptual. The dimensions and ratios of each drawing are not necessarily the same as those in reality. Illustrations of components are omitted as appropriate. Hatching added to plan views does not necessarily relate to the material or characteristics of the components. In this specification, components having approximately the same function and configuration are assigned the same reference numerals. Numbers and letters added to reference numerals are used to refer to the same reference numerals and to distinguish between similar elements.

[0008] <1> First embodiment The first embodiment relates to a memory device having a structure in which the source lines are removed from the region where the edge of the memory cell array overlaps with the pad exposed on the surface of the memory device, and an insulating film is buried in that region. A memory device 1 according to the first embodiment will be described below.

[0009] <1-1> Configuration First, the configuration of the memory device 1 according to the first embodiment will be described.

[0010] <1-1-1> Overall configuration of memory device 1 1 is a block diagram showing an example of the overall configuration of a memory system including a memory device 1 according to a first embodiment. As shown in FIG. 1, the memory device 1 is controlled by an external memory controller 2. The memory device 1 is, for example, a NAND flash memory capable of storing data in a non-volatile manner. The memory device 1 includes, for example, a memory cell array 10, an input / output circuit 11, a logic controller 12, a register circuit 13, a sequencer 14, a driver circuit 15, a row decoder module 16, and a sense amplifier module 17.

[0011] The memory cell array 10 includes a plurality of blocks BLK0 to BLKn ("n" is an integer equal to or greater than 1). A block BLK is a collection of a plurality of memory cells. A block BLK corresponds, for example, to a unit of data erasure. A block BLK includes a plurality of pages. A page corresponds to a unit in which data is read and written. Although not shown, the memory cell array 10 is provided with a plurality of bit lines BL0 to BLm ("m" is an integer equal to or greater than 1) and a plurality of word lines WL. Each memory cell is associated, for example, with one bit line BL and one word line WL.

[0012] The input / output circuit 11 is an interface circuit that controls transmission and reception of input / output signals to and from the memory controller 2. The input / output signals include, for example, data DAT, status information, address information, commands, etc. The input / output circuit 11 can input and output data DAT between the sense amplifier module 17 and the memory controller 2. The input / output circuit 11 can output status information transferred from the register circuit 13 to the memory controller 2. The input / output circuit 11 can output address information and commands transferred from the memory controller 2 to the register circuit 13.

[0013] The logic controller 12 controls each of the input / output circuit 11 and the sequencer 14 based on the control signal input from the memory controller 2. For example, the logic controller 12 controls the sequencer 14 to enable the memory device 1. The logic controller 12 notifies the input / output circuit 11 that the input / output signal received by the input / output circuit 11 is a command, address information, or the like. The logic controller 12 instructs the input / output circuit 11 to input or output the input / output signal.

[0014] The register circuit 13 temporarily stores status information, address information, and commands. The status information is updated under the control of the sequencer 14 and transferred to the input / output circuit 11. The address information includes a block address, a page address, a column address, etc. The commands include instructions for various operations of the memory device 1.

[0015] The sequencer 14 controls the overall operation of the memory device 1. Based on the command and address information stored in the register circuit 13, the sequencer 14 executes read operations, write operations, erase operations, and the like.

[0016] The driver circuit 15 generates voltages used in read operations, write operations, erase operations, etc. The driver circuit 15 then supplies the generated voltages to the row decoder module 16, the sense amplifier module 17, etc.

[0017] The row decoder module 16 is a circuit used to select a block BLK to be operated and to transfer a voltage to wiring such as a word line WL. The row decoder module 16 includes a plurality of row decoders RD0 to RDn. The row decoders RD0 to RDn are associated with the blocks BLK0 to BLKn, respectively, and are used to select the blocks BLK. Each row decoder RD transfers a voltage generated by the driver circuit 15 to various wirings provided in the memory cell array 10.

[0018] The sense amplifier module 17 is a circuit used to transfer voltages to each bit line BL and to read data. The sense amplifier module 17 includes a plurality of sense amplifier units SAU0 to SAUm. The sense amplifier units SAU0 to SAUm are associated with a plurality of bit lines BL0 to BLm, respectively. Each sense amplifier unit SAU includes a sense amplifier capable of determining data based on the voltage of the associated bit line BL, a latch circuit for temporarily holding data, and the like.

[0019] The combination of the memory device 1 and the memory controller 2 may constitute one semiconductor device. TM Examples include memory cards and solid state drives (SSDs).

[0020] <1-1-2> Circuit configuration of memory cell array 10 2 is a circuit diagram showing an example of a circuit configuration of a memory cell array 10 included in the memory device 1 according to the first embodiment. FIG. 2 shows two blocks BLK0 and BLK1 out of a plurality of blocks BLK included in the memory cell array 10. As shown in FIG. 2, in the memory cell array 10, select gate lines SGD and SGS and word lines WL0 to WL(N-1) (N is an integer of 2 or more) are provided for each block BLK. Bit lines BL0 to BLm and source lines SL are shared by, for example, a plurality of blocks BLK.

[0021] Each block BLK includes multiple NAND strings NS. The multiple NAND strings NS are associated with bit lines BL0 to BLm, respectively. In other words, each bit line BL is shared among multiple blocks BLK by NAND strings NS assigned the same column address. Each NAND string NS is connected between the associated bit line BL and source line SL. Each NAND string NS includes, for example, N memory cell transistors MT0 to MT(N-1) and select transistors ST1 and ST2. Each memory cell transistor MT is a memory cell having a control gate and a charge storage layer, and retains (stores) data in a non-volatile manner. Each of the select transistors ST1 and ST2 is used to select the block BLK.

[0022] In each NAND string NS, a select transistor ST1, memory cell transistors MT(N-1) to MT0, and a select transistor ST2 are connected in series in this order. Specifically, the drain and source terminals of the select transistor ST1 are connected to the associated bit line BL and the drain terminal of the memory cell transistor MT(N-1), respectively. The drain and source terminals of the select transistor ST2 are connected to the source terminal of the memory cell transistor MT0 and the source line SL, respectively. The memory cell transistors MT0 to MT(N-1) are connected in series between the select transistors ST1 and ST2.

[0023] Each select gate line SGD is connected to the gate terminal of each of the select transistors ST1 included in the associated block BLK. Each select gate line SGS is connected to the gate terminal of each of the select transistors ST2 included in the associated block BLK. Word lines WL0 to WL(N-1) are connected to the control gate terminals of each of the memory cell transistors MT0 to MT(N-1) included in the associated block BLK. A "page" corresponds to a set of memory cell transistors MT connected to a common word line WL within the same block BLK. A set of memory cell transistors MT connected to a common word line WL within the same block BLK can have a storage capacity of two or more pages of data depending on the number of bits stored in the memory cell transistors MT.

[0024] The memory cell array 10 may have other circuit configurations. For example, each block BLK may be provided with a plurality of independently controllable select gate lines SGD. In this case, each block BLK is configured to be selectable in units of a plurality of units each associated with a plurality of select gate lines SGD.

[0025] In the following, the memory device 1 according to the first embodiment will be described taking as an example a case where each NAND string NS has eight memory cell transistors MT0 to MT7 connected to word lines WL0 to WL7, respectively (i.e., a case where N=8).

[0026] <1-1-3> Structure of memory device 1 The structure of the memory device 1 according to the first embodiment will be described below.

[0027] In the drawings referred to below, a three-dimensional Cartesian coordinate system is used. The X direction corresponds to the extension direction of the word lines WL. The Y direction corresponds to the extension direction of the bit lines BL. The Z direction corresponds to the vertical direction with respect to the surface of the reference semiconductor substrate. "Up and down" are defined based on the direction along the Z direction. The positive direction (up) corresponds to the direction away from the reference semiconductor substrate. The XY plane (cross section) corresponds to a plane (cross section) parallel to each of the X and Y directions. The YZ cross section corresponds to a cross section parallel to each of the Y and Z directions. The XZ cross section corresponds to a cross section parallel to each of the X and Z directions.

[0028] (1: Appearance of memory device 1) First, the appearance of the memory device 1 according to the first embodiment will be described. The memory device 1 according to the first embodiment is formed by bonding two semiconductor circuit substrates, each having a semiconductor circuit formed thereon, and then separating the bonded semiconductor circuit substrates into individual chips. That is, the memory device 1 according to the first embodiment has a bonding surface formed by bonding semiconductor substrates W1 and W2. Each of the semiconductor substrates W1 and W2 is a silicon substrate. Below, a case will be described in which the semiconductor substrate W2 is removed during the manufacturing process of the memory device 1. Depending on the structure of the memory cell array 10, a portion of the semiconductor substrate W2 may remain after bonding the semiconductor substrates W1 and W2 together.

[0029] 3 is a perspective view showing an example of the appearance of the memory device 1 according to the first embodiment. As shown in FIG. 3, the memory device 1 includes, for example, a semiconductor substrate W1, a CMOS layer 100, a bonding layer B1, a bonding layer B2, a memory layer 200, and a wiring layer 300.

[0030] The CMOS layer 100 is disposed on a semiconductor substrate W1. The CMOS layer 100 includes a CMOS circuit (control circuit) formed using the semiconductor substrate W1. The semiconductor substrate W1 has impurity diffusion regions and the like according to the design of the CMOS circuit. The CMOS layer 100 includes, for example, an input / output circuit 11, a logic controller 12, a register circuit 13, a sequencer 14, a driver circuit 15, a row decoder module 16, and a sense amplifier module 17. The CMOS layer 100 may also be referred to as a circuit layer.

[0031] The bonding layer B1 is disposed on the CMOS layer 100. The bonding layer B1 is formed using a semiconductor substrate W1. The bonding layer B1 includes a plurality of bonding pads that are electrically connected to a CMOS circuit provided in the CMOS layer 100 and form part of the semiconductor circuit.

[0032] The bonding layer B2 is disposed on the bonding layer B1. The bonding layer B2 is formed using a semiconductor substrate W2 (not shown). The bonding layer B2 includes a plurality of bonding pads that are electrically connected to the memory cell array 10 provided in the memory layer 200 and form part of a semiconductor circuit. The plurality of bonding pads included in the bonding layer B2 are respectively connected to the plurality of bonding pads included in the bonding layer B1. The space between the bonding layers B1 and B2 corresponds to the boundary, i.e., the bonding surface, between the layer formed using the semiconductor substrate W1 and the layer formed using the semiconductor substrate W2.

[0033] The memory layer 200 is disposed on the bonding layer B2. The memory layer 200 includes a memory cell array 10 formed using a semiconductor substrate W2. The memory layer 200 may also be called a circuit layer.

[0034] The wiring layer 300 is disposed on the memory layer 200. The wiring layer 300 is formed after bonding the semiconductor substrates W1 and W2 together. The wiring layer 300 includes wiring connected to a semiconductor circuit provided in the memory layer 200 and a plurality of pad portions PD. The plurality of pad portions PD include conductive portions (pads) exposed on the surface of the memory device 1. The plurality of pad portions PD are used for connecting the memory device 1 to the memory controller 2 and the like, for supplying power, and the like.

[0035] (2: Planar layout of memory device 1) 4 is a plan view showing an example of the planar layout of the memory device 1 according to the first embodiment. As shown in FIG. 4, the memory device 1 includes, for example, a core region CR, a peripheral region PR, a wall region WR, and a kerf region KR.

[0036] The core region CR is, for example, a rectangular region provided near the center of the semiconductor substrate W1. In the core region CR, for example, a memory cell array 10, a register circuit 13, a sequencer 14, a driver circuit 15, a row decoder module 16, and a sense amplifier module 17 are arranged.

[0037] The peripheral region PR is a quadrangular ring-shaped region provided so as to surround the outer periphery of the core region CR. In the peripheral region PR, for example, an input / output circuit 11, a logic controller 12, etc. are arranged. In addition, in the peripheral region PR, for example, contacts for connecting wiring provided in the wiring layer 300 with circuits provided in the CMOS layer 100 and the memory layer 200, etc. are arranged.

[0038] The wall region WR is a quadrangular ring-shaped region provided so as to surround the outer periphery of the peripheral region PR. At least one sealing portion ES (not shown) is disposed in the wall region WR so as to surround the outer periphery of the peripheral region PR. Details of the sealing portion ES will be described later. The kerf region KR is a quadrangular ring-shaped region provided to surround the outer periphery of the wall region WR. The kerf region KR is in contact with the outermost periphery of the memory device 1. For example, alignment marks used in manufacturing the memory device 1 are arranged in the kerf region KR. The structure of the kerf region KR may be removed during a dicing process in which the semiconductor circuit substrate is cut into individual chips (memory devices 1).

[0039] (3: Planar layout of memory cell array 10) 5 is a plan view showing an example of a planar layout of a core region CR of a memory cell array 10 included in the memory device 1 according to the first embodiment. As shown in FIG. 5, the memory cell array 10 includes a plurality of slits SLT, a plurality of memory pillars MP, and a plurality of contacts CV and CC. The memory cell array 10 also includes, for example, a storage region SA and a contact region CA aligned in the X direction.

[0040] Each slit SLT is a plate-like member extending along the X direction. Each slit SLT has a portion extending along the X direction and crosses the storage region SA and the contact region CA along the X direction. Multiple slits SLT are aligned in the Y direction. Each slit SLT separates adjacent wirings (e.g., word lines WL0 to WL7 and select gate lines SGD and SGS) through the slit SLT. In each slit SLT, a conductor with an insulating spacer on its sidewall may be arranged insulated from the wirings, or an insulator may be embedded. In the memory cell array 10, each of the regions partitioned along the Y direction by the slits SLT corresponds to one block BLK.

[0041] The storage area SA includes multiple memory pillars MP. Each memory pillar MP is, for example, a pillar-shaped component that functions as one NAND string NS. The multiple memory pillars MP are arranged in a grid pattern for each block BLK. At least one bit line BL is arranged to overlap each memory pillar MP. Each of the multiple bit lines BL has a portion extending in the Y direction and is aligned in the X direction. In this example, two bit lines BL are arranged to overlap one memory pillar MP. The associated memory pillar MP and bit line BL are electrically connected via contacts CV.

[0042] The contact area CA is used for connecting stacked wiring (e.g., word lines WL, select gate lines SGD and SGS) included in the memory cell array 10 to the row decoder module 16. In the contact area CA, a plurality of contacts CC are arranged for each block BLK. For each block BLK, each of the plurality of contacts CC is electrically connected to an associated one of the stacked wirings. In each block BLK, at least one contact CC is electrically connected to each of the select gate line SGS, word lines WL0 to WL7, and select gate line SGD.

[0043] In the contact area CA, the contacts CC in each block BLK are not limited to being arranged in a line in the X direction as shown in Fig. 5, but may be arranged in a grid pattern for each block BLK. Two contact areas CA may be arranged in the core region CR so as to sandwich the storage area SA in the X direction. The contact areas CA may also be arranged so as to divide the storage area SA in the X direction.

[0044] Furthermore, the core region CR includes active regions AA and dummy regions DA aligned in the Y direction. The active regions AA and dummy regions DA overlap with the storage regions SA and contact regions CA, respectively. A plurality of memory pillars MP used for storing data are arranged in the overlapping region between the storage regions SA and the active regions AA. A plurality of contacts CC used for controlling the active blocks BLK are arranged in the overlapping region between the contact regions CA and the active regions AA.

[0045] The dummy region DA is arranged at the end of the core region CR in the Y direction. Two dummy regions DA may be arranged in the core region CR, sandwiching the active region AA in the Y direction. The dummy block DBLK corresponds to an area within the dummy region DA separated in the Y direction by a slit SLT. The dummy region DA includes at least one dummy block DBLK. Figure 5 shows two dummy blocks DBLK0 and DBLK1 aligned in the Y direction. Multiple dummy pillars DMP may be arranged in the area of ​​the dummy block DBLK that overlaps with the storage region SA. The dummy pillar DMP is a pattern for compensating for the shape of the memory pillar MP and has a structure similar to that of the memory pillar MP. The dummy pillar DMP is not connected to the contact CV or the bit line BL. Therefore, the dummy pillar DMP is not used to store data.

[0046] The dummy region DA further includes a dummy staircase portion DS in a portion corresponding to the outer edge of the core region CR. The dummy staircase portion DS includes the end of the laminated wiring formed in a staircase shape. In the dummy staircase portion DS, a sacrificial member SM remains in the portion corresponding to the laminated wiring. The sacrificial member SM is a member used in a replacement process to form the laminated wiring. In the replacement process, the sacrificial member SM is replaced with a conductor among the alternately stacked sacrificial members SM and insulator layers to form the laminated wiring. More specifically, in the replacement process, the sacrificial member SM is removed through the slit SLT, and the conductor is filled in the space where the sacrificial member SM was removed. Therefore, the sacrificial member SM provided in the portion away from the slit SLT may remain without being replaced with a conductor in the replacement process. As a result, the end of the laminated sacrificial member SM is formed in a staircase shape. An example of the structure of the dummy staircase portion DS is shown in FIG. 11, which will be described later.

[0047] (4: Cross-sectional structure of the storage area SA of the memory cell array 10) Fig. 6 is a cross-sectional view taken along line VI-VI in Fig. 5, showing an example of the cross-sectional structure of the storage region SA of the memory cell array 10 included in the memory device 1 according to the first embodiment. Fig. 6 shows an example of the structure of the memory cell array 10 formed on the semiconductor substrate W2 before being bonded to the semiconductor substrate W1, and the bonding layer B2 thereover, and displays coordinate axes based on the semiconductor substrate W2. As shown in Fig. 6, the memory cell array 10 includes, for example, conductor layers 21-24, insulator layers 31-34, an insulating member 36, and contacts CV, V1, and V2 in the storage region SA.

[0048] A conductor layer 21 is provided on a semiconductor substrate W2. An insulator layer 31 is provided on the conductor layer 21. Conductor layers 22 and insulator layers 32 are provided alternately in the Z direction on the insulator layer 31. That is, a plurality of conductor layers 22 are lined up in the Z direction. In this manner, the stacked body corresponding to the memory cell array 10 includes conductor layers 22 and insulator layers 32 provided alternately in the Z direction. The number of layers of the conductor layers 22 corresponds to, for example, the number of layers of the stacked wiring (select gate lines SGS, word lines WL, and select gate lines SGD).

[0049] An insulating layer 33, a conductive layer 23, and an insulating layer 34 are provided in this order on the uppermost conductive layer 22. Each of the conductive layers 21 and 22 is formed, for example, in the shape of a plate extending along the XY plane. The conductive layer 23 has, for example, a portion formed in the shape of a line extending in the Y direction. The conductive layer 21 is used as a source line SL. In this example, the ten conductive layers 22 aligned in the Z direction are used, in order from the source line SL side, as a select gate line SGS, word lines WL0 to WL7, and a select gate line SGD. The conductive layer 23 is used as a bit line BL. The conductive layer 21 contains, for example, polysilicon (Si). The conductive layer 22 contains, for example, tungsten (W). The conductive layer 23 contains, for example, copper (Cu).

[0050] A conductive layer 24 is provided above the conductive layer 23. The conductive layer 24 is a wiring that relays the connection between the bit line BL and the sense amplifier module 17. The conductive layer 23 and the conductive layer 24 are connected via a contact V1. A conductive layer 25 is provided above the conductive layer 24. The conductive layer 25 corresponds to a bonding pad. The conductive layer 24 and the conductive layer 25 are connected via a contact V2. Side surfaces of the conductive layer 24 and the contacts V1 and V2 are covered with an insulator layer 34. The insulator layer 34 may be composed of multiple insulating films. Side surfaces of the conductive layer 25 are covered with the insulator layer 35. The insulator layer 35 and the conductive layer 25 are included in the bonding layer B2. The memory cell array 10 may include multiple conductive layers 24. The bonding layer B2 may include multiple conductive layers 25. The conductive layer 25 includes, for example, copper.

[0051] The insulating member 36 has a plate-like portion extending along the XZ plane. The insulating member 36 separates the insulating layer 31 from the alternately arranged conductor layers 22 and 32. In this example, the insulating member 36 is embedded in the slit SLT. A conductor having an insulating spacer on its side wall may be arranged in the slit SLT so as to be insulated from each of the conductor layers 21 and 22.

[0052] Each memory pillar MP extends along the Z direction, penetrates the insulator layer 31, and the alternately arranged conductor layers 22 and insulator layers 32, and is connected to the conductor layer 21. Each memory pillar MP includes, for example, a core member 40, a semiconductor layer 41, and a stacked film 42. The core member 40 is an insulator extending along the Z direction. The semiconductor layer 41 covers the core member 40. A portion of the side surface of the semiconductor layer 41 contacts the conductor layer 21. That is, the semiconductor layer 41 and the conductor layer 21 (source line SL) in the memory pillar MP are electrically connected via the side surface of the memory pillar MP. The stacked film 42 covers the side surface and bottom surface of the semiconductor layer 41, except for the contact portion between the semiconductor layer 41 and the conductor layer 21. The associated semiconductor layer 41 (memory pillar MP) and the conductor layer 23 (bit line BL) are connected via a contact CV.

[0053] The portion where the conductive layer 22 used as the select gate line SGS intersects with the memory pillar MP functions as a select transistor ST2. The portion where the conductive layer 22 used as the word line WL intersects with the memory pillar MP functions as a memory cell transistor MT. The portion where the conductive layer 22 used as the select gate line SGD intersects with the memory pillar MP functions as a select transistor ST1. In each memory pillar MP, the semiconductor layer 41 is used as the channel (current path) of the memory cell transistors MT0 to MT7 and the select transistors ST1 and ST2 included in the NAND string NS.

[0054] (5: Cross-sectional structure of memory pillar MP) FIG. 7 is a cross-sectional view taken along line VII-VII in FIG. 6, showing an example of the cross-sectional structure of a memory pillar MP included in the memory device 1 according to the first embodiment. FIG. 6 illustrates a cross section including the memory pillar MP and the conductive layer 22 and parallel to the surface of the semiconductor substrate W2. As shown in FIG. 6, the stacked film 42 includes, for example, a tunnel insulating film 43, an insulating film 44, and a block insulating film 45. The tunnel insulating film 43 surrounds the side surface of the semiconductor layer 41. The insulating film 44 surrounds the side surface of the tunnel insulating film 43. The block insulating film 45 surrounds the side surface of the insulating film 44. The conductive layer 22 surrounds the side surface of the block insulating film 45. Each of the tunnel insulating film 43 and the block insulating film 45 includes, for example, a silicon oxide film (SiO2). The insulating film 44 is used as a charge storage layer for the memory cell transistor MT. The insulating film 44 includes, for example, silicon nitride (SiN).

[0055] (6: Cross-sectional structure of memory device 1) FIG. 8 is a cross-sectional view showing an example of the cross-sectional structure of the memory device 1 according to the first embodiment. FIG. 8 shows a portion of the core region CR, the peripheral region PR, and the wall region WR after the semiconductor substrates W1 and W2 are bonded, and indicates coordinate axes based on the semiconductor substrate W1. In this example, the semiconductor substrate W2 is removed after the bonding process of the semiconductor substrates W1 and W2. The memory layer 200 and the bonding layer B2 have a structure in the core region CR in which the structure related to the memory cell array 10 shown in FIG. 6 is vertically inverted. As shown in FIG. 8, the CMOS layer 100 includes an insulator layer 110. The bonding layer B1 includes an insulator layer 111. The memory layer 200 includes an insulator layer 210, a conductor layer 211, a sacrificial member 212, and a conductor layer 213. The wiring layer 300 includes an insulator layer 301 , an insulating member 302 , a conductor layer 303 , an insulator layer 304 , an insulator layer 305 , and an insulator layer 306 .

[0056] The insulator layer 110 is provided on the semiconductor substrate W1. The insulator layer 110 covers at least a portion of the wiring, contacts, elements, etc. provided in the CMOS layer 100. The insulator layer 110 may be composed of multiple types of insulating films. The insulator layer 111 is provided on the insulator layer 110. The insulator layer 111 covers the side surfaces of the bonding pads provided on the bonding layer B1. The insulator layer 35 of the bonding layer B2 is provided on the insulator layer 111.

[0057] The insulator layer 210 is provided on the insulator layer 35. The insulator layer 210 covers at least a portion of the wiring, contacts, elements, etc. provided in the memory layer 200. The insulator layer 210 may be composed of multiple types of insulating films and may include insulator layers 33 and 34. A conductor layer 211, a sacrificial member 212, and a conductor layer 213 are stacked in this order on the insulator layer 210. The set of the conductor layer 211, the sacrificial member 212, and the conductor layer 213 is provided at the same height as the conductor layer 21. Specifically, the height of the lower surface of the conductor layer 211 is aligned with the height of the lower surface of the conductor layer 21 (source line SL). The height of the upper surface of the conductor layer 213 is aligned with the height of the upper surface of the conductor layer 21 (source line SL). The conductive layer 21 in the core region CR corresponds to a structure in which the conductive layer 211, the sacrificial member 212, and the conductive layer 213 are stacked, and then the sacrificial member 212 is replaced with a conductor. That is, the height of the sacrificial member 212 is the same as the height at which the conductive layer 21 and the semiconductor layer 41 in each memory pillar MP are connected. Each of the conductive layers 211 and 213 contains, for example, polysilicon (Si). The sacrificial member 212 contains, for example, silicon nitride (SiN).

[0058] The insulating layer 301 is provided on the conductor layer 213 and the conductor layer 21. The insulating member 302 is provided in a part of the peripheral region PR and a part of the wall region WR, penetrating the insulator layer 301, the conductor layer 213, the sacrificial member 212, and the conductor layer 211. The upper surface of the insulating member 302 may be flush with the upper surface of the insulator layer 301, or a step may be formed between the insulating member 302 and the insulator layer 301. The lower surface of the insulating member 302 may be flush with the lower surface of the conductor layer 211, or may be located at a height between the lower surface of the conductor layer 211 and a conductor layer 26 described later.

[0059] The conductor layer 303 is provided on the insulator layer 301. The conductor layer 303 may have a portion provided on the insulating member 302 in the peripheral region PR and the wall region WR. The conductor layer 303 is divided (insulated) at least between the peripheral region PR and the wall region WR. The conductor layer 303 may have a portion provided continuously between the core region CR and the peripheral region PR.

[0060] The wiring layer 300 includes a via VA in the core region CR, a via VB in the peripheral region PR, and a via VC in the wall region WR. The via VA penetrates the insulator layer 301. The conductor layer 303 in the core region CR is provided along the via VA and may have a portion connected to the conductor layer 21 via the via VA. The via VB penetrates the insulating member 302. The conductor layer 303 in the peripheral region PR is provided along the via VB and may have a portion connected to the contact C3 (described later) via the via VB. The portion of the conductor layer 303 provided at the via VB is insulated from the conductor layers 211 and 213 by the insulating member 302. The via VC penetrates the insulating member 302. The conductor layer 303 in the wall region WR is provided along the via VC and may have a portion connected to the sealing portions ES1 and ES2 (described later) via the via VC. The portion of the conductive layer 303 provided in the via VC is insulated from the conductive layers 211 and 213 by the insulating member 302 .

[0061] The insulator layer 304, the insulator layer 305, and the insulator layer 306 are provided in this order on the insulator layer 301 or the conductor layer 303. The insulator layer 304, the insulator layer 305, and the insulator layer 306 each have a portion provided along the vias VA, VB, and VC, respectively. The insulator layer 301, the insulating member 302, and the insulator layer 304 each include, for example, a silicon oxide film (SiO2). The insulator layer 305 includes, for example, silicon nitride (SiN). The insulator layer 306 includes, for example, polyimide.

[0062] In the core region CR, the CMOS layer 100 includes a gate insulating film 101, a gate electrode 102, conductive layers 103 and 104, and contacts C0 to C2, and the junction layer B1 includes a conductive layer 105. The gate insulating film 101 is provided on a semiconductor substrate W1. The gate electrode 102 in the core region CR is provided on the gate insulating film 101 and is used as the gate electrode of a transistor TR1. The transistor TR1 is included in, for example, a sense amplifier module 17. The conductive layer 103 is a wiring layer above the gate electrode 102. The contact C0 connects the gate electrode 102 and the conductive layer 103. The contact C1 connects the impurity diffusion region of the transistor TR1 provided in the semiconductor substrate W1 with the conductive layer 103. The conductive layer 104 is a wiring layer provided at a height between the conductive layer 103 and the junction layer B1. The contact C2 is provided at a height between the conductive layer 103 and the junction layer B1. At least one conductor layer 103 is connected to a conductor layer 105 via at least one contact C2 and at least one conductor layer 104. The conductor layer 105 corresponds to a bonding pad disposed on the bonding layer B1. The conductor layer 105 is in contact with a conductor layer 25 disposed opposite the conductor layer 105 in the bonding layer B2. As a result, the semiconductor layer 41 in the core region CR is electrically connected to the transistor TR1 via the contact CV, the conductor layers 23 to 25 and 103 to 105, and the contacts CV, V1, V2, C1, and C2.

[0063] In the peripheral region PR, the CMOS layer 100, like the core region CR, includes a gate insulating film 101, a gate electrode 102, conductive layers 103 and 104, and contacts C0 to C2, and the junction layer B1 includes a conductive layer 105. The gate electrode 102 in the peripheral region PR is used as the gate electrode of the transistor TR2. The transistor TR2 may be, for example, a transistor connected to a power supply line or a transistor included in the input / output circuit 11. In the peripheral region PR, the junction layer B2 includes a conductive layer 25, and the memory layer 200 includes conductive layers 24 and 26 and contacts V1, V2, and C3. The conductive layer 26 is a wiring provided in the same layer as the conductive layer 23. At least one contact C3 is provided on the conductive layer 26. The upper portion of each contact C3 reaches at least the height of the conductive layer 211. The upper portion of each contact C3 is covered with the conductive layer 303 and is electrically connected to the conductive layer 303. As a result, the conductive layer 303 in the peripheral region PR is electrically connected to the transistor TR2 via at least one contact C3, the conductive layers 24 to 26 and 103 to 105, and the contacts V1, V2, C1, and C2.

[0064] Within the wall region WR, the memory device 1 includes contacts C1W, C2W, C3W, V1W, and V2W and conductive layers 103W, 104W, 105W, 24W, 25W, and 26W for each of the sealing portions ES1 and ES2. The contacts C1W, C2W, C3W, V1W, and V2W are provided in the same layer as the contacts C1, C2, C3, V1, and V2, respectively. The conductive layers 103W, 104W, 105W, 24W, 25W, and 26W are provided in the same layer as the conductive layers 103, 104, 105, 24, 25, and 26, respectively. Although not shown, the sets of contacts C1W, C2W, C3W, V1W, and V2W and conductive layers 103W, 104W, 105W, 24W, 25W, and 26W are arranged in an annular shape in a plan view. That is, each of sealing portions ES1 and ES2 is arranged in a quadrangular annular shape in the wall region WR so as to surround the outer periphery of the core region CR and surround the peripheral region PR. The sealing portion ES2 is arranged outside the sealing portion ES1.

[0065] In the wall region WR, the semiconductor substrate W1 includes a P-type well region PW and an N-type well region NW. The P-type well region PW is a diffusion region of P-type impurities (p + The N-type well region NW is a diffusion region of N-type impurities provided in the vicinity of the upper surface of the semiconductor substrate W1 (n + The P-type well region PW and the N-type well region NW correspond to the sealing portions ES1 and ES2, respectively. The conductive layer 303 in the wall region WR is connected to the P-type well region PW via contacts C1W, C2W, C3W, V1W, and V2W corresponding to the sealing portion ES1 and conductive layers 103W, 104W, 105W, 24W, 25W, and 26W. The conductive layer 303 in the wall region WR is connected to the N-type well region NW via contacts C1W, C2W, C3W, V1W, and V2W corresponding to the sealing portion ES2 and conductive layers 103W, 104W, 105W, 24W, 25W, and 26W.

[0066] The sealing portions ES1 and ES2 described above are structures that can release positive and negative charges generated inside and outside the wall region WR to the semiconductor substrate W1. Furthermore, each of the sealing portions ES1 and ES2 can prevent moisture and the like from penetrating from the outside of the wall region WR into the core region CR. Each of the sealing portions ES1 and ES2 can suppress stress generated in an interlayer insulating film (e.g., tetraethoxysilane (TEOS)) of the memory device 1. Furthermore, each of the sealing portions ES1 and ES2 can also be used as a crack stopper.

[0067] (7: Planar layout of wiring layer 300) 9 is a plan view showing an example of a planar layout of the wiring layer 300 in the memory device 1 according to the first embodiment. FIG. 9 shows the core region CR, the peripheral region PR, the wall region WR, and some of the wiring and pad portions PD. As shown in FIG. 9, within the wall region WR, the sealing portion ES1 is provided so as to surround the outer peripheries of the core region CR and the peripheral region PR. The sealing portion ES2 is provided so as to surround the outer periphery of the sealing portion ES1.

[0068] A plurality of conductor layers 303 are arranged inside the wall region WR. Each of the plurality of conductor layers 303 has a portion extending in the Y direction. The plurality of conductor layers 303 are aligned in the X direction. The plurality of conductor layers 303 include, for example, a conductor layer 303A used as part of the source line SL and a conductor layer 303B used as part of the power line PL. The conductor layers 303A and 303B are arranged alternately, for example. The conductor layer 303A corresponds to, for example, the conductor layer 303 having a portion connected to the conductor layer 21 through the via VA in the core region CR shown in FIG. 8. On the other hand, the conductor layer 303B does not have a portion connected to the conductor layer 21 through the via VA.

[0069] A plurality of pad portions PD are arranged inside the wall region WR. One pad portion PD is connected to each conductive layer 303B. A power supply voltage, a ground voltage, etc. are applied to the pad portions PD connected to the conductive layer 303B. On the other hand, the pad portions PD that do not overlap with either the conductive layers 303A or 303B are connected to interface circuits such as the input / output circuit 11 or the logic controller 12. At least the pad portions PD that do not overlap with either the conductive layers 303A or 303B are arranged to overlap with each of the core region CR and the peripheral region PR.

[0070] (8: Planar layout of pad section PD) 10 is a plan view showing an example of a planar layout near the pad portion PD in the memory device 1 according to the first embodiment. Fig. 10 shows the pad portion PD used for connection to the input / output circuit 11, the logic controller 12, etc. in the memory device 1, and a part of each of the core region CR and the peripheral region PR.

[0071] 10, the pad portion PD overlaps with both the core region CR and the peripheral region PR. The pad portion PD has a portion that overlaps with the dummy region DA of the core region CR, but does not have a portion that overlaps with the active region AA. The pad portion PD includes a conductive portion MA, an insulating portion BA, a via TV, and a via VB.

[0072] The conductive portion MA is formed, for example, by a conductive layer 303. The conductive portion MA is provided, for example, in a rectangular shape in a plan view. The outer edge of the conductive portion MA corresponds to the outer edge of the pad portion PA. The insulating portion BA is formed, for example, by an insulating member 302. The insulating portion BA is provided, for example, in a rectangular shape in a plan view, and overlaps with the conductive portion MA. The outer edge of the insulating portion BA is located inside the outer edge of the conductive portion MA.

[0073] Each of the vias TV and VB is, for example, rectangular in plan view and overlaps with the conductive portion MA. The vias TV and VB are aligned in the Y direction. The outer edges of each of the vias TV and VB are located inside the outer edges of the insulating portion BA. The via TV is included in each of the dummy area DA and the peripheral area PR. Therefore, the boundary between the dummy area DA and the peripheral area PR overlaps with the via TV in plan view. A portion of the conductive portion MA is exposed through the via TV. The portion of the conductive portion MA exposed through the via TV corresponds to a pad used to connect the memory device 1 and the memory controller 2. The via VB is included in the peripheral area PR and is provided penetrating a portion of the insulating portion BA. The conductive portion MA is electrically connected to a plurality of contacts C3 arranged to overlap with the via VB via the via VB.

[0074] (9: Cross-sectional structure of pad part PD) FIG. 11 is a cross-sectional view taken along line XI-XI in FIG. 10 , showing an example of a cross-sectional structure near the pad portion PD in the memory device 1 according to the first embodiment. As shown in FIG. 11 , in the memory device 1, the stacked body corresponding to the memory cell array 10 includes, in the dummy region DA, insulating layers 32 and conductive layers 22 alternately stacked in the Z direction, or insulating layers 32 and sacrificial members SM alternately stacked in the Z direction. The sacrificial members SM are made of a different material from the insulating layers 32 and conductive layers 22. The dummy staircase portion DS is composed of, for example, insulating layers 32 and sacrificial members SM alternately stacked in the Z direction. In other words, the stacked body corresponding to the memory cell array 10 includes, in the dummy region DA, a stacked body portion in which the insulating layers 32 and the sacrificial members SM are alternately stacked in the Z direction. In this stacked body portion, the ends of the stacked sacrificial members SM are provided in a staircase shape. A plurality of dummy pillars DMP penetrate the stacked body corresponding to the memory cell array 10 in the Z direction within the dummy region DA.

[0075] The via TV penetrates the insulating layers 304, 305, and 306. At the bottom of the via TV, a portion of the conductive layer 303 corresponding to the conductive portion MA is exposed. The insulating member 302 corresponding to the insulating portion BA is provided in a region that is the same height as the source line SL and overlaps with the via TV in the Z direction. Therefore, the conductive layers 21, 211, and 213 are not provided in the region that overlaps with the via TV in the Z direction. In other words, the portion of the conductive layer 303 corresponding to the conductive portion MA whose surface is exposed through the via TV does not have a portion that overlaps with the conductive layers 21, 211, and 213 in the Z direction. In the memory device 1 according to the first embodiment, at least the source line SL between the dummy staircase portion DS and the conductive layer 303 is removed.

[0076] The conductive layer 303 corresponding to the conductive portion MA has a portion provided along the via VB and is connected to a plurality of contacts C3 via the via VB. The conductive layer 303 corresponding to the conductive portion MA is electrically connected to the transistor TR2 on the semiconductor substrate W1 via the plurality of contacts C3. In other words, the pad corresponding to the conductive portion MA is electrically connected to an interface circuit (e.g., the input / output circuit 11 or the logic controller 12) included in the CMOS circuit provided in the CMOS layer 100 via the memory layer 200.

[0077] When a step is formed between the insulator layer 301 and the insulating member 302, the conductor layer 303 may have a portion provided along the step formed between the insulator layer 301 and the insulating member 302. The via TV has at least a portion facing the dummy staircase portion DS in the Z direction, and may have a portion facing the dummy pillar DMP in the Z direction. The insulating portion BA may be provided so as to remove a portion of the dummy pillar DMP, or may be provided so as to remove a portion of the dummy staircase portion DS.

[0078] In the memory device 1 described above, the memory layer 200 includes a first sub-layer (e.g., a conductive layer 211) provided in the same layer as the source lines SL in the peripheral region PR and containing the same material as at least a portion of the source lines SL as a main component, and a second sub-layer (e.g., a conductive layer 213) provided above the first sub-layer via a member (e.g., a sacrificial member 212). The via TV does not have a portion overlapping the first sub-layer and the second sub-layer in the Z direction.

[0079] The conductive layer 303 is provided above the source line SL in the Z direction, includes a portion corresponding to the pad (via TV), and is electrically connected to the CMOS circuit on the semiconductor substrate W1. The conductive layer 303 has a portion overlapping the dummy pillar DMP in the Z direction, and this portion of the conductive layer 303 faces the dummy pillar DMP in the Z direction via an insulating member 302 provided at the same height as the source line SL, without the source line SL in between. The pad (via TV) has a portion overlapping the dummy pillar DMP in the Z direction, but does not have a portion overlapping with the source line SL in the Z direction. The insulator layer 304 is provided so as to cover the upper part of the conductive layer 303. A via TV is provided in the insulator layer 304 so that the surface of the conductive layer 303 corresponding to the pad is exposed. The memory layer 200 further includes an insulator layer 210 provided around a stack corresponding to the memory cell array 10 in a plan view, and at least one contact C3, the portion of which is provided at the same height as the stack and extends in the Z direction within the insulator layer 210 and is electrically connected to the CMOS circuit. The conductor layer 303 further includes a portion electrically connected to the at least one contact C3.

[0080] <1-2> Manufacturing method Next, as a method for manufacturing the memory device 1 according to the first embodiment, a method for forming the pad portion PD after bonding the semiconductor substrate W1 and the semiconductor substrate W2 will be described with appropriate reference to Fig. 12. Fig. 12 is a flowchart showing an example of a method for manufacturing the memory device 1 according to the first embodiment. Each of Figs. 13 to 17 is a cross-sectional view showing an example of a cross-sectional structure in the manufacturing process of the memory device 1 according to the first embodiment, and shows a cross section including a region near the pad portion PD.

[0081] First, the semiconductor substrate W2 is removed from the bonded semiconductor substrates W1 and W2 (step ST11). For example, a chemical mechanical polishing (CMP) process is used to remove the semiconductor substrate W2. After the semiconductor substrate W2 is removed, an insulator layer 301 is formed as shown in FIG. 13. The insulator layer 301 may be formed in advance between the semiconductor substrate W2 and the conductor layer 21. In this case, the surface of the insulator layer 301 is exposed by the process of step ST11.

[0082] Next, as shown in FIG. 14, an opening BAH is formed (step ST12). Specifically, first, a mask is formed with an opening corresponding to the insulating portion BA in plan view. Then, an anisotropic etching process is performed to remove the insulating layer 301, the conductor layers 21, 211, and 213, and the sacrificial member 202 from the opening of the mask, thereby forming the opening BAH. In the opening BAH, upper portions of the multiple dummy pillars DMP and the multiple contacts C3 are exposed. The upper portions of the multiple dummy pillars DMP and the multiple contacts C3 can remain in a convex shape within the opening BAH.

[0083] 15, an insulating member 302 is formed in the opening BAH (step ST13). Specifically, first, the insulating member 302 is formed so as to fill the opening BAH. Then, the insulating member 302 formed outside the opening BAH is removed by, for example, CMP processing. As a result, the insulating member 302 remaining in the opening BAH corresponds to the insulating portion BA. Note that the CMP processing in step ST13 may leave a step between the insulating layer 301 and the insulating member 302.

[0084] 16, vias VB are formed (step ST14). Specifically, a mask is first formed with openings corresponding to the vias VB in a plan view. Then, an anisotropic etching process is performed to remove the insulating member 302 from the openings in the mask, thereby forming the vias VB. In the vias VB, the upper portions of the multiple contacts C3 are exposed.

[0085] 17, a conductor layer 303 is formed (step ST15). Specifically, for example, first, the conductor layer 303 is formed by CVD (Chemical Vapor Deposition) or the like, and a mask covering the conductor portion MA is formed. Thereafter, an anisotropic etching process is performed, and the conductor layer 303 is processed into the shape of the conductor portion MA.

[0086] Next, the insulating layers 304, 305, and 306 are formed (step ST16), and the vias TV are formed (step ST17), thereby completing the structure corresponding to the pad portion PD shown in FIG.

[0087] <1-3> Effects of the first embodiment According to the memory device 1 according to the first embodiment described above, it is possible to reduce the chip size while suppressing degradation of the interface speed. The effects of the memory device 1 according to the first embodiment will be described below using a first comparative example and a second comparative example.

[0088] 18 is a plan view showing an example of a planar layout near the pad portion PDy in the memory device 1Y according to the first comparative example. As shown in Fig. 18, the pad portion PDy in the memory device 1Y according to the first comparative example is included in the peripheral region PR and is separated from the core region CR. Unlike the pad portion PD, the pad portion PDy does not have an insulating portion BA.

[0089] FIG. 19 is a cross-sectional view taken along line XIX-XIX in FIG. 18 , showing an example of a cross-sectional structure near the pad portion PDy in the memory device 1Y according to the first comparative example. As shown in FIG. 19 , in the memory device 1Y, the insulating member 302 is replaced with an insulating layer 307. The insulating layer 307 is provided on the insulating layer 301 and has portions provided along the openings BAH and vias VB. The conductive layer 303 corresponding to the conductive portion MA is provided along the insulating layer 307 and is connected to a plurality of contacts C3 through the vias VB. In the memory device 1Y, the structure corresponding to the source line SL is removed below the via TV. This can suppress parasitic capacitance between the conductive portion MA and the source line SL. On the other hand, the chip size of the memory device 1Y can increase depending on the layout of the pad portion PDy.

[0090] 20 is a plan view showing an example of a planar layout near a pad portion PDz in a memory device 1Z according to a second comparative example. As shown in Fig. 20, the pad portion PDz in the memory device 1Z according to the second comparative example has a portion overlapping with a dummy area DA, similar to the first embodiment. On the other hand, the insulating portion BA in the pad portion PDz is arranged so as not to overlap with the via TV in a plan view.

[0091] FIG. 21 is a cross-sectional view taken along line XXI-XXI in FIG. 20, showing an example of a cross-sectional structure near a pad portion PDz in a memory device 1Z according to a second comparative example. As shown in FIG. 21, in the memory device 1Z, the via TV is arranged so as to overlap with a dummy region DA (e.g., a dummy staircase portion DS). Meanwhile, unlike the first embodiment, the memory device 1Z has a conductor layer 21 or conductor layers 211 and 213 arranged in a portion facing the via TV in the Z direction. Therefore, while the memory device 1Z can have a smaller chip size than the first comparative example, the parasitic capacitance between the conductive portion MA and the source line SL may increase. Therefore, the interface speed in the second comparative example may be lower than that in the first comparative example.

[0092] In contrast, the memory device 1 according to the first embodiment has a structure in which the source lines SL are removed from regions where the ends (dummy areas DA) of the memory cell array 10 overlap with the pad portions PD, and an insulating member 302 is embedded in the regions. Specifically, in the memory device 1 according to the first embodiment, the memory layer 100 includes a stacked body including insulating layers 32 and conductive layers 22 alternately stacked in the Z direction in the active area AA and including a sacrificial member SM provided in the same layer as the conductive layer 22 in the dummy area DA, a plurality of memory pillars MP and a plurality of dummy pillars DMP penetrating the stacked body, and a source line SL (conductive layer 21) connected to the plurality of memory pillars MP above the stacked body. Furthermore, a pad (via TV) corresponding to a portion of the conductive portion MA exposed in the via TV has a portion overlapping with the sacrificial member SM in the Z direction, but does not have a portion overlapping with the source line SL in the Z direction.

[0093] As a result, in the memory device 1 according to the first embodiment, the parasitic capacitance between the conductive portion MA and the source line SL, i.e., the parasitic capacitance of the pad, can be reduced. Furthermore, the chip size of the memory device 1 according to the first embodiment can be reduced in the same way as in the second comparative example, because the pad portion PD and the dummy area DA have portions where they overlap in the Z direction. Therefore, the memory device 1 according to the first embodiment can reduce its chip size while suppressing degradation in interface speed.

[0094] <2> Second embodiment The memory device 1A according to the second embodiment has a structure in which a contact VBP penetrating the insulating member 302 is formed instead of the via VB described in the first embodiment, and the conductive layer 303 and the contact C3 are electrically connected via the contact VBP. Details of the memory device 1A according to the second embodiment will be described below.

[0095] <2-1> Configuration The memory device 1A according to the second embodiment has the same configuration as the memory device 1 according to the first embodiment except for the structure of the pad portion PD. The planar layout and cross-sectional structure of the pad portion PDa in the memory device 1A according to the second embodiment will be described below.

[0096] <2-1-1> Planar layout of pad section PDa 22 is a plan view showing an example of a planar layout near the pad portion PDa in the memory device 1A according to the second embodiment. Fig. 22 shows the pad portion PDa used for connection to the input / output circuit 11, the logic controller 12, etc. in the memory device 1A, and parts of the core region CR and the peripheral region PR.

[0097] 22, the pad portion PDa overlaps with both the core region CR and the peripheral region PR. The pad portion PDa has a portion that overlaps with the dummy region DA of the core region CR, but does not have a portion that overlaps with the active region AA. The pad portion PDa includes a conductive portion MA, an insulating portion BA, a via TV, and a plurality of contacts VBP.

[0098] The configurations of the conductive portion MA, insulating portion BA, and via TV in the pad portion PDa are the same as those of the pad portion PD in the first embodiment. Each of the multiple contacts VBP is included in the peripheral region PR and is provided so as to penetrate a part of the insulating portion BA. The region in which the multiple contacts VBP are formed is adjacent to the via TV in the Y direction and is arranged so as not to overlap with the via TV. The multiple contacts VBP are arranged, for example, in a lattice pattern. The multiple contacts VBP overlap with the multiple contacts C3, respectively. A pair of overlapping contacts VBP and contact C3 are electrically connected.

[0099] <2-1-2> Cross-sectional structure of pad section PDa FIG. 23 is a cross-sectional view taken along line XXIII-XXIII in FIG. 22, showing an example of a cross-sectional structure in the vicinity of the pad portion PDa in the memory device 1A according to the second embodiment. As shown in FIG. 23, the pad portion PDa has a configuration in which the via VB is omitted and multiple contacts VBP are added to the pad portion PD described using FIG. 11 in the first embodiment. Each of the multiple contacts VBP is provided penetrating the insulating member 302 corresponding to the insulating portion BA. The bottom of each of the multiple contacts VBP is connected to the upper part of the contact C3 provided overlapping in the Z direction. In the pad portion PDa, the upper surface of the insulating member 302, the upper surface of the contact VBP, and the upper surface of the insulator layer 301 are flush with each other.

[0100] The conductive layer 303 corresponding to the conductive portion MA is provided on the upper surfaces of the planarized insulating member 302 and the contact VBP. The conductive portion MA of the second embodiment does not have a step at the boundary between the insulating layer 301 and the insulating member 302. Other configurations of the pad portion PDa are the same as those of the pad portion PD in the first embodiment.

[0101] <2-2> Manufacturing method Next, as a method for manufacturing the memory device 1A according to the second embodiment, a method for forming the pad portion PDa after bonding the semiconductor substrates W1 and W2 will be described with appropriate reference to Figure 24. Figure 24 is a flowchart showing an example of a method for manufacturing the memory device 1A according to the second embodiment. Each of Figures 25 to 27 is a cross-sectional view showing an example of a cross-sectional structure in the manufacturing process of the memory device 1A according to the second embodiment, and shows a cross section including the vicinity of the pad portion PDa.

[0102] First, similarly to the first embodiment, the semiconductor substrate W2 is removed (step ST11), an opening BAH is formed (step ST12), and an insulating member 302 is formed in the opening BAH (step ST13).

[0103] 25, a plurality of holes VBH are formed (step ST21). Specifically, first, a mask is formed with openings that overlap with the contacts C3 in a plan view. Then, an anisotropic etching process is performed to remove the insulating member 302 at the openings of the mask, thereby forming a plurality of holes VBH. At the bottom of each hole VBH, the top of the associated contact C3 is exposed.

[0104] 26, conductive members 310 are formed in each hole VBH (step ST22). Specifically, first, conductive members 310 are formed by CVD or the like so as to fill each hole VBH. Thereafter, conductive members 310 formed outside each hole VBH are removed by, for example, CMP processing, and multiple contacts VBP are formed. This CMP processing aligns the upper surfaces of the conductive members 310 (contacts VBP) in each hole VBH with the upper surface of the insulating member 302 and the upper surface of the insulator layer 301.

[0105] 27, a conductor layer 303 is formed (step ST23). Specifically, for example, first, the conductor layer 303 is formed, and then a mask covering the conductor portion MA is formed. Thereafter, an anisotropic etching process is performed, and the conductor layer 303 is processed into the shape of the conductor portion MA.

[0106] Thereafter, similarly to the first embodiment, the insulating layers 304, 305, and 306 are formed (step ST16), and the via TV is formed (step ST17), thereby completing the structure corresponding to the pad portion PDa shown in FIG.

[0107] <2-3> Effects of the second embodiment The memory device 1A according to the second embodiment, like the first embodiment, has a structure in which the structure corresponding to the source line SL is removed from the dummy area DA and the dummy area DA and the pad portion PDa overlap in the Z direction. Therefore, like the first embodiment, the memory device 1A according to the second embodiment can reduce the parasitic capacitance of the pad and can reduce the chip size while suppressing deterioration in interface speed.

[0108] Furthermore, the memory device 1A according to the second embodiment uses contacts VBP to connect the conductive portions MA and contacts C3, rather than vias VB as in the first embodiment. Furthermore, in the memory device 1A, the upper surfaces of the insulating portions BA and the contacts VBP are planarized when the contacts VBP are formed. As a result, the memory device 1A according to the second embodiment can suppress the occurrence of defects caused by steps in the conductive portions MA formed along the vias VB as in the first embodiment. Therefore, the memory device 1A according to the second embodiment can improve the yield compared to the first embodiment.

[0109] <3> Third embodiment The memory device 1B according to the third embodiment has a structure in which a conductive member 320 is formed so as to cover the upper portions of the plurality of contacts C3 described in the first embodiment, and the conductive layer 303 and each contact C3 are electrically connected via the conductive member 320. Details of the memory device 1B according to the third embodiment will be described below.

[0110] <3-1> Configuration The memory device 1B according to the third embodiment has the same configuration as the memory device 1 according to the first embodiment except for the structure of the pad part PD. The planar layout and cross-sectional structure of the pad part PDb in the memory device 1B according to the third embodiment will be described below.

[0111] <3-1-1> Planar layout of pad section PDb 28 is a plan view showing an example of a planar layout near the pad portion PDb in the memory device 1B according to the third embodiment. Fig. 28 shows the pad portion PDb used for connection to the input / output circuit 11, the logic controller 12, etc. in the memory device 1B, and parts of the core region CR and the peripheral region PR.

[0112] 28, the pad portion PDb overlaps with both the core region CR and the peripheral region PR. The pad portion PDb has a portion that overlaps with the dummy region DA of the core region CR, but does not have a portion that overlaps with the active region AA. The pad portion PDb includes a conductive portion MA, an insulating portion BA, a via TV, a conductive portion ZB, and a plurality of vias VBa.

[0113] The configurations of the conductive portion MA, insulating portion BA, and via TV in the pad portion PDb are the same as those of the pad portion PD in the first embodiment. The conductive portion ZB is included in the peripheral region PR and is arranged overlapping with each of the conductive portion MA and insulating portion BA. The conductive portion ZB is adjacent to the via TV in the Y direction and is arranged so as not to overlap with the via TV. The conductive portion ZB is connected to each of the multiple contacts C3 electrically connected to the conductive portion MA. Each of the multiple vias VBa is arranged overlapping with the conductive portion ZB in a plan view and is provided to penetrate a part of the insulating portion BA. The multiple vias VBa are arranged, for example, in a lattice pattern. The conductive portion MA is electrically connected to the conductive portion ZB via the multiple vias VBa. That is, the conductive portion MA is electrically connected to the multiple contacts C3 via the conductive portion ZB.

[0114] <3-1-2> Cross-sectional structure of pad section PDb FIG. 29 is a cross-sectional view taken along line XXIX-XXIX in FIG. 28, showing an example of a cross-sectional structure near a pad portion PDb in a memory device 1B according to the third embodiment. As shown in FIG. 29, the pad portion PDb has a configuration similar to that of the pad portion PD described with reference to FIG. 11 in the first embodiment, except that the via VB is replaced with multiple vias VBa and a conductive portion ZB is added. A conductive member 320 corresponding to the conductive portion ZB is provided so as to cover the upper portions of the multiple contacts C3. An upper portion of the conductive member 320 has a portion covered by the insulating member 302 corresponding to the insulating portion BA. The multiple vias VBa penetrate the insulating member 302. The bottoms of the multiple vias VBa each reach the conductive member 320.

[0115] The conductive layer 303 corresponding to the conductive portion MA is provided on the insulating member 302 and has a portion provided along the multiple vias VBa. The conductive layer 303 fills the multiple vias VBa and is connected to the conductive member 320 at the bottom of the vias VBa. The conductive layer 303 is then electrically connected to the multiple contacts C3 via the conductive member 320 and electrically connected to the transistor TR2 via the multiple contacts C3. The conductive layer 303 may have a concave portion above the vias VBa. The other configurations of the pad portion PDb are similar to those of the pad portion PD in the first embodiment.

[0116] <3-2> Manufacturing method Next, as a method for manufacturing the memory device 1B according to the third embodiment, a method for forming the pad portion PDb after bonding the semiconductor substrate W1 and the semiconductor substrate W2 will be described with appropriate reference to Figure 30. Figure 30 is a flowchart showing an example of a method for manufacturing the memory device 1B according to the third embodiment. Each of Figures 31 to 34 is a cross-sectional view showing an example of a cross-sectional structure in the manufacturing process of the memory device 1B according to the third embodiment, and shows a cross section including a region near the pad portion PDb.

[0117] First, similarly to the first embodiment, the semiconductor substrate W2 is removed (step ST11), and the opening BAH is formed (step ST12).

[0118] 31, a conductive member 320 is formed in a part of the opening BAH (step ST31). Specifically, for example, first, the conductive member 320 is formed by CVD or the like, and a mask that covers the conductive portion ZB is formed. Thereafter, an anisotropic etching process is performed, and the conductive member 320 is processed into the shape of the conductive portion ZB.

[0119] Next, as shown in FIG. 32, an insulating member 302 is formed in the opening BAH (step ST32). Specifically, first, the insulating member 302 is formed so as to fill the opening BAH. Then, the insulating member 302 formed outside the opening BAH is removed by, for example, CMP processing. The insulating member 302 remaining in the opening BAH corresponds to the insulating portion BA. Note that the CMP processing in step ST32 may leave a step between the insulating layer 301 and the insulating member 302.

[0120] Next, as shown in Fig. 33, the via VBa is formed (step ST33). Specifically, first, a mask is formed with an opening in the area of ​​the via VBa in plan view. Then, an anisotropic etching process is performed to remove the insulating member 302 at the opening of the mask, thereby forming the via VBa. In the via VBa, the upper part of the conductive portion ZB is exposed.

[0121] 34, a conductor layer 303 is formed (step ST34). Specifically, for example, first, the conductor layer 303 is formed by CVD or the like so as to fill the via VBa, and a mask covering the conductor portion MA is formed. Thereafter, an anisotropic etching process is performed, and the conductor layer 303 is processed into the shape of the conductor portion MA.

[0122] Thereafter, similarly to the first embodiment, the insulating layers 304, 305, and 306 are formed (step ST16), and the via TV is formed (step ST17), thereby completing the structure corresponding to the pad portion PDb shown in FIG.

[0123] <3-3> Effects of the third embodiment As in the first embodiment, the memory device 1B according to the third embodiment has a structure in which the structure corresponding to the source line SL is removed from the dummy area DA and the dummy area DA and the pad part PDb overlap in the Z direction. Therefore, as in the first embodiment, the memory device 1B according to the third embodiment can reduce the parasitic capacitance of the pad, and can reduce the chip size while suppressing degradation of the interface speed.

[0124] Furthermore, in the memory device 1B according to the third embodiment, the conductive portion MA and the contact C3 are connected via the conductive portion ZB. This allows for a more reliable electrical connection between the conductive layer 303 and the contact C3 than when the conductive layer 303 is directly connected to the protruding portion of the contact C3. Therefore, the memory device 1B according to the third embodiment can achieve a higher yield than the first embodiment.

[0125] <4> Fourth embodiment The memory device 1C according to the fourth embodiment has a structure in which the region where the contacts VBP and C3 are formed and the region where the via TV is formed overlap in the Z direction in the memory device 1A according to the second embodiment. Details of the memory device 1C according to the fourth embodiment will be described below.

[0126] <4-1> Configuration The memory device 1C according to the fourth embodiment has the same configuration as the memory device 1A according to the second embodiment except for the structure of the pad portion PDa. The planar layout and cross-sectional structure of the pad portion PDc in the memory device 1C according to the fourth embodiment will be described below.

[0127] <4-1-1> Planar layout of pad section PDc 35 is a plan view showing an example of a planar layout near the pad portion PDc in the memory device 1C according to the fourth embodiment. Fig. 35 shows the pad portion PDc used for connection to the input / output circuit 11, the logic controller 12, etc. in the memory device 1C, and parts of the core region CR and the peripheral region PR.

[0128] 35, the pad portion PDc overlaps with both the core region CR and the peripheral region PR. The pad portion PDc has a portion that overlaps with the dummy region DA of the core region CR, but does not have a portion that overlaps with the active region AA. The pad portion PDc includes a conductive portion MA, an insulating portion BA, a via TV, and a plurality of contacts VBP.

[0129] The configurations of the conductive portion MA, insulating portion BA, and via TV in the pad portion PDc are the same as those of the pad portion PDa in the second embodiment. Each of the multiple contacts VBP is included in the peripheral region PR and is provided penetrating a part of the insulating portion BA. The region in which the multiple contacts VBP are formed overlaps the via TV in a plan view. The multiple contacts VBP overlap with the multiple contacts C3, respectively. A pair of overlapping contacts VBP and contact C3 are electrically connected.

[0130] <4-1-2> Cross-sectional structure of pad section PDc FIG. 36 is a cross-sectional view taken along line XXXVI-XXXVI in FIG. 35, showing an example of a cross-sectional structure in the vicinity of the pad portion PDc in the memory device 1C according to the fourth embodiment. As shown in FIG. 36, the pad portion PDc has a configuration in which a plurality of contacts VBP and vias TV are arranged overlapping in the Z direction within the pad portion PDa described in the second embodiment using FIG. 23. For this reason, the pad portion PDc of the fourth embodiment can be designed to be smaller than the pad portion PDa of the second embodiment. The other configurations of the pad portion PDc are similar to those of the pad portion PDa of the second embodiment.

[0131] <4-2> Manufacturing method The manufacturing method for the memory device 1C of the fourth embodiment is similar to the manufacturing method for the memory device 1A of the second embodiment described using Figures 24 to 27, except that the area in which the contacts VBP and C3 are formed and the area in which the via TV is formed are arranged to overlap in the Z direction.

[0132] <4-3> Effects of the fourth embodiment The memory device 1C according to the fourth embodiment, like the first embodiment, has a structure in which the structure corresponding to the source line SL is removed from the dummy area DA and the dummy area DA and the pad part PDc overlap in the Z direction. Therefore, like the first embodiment, the memory device 1C according to the fourth embodiment can reduce the parasitic capacitance of the pad and can reduce the chip size while suppressing degradation of the interface speed.

[0133] Furthermore, in the memory device 1C according to the fourth embodiment, the via TV and the multiple contacts VBP are arranged to overlap in the Z direction. This allows the memory device 1C according to the fourth embodiment to have a smaller chip area than the memory device 1A according to the second embodiment. As a result, the memory device 1C according to the fourth embodiment can have a lower manufacturing cost than the memory device 1A according to the second embodiment.

[0134] <5> Fifth embodiment The memory device 1D according to the fifth embodiment has a structure in which the region where the plurality of contacts C3 and conductive members 320 are formed and the region where the via TV is formed overlap in the Z direction in the memory device 1B according to the third embodiment. Details of the memory device 1D according to the fifth embodiment will be described below.

[0135] <5-1> Configuration The memory device 1D according to the fifth embodiment has the same configuration as the memory device 1B according to the third embodiment except for the structure of the pad portion PDb. The planar layout and cross-sectional structure of the pad portion PDd in the memory device 1D according to the fifth embodiment will be described below.

[0136] <5-1-1> Planar layout of pad section PDd 37 is a plan view showing an example of a planar layout near the pad portion PDd in the memory device 1D according to the fifth embodiment. Fig. 37 shows the pad portion PDd used for connection to the input / output circuit 11, the logic controller 12, etc. in the memory device 1D, and parts of the core region CR and the peripheral region PR.

[0137] 37, the pad portion PDd overlaps with both the core region CR and the peripheral region PR. The pad portion PDd has a portion that overlaps with the dummy region DA of the core region CR, but does not have a portion that overlaps with the active region AA. The pad portion PDd includes a conductive portion MA, an insulating portion BA, a via TV, a conductive portion ZB, and a plurality of vias VBa.

[0138] The configurations of the conductive portion MA, insulating portion BA, and via TV in the pad portion PDd are the same as those of the pad portion PDb in the third embodiment. The conductive portion ZB is included in the peripheral region PR and is arranged overlapping with each of the conductive portion MA and insulating portion BA. Furthermore, the conductive portion ZB overlaps with the via TV in a plan view. The conductive portion ZB is connected to each of the multiple contacts C3 electrically connected to the conductive portion MA. Each of the multiple vias VBa is arranged overlapping with the conductive portion ZB in a plan view and is provided to penetrate a portion of the insulating portion BA. The conductive portion MA is electrically connected to the conductive portion ZB via the multiple vias VBa. That is, the conductive portion MA is electrically connected to the multiple contacts C3 via the conductive portion ZB.

[0139] <5-1-2> Cross-sectional structure of pad section PDd FIG. 38 is a cross-sectional view taken along line XXXVIII-XXXVIII in FIG. 37, showing an example of a cross-sectional structure in the vicinity of the pad portion PDd in the memory device 1D according to the fifth embodiment. As shown in FIG. 38, the pad portion PDd has a configuration in which the conductive portion ZB and the via TV in the pad portion PDb described in the third embodiment using FIG. 29 are arranged to overlap in the Z direction. For this reason, the pad portion PDd of the fifth embodiment can be designed to be smaller than the pad portion PDb of the third embodiment. The other configurations of the pad portion PDd are similar to those of the pad portion PDb of the third embodiment.

[0140] <5-2> Manufacturing method The manufacturing method for memory device 1D of the fifth embodiment is similar to the manufacturing method for memory device 1B of the third embodiment described using Figures 30 to 34, except that the area in which conductive portion ZB and contact C3 are formed and the area in which via TV are formed are arranged to overlap in the Z direction.

[0141] <5-3> Effects of the fifth embodiment The memory device 1D according to the fifth embodiment, like the first embodiment, has a structure in which the structure corresponding to the source line SL is removed from the dummy area DA and the dummy area DA and the pad part PDd overlap in the Z direction. Therefore, like the first embodiment, the memory device 1D according to the fifth embodiment can reduce the parasitic capacitance of the pad and can reduce the chip size while suppressing deterioration in interface speed.

[0142] Furthermore, in the memory device 1D according to the fifth embodiment, the via TV and the conductive portion ZB are arranged to overlap in the Z direction. This allows the memory device 1D according to the fifth embodiment to have a smaller chip area than the memory device 1B according to the third embodiment. As a result, the memory device 1D according to the fifth embodiment can have a lower manufacturing cost than the memory device 1B according to the third embodiment.

[0143] <6> Sixth embodiment The sixth embodiment relates to a memory device in which a source line SL having a different structure is applied to the memory device 1 according to the first embodiment. Details of a memory device 1E according to the sixth embodiment will be described below.

[0144] <6-1> Configuration The memory device 1E according to the sixth embodiment has the same configuration as the memory device 1 according to the first embodiment, except for the structure of the source lines SL. The cross-sectional structure of the memory cell array 10 in the memory device 1E according to the sixth embodiment, and the planar layout and cross-sectional structure of the pad part PD will be described below.

[0145] <6-1-1> Cross-sectional structure of memory cell array 10 FIG. 39 is a cross-sectional view showing an example of the cross-sectional structure of the memory cell array 10 included in a memory device 1E according to the sixth embodiment. FIG. 39 shows an example of the structure of the memory cell array 10 formed on a semiconductor substrate W2 before being bonded to the semiconductor substrate W1, and displays coordinate axes based on the semiconductor substrate W2. The area shown in FIG. 39 corresponds to the same area as FIG. 6 described in the first embodiment. As shown in FIG. 39, in the memory device 1E, the memory cell array 10 formed on the semiconductor substrate W2 before being bonded to the semiconductor W1 has a structure in which, for example, the conductor layer 21 of the memory cell array 10 of the first embodiment is replaced with a semiconductor layer 214, a member 215, and a semiconductor layer 216.

[0146] The semiconductor layer 216 is provided on the semiconductor substrate W2 via, for example, an insulator layer 301. The member 215 is provided on the semiconductor layer 216. The semiconductor layer 214 is provided on the member 215. The insulator layer 31 is provided on the semiconductor layer 214. Each of the semiconductor layers 214 and 216 is made of, for example, amorphous silicon. The semiconductor layer 216 is used, for example, as an etching stopper layer when forming the memory pillars MP and the slits SLT. For example, each of the memory pillars MP and the slits SLT penetrates the semiconductor layer 214. The bottoms of the memory pillars MP and the slits SLT reach the semiconductor layer 216. Other structures of the memory cell array 10 of the sixth embodiment are similar to those of the memory cell array 10 of the first embodiment.

[0147] <6-1-2> Planar layout of pad section PD 40 is a plan view showing an example of a planar layout near the pad portion PD in the memory device 1E according to the sixth embodiment. Fig. 40 shows the pad portion PD used for connection to the input / output circuit 11, the logic controller 12, etc. in the memory device 1E, and parts of the core region CR and the peripheral region PR.

[0148] As shown in FIG. 40, the memory device 1E has a configuration in which the active region AA and dummy region DA of the core region CR in the memory device 1 according to the first embodiment are replaced with active region AAa and dummy region DAa, respectively. The active region AAa and dummy region DAa have different structures in the portions corresponding to the source lines SL compared to the active region AA and dummy region DA, respectively. The structure of the source lines SL in the memory device 1E will be described in detail later. The pad portion PD of the sixth embodiment overlaps with both the core region CR and the peripheral region PR. The pad portion PD of the sixth embodiment has a portion of the core region CR that overlaps with the dummy region DAa, but does not have a portion that overlaps with the active region AAa. The pad portion PD of the sixth embodiment includes a conductive portion MA, an insulating portion BA, a via TV, and a via VB, similar to the pad portion PD of the first embodiment.

[0149] <6-1-3> Cross-sectional structure near the pad part PD Fig. 41 is a cross-sectional view taken along line XLI-XLI in Fig. 40, showing an example of a cross-sectional structure near the pad portion PD in the memory device 1E according to the sixth embodiment. Fig. 41 shows a part of the active region AAa, the dummy region DAa, and the peripheral region PR after the semiconductor substrates W1 and W2 are bonded and the wiring layer 300 is formed, and displays coordinate axes based on the semiconductor substrate W1. Note that in the memory device 1E, the structure in the wall region WR is similar to that in the peripheral region PR, and therefore a description of the structure in the wall region WR will be omitted.

[0150] As shown in FIG. 41 , in the memory device 1E, the laminated film 42 on the upper part of the memory pillars MP has been removed. Also, the laminated film 42 on the upper part of the dummy pillars DMP has been removed. In the active region AAa, the dummy region DA, and the peripheral region PRa, a semiconductor layer 214 is provided on the laminated body corresponding to the memory cell array 10 or on the insulator layer 210. On the semiconductor layer 214, a member 215, a semiconductor layer 216, and an insulator layer 310 are provided in this order in the peripheral region PR and in the portion of the dummy region DAa on the peripheral region PR side. Also, on the semiconductor layer 214, a semiconductor layer 217, a conductor layer 218, and an insulator layer 330 are provided in this order in the active region AAa and in the portion of the dummy region DAa on the active region AAa side.

[0151] Each of the semiconductor layers 214, 216, and 217 is, for example, polysilicon. The semiconductor layer 217 is doped with impurities. Therefore, the semiconductor layer 217 functions as a conductor. When the semiconductor layer 217 is doped with impurities, impurities may diffuse into the semiconductor layer 214 in the active region AAa. Therefore, the semiconductor layer 214 in the active region AAa contains impurities and can function as a conductor. On the other hand, the peripheral region PR is excluded from the region to be doped with impurities when the semiconductor layer 217 is doped with impurities. Therefore, the semiconductor layer 214 in the peripheral region PR does not contain such impurities.

[0152] The semiconductor layer 217 is provided so as to cover the semiconductor layer 41 on the upper part of each memory pillar MP, the semiconductor layer 41 (not shown) on the upper part of each dummy pillar DMP, and the upper part of the slit SLT. Therefore, each of the conductor layer 217 and the conductor layer 218 has a portion provided along the upper part of each memory pillar MP, dummy pillar DMP, and slit SLT. The semiconductor layer 217 is electrically connected to the semiconductor layer 41 of each memory pillar MP. In the memory device 1E, a set of the semiconductor layers 214 and 217 and the conductor layer 218 functions as a part of the source line SL. The upper surface of the insulator layer 330 is flush with, for example, the upper surface of the insulator layer 301 in the peripheral region PR.

[0153] The insulating member 302 of the memory device 1E is provided in a part of the peripheral region PR, penetrating the insulator layer 301, the semiconductor layer 216, the member 215, and the semiconductor layer 214. The insulating member 302 is also provided in a part of the dummy region DAa, penetrating the insulator layer 330, the conductor layer 218, the semiconductor layer 217, and the semiconductor layer 214. The upper surface of the insulating member 302 may be flush with the upper surfaces of the insulator layers 301 and 330, or a step may be formed between the insulating member 302 and the insulator layers 301 and 330. The lower surface of the insulating member 302 may be flush with the lower surface of the semiconductor layer 214, or may be located at a height between the lower surface of the semiconductor layer 214 and the conductor layer 26.

[0154] The conductor layer 303 of the memory device 1E is provided on the insulator layers 301 and 330. The conductor layer 303 may have a portion provided on the insulating member 302 in the dummy region DAa and the peripheral region PR. The insulator layers 304, 305, and 306 are provided in this order on the insulator layers 301 and 330 and the conductor layer 303.

[0155] The pad portion PD in the sixth embodiment has the same configuration as the pad portion PD described in the first embodiment using FIG. 11. In the pad portion PD in the sixth embodiment, the semiconductor layers 214, 216, and 217 and the conductor layer 218 are not provided in the region overlapping with the via TV in the Z direction. That is, in the memory device 1E, the portion of the conductor layer 303 corresponding to the conductive portion MA whose surface is exposed through the via TV does not have a portion overlapping with the semiconductor layers 214, 216, and 217 and the conductor layer 218 in the Z direction. The other configurations of the memory device 1E according to the sixth embodiment are the same as those of the memory device 1 according to the first embodiment.

[0156] <6-2> Manufacturing method Next, as a method for manufacturing the memory device 1E according to the sixth embodiment, a method for forming the source lines SL and the pad portions PD after bonding the semiconductor substrates W1 and W2 will be described with appropriate reference to Fig. 42. Fig. 42 is a flowchart showing an example of a method for manufacturing the memory device 1E according to the sixth embodiment. Fig. 43 and Fig. 44 are each cross-sectional views showing an example of a cross-sectional structure in the manufacturing process of the memory device 1E according to the sixth embodiment, and show a cross section including a region near the pad portions PD.

[0157] First, similarly to the first embodiment, the semiconductor substrate W2 is removed (step ST11).

[0158] Next, as shown in FIG. 43, the insulator layer 301, the semiconductor layer 216, and the component 215 in the active region AAa, as well as a portion of the laminated film 42, are removed (step ST61). Specifically, first, a mask having an opening corresponding to the active region AAa is formed. Then, the insulator layer 301, the semiconductor layer 216, and the component 215 are removed through the opening of the mask by anisotropic etching. At this time, the component 215 and the semiconductor layer 214 can each be used as an etching stopper layer. Thereafter, for example, the laminated film 42 provided above the insulator layer 214 in the active region AAa is selectively removed by wet etching. Note that in step ST61, the insulator layer 301, the semiconductor layer 216, the component 215, and a portion of the laminated film 42 in the dummy region DAa may also be removed depending on the shape of the mask used.

[0159] Next, a semiconductor layer 217 and a conductor layer 218 are formed (step ST62). Specifically, first, amorphous silicon corresponding to the semiconductor layer 217 is formed in the exposed surface portion of the semiconductor layer 214. Then, by introducing impurities into the formed amorphous silicon and subsequent heat treatment, the impurities diffuse into the semiconductor layers 214 and 217, and the formed amorphous silicon is transformed into polysilicon. Then, a conductor layer 218 is formed on the semiconductor layer 217. The conductor layer 218 contains, for example, at least one of tungsten, aluminum, titanium, and titanium nitride. Note that in step ST62, the semiconductor layers 214 and 216 are transformed from amorphous silicon to polysilicon during the heat treatment that transforms the semiconductor layer 217 into polysilicon. Thereafter, as shown in FIG. 44, an insulator layer 330 is formed (step ST63). In step ST63, for example, first, the insulator layer 330 is formed on the conductor layer 218 and the insulator layer 301. Then, the upper surfaces of the insulator layers 330 and 301 are planarized by a CMP process or the like. In this example, the insulator layer 330 formed on the insulator layer 301 is removed. Note that the insulator layer 330 may remain on the upper surface of the insulator layer 301.

[0160] Then, similarly to the first embodiment, the processes of steps ST12 to ST17 are executed in order. This completes the structure corresponding to the source lines SL and the structure corresponding to the pad parts PD shown in Fig. 41. In this way, the method for manufacturing the memory device 1E according to the sixth embodiment has a configuration in which the processes of steps ST61, ST62, and ST63 are inserted between steps ST11 and ST12 in the method for manufacturing the memory device 1 according to the first embodiment shown in Fig. 12.

[0161] <6-3> Effects of the sixth embodiment The memory device 1E according to the sixth embodiment has a structure in which the structure corresponding to the source line SL is removed from the dummy area DAa, and the dummy area DAa and the pad part PD overlap in the Z direction. Therefore, like the first embodiment, the memory device 1E according to the sixth embodiment can reduce the parasitic capacitance of the pad, and can reduce the chip size while suppressing deterioration in interface speed.

[0162] <7> Seventh embodiment The memory device 1F according to the seventh embodiment has a structure in which the pad portion PDa described in the second embodiment and the source line SL described in the sixth embodiment are combined. Details of the memory device 1F according to the seventh embodiment will be described below.

[0163] <7-1> Configuration The memory device 1F according to the seventh embodiment has the same configuration as the memory device 1A according to the second embodiment except for the structure of the source lines SL. The planar layout and cross-sectional structure of the pad portion PDa in the memory device 1F according to the seventh embodiment will be described below.

[0164] <7-1-1> Planar layout of pad section PDa 45 is a plan view showing an example of a planar layout near the pad portion PDa in the memory device 1F according to the seventh embodiment. Fig. 45 shows the pad portion PDa used for connection to the input / output circuit 11, the logic controller 12, etc. in the memory device 1F, and parts of the core region CR and the peripheral region PR.

[0165] 45, the memory device 1F has a configuration in which the active region AA and dummy region DA of the core region CR in the memory device 1A according to the second embodiment are replaced with the active region AAa and dummy region DAa of the sixth embodiment, respectively. The pad portion PDa of the seventh embodiment overlaps with each of the core region CR and the peripheral region PR. The pad portion PDa of the seventh embodiment has a portion of the core region CR that overlaps with the dummy region DAa, but does not have a portion that overlaps with the active region AAa. Like the pad portion PDa of the second embodiment, the pad portion PDa of the seventh embodiment includes a conductive portion MA, an insulating portion BA, a via TV, and a plurality of contacts VBP.

[0166] <7-1-2> Cross-sectional structure of pad section PDa 46 is a cross-sectional view taken along line XLVI-XLVI in FIG. 45, showing an example of a cross-sectional structure near the pad portion PDa in the memory device 1F according to the seventh embodiment. As shown in FIG. 46, the memory device 1F has a structure in which the source lines SL in the active region AAa and dummy region DAa described in the sixth embodiment using FIG. 41 are combined with the pad portion PDa described in the second embodiment using FIG. 23. The other configurations of the memory device 1F according to the seventh embodiment are similar to those of the memory device 1A according to the second embodiment.

[0167] <7-2> Manufacturing method The method for manufacturing the memory device 1F according to the seventh embodiment is similar to the method for manufacturing the memory device 1A according to the second embodiment shown in Fig. 24, except that steps ST61, ST62, and ST63 shown in Fig. 42 are inserted between steps ST11 and ST12. That is, in the method for manufacturing the memory device 1F according to the seventh embodiment, the source lines SL are formed after removing the semiconductor substrate W2 as in the sixth embodiment, and then a structure corresponding to the pad portions PDa is formed as in the second embodiment.

[0168] <7-3> Effects of the Seventh Embodiment In the memory device 1F according to the seventh embodiment, the structure corresponding to the source line SL is removed from the dummy area DAa, and the dummy area DAa and the pad portion PDa overlap in the Z direction, similar to the sixth embodiment. Therefore, similar to the sixth embodiment, the memory device 1F according to the seventh embodiment can reduce the parasitic capacitance of the pad, suppressing degradation of the interface speed while reducing the chip size. Furthermore, the memory device 1F according to the seventh embodiment can suppress the occurrence of defects caused by steps in the conductive portion MA, and similar to the second embodiment, can improve the yield.

[0169] <8> Eighth embodiment The memory device 1G according to the eighth embodiment has a structure in which the pad portion PDb described in the third embodiment and the source line SL described in the sixth embodiment are combined. Details of the memory device 1G according to the eighth embodiment will be described below.

[0170] <8-1> Configuration The memory device 1G according to the eighth embodiment has the same configuration as the memory device 1B according to the third embodiment except for the structure of the source lines SL. The planar layout and cross-sectional structure of the pad portion PDb in the memory device 1G according to the eighth embodiment will be described below.

[0171] <8-1-1> Planar layout of pad section PDb 47 is a plan view showing an example of a planar layout near the pad portion PDb in the memory device 1G according to the eighth embodiment. Fig. 47 shows the pad portion PDb used for connection to the input / output circuit 11, the logic controller 12, etc. in the memory device 1G, and parts of the core region CR and the peripheral region PR.

[0172] 47, the memory device 1G has a configuration in which the active area AA and dummy area DA of the core region CR in the memory device 1B according to the third embodiment are replaced with the active area AAa and dummy area DAa of the sixth embodiment, respectively. The pad portion PDb of the eighth embodiment overlaps with each of the core region CR and the peripheral region PR. The pad portion PDb of the eighth embodiment has a portion of the core region CR that overlaps with the dummy area DAa, but does not have a portion that overlaps with the active area AAa. Like the pad portion PDb of the third embodiment, the pad portion PDb of the eighth embodiment includes a conductive portion MA, an insulating portion BA, a via TV, a conductive portion ZB, and a plurality of vias VBa.

[0173] <8-1-2> Cross-sectional structure of pad section PDb 48 is a cross-sectional view taken along line XLVIII-XLVIII in FIG. 47, showing an example of a cross-sectional structure near the pad portion PDb in the memory device 1G according to the eighth embodiment. As shown in FIG. 48, the memory device 1G has a structure in which the source lines SL in the active region AAa and dummy region DAa described in the sixth embodiment using FIG. 41 are combined with the pad portion PDb described in the third embodiment using FIG. 29. The other configurations of the memory device 1G according to the eighth embodiment are similar to those of the memory device 1B according to the third embodiment.

[0174] <8-2> Manufacturing method The method for manufacturing the memory device 1G according to the eighth embodiment is similar to the method for manufacturing the memory device 1B according to the third embodiment shown in Fig. 30, except that steps ST61, ST62, and ST63 shown in Fig. 42 are inserted between steps ST11 and ST12. That is, in the method for manufacturing the memory device 1G according to the eighth embodiment, the source line SL is formed after removing the semiconductor substrate W2 as in the sixth embodiment, and then a structure corresponding to the pad portion PDb is formed as in the third embodiment.

[0175] <8-3> Effects of the eighth embodiment The memory device 1G according to the eighth embodiment, like the sixth embodiment, has a structure in which the structure corresponding to the source line SL is removed from the dummy area DAa, and the dummy area DAa and the pad portion PDb overlap in the Z direction. Therefore, like the sixth embodiment, the memory device 1G according to the eighth embodiment can reduce the parasitic capacitance of the pad, suppressing degradation of the interface speed while reducing the chip size. Furthermore, like the third embodiment, the memory device 1G according to the eighth embodiment can improve the yield by connecting the conductive portion MA and the contact C3 via the conductive portion ZB.

[0176] <9> Ninth embodiment The memory device 1H according to the ninth embodiment has a structure in which the pad portion PDc described in the fourth embodiment and the source line SL described in the sixth embodiment are combined. Details of the memory device 1H according to the ninth embodiment will be described below.

[0177] <9-1> Configuration The memory device 1H according to the ninth embodiment has the same configuration as the memory device 1C according to the fourth embodiment except for the structure of the source lines SL. The planar layout and cross-sectional structure of the pad portion PDc in the memory device 1H according to the ninth embodiment will be described below.

[0178] <9-1-1> Planar layout of pad section PDc 49 is a plan view showing an example of a planar layout near the pad portion PDc in the memory device 1H according to the ninth embodiment. Fig. 49 shows the pad portion PDc used for connection to the input / output circuit 11, the logic controller 12, etc., in the memory device 1H, and parts of the core region CR and the peripheral region PR.

[0179] 49, the memory device 1H has a configuration in which the active region AA and dummy region DA of the core region CR in the memory device 1C according to the fourth embodiment are replaced with the active region AAa and dummy region DAa of the sixth embodiment, respectively. The pad portion PDc of the ninth embodiment overlaps with each of the core region CR and the peripheral region PR. The pad portion PDc of the ninth embodiment has a portion of the core region CR that overlaps with the dummy region DAa, but does not have a portion that overlaps with the active region AAa. The pad portion PDc of the ninth embodiment includes a conductive portion MA, an insulating portion BA, a via TV, and a plurality of contacts VBP, similar to the pad portion PDc of the fourth embodiment.

[0180] <9-1-2> Cross-sectional structure of pad section PDc 50 is a cross-sectional view taken along line LL in FIG. 49, showing an example of a cross-sectional structure near the pad portion PDc in the memory device 1H according to the ninth embodiment. As shown in FIG. 50, the memory device 1H has a structure in which the source lines SL in the active region AAa and dummy region DAa described in the sixth embodiment using FIG. 41 are combined with the pad portion PDc described in the fourth embodiment using FIG. 36. The other configurations of the memory device 1H according to the ninth embodiment are similar to those of the memory device 1C according to the fourth embodiment.

[0181] <9-2>Manufacturing method The method for manufacturing the memory device 1H according to the ninth embodiment is similar to the method for manufacturing the memory device 1C according to the fourth embodiment, which is based on the method for manufacturing the memory device 1A according to the second embodiment shown in Fig. 24, except that steps ST61, ST62, and ST63 shown in Fig. 42 are inserted between steps ST11 and ST12. That is, in the method for manufacturing the memory device 1H according to the ninth embodiment, the source line SL is formed after removing the semiconductor substrate W2 as in the sixth embodiment, and then a structure corresponding to the pad portion PDc is formed as in the fourth embodiment.

[0182] <9-3> Effects of the ninth embodiment The memory device 1H according to the ninth embodiment, like the sixth embodiment, has a structure in which the structure corresponding to the source line SL is removed from the dummy region DAa, and the dummy region DAa and the pad portion PDc overlap in the Z direction. Therefore, like the sixth embodiment, the memory device 1H according to the ninth embodiment can reduce the parasitic capacitance of the pad, and can reduce the chip size while suppressing degradation of the interface speed. Furthermore, like the fourth embodiment, the memory device 1H according to the ninth embodiment can reduce the chip area by arranging the via TV and the multiple contacts VBP to overlap in the Z direction.

[0183] <10> Tenth embodiment The memory device 1I according to the tenth embodiment has a structure in which the pad portion PDd described in the fifth embodiment and the source line SL described in the sixth embodiment are combined. Details of the memory device 1I according to the tenth embodiment will be described below.

[0184] <10-1> Configuration The memory device 1I according to the tenth embodiment has the same configuration as the memory device 1D according to the fifth embodiment, except for the structure of the source lines SL. The planar layout and cross-sectional structure of the pad portion PDd in the memory device 1I according to the tenth embodiment will be described below.

[0185] <10-1-1> Planar layout of pad section PDd 51 is a plan view showing an example of a planar layout near a pad portion PDd in a memory device 1I according to the tenth embodiment. Fig. 51 shows the pad portion PDd used for connection to the input / output circuit 11, the logic controller 12, etc. in the memory device 1I, and parts of the core region CR and the peripheral region PR.

[0186] As shown in FIG. 51, the memory device 1I has a configuration in which the active area AA and dummy area DA of the core region CR in the memory device 1D according to the fifth embodiment are replaced with the active area AAa and dummy area DAa of the sixth embodiment, respectively. The pad portion PDd of the tenth embodiment overlaps with each of the core region CR and the peripheral region PR. The pad portion PDd of the tenth embodiment has a portion of the core region CR that overlaps with the dummy area DAa, but does not have a portion that overlaps with the active area AAa. Like the pad portion PDd of the fifth embodiment, the pad portion PDd of the tenth embodiment includes a conductive portion MA, an insulating portion BA, a via TV, a conductive portion ZB, and a plurality of vias VBa.

[0187] <10-1-2> Cross-sectional structure of pad section PDd 52 is a cross-sectional view taken along line LII-LII in FIG. 51, showing an example of a cross-sectional structure near the pad portion PDd in the memory device 1I according to the tenth embodiment. As shown in FIG. 52, the memory device 1I has a structure in which the source lines SL in the active region AAa and dummy region DAa described in the sixth embodiment using FIG. 41 are combined with the pad portion PDd described in the fifth embodiment using FIG. 38. The other configurations of the memory device 1I according to the tenth embodiment are similar to those of the memory device 1D according to the fifth embodiment.

[0188] <10-2> Manufacturing method The method for manufacturing the memory device 1I according to the tenth embodiment is similar to the method for manufacturing the memory device 1D according to the fifth embodiment, which is based on the method for manufacturing the memory device 1B according to the third embodiment shown in Fig. 30, except that steps ST61, ST62, and ST63 shown in Fig. 42 are inserted between steps ST11 and ST12. That is, in the method for manufacturing the memory device 1I according to the tenth embodiment, the source line SL is formed after removing the semiconductor substrate W2 as in the sixth embodiment, and then a structure corresponding to the pad portion PDd is formed as in the fifth embodiment.

[0189] <10-3> Effects of the 10th embodiment The memory device 1I according to the tenth embodiment, like the sixth embodiment, has a structure in which the structure corresponding to the source line SL is removed from the dummy region DAa, and the dummy region DAa and the pad portion PDd overlap in the Z direction. Therefore, like the sixth embodiment, the memory device 1I according to the tenth embodiment can reduce the parasitic capacitance of the pad, and can reduce the chip size while suppressing degradation of the interface speed. Furthermore, like the fifth embodiment, the memory device 1I according to the tenth embodiment can reduce the chip area by arranging the via TV and the conductive portion ZB to overlap in the Z direction.

[0190] <11> Eleventh embodiment The memory device 1J according to the eleventh embodiment has a structure in which the size of the conductive portion MA of the pad portion PD in a plan view is designed to be smaller than the size of the insulating portion BA in a plan view in the memory device 1 according to the first embodiment. Details of the memory device 1J according to the eleventh embodiment will be described below.

[0191] <11-1> Configuration The memory device 1J according to the eleventh embodiment has the same configuration as the memory device 1 according to the first embodiment except for the structure of the pad part PD. The planar layout and cross-sectional structure of the pad part PDe in the memory device 1J according to the eleventh embodiment will be described below.

[0192] <11-1-1> Planar layout of pad section PDe 53 is a plan view showing an example of a planar layout near the pad portion PDe in the memory device 1J according to the 11th embodiment. Fig. 53 shows the pad portion PDe used for connection to the input / output circuit 11, the logic controller 12, etc. in the memory device 1J, and parts of the core region CR and the peripheral region PR.

[0193] As shown in FIG. 53, the pad portion PDe overlaps with each of the core region CR and the peripheral region PR. The pad portion PDe has a portion that overlaps with the dummy region DA of the core region CR, but does not have a portion that overlaps with the active region AA. The pad portion PDe includes a conductive portion MA, an insulating portion BA, a via TV, and a via VB. The insulating portion BA is, for example, rectangular in plan view. The outer edge of the insulating portion BA corresponds to the outer edge of the pad portion PDe. The conductive portion MA is, for example, rectangular in plan view, and overlaps with the conductive portion MA. The outer edge of the conductive portion MA is located inside the outer edge of the insulating portion BA. The configurations of the vias TV and VB in the pad portion PDe are similar to those of the vias TV and VB described in the first embodiment.

[0194] <11-1-2> Cross-sectional structure of pad section PDe 54 is a cross-sectional view taken along line LIV-LIV in FIG. 53, showing an example of a cross-sectional structure in the vicinity of the pad portion PDe in the memory device 1J according to the eleventh embodiment. As shown in FIG. 54, the pad portion PDe has a configuration in which the outer edge of the conductive portion MA is disposed more inward than the outer edge of the insulating portion BA in the pad portion PD described in the first embodiment using FIG. 11. Therefore, the conductive layer 303 corresponding to the conductive portion MA does not have a portion that overlaps with the conductive layers 21, 211, and 213 in the Z direction. The other configurations of the memory device 1J according to the eleventh embodiment are similar to those of the memory device 1 according to the first embodiment.

[0195] <11-2> Manufacturing method The manufacturing method for the memory device 1J according to the 11th embodiment is similar to the manufacturing method for the memory device 1 according to the first embodiment described using Figures 12 to 17, except that the conductive portion MA is positioned more inward than the insulating portion BA in a planar view.

[0196] <11-3> Effects of the 11th embodiment In the memory device 1J according to the 11th embodiment, the area of ​​the portion where the conductive portion MA and the source line SL face each other in the Z direction can be reduced more than in the first embodiment. As a result, the memory device 1J according to the 11th embodiment can reduce the parasitic capacitance of the pad more than in the first embodiment, and can suppress deterioration of the interface speed.

[0197] The idea described in the eleventh embodiment may be combined with the second to tenth embodiments. That is, in each of the second to tenth embodiments, the outer edge of the conductive portion MA may be configured to be located more inward than the outer edge of the insulating portion BA. As a result, the second to tenth embodiments can achieve the same effects as the eleventh embodiment.

[0198] <12> Variations, etc. The memory device 1 described above can be modified in various ways.

[0199] FIG. 55 is a cross-sectional view showing an example of a detailed cross-sectional structure near two opposing bond pads in the memory device 1 according to the first embodiment. FIG. 55 shows a conductive layer 105 (bond pad) formed using a semiconductor substrate W1 (not shown), a conductive layer 25 (bond pad) formed using a semiconductor substrate W2 (not shown), some contacts C2 and V2 connected thereto, and conductive layers 104 and 24. As shown in FIG. 55, the two opposing bond pads may have different tapered shapes based on the etching direction used during their formation. Specifically, the conductive layer 105 formed using the semiconductor substrate W1 has, for example, an inverse tapered shape. The conductive layer 25 formed using the semiconductor substrate W2 has, for example, a tapered shape. Therefore, the cross-sectional shape along the Z direction at the bonded portion of the conductive layer 105 and the conductive layer 25 may not have linear sidewalls but may be non-rectangular. Furthermore, the pair of opposing bond pads may be misaligned during bonding depending on the alignment during the bonding process. Therefore, a step may be formed between the side of the conductive layer 105 and the side of the conductive layer 25. The pair of two bond pads arranged opposite each other may have a boundary or may be integrated. The bond pads and the contacts C2, V2 connected to the bond pads may be formed integrally. A plurality of corresponding contacts C2, V2 may be connected to the bond pads. For example, the conductive layer 105 may be connected to the conductive layer 104 via a plurality of contacts C2. Similarly, the conductive layer 25 may be connected to the conductive layer 24 via a plurality of contacts V2.

[0200] In the above embodiment, the memory device 1 may include a plurality of memory cell arrays 10. When the memory device 1 includes a plurality of memory cell arrays 10, the memory device 1 may have a sense amplifier module 17 and a row decoder module 16 for each memory device 10. In this case, stacked wiring including a plurality of word lines WL is provided for each memory cell array 10. Then, the set of conductor layers 21, 211, and 213 corresponding to the source line SL, or the set of semiconductor layers 214 and 217 and conductor layer 218 corresponding to the source line SL, is separated for each memory cell array 10.

[0201] In the above embodiment, the circuit configuration, planar layout, and cross-sectional structure of the memory device 1 may be modified as appropriate. Other contacts may be inserted between the memory pillar MP and the conductive layer 23. Other contacts may be inserted between the contact C3 and the conductive layer 26. A conductive layer may be inserted at the connection portion between multiple contacts. The number of wiring layers and contacts included in the memory device 1 may be modified as appropriate depending on the circuit design. The memory pillar MP and each contact may have a tapered shape, an inverted tapered shape, or a bowing shape. The XY cross-sectional structure of the memory pillar MP may be circular or elliptical. Each wiring in the stacked wiring may include a metal oxide film around a conductor such as tungsten. Conductor layers alternately stacked with insulator layers in the stacked wiring may be considered to include such a metal oxide film.

[0202] In this specification, "connection" refers to electrical connection and does not exclude, for example, the presence of another element therebetween. "Electrically connected" may also refer to an insulator as long as it operates similarly to an electrically connected element. A "semiconductor substrate" may simply be referred to as a "substrate." A "semiconductor layer" may also be referred to as a "conductor layer." A "region" may be considered a structure contained in a substrate. For example, if a semiconductor substrate W1 is defined to include a storage region SA and a contact region CA, the storage region SA and the contact region CA are respectively associated with different regions above the semiconductor substrate W1. "Height" corresponds, for example, to the distance in the Z direction between the structure to be measured and the semiconductor substrate W1. A structure other than the semiconductor substrate W1 may also be used as the basis for "height." A "top (planar) view" corresponds, for example, to viewing the surface of the semiconductor substrate W1 from the vertical direction of the semiconductor substrate W1. A "via" may also be referred to as an opening.

[0203] Although several embodiments of the present invention have been described, these embodiments are presented as examples and are not intended to limit the scope of the invention. These novel embodiments can be embodied in various other forms, and various omissions, substitutions, and modifications can be made without departing from the spirit of the invention. These embodiments and their modifications are included within the scope and spirit of the invention, and are also included in the inventions and their equivalents as defined in the claims. [Explanation of symbols]

[0204] 1, 1A, 1B, 1C, 1D, 1E, 1F, 1G, 1H, 1I, 1J, 1Y, 1Z... memory device, 2... memory controller, 10... memory cell array, 11... input / output circuit, 12... logic controller, 13... register circuit, 14... sequencer, 15... driver circuit, 16... row decoder module, 17... sense amplifier module, 21 to 26, 24W, 25W, 26W, 103 to 105, 103 W, 104W, 105W, 211, 213, 218, 303, 303A, 303B...conductor layer, 310, 320...conductive member, 31 to 35, 110, 111, 210, 301, 304 to 307, 330...insulating layer, 215...member, 36, 302...insulating member, 40...core member, 41, 214, 217...semiconductor layer, 42...laminated film, 43...tunnel insulating film, 44...insulating film, 45...block insulating film, 100...CMO S layer, 101...gate insulating film, 102...gate electrode, 200...memory layer, 212...sacrificial member, 300...wiring layer, V1, V2, C0 to C3, C1W, C2W, C3W, VBP...contact, ES1, ES2...sealing portion, B1, B2...junction layer, CR...core region, PR...peripheral region, WR...wall region, KR...kerf region, SA...storage region, CA...contact region, AA, AAa...active region, DA, DAa...dummy region, DS...dummy staircase portion, VA, VB, VBa, VC, TV...via, BA...insulating portion, MA, ZB...conductive portion, W1, W2...semiconductor substrate, BLK...block, DBLK...dummy block, SL...source line, BL...bit line, WL...word line, MT...memory cell transistor, ST1, ST2...select transistor, RD...row decoder, SAU...sense amplifier unit, TR1, TR2...transistor

Claims

1. 1. A memory device having a bonding surface, comprising: a substrate having a first region and a second region aligned in a first direction; a first circuit layer disposed between the substrate and the bonding surface and including a CMOS circuit; a second circuit layer provided above the bonding surface; a wiring layer provided above the second circuit layer and including a pad electrically connected to the CMOS circuit via the second circuit layer; the second circuit layer includes: a stacked body including, in the first region, first insulating layers and first conductive layers alternately stacked in a second direction intersecting the first direction, and in the second region, including a first member made of a material different from the first insulating layers and the first conductive layers alternately stacked in the second direction or the first insulating layers and the first insulating layers and the first conductive layers alternately stacked in the second direction; and a plurality of first pillars that penetrate the stacked body in the second direction in the first region and are electrically connected to source lines above the stacked body; the pad has a portion overlapping the stack in the second direction and does not have a portion overlapping the source line in the second direction; Memory device.

2. the laminate has a laminate portion in the second region in which the first insulating layers and the first members are alternately laminated in the second direction, and an end of the laminated first members is provided in a stepped shape. The memory device of claim 1 .

3. the second circuit layer further includes a plurality of second pillars that penetrate the stack in the second direction within the second region; the plurality of first pillars are configured to store data at intersections with the first conductive layer, and the plurality of second pillars are not used to store data; the pad has a portion overlapping the plurality of second pillars in the second direction, the second pillars are electrically insulated from the source line; The memory device of claim 1 .

4. 1. A memory device having a bonding surface, comprising: a first circuit layer disposed between the substrate and the bonding surface, the first circuit layer including a CMOS circuit; a second circuit layer including: a stacked body provided above the first circuit layer via the bonding surface, the stacked body including first insulating layers and first conductive layers alternately stacked in a first direction; and a plurality of pillars each extending in the first direction within the stacked body, the plurality of pillars including a first pillar electrically connected to a source line above the stacked body and configured to store data at an intersection with the first conductive layer, and a second pillar not used for storing data; a second conductive layer provided above the source line in the first direction, including a portion corresponding to a pad, and electrically connected to the CMOS circuit; the second conductive layer has a portion overlapping the second pillar in the first direction, and the portion of the second conductive layer faces the second pillar in the first direction via an insulating member provided at the same height as the source line but without the source line therebetween. Memory device.

5. the pad has a portion overlapping the second pillar in the first direction and does not have a portion overlapping the source line in the first direction; The memory device of claim 4 .

Images