Display device and electronic device including the same

Abstract

To provide a display device capable of reducing power consumption while having high resolution, and an electronic device including the same.SOLUTION: In the display device, each pixel includes a light emitting element, first to fourth transistors, a storage capacitor, and first and second boost capacitors. The first transistor is connected between the light emitting element and a first driving voltage line and operates according to a potential of a first node, and the second transistor is connected to a data line, a first electrode of the first transistor, and a first scan line. The third transistor is connected to the first node, a second electrode of the first transistor, and a second scan line. The storage capacitor is connected between the first node and a first driving voltage line, the first boost capacitor is connected between the first node and a first scan line, and the second boost capacitor is connected between the first node and a second scan line.SELECTED DRAWING: Figure 5

Description

[Technical Field]

[0001] The present invention relates to a display device and an electronic device including the same, and more particularly to a display device having high resolution and an electronic device including the same. [Background technology]

[0002] Among display devices, emissive display devices display images using light-emitting diodes (LEDs), which generate light through the recombination of electrons and holes. These emissive display devices have the advantages of having a fast response speed and being driven with low power consumption.

[0003] An emissive display device includes a display panel on which pixels connected to data lines and scan lines are arranged. A pixel typically includes a light emitting diode (LED) and a pixel circuit for controlling the amount of current flowing through the LED. The pixel circuit controls the amount of current flowing from a first driving voltage to a second driving voltage via the LED in response to a data signal. Light of a predetermined brightness is generated in response to the amount of current flowing through the LED. [Prior art documents] [Patent documents]

[0004] [Patent Document 1] Korean Patent Publication No. 2023-0168631 (KR 10-2023-0168631A) Summary of the Invention [Problem to be solved by the invention]

[0005] SUMMARY OF THE INVENTION An object of the present invention is to provide a display device that has high resolution and can reduce power consumption, and an electronic device including the same. [Means for solving the problem]

[0006] A display device according to one aspect of the present invention includes a display panel including pixels.

[0007] The pixel includes: (1) a light-emitting element; (2) a first transistor connected between the light-emitting element and a first driving voltage line and operating in response to a potential of a first node; (3) a second transistor connected between a data line and a first electrode of the first transistor and receiving a first scan signal through a first scan line; (4) a third transistor connected between the first node and a second electrode of the first transistor and receiving a second scan signal through a second scan line; (5) a fourth transistor connected between the first node and a first initialization voltage line and receiving a third scan signal through a third scan line; (6) a storage capacitor connected between the first node and the first driving voltage line; (7) a first boost capacitor connected between the first node and the first scan line; and (8) a second boost capacitor connected between the first node and the second scan line.

[0008] According to one aspect of the present invention, a display device includes an element layer including a light emitting element, and a circuit layer including a pixel circuit portion connected to the light emitting element.

[0009] The circuit layer includes: (1) a first transistor including a gate electrode connected to a first node, a first electrode connected to a second node, and a second electrode connected to a third node; (2) a second transistor including a gate electrode connected to a first scan line, a first electrode connected to a data line, and a second electrode connected to the second node; (3) a third transistor including a gate electrode connected to a second scan line, a first electrode connected to the third node, and a second electrode connected to the first node; (4) a fourth transistor including a gate electrode connected to a third scan line, a first electrode connected to the first node, and a second electrode connected to a first initialization voltage line; (5) a first capacitor electrode extending from the gate electrode of the first transistor; (6) a second capacitor electrode facing the first capacitor electrode to form a storage capacitor and connected to a first driving voltage line; and (7) an additional gate electrode connected to the gate electrode of the first transistor and overlapping the first scan line to form a first boost capacitor.

[0010] The additional gate electrode is disposed on a layer different from the gate electrode of the first transistor, the second capacitor electrode, and the first scan line.

[0011] According to one aspect of the present invention, an electronic device includes a display panel including pixels, a panel driver for driving the display panel, and a main processor for providing image signals to the panel driver.

[0012] The pixel includes: (1) a light-emitting element; (2) a first transistor connected between the light-emitting element and a first driving voltage line and operating in response to a potential of a first node; (3) a second transistor connected between a data line and a first electrode of the first transistor and receiving a first scan signal through a first scan line; (4) a third transistor connected between the first node and a second electrode of the first transistor and receiving a second scan signal through a second scan line; (5) a fourth transistor connected between the first node and a first initialization voltage line and receiving a third scan signal through a third scan line; (6) a storage capacitor connected between the first node and the first driving voltage line; (7) a first boost capacitor connected between the first node and the first scan line; and (8) a second boost capacitor connected between the first node and the second scan line. [Effects of the Invention]

[0013] According to the present invention, by providing the first and second boost capacitors in the pixel circuit unit, the potential of the first node can be increased to the target voltage during a given data write period through a boosting operation without supplying a data voltage higher than the black data voltage (i.e., the target voltage) to the pixel circuit unit.

[0014] Therefore, it is not necessary to apply a data voltage higher than the target voltage to the pixel circuit unit in order to express the black gradation, and as a result, the power consumption of the display device can be reduced. [Brief explanation of the drawings]

[0015] [Figure 1] 1 is a perspective view of a display device according to an embodiment of the present invention; [Figure 2] 1 is an exploded perspective view of a display device according to an embodiment of the present invention; [Figure 3] 1 is a block diagram of a display device according to an embodiment of the present invention; [Figure 4A]FIG. 1 is a plan view (1) showing the arrangement of light-emitting element units according to an embodiment of the present invention. [Figure 4B] FIG. 2 is a plan view (2) showing the arrangement of the light-emitting element units according to the embodiment of the present invention. [Figure 4C] FIG. 3 is a plan view (3) showing the arrangement of the light-emitting element units according to the embodiment of the present invention. [Figure 4D] FIG. 4 is a plan view (4) showing the arrangement of the light-emitting element units according to the embodiment of the present invention. [Figure 5] FIG. 2 is a circuit diagram of a pixel according to an embodiment of the present invention. [Figure 6A] FIG. 1 is a timing diagram (1) illustrating the operation of a pixel according to an embodiment of the present invention. [Figure 6B] FIG. 10 is a timing diagram (2) illustrating the operation of a pixel according to an embodiment of the present invention. [Figure 7] 2 is a cross-sectional view of a portion of a display panel according to an embodiment of the present invention; [Figure 8] 1 is a plan view showing a portion of a display panel according to an embodiment of the present invention; [Figure 9A] FIG. 1 is a plan view (1) showing the layout of layers stacked on a display panel. [Figure 9B] FIG. 2 is a plan view (2) showing the layout of layers stacked on the display panel. [Figure 9C] FIG. 3 is a plan view (3) showing the layout of layers stacked on the display panel. [Figure 9D] FIG. 4 is a plan view (4) showing the layout of layers stacked on the display panel. [Figure 9E] FIG. 5 is a plan view (5) showing the layout of layers stacked on the display panel. [Figure 9F] FIG. 6 is a plan view (6) showing the layout of layers stacked on the display panel. [Figure 9G] FIG. 7 is a plan view (7) showing the layout of layers stacked on the display panel. [Figure 10] 1 is a block diagram of an electronic device according to one embodiment of the present invention. DETAILED DESCRIPTION OF THE INVENTION

[0016] In this specification, when a certain component (or region, layer, section, etc.) is described as being "on," "coupled," or "bonded" to another component, it means that it may be directly disposed / coupled / bonded to the other component, or that a third component may be disposed therebetween.

[0017] The same reference numerals refer to the same elements. Also, in the drawings, thickness, ratio, and dimensions of elements are exaggerated for efficient explanation of technical content. "And / or" includes all one or more combinations that the associated elements can define.

[0018] Terms such as "first," "second," etc. may be used to describe various components, but the components should not be limited by these terms. These terms are used only to distinguish one component from another. For example, a first component may be referred to as a "second component," and similarly, a second component may be referred to as a "first component" without departing from the scope of the present invention. A singular expression includes a plural expression unless the context clearly dictates otherwise.

[0019] Furthermore, terms such as "under," "below," "on," and "above" are used to describe the relationship between components shown in the drawings. These terms are relative concepts and are described based on the directions shown in the drawings.

[0020] It should be understood that the use of terms such as "comprise" or "have" is intended to specify the presence of a stated feature, number, step, operation, component, part, or combination thereof, but does not preclude the possible presence or addition of one or more other features, numbers, steps, operations, components, parts, or combinations thereof.

[0021] Unless otherwise defined, all terms (including technical and scientific terms) used herein have the same meaning as commonly understood by those skilled in the art to which the present invention belongs. Furthermore, terms such as those defined in commonly used dictionaries should be interpreted as having a meaning consistent with the meaning they have in the context of the relevant art, and should not be interpreted as being overly ideal or overly formal unless explicitly defined herein.

[0022] Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings.

[0023] FIG. 1 is a perspective view of a display device according to an embodiment of the present invention, and FIG. 2 is an exploded perspective view of the display device according to an embodiment of the present invention.

[0024] 1 and 2, the display device DD may be a device activated in response to an electrical signal. The display device DD according to the present invention may be a large display device such as a television or monitor, or a small or medium-sized display device such as a mobile phone, tablet, laptop, car navigation system, or game console. These examples are merely exemplary, and the display device DD may be embodied in other forms without departing from the concept of the present invention. The display device DD has a rectangular shape with long sides extending in a first direction DR1 and short sides extending in a second direction DR2 intersecting the first direction DR1. However, the shape of the display device DD is not limited thereto, and various shapes of display device DD may be provided. The display device DD may display an image IM on a display surface IS parallel to each of the first direction DR1 and the second direction DR2, toward a third direction DR3. The display surface IS on which the image IM is displayed may correspond to the front surface of the display device DD.

[0025] In this embodiment, the front surface (or upper surface) and the back surface (or lower surface) of each component are defined based on the direction in which the image IM is displayed. The front surface and the back surface are opposed to each other in a third direction DR3, and the normal directions of the front surface and the back surface may be parallel to the third direction DR3.

[0026] The distance between the front and rear surfaces in the third direction DR3 may correspond to the thickness of the display device DD in the third direction DR3. Meanwhile, the directions indicated by the first to third directions DR1, DR2, and DR3 are relative concepts and may be converted to other directions.

[0027] The display device DD can sense an external input applied from the outside. The external input can include various types of input provided from outside the display device DD. A display device DD according to an embodiment of the present invention can sense a user's external input applied from the outside. The user's external input can be any one or a combination of various types of external input, such as a part of the user's body, light, heat, gaze, or pressure. In addition, the display device DD can sense a user's external input applied to the side or back of the display device DD depending on the structure of the display device DD, and is not limited to any one embodiment. In one example of the present invention, the external input can include an input using an input device (e.g., a stylus pen, an active pen, a touch pen, an electronic pen, an e-pen, etc.).

[0028] The display surface IS of the display device DD may be divided into a display area DA and a non-display area NDA. The display area DA may be an area where an image IM is displayed. A user views the image IM through the display area DA. In this embodiment, the display area DA is illustrated as a rectangle with rounded vertices (corners). However, this is merely an example, and the display area DA may have various shapes and is not limited to any one embodiment.

[0029] The non-display area NDA is adjacent to the display area DA. The non-display area NDA may have a predetermined color. The non-display area NDA may surround the display area DA. Therefore, the shape of the display area DA may be substantially defined by the non-display area NDA. However, this is shown as an example, and the non-display area NDA may be disposed adjacent to only one side of the display area DA or may be omitted. A display device DD according to an embodiment of the present invention may include various embodiments and is not limited to any one embodiment.

[0030] 2, the display device DD may include a display module DM and a window WM disposed on the display module DM. The display module DM may include a display panel DP and an input sensing layer ISP.

[0031] The display panel DP according to an embodiment of the present invention may be an emissive display panel. For example, the display panel DP may be an organic light-emitting display panel, an inorganic light-emitting display panel, or a quantum dot light-emitting display panel. The light-emitting layer of the organic light-emitting display panel may include an organic light-emitting material. The light-emitting layer of the inorganic light-emitting display panel may include an organic light-emitting material. The light-emitting layer of the quantum dot light-emitting display panel may include quantum dots, quantum rods, etc.

[0032] The display panel DP outputs an image IM, which can be displayed on a display surface IS.

[0033] The input sensing layer ISP is disposed on the display panel DP to sense an external input. The input sensing layer ISP can be disposed directly on the display panel DP. According to an embodiment of the present invention, the input sensing layer ISP can be formed on the display panel DP through a continuous process. That is, when the input sensing layer ISP is disposed directly on the display panel DP, an inner adhesive film (not shown) is not disposed between the input sensing layer ISP and the display panel DP. However, an inner adhesive film can be disposed between the input sensing layer ISP and the display panel DP. In this case, the input sensing layer ISP is not manufactured through a continuous process with the display panel DP, but is manufactured through a process separate from the display panel DP and then fixed to the upper surface of the display panel DP by the inner adhesive film.

[0034] The window WM may be made of a transparent material capable of emitting the image IM, such as glass, sapphire, plastic, etc. Although the window WM is illustrated as a single layer, it is not limited thereto and may include multiple layers.

[0035] Meanwhile, although not shown, the non-display area NDA of the display device DD described above may be provided as an area of ​​the window WM on which a material containing a predetermined color is printed. In one example of the present invention, the window WM may include a light-blocking pattern for defining the non-display area NDA. The light-blocking pattern may be formed as a colored organic film, for example, by a coating method.

[0036] The window WM may be coupled to the display module DM through an adhesive film. In one embodiment of the present invention, the adhesive film may include an optically clear adhesive film (OCA). However, the adhesive film is not limited thereto and may include a conventional adhesive or pressure-sensitive adhesive. For example, the adhesive film may include an optically clear resin (OCR) or a pressure-sensitive adhesive film (PSA).

[0037] An anti-reflection layer may be further disposed between the window WM and the display module DM. The anti-reflection layer reduces the reflectance of external light incident from above the window WM. The anti-reflection layer according to an embodiment of the present invention may include a phase retarder and a polarizer. The phase retarder may be a film type or a liquid crystal coating type and may include a λ / 2 phase retarder and / or a λ / 4 phase retarder. The polarizer may also be a film type or a liquid crystal coating type. The film type may include a stretched synthetic resin film, and the liquid crystal coating type may include liquid crystals aligned in a predetermined array. The phase retarder and the polarizer may be implemented as a single polarizing film.

[0038] In one embodiment of the present invention, the anti-reflection layer may include color filters. The arrangement of the color filters may be determined taking into consideration the color of light generated by the pixels PX (see FIG. 3) included in the display panel DP. In this case, the anti-reflection layer may further include a light-blocking pattern disposed between the color filters.

[0039] The display module DM displays an image IM in response to an electrical signal and can transmit / receive information in response to an external input. The display module DM may be divided (defined) into an active area AA and a non-active area NAA. The active area AA may be defined as an area where the image IM is output from the display panel DP (i.e., an area where the image IM is displayed). The active area AA may also be defined as an area where the input sensing layer ISP senses an external input applied from the outside. According to an embodiment, the active area AA of the display module DM may correspond to (or overlap with) at least a portion of the display area DA.

[0040] The non-active area NAA is adjacent to the active area AA. The non-active area NAA may be an area where the image IM is not substantially displayed. For example, the non-active area NAA may surround the active area AA. However, this is shown by way of example only, and the non-active area NAA may be defined in various shapes and is not limited to any one embodiment. According to one embodiment, the non-active area NAA of the display module DM may correspond to (or overlap with) at least a portion of the non-display area NDA.

[0041] The display device DD may further include a plurality of flexible films FF connected to the display panel DP. A driver chip DIC may be mounted on each of the flexible films FF. In one example of the present invention, the data driver 200 (see FIG. 3) may include a plurality of driver chips DIC, and the plurality of driver chips DIC may be mounted on the plurality of flexible films FF, respectively.

[0042] The display device DD may further include at least one circuit board PCB coupled to the plurality of flexible films FF. In one example of the present invention, two circuit boards PCBs are provided in the display device DD, but the number of circuit boards PCBs is not limited to this. Two adjacent circuit boards among the circuit boards PCBs may be electrically connected to each other by a connecting film CF. At least one of the circuit boards PCBs may be electrically connected to the main board. A drive controller 100 (see FIG. 3) and a voltage generator 400 (see FIG. 3) may be disposed on at least one of the circuit boards PCBs.

[0043] 2 illustrates a structure in which the driver chips DIC are mounted on the flexible film FF, but the present invention is not limited to this. For example, the driver chips DIC may be mounted directly on the display panel DP. In this case, the portion of the display panel DP on which the driver chips DIC are mounted may be bent and disposed on the rear surface of the display module DM.

[0044] The input sensing layer ISP may be electrically connected to the circuit board PCB through a flexible film FF. However, embodiments of the present invention are not limited thereto. That is, the display module DM may additionally include another flexible film for electrically connecting the input sensing layer ISP to the circuit board PCB.

[0045] The display device DD further includes a housing EDC that houses the display module DM. The housing EDC can be combined with the window WM to define the appearance of the display device DD. The housing EDC protects the components housed in the housing EDC by absorbing external impacts and preventing foreign substances / moisture from penetrating into the display module DM. Meanwhile, in one example of the present invention, the housing EDC may be provided in a form in which a plurality of housing members are combined.

[0046] According to one embodiment, the display device DD may further include an electronic module including various functional modules for operating the display module DM, a power supply module (e.g., a battery) that supplies the power required for the overall operation of the display device DD, a bracket that is coupled to the display module DM and / or the housing EDC to divide the internal space of the display device DD, etc.

[0047] FIG. 3 is a block diagram of a display device according to an embodiment of the present invention.

[0048] 3, the display device DD may be a device that is activated in response to an electrical signal to display an image. The display device DD may be applied to electronic devices such as smart watches, tablets, laptops, computers, and smart TVs.

[0049] The display device DD includes a display panel DP and a panel driver PDD for driving the display panel DP. In one example of the present invention, the panel driver PDD may include a drive controller 100, a data driver 200, a scan driver 300, a light emitting driver 350, and a voltage generator 400.

[0050] The drive controller 100 receives the image signal RGB and the control signal CTRL. The drive controller 100 generates image data DATA by converting the data format of the image signal RGB to conform to the interface specifications with the data driver 200. The drive controller 100 outputs a scan control signal SCS, a data control signal DCS, and a light emission drive control signal ECS.

[0051] The data driver 200 receives a data control signal DCS and image data DATA from the drive controller 100. The data driver 200 converts the image data DATA into a data signal and outputs the data signal to a plurality of data lines DL1 to DLm (described later). The data signal is an analog data voltage corresponding to the grayscale value of the image data DATA.

[0052] The voltage generator 400 generates voltages required for the operation of the display panel DP. As an example of the present invention, the voltage generator 400 generates a first driving voltage ELVDD, a second driving voltage ELVSS, a first initialization voltage Vint, and a second initialization voltage Vaint. The first initialization voltage Vint may have a different voltage level from the second initialization voltage Vaint. The voltage generator 400 generates voltages required for the operation of the display panel DP. As an example of the present invention, the voltage generator 400 may further generate a bias voltage Vbias to be supplied to the display panel DP.

[0053] The scan driver 300 receives a scan control signal SCS from the drive controller 100. The scan control signal SCS may include a start signal for starting the operation of the scan driver 300 and a plurality of clock signals. The scan driver 300 generates a plurality of scan signals and sequentially outputs the plurality of scan signals to scan lines described below. The light emitting driver 350 may output light emitting control signals to light emitting control lines EML1 to EMLn described below in response to the light emitting drive control signal ECS from the drive controller 100. In one embodiment, the scan driver 300 and the light emitting driver 350 may be integrated into a single circuit.

[0054] The scan driver 300 outputs initialization scan signals to the initialization scan lines GIL1 to GILn of the display panel DP, outputs compensation scan signals to the compensation scan lines GCL1 to GCLn of the display panel DP, outputs write scan signals to the write scan lines GWL1 to GWLn of the display panel DP, and outputs black scan signals to the black scan lines GBL1 to GBLn of the display panel DP.

[0055] The display panel DP includes initialization scan lines GIL1 to GILn, compensation scan lines GCL1 to GCLn, write scan lines GWL1 to GWLn, black scan lines GBL1 to GBLn, emission control lines EML1 to EMLn, data lines DL1 to DLm, and pixels PX. A display area DA and a non-display area NDA are defined in the display panel DP. The initialization scan lines GIL1 to GILn, compensation scan lines GCL1 to GCLn, write scan lines GWL1 to GWLn, black scan lines GBL1 to GBLn, emission control lines EML1 to EMLn, data lines DL1 to DLm, and pixels PX may be arranged in the display area DA. The initialization scan lines GIL1 to GILn, the compensation scan lines GCL1 to GCLn, the write scan lines GWL1 to GWLn, the black scan lines GBL1 to GBLn, and the emission control lines EML1 to EMLn extend in a first direction DR1 and are spaced apart in a second direction DR2. The data lines DL1 to DLm extend in the second direction DR2 and are spaced apart in the first direction DR1.

[0056] The scan driver 300 and the emission driver 350 may be disposed in the non-display area NDA of the display panel DP. In one example of the present invention, the scan driver 300 is disposed adjacent to a first side of the display area DA, and the emission driver 350 is disposed adjacent to a second side of the display area DA opposite the first side. In the example shown in FIG. 3, the scan driver 300 and the emission driver 350 are disposed on both sides of the display area DA, respectively, but the present invention is not limited thereto. For example, the scan driver 300 and the emission driver 350 may be disposed adjacent to one of the first and second sides of the display panel DP.

[0057] The pixels PX are electrically connected to the initialization scan lines GIL1 through GILn, the compensation scan lines GCL1 through GCLn, the write scan lines GWL1 through GWLn, the black scan lines GBL1 through GBLn, the emission control lines EML1 through EMLn, and the data lines DL1 through DLm, respectively. Each of the pixels PX may be electrically connected to four scan lines and one emission control line. For example, as shown in FIG. 3, the pixels in a first row may be connected to the first initialization scan line GIL1, the first compensation scan line GCL1, the first write scan line GWL1, the first black scan line GBL1, and the first emission control line EML1. The pixels in a second row may be connected to the second initialization scan line GIL2, the second compensation scan line GCL2, the second write scan line GWL2, the second black scan line GBL2, and the second emission control line EML2. However, the number of scan lines and the number of light emission control lines connected to each pixel PX are not limited to this and may be changed.

[0058] Each of the plurality of pixels PX includes a light emitting element ED (see FIG. 5) and a pixel circuit unit PXC (see FIG. 5) that controls the emission of the light emitting element ED. The pixel circuit unit PXC may include one or more transistors and one or more capacitors. The scan driver 300 and the emission driver 350 may be directly formed in the non-display area NDA of the display panel DP through the same process as the transistors of the pixel circuit unit PXC.

[0059] Each of the plurality of pixels PX receives a first driving voltage ELVDD, a second driving voltage ELVSS, and first and second initialization voltages Vint and Vaint from the voltage generator 400. Alternatively, each of the plurality of pixels PX may further receive a bias voltage Vbias from the voltage generator 400.

[0060] 4A to 4D are plan views showing the arrangement of light-emitting element units according to an embodiment of the present invention, each showing one light-emitting element unit EDU.

[0061] 4A, the light-emitting element unit EDU may include three light-emitting elements (hereinafter referred to as first to third light-emitting elements ED_R, ED_G, and ED_B). The first light-emitting element ED_R generates a first light (e.g., red light), the second light-emitting element ED_G generates a second light (e.g., green light), and the third light-emitting element ED_B generates a third light (e.g., blue light). In one example of the present invention, the first light-emitting element ED_R is included in a first pixel (or red pixel) among the plurality of pixels PX, the second light-emitting element ED_G is included in a second pixel (or green pixel) among the plurality of pixels PX, and the third light-emitting element ED_B is included in a third pixel (or blue pixel) among the plurality of pixels PX.

[0062] Within the light-emitting element unit EDU, the first light-emitting element ED_R and the second light-emitting element ED_G are arranged along the second direction DR2, and the third light-emitting element ED_B is disposed adjacent to each of the first light-emitting element ED_R and the second light-emitting element ED_G in the first direction DR1. In this embodiment, the third light-emitting element ED_B is illustrated with a size that overlaps each of the first light-emitting element ED_R and the second light-emitting element ED_G when viewed in the first direction DR1. Alternatively, the third light-emitting element ED_B may include a first sub-light-emitting element adjacent to the first light-emitting element ED_R and a second sub-light-emitting element adjacent to the second light-emitting element ED_G. The first and second sub-light-emitting elements may share one anode electrode.

[0063] Meanwhile, the shapes and arrangements of the first to third light emitting elements ED_R, ED_G, and ED_B, or the number of light emitting elements constituting the light emitting element unit EDU may be selected in various ways and are not limited to any one embodiment.

[0064] The arrangement order of the first to third light emitting elements ED_R, ED_G, and ED_B may be variously combined depending on the required display quality characteristics, and the areas of the first to third light emitting elements ED_R, ED_G, and ED_B are not limited to those shown in FIG.

[0065] As shown in FIG. 4B, the light-emitting device unit EDU1 may include four light-emitting devices (hereinafter referred to as first and second sub-light-emitting devices ED_R1 and ED_R2, and second and third light-emitting devices ED_G and ED_B). The first and second sub-light-emitting devices ED_R1 and ED_R2 may generate a first light (e.g., red light). The first and second sub-light-emitting devices ED_R1 and ED_R2 may be included in a first pixel (or red pixel), the second light-emitting device ED_G may be included in a second pixel (or green pixel), and the third light-emitting device ED_B may be included in a third pixel (or blue pixel). The first and second sub-light-emitting devices ED_R1 and ED_R2 may share one anode electrode.

[0066] The first and second sub-light-emitting elements ED_R1 and ED_G may be adjacent to each other in the first direction DR2, and the second sub-light-emitting elements ED_R2 and ED_G may be adjacent to each other in the second direction DR2. The first and third sub-light-emitting elements ED_R1 and ED_B may be adjacent to each other in the second direction DR2, and the second and third sub-light-emitting elements ED_R2 and ED_B may be adjacent to each other in the first direction DR1.

[0067] In one embodiment of the present invention, the third light-emitting element ED_B may have the same shape as the second light-emitting element ED_G and may be larger in size than the second light-emitting element ED_G. The first and second sub-light-emitting elements ED_R1 and ED_R2 may have the same size and shape as each other. Furthermore, the first and second sub-light-emitting elements ED_R1 and ED_R2 may have a different shape from the second and third light-emitting elements ED_G and ED_B, but the present invention is not limited thereto.

[0068] 4C, the light emitting device unit EDU2 may have a stripe pixel structure in which the first to third light emitting devices ED_R, ED_G, and ED_B are arranged in order in the first direction DR1. Here, the areas of the first to third light emitting devices ED_R, ED_G, and ED_B may be the same, but the embodiment is not limited thereto.

[0069] 4D, the light-emitting element unit EDU3 may have the first to fourth light-emitting elements ED_R, ED_G1, ED_B, and ED_G2 arranged in a PENTILE™ configuration. Specifically, the second and fourth light-emitting elements ED_G1 and ED_G2 may emit green light. The first light-emitting element ED_R may be included in the first pixel (or red pixel), the second light-emitting element ED_G1 may be included in the second pixel (or first green pixel), the third light-emitting element ED_B may be included in the third pixel (or blue pixel), and the fourth light-emitting element ED_G2 may be included in the fourth pixel (or second green pixel).

[0070] Each of the first to fourth light emitting elements ED_R, ED_G1, ED_B, and ED_G2 may have a diamond shape, and the areas of the second and fourth light emitting elements ED_G1 and ED_G2 may be smaller than those of the first and third light emitting elements ED_R and ED_B, but the embodiment is not limited thereto.

[0071] 5 is a circuit diagram of a pixel according to an embodiment of the present invention, and FIGS. 6A and 6B are timing diagrams illustrating the operation of a pixel according to an embodiment of the present invention. Each of the pixels PX illustrated in FIG. 3 may have the same configuration. Therefore, in FIG. 5, the configuration of one pixel PXij among the series of pixels PX will be described, and the configurations of the remaining pixels will not be described.

[0072] 5, pixel PXij is connected to the j-th initialization scan line GILj among the series of initialization scan lines GIL1 to GILn, the j-th compensation scan line GCLj among the series of compensation scan lines GCL1 to GCLn, the j-th write scan line GWLj among the series of write scan lines GWL1 to GWLn, and the j-th black scan line GBLj among the series of black scan lines GBL1 to GBLn shown in Fig. 3. Also, pixel PXij is connected to the ith data line DLi among the data lines DL1 to DLm shown in Fig. 3, and to the j-th emission control line EMLj among the emission control lines EML1 to EMLn.

[0073] 5, a pixel PXij according to an embodiment includes a pixel circuit unit PXC and a light emitting element ED. In one example of the present invention, the pixel circuit unit PXC includes eight transistors and five capacitors. Hereinafter, the eight transistors will be referred to as first to eighth transistors T1, T2, T3, T4, T5, T6, T7, and T8, respectively, and the five capacitors will be referred to as a storage capacitor Cst, first and second boost capacitors Cbst1 and Cbst2, and first and second node capacitors Cn1 and Cn2.

[0074] In this embodiment, each of the first to eighth transistors T1 to T8 is a P-type transistor having an LTPS (low-temperature polycrystalline silicon) semiconductor layer. Alternatively, each of the first to eighth transistors T1 to T8 may be an N-type transistor. Also, at least one of the first to eighth transistors T1 to T8 may be an N-type transistor and the rest may be P-type transistors. Alternatively, at least one of the first to eighth transistors T1 to T8 may be a transistor having an oxide semiconductor layer. For example, some of the first to eighth transistors T1 to T8 may be oxide semiconductor transistors and the rest may be LTPS transistors.

[0075] The circuit configuration of the pixel PXij according to the present invention is not limited to the circuit configuration shown in Fig. 5. The pixel PXij shown in Fig. 5 is merely an example, and the circuit configuration of the pixel PXij may be modified and implemented. As an example of the present invention, one of the first to eighth transistors T1 to T8 (e.g., the eighth transistor T8) may be deleted from the pixel circuit unit PXC. Alternatively, the pixel circuit unit PXC may further include one or more additional transistors in addition to the eight transistors T1 to T8.

[0076] The jth write scan line GWLj (or referred to as the first scan line) supplies the jth write scan signal GWj (or referred to as the first scan signal) to the pixel PXij, the jth compensation scan line GCLj (or referred to as the second scan line) supplies the jth compensation scan signal GCj (or referred to as the second scan signal) to the pixel PXij, the jth initialization scan line GILj (or referred to as the third scan line) supplies the jth initialization scan signal GIj (or referred to as the third scan signal) to the pixel PXij, and the jth black scan line GBLj (or referred to as the fourth scan line) supplies the jth black scan signal GBj (or referred to as the fourth scan signal) to the pixel PXij. The j-th light emitting control line EMLj supplies the j-th light emitting control signal EMj to the pixel PXij, and the i-th data line DLi transmits the i-th data voltage Vdata to the pixel PXij. The i-th data voltage Vdata may have a voltage level corresponding to the image data DATA input to the display device DD (see FIG. 3).

[0077] The pixel PXij may be connected to a first driving voltage line VL1, a second driving voltage line VL2, a first initialization voltage line VIL, a second initialization voltage line VAIL, and a bias voltage line VBL.

[0078] 3 to the pixel PXij, and the second driving voltage line VL2 to the pixel PXij. The first initialization voltage line VIL and the second initialization voltage line VAIL receive the first initialization voltage Vint and the second initialization voltage Vaint, respectively, from the voltage generator 400 and transmit them to the pixel PXij. The bias voltage line VBL receives the bias voltage Vbias from the voltage generator 400 and transmits it to the pixel PXij.

[0079] Each of the first to eighth transistors T1 to T8 may include an input electrode (or source electrode), an output electrode (or drain electrode), and a control electrode (or gate electrode). For convenience in this specification, the input electrode, the output electrode, and the control electrode may be referred to as a first electrode, a second electrode, and a third electrode, respectively.

[0080] The first transistor T1 (also referred to as a driving transistor) may be provided between a first driving voltage line VL1 and the light emitting element ED. Specifically, the first transistor T1 includes a gate electrode (or a third electrode) connected to a first node N1, a first electrode electrically connected to the first driving voltage line VL1, and a second electrode electrically connected to a third node N3. The first transistor T1 may operate according to the potential of the first node N1. The first transistor T1 may receive a first driving voltage ELVDD through the first driving voltage line VL1. A first electrode of the first transistor T1 may be connected to the first driving voltage line VL1 via a fifth transistor T5, and a second electrode of the first transistor T1 may be electrically connected to the anode of the light emitting element ED via a sixth transistor T6.

[0081] The second transistor T2 (also referred to as a switching transistor) may be connected between the ith data line DLi and a second node N2. Specifically, the second transistor T2 includes a gate electrode receiving a jth write scan signal GWj through a jth write scan line GWLj, a first electrode connected to the ith data line DLi, and a second electrode connected to a second node N2. During a data write period AP3 (see FIG. 6A), the second transistor T2 is turned on in response to the jth write scan signal GWj provided to the jth write scan line GWLj. The turned-on second transistor T2 electrically connects the ith data line DLi to the second node N2, and the ith data voltage Vdata applied to the ith data line DLi may be applied to the second node N2 through the turned-on second transistor T2.

[0082] The storage capacitor Cst is connected between the first node N1 and the first driving voltage line VL1, and includes a first capacitor electrode electrically connected to the first node N1 and a second capacitor electrode electrically connected to the first driving voltage line VL1.

[0083] The first boost capacitor Cbst1 is connected between the first node N1 and the j-th write scan line GWLj, and is provided in a region where the additional gate electrode T1_gate (see FIG. 7) electrically connected to the first node N1 and the j-th write scan line GWLj overlap.

[0084] The third transistor T3 (also referred to as a compensation transistor) is connected between the second electrode of the first transistor T1 and the third electrode of the first transistor T1. In one embodiment of the present invention, the third transistor T3 includes a first sub-transistor T3-1 and a second sub-transistor T3-2 connected in series between the first and third nodes N1 and N3. The first sub-transistor T3-1 is connected between the first node N1 and the first junction node GN1, and the second sub-transistor T3-2 is connected between the first junction node GN1 and the third node N3.

[0085] The second sub-transistor T3-2 includes a first electrode connected to the third node N3, a second electrode connected to the first junction node GN1, and a third electrode receiving the j-th compensation scan signal GCj through the j-th compensation scan line GCLj. The first sub-transistor T3-1 includes a first electrode connected to the first junction node GN1, a second electrode connected to the first node N1, and a third electrode receiving the j-th compensation scan signal GCj through the j-th compensation scan line GCLj. The first transistor T1 may be diode-connected by the first and second sub-transistors T3-1 and T3-2 being turned on during the compensation period AP2.

[0086] The first node capacitor Cn1 is connected between the first coupling node GN1 and the first driving voltage line VL1, and includes a first node capacitor electrode electrically connected to the first coupling node GN1 and a second node capacitor electrode electrically connected to the first driving voltage line VL1.

[0087] 5, the third transistor T3 includes two sub-transistors, but the present invention is not limited to this. For example, the third transistor T3 may be configured as a single transistor, or alternatively, may include three or more sub-transistors.

[0088] The second boost capacitor Cbst2 is connected between the first node N1 and the j-th compensation scan line GCLj, and is provided in a region where the additional gate electrode T1_gate (see FIG. 7) electrically connected to the first node N1 and the j-th compensation scan line GCLj overlap.

[0089] The fourth transistor T4 (also referred to as the first initialization transistor) is electrically connected between the first node N1 and the first initialization voltage line VIL. In one embodiment of the present invention, the fourth transistor T4 includes a third sub-transistor T4-1 and a fourth sub-transistor T4-2 connected in series between the first node N1 and the first initialization voltage line VIL. The third sub-transistor T4-1 is connected between the first node N1 and the second junction node GN2, and the fourth sub-transistor T4-2 is connected between the second junction node GN2 and the first initialization voltage line VIL.

[0090] The third sub-transistor T4-1 includes a first electrode electrically connected to the first node N1, a second electrode electrically connected to the second connection node GN2, and a third electrode receiving the jth initialization scan signal GIj through the jth initialization scan line GILj. The fourth sub-transistor T4-2 includes a first electrode electrically connected to the second connection node GN2, a second electrode electrically connected to the first initialization voltage line VIL, and a third electrode receiving the jth initialization scan signal GIj through the jth initialization scan line GILj.

[0091] A first initialization voltage Vint may be applied to the first initialization voltage line VIL. During an initialization period AP1 (see FIG. 6A), the third and fourth sub-transistors T4-1 and T4-2 are turned on in response to a j-th initialization scan signal GIj provided to the j-th initialization scan line GILj. Due to the third and fourth sub-transistors T4-1 and T4-2 being turned on during the initialization period AP1, the first node N1 may be initialized to the first initialization voltage Vint.

[0092] The second node capacitor Cn2 is connected between the second connection node GN2 and the first initialization voltage line VIL, and includes a third node capacitor electrode electrically connected to the second connection node GN2 and a fourth node capacitor electrode electrically connected to the first initialization voltage line VIL.

[0093] 5 exemplarily illustrates a structure in which the fourth transistor T4 includes two sub-transistors, but the present invention is not limited thereto. For example, the fourth transistor T4 may be configured as a single transistor, or alternatively, may include three or more sub-transistors.

[0094] In one example of the present invention, each of the third and fourth transistors T3 and T4 may have a structure including multiple sub-transistors connected in series (e.g., referred to as a dual transistor structure). When the third and fourth transistors T3 and T4 have a dual transistor structure, leakage current during turn-off can be reduced. Alternatively, at least one of the first to eighth transistors T1 to T8 may have a dual gate structure including two gate electrodes.

[0095] In this way, by additionally forming first and second node capacitors Cn1 and Cn2 at the first and second junction nodes GN1 and GN2, respectively, of the third and fourth transistors T3 and T4 having a dual transistor structure, the leakage current blocking effect of the third and fourth transistors T3 and T4 can be further improved.

[0096] 5, the pixel circuit unit PXC includes two node capacitors Cn1 and Cn2, but the present invention is not limited to this. For example, one of the first and second node capacitors Cn1 and Cn2 may be omitted from the pixel circuit unit PXC.

[0097] The fifth transistor T5 may be electrically connected between the second node N2 and the first driving voltage line VL1, and includes a gate electrode receiving a j-th light emitting control signal EMj through a j-th light emitting control line EMLj, a first electrode connected to the first driving voltage line VL1, and a second electrode electrically connected to the second node N2.

[0098] The sixth transistor T6 may be electrically connected between the third node N3 and the light emitting element ED, and includes a gate electrode receiving a j-th light emitting control signal EMj through a j-th light emitting control line EMLj, a first electrode connected to the third node N3, and a second electrode electrically connected to the anode of the light emitting element ED.

[0099] In one example of the present invention, the gate electrodes of the fifth and sixth transistors T5 and T6 are commonly connected to the j-th light-emitting control line EMLj, but the present invention is not limited thereto. That is, the gate electrode of the fifth transistor T5 and the gate electrode of the sixth transistor T6 may be connected to different light-emitting control lines and receive different light-emitting control signals.

[0100] During the non-light-emitting period NEP (see FIG. 6A), the fifth and sixth transistors T5 and T6 are turned off by the jth light-emitting control signal EMj in a high state, and during the light-emitting period, the fifth and sixth transistors T5 and T6 are turned on by the jth light-emitting control signal EMj in a low state.

[0101] The light emitting element ED may be electrically connected between the sixth transistor T6 and the second driving voltage line VL2. The anode of the light emitting element ED is connected to the second electrode of the sixth transistor T6, and the cathode of the light emitting element ED is connected to the second driving voltage line VL2. A second driving voltage ELVSS may be applied to the second driving voltage line VL2. The second driving voltage ELVSS has a lower level than the first driving voltage ELVDD. Therefore, the light emitting element ED may emit light in response to a voltage corresponding to the difference between the signal transmitted through the sixth transistor T6 and the second driving voltage ELVSS during the light emitting period.

[0102] The seventh transistor T7 (also referred to as a second initialization transistor) is connected between the second initialization voltage line VAIL and the anode of the light-emitting element ED. The seventh transistor T7 includes a gate electrode that receives a jth black scan signal GBj (also referred to as an initialization control signal) through the jth black scan line GBLj, a first electrode connected to the anode of the light-emitting element ED, and a second electrode connected to the second initialization voltage line VAIL. A second initialization voltage Vaint may be applied to the second initialization voltage line VAIL. In one embodiment, the second initialization voltage Vaint has a voltage level different from the first initialization voltage Vint. The seventh transistor T7 is turned on in response to the jth black scan signal GBj provided to the jth black scan line GBLj. The turned-on seventh transistor T7 may initialize the anode of the light-emitting element ED with the second initialization voltage Vaint. Alternatively, the gate electrode of the seventh transistor T7 may be coupled to the j+1th write scan line to receive the j+1th write scan signal as the jth black scan signal GBj.

[0103] The eighth transistor (also referred to as a bias transistor) T8 may be electrically connected between the first transistor T1 and a bias voltage line VBL. Specifically, the eighth transistor T8 includes a gate electrode receiving a jth black scan signal GBj (also referred to as a bias control signal) through a jth black scan line GBLj, a first electrode electrically connected to the bias voltage line VBL, and a second electrode electrically connected to the first electrode of the first transistor T1 (i.e., the second node N2). A bias voltage Vbias may be applied to the bias voltage line VBL. The eighth transistor T8 is turned on in response to the jth black scan signal GBj provided to the jth black scan line GBLj. The turned-on eighth transistor T8 may apply the bias voltage Vbias to the second node N2.

[0104] 5 and 6A, the j-th light emitting control signal EMj includes a non-light emitting period NEP. In one embodiment, the non-light emitting period NEP may be defined as an inactive period (i.e., a high level period) of the j-th light emitting control signal EMj. The low level period of the j-th light emitting control signal EMj may be defined as a light emitting period.

[0105] The jth initialization scan signal GIj may have an initialization period AP1 (i.e., a low level period) within the non-light-emitting period NEP. The jth initialization scan signal GIj is supplied to the fourth transistor T4 through the jth initialization scan line GILj, and the fourth transistor T4 is turned on during the initialization period AP1 in which the jth initialization scan signal GIj is activated. Due to the fourth transistor T4 being turned on during the initialization period AP1, the potential of the first node N1 may be initialized to the first initialization voltage Vint.

[0106] The jth compensation scan signal GCj may have a compensation interval AP2 (i.e., a low level interval) within the non-light-emitting interval NEP. When the jth compensation scan signal GCj is supplied to the third transistor T3 through the jth compensation scan line GCLj, the third transistor T3 is turned on during the compensation interval AP2. The first transistor T1 is diode-connected and forward-biased by the turned-on third transistor T3. As a result, a compensation voltage "ELVDD-Vth," which is reduced from the first driving voltage ELVDD by the threshold voltage Vth of the first transistor T1, may be applied to the first node N1. That is, the potential of the first node N1 may be compensated for by the compensation voltage "ELVDD-Vth" during the compensation interval AP2.

[0107] As an example of the present invention, the duration of the compensation period AP2 may be the same as the duration of the initialization period AP1.

[0108] The jth write scan signal GWj may have a data write interval AP3 (i.e., a low level interval) within the non-light-emitting interval NEP. The jth write scan signal GWj is supplied to the second transistor T2 through the jth write scan line GWLj, and the second transistor T2 is turned on during the data write interval AP3. During the data write interval AP3, the ith data voltage Vdata may be applied to the second node N2 through the turned-on second transistor T2. As a result, the potential of the second node N2 is changed to the ith data voltage Vdata.

[0109] As an example of the present invention, the duration of the compensation period AP2 may be greater than or equal to the duration of the data write period AP3. While FIG. 6A illustrates an example in which the start point (e.g., falling point) of the data write period AP3 follows the start point (e.g., falling point) of the compensation period AP2 and the end point (e.g., rising point) of the data write period AP3 precedes the end point (e.g., rising point) of the compensation period AP2, the present invention is not limited thereto. Alternatively, as shown in FIG. 6B, the falling point (start point) of the data write period AP3 may follow the falling point of the compensation period AP2a and the rising point (end point) of the data write period AP3 may coincide with the rising point of the compensation period AP2a.

[0110] During the data write interval AP3, the third transistor T3 maintains its on-state, and the potential of the first node N1 changes according to the i-th data voltage Vdata. For example, if the i-th data voltage Vdata is a black data voltage representing a black gradation, the potential of the first node N1 may gradually increase from the falling point of the data write interval AP3 and stop increasing at the rising point of the data write interval AP3. However, if the duration of the data write interval AP3 is short, the potential of the first node N1 may end without increasing to the black data voltage.

[0111] The first boost capacitor Cbst1 is connected between the jth write scan line GWLj and the first node N1, and can primarily boost the potential of the first node N1 due to a coupling phenomenon when the jth write scan signal GWj applied to the jth write scan line GWLj rises to a high level at the rising point of the data write period AP3. Therefore, the potential of the first node N1 can be boosted (or increased) by a predetermined level at the rising point of the data write period AP3.

[0112] Thereafter, the second boost capacitor Cbst2 is connected between the jth compensation scan line GCLj and the first node N1, and when the jth compensation scan signal GCj applied to the jth compensation scan line GCLj rises to a high level at the rising time, the second boost capacitor Cbst2 can secondarily boost the potential of the first node N1 due to a coupling phenomenon, and the potential of the first node N1 can be re-boosted (or re-raised) by a predetermined level at the rising time of the compensation interval AP2.

[0113] Therefore, compared to a pixel circuit unit PXC that does not have the first and second boost capacitors Cbst1 and Cbst2, the potential of the first node N1 can be sufficiently increased to the black data voltage, and as a result, the pixel can accurately represent the black gradation.

[0114] 6B, when the jth compensation scan signal GCj rises at the same time as the jth write scan signal GWj rises, the first and second boosting operations may occur simultaneously, i.e., when the jth compensation scan signal GCj and the jth write scan signal GWj rise, the potential of the first node N1 may rise to the black data voltage in one boosting operation.

[0115] Furthermore, if the pixel circuit unit PXC does not include the first and second boost capacitors Cbst1 and Cbst2, an i-th data voltage Vdata higher than the target voltage must be supplied to the pixel circuit unit PXC to raise the potential of the first node N1 to a desired black data voltage (i.e., target voltage) during a given data write period AP3. This can result in a large amount of power being consumed to drive the display device DD (see FIG. 3). However, if the pixel circuit unit PXC includes the first and second boost capacitors Cbst1 and Cbst2, the potential of the first node N1 is raised through the boosting operation, so it is not necessary to apply the i-th data voltage Vdata higher than the target voltage to represent black gradation, thereby reducing the power consumption of the display device DD.

[0116] FIG. 7 is a cross-sectional view of a display panel according to an embodiment of the present invention.

[0117] Referring to FIG. 7, the display panel DP may include a base layer BL, a circuit layer DP_CL, and an element layer DP_ED.

[0118] The base layer BL may include a synthetic resin layer. The synthetic resin layer may include a thermosetting resin. In particular, the synthetic resin layer may be a polyimide-based resin layer, and the material thereof is not particularly limited. The synthetic resin layer may include at least one of an acrylic resin, a methacrylic resin, a polyisoprene, a vinyl resin, an epoxy resin, a urethane resin, a cellulose resin, a siloxane resin, a polyamide resin, and a perylene resin. In addition, the base layer may include a glass substrate, a metal substrate, an organic / inorganic composite material substrate, or the like.

[0119] The circuit layer DP_CL is disposed on the base layer BL. The circuit layer DP_CL may include at least one inorganic layer disposed on the upper surface of the base layer BL. The inorganic layer may include at least one of aluminum oxide, titanium oxide, silicon oxide, silicon oxynitride, zirconium oxide, and hafnium oxide. The inorganic layer may be formed in a multilayer (stacked film). The multilayer inorganic layer may constitute a barrier layer BRL and / or a buffer layer BFL. The barrier layer BRL and the buffer layer BFL may be selectively disposed.

[0120] The barrier layer BRL is disposed on the base layer BL to prevent foreign substances from entering from the outside. The barrier layer BRL may include a silicon oxide layer and a silicon nitride layer. Each of these may be provided in multiple layers, and the silicon oxide layer and the silicon nitride layer may be stacked alternately.

[0121] The buffer layer BFL may be disposed on the barrier layer BRL. The buffer layer BFL improves the bonding strength between the base layer BL and the semiconductor pattern and / or the conductive pattern. The buffer layer BFL may include a silicon oxide layer and a silicon nitride layer. The silicon oxide layer and the silicon nitride layer may be alternately stacked. The barrier layer BRL and the buffer layer BFL may be omitted.

[0122] The circuit layer DP_CL includes a semiconductor pattern disposed on the buffer layer BFL. The semiconductor pattern may include a silicon semiconductor. The semiconductor pattern may include polysilicon. However, without being limited thereto, the semiconductor pattern may include amorphous silicon or an oxide semiconductor.

[0123] The electrical properties of semiconductor patterns vary depending on whether they are doped or not. Each semiconductor pattern can include doped and undoped regions. The doped regions can be doped with N-type or P-type dopants. A P-type transistor includes a doped region doped with P-type dopants, and an N-type transistor includes a doped region doped with N-type dopants.

[0124] The doped regions have higher conductivity than the undoped regions and substantially function as electrodes or signal lines. The undoped regions substantially correspond to the channel portions CH1, CH2, CH3-1, CH3-2, CH4-1, and CH4-2 of the transistors. In other words, some portions of the semiconductor patterns may be the channel portions CH1, CH2, CH3-1, CH3-2, CH4-1, and CH4-2 of the transistors, other portions may be the sources or drains of the transistors, and other portions may be the connecting signal lines (or connecting electrodes) SCL.

[0125] 7, the first electrode S1, channel portion CH1, and second electrode D1 of the first transistor T1 are formed from semiconductor patterns. The first electrode S1 and second electrode D1 of the first transistor T1 extend in opposite directions from the channel portion CH1. The first electrode S2, channel portion CH2, and second electrode D2 of the second transistor T2 are formed from semiconductor patterns. The first electrode S2 and second electrode D2 of the second transistor T2 extend in opposite directions from the channel portion CH2. The second electrode D2 of the second transistor T2 and the first electrode S1 of the first transistor T1 may be integrally formed.

[0126] The first electrode, channel portion CH3-1, and second electrode D3-1 of the first sub-transistor T3-1 are formed using a semiconductor pattern, and the first electrode S3-2, channel portion CH3-2, and second electrode of the second sub-transistor T3-2 are formed using a semiconductor pattern. The first electrode and second electrode D3-1 of the first sub-transistor T3-1 extend in opposite directions from the channel portion CH3-1, and the first electrode S3-2 and second electrode of the second sub-transistor T3-2 extend in opposite directions from the channel portion CH3-2. The first electrode of the first sub-transistor T3-1 and the second electrode of the second sub-transistor T3-2 may be integrally formed. The first electrode of the first sub-transistor T3-1 and the second electrode of the second sub-transistor T3-2 may be integrally formed with a first node capacitor electrode NCE1 of the first node capacitor Cn1. The first electrode S3-2 of the second sub-transistor T3-2 and the second electrode D1 of the first transistor T1 may be integrally formed.

[0127] The first electrode S4-1, channel portion CH4-1, and second electrode of the third sub-transistor T4-1 are formed from one semiconductor pattern, and the first electrode, channel portion CH4-2, and second electrode D4-2 of the fourth sub-transistor T4-2 are formed from the same or another semiconductor pattern. The first electrode S4-1 and second electrode of the third sub-transistor T4-1 extend in opposite directions from the channel portion CH4-1, and the first electrode and second electrode D4-2 of the fourth sub-transistor T4-2 extend in opposite directions from the channel portion CH4-2. The second electrode of the third sub-transistor T4-1 and the first electrode of the fourth sub-transistor T4-2 may be integrally formed. The second electrode of the third sub-transistor T4-1 and the first electrode of the fourth sub-transistor T4-2 may be integrally formed with a third-node capacitor electrode NCE3 of the second-node capacitor Cn2.

[0128] A first insulating layer 10 (or gate insulating layer) is disposed on the buffer layer BFL. The first insulating layer 10 overlaps a plurality of pixels PX (see FIG. 3) in common and covers the semiconductor pattern. The first insulating layer 10 is an inorganic layer and / or an organic layer and may have a single-layer or multi-layer structure. The first insulating layer 10 may include at least one of aluminum oxide, titanium oxide, silicon oxide, silicon oxynitride, zirconium oxide, and hafnium oxide. In this embodiment, the first insulating layer 10 may be a single-layer silicon oxide layer. Not only the first insulating layer 10 but also the insulating layers of the circuit layer DP_CL described below may be inorganic layers and / or organic layers and may have a single-layer or multi-layer structure. The inorganic layer may include at least one of the materials described above.

[0129] A gate electrode G1 of the first transistor T1, a gate electrode G2 of the second transistor T2, a gate electrode G3-1 of the first sub-transistor T3-1, a gate electrode G3-2 of the second sub-transistor T3-2, a gate electrode G4-1 of the third sub-transistor T4-1, and a gate electrode G4-2 of the fourth sub-transistor T4-2 are arranged on the first insulating layer 10. The gate electrode G1 of the first transistor T1 overlaps the channel portion CH1 of the first transistor T1, and the gate electrode G2 of the second transistor T2 overlaps the channel portion CH2 of the second transistor T2. The gate electrode G3-1 of the first sub-transistor T3-1 overlaps the channel portion CH3-1 of the first sub-transistor T3-1, and the gate electrode G3-2 of the second sub-transistor T3-2 overlaps the channel portion CH3-2 of the second sub-transistor T3-2. The gate electrode G4-1 of the third sub-transistor T4-1 overlaps with the channel portion CH4-1 of the third sub-transistor T4-1, and the gate electrode G4-2 of the fourth sub-transistor T4-2 overlaps with the channel portion CH4-2 of the fourth sub-transistor T4-2.

[0130] A first capacitor electrode CE1 is further disposed on the first insulating layer 10. The first capacitor electrode CE1 may extend from the gate electrode G1 of the first transistor T1 and have a shape integral with the gate electrode G1 of the first transistor T1. The gate electrodes G1, G2, G3-1, G3-2, G4-1, and G4-2 of the transistors T1, T2, T3-1, T3-2, T4-1, and T4-2 and the first capacitor electrode CE1 may be part of the first gate pattern layer GAT1 shown in FIG. 9B .

[0131] A second insulating layer 20 is disposed on the first insulating layer 10, covering the gate electrodes G1, G2, G3-1, G3-2, G4-1, and G4-2 of the transistors T1, T2, T3-1, T3-2, T4-1, and T4-2 and the first capacitor electrode CE1. The second insulating layer 20 overlaps a plurality of pixels PX in common. The second insulating layer 20 is an inorganic and / or organic layer and may have a single-layer or multi-layer structure. In this embodiment, the second insulating layer 20 may be a single silicon oxide layer.

[0132] A second capacitor electrode CE2 may be disposed on the second insulating layer 20. The second capacitor electrode CE2 faces the first capacitor electrode CE1 through the second insulating layer 20 to form a storage capacitor Cst. A second node capacitor electrode NCE2 and a fourth node capacitor electrode NCE4 may also be disposed on the second insulating layer 20. The second node capacitor electrode NCE2 faces the first node capacitor electrode NCE1 through the first insulating layer 10 and the second insulating layer 20 to form a first node capacitor Cn1. The fourth node capacitor electrode NCE4 faces the third node capacitor electrode NCE3 through the first insulating layer 10 and the second insulating layer 20 to form a second node capacitor Cn2.

[0133] The second capacitor electrode CE2 and the second and fourth node capacitor electrodes NCE2 and NCE4 may be part of the second gate pattern layer GAT2 shown in FIG. 9C.

[0134] A third insulating layer 30 covering the second capacitor electrode CE2 and the second and fourth node capacitor electrodes NCE2 and NCE4 is disposed on the second insulating layer 20. In this embodiment, the third insulating layer 30 may be a single silicon oxide layer.

[0135] An additional gate electrode T1_gate may be disposed on the third insulating layer 30. The additional gate electrode T1_gate may be connected to the gate electrode G1 of the first transistor T1 through a contact hole penetrating the second and third insulating layers 20 and 30. The additional gate electrode T1_gate may also be connected to the second electrode D3-1 of the first sub-transistor T3-1 through a contact hole penetrating the first to third insulating layers 10, 20 and 30.

[0136] The additional gate electrode T1_gate faces the gate electrode G3-1 of the first sub-transistor T3-1 via the second and third insulating layers 20 and 30 to form a second boost capacitor Cbst2. The additional gate electrode T1_gate may be part of the third gate pattern layer GAT3 shown in FIG. 9D. The additional gate electrode T1_gate may be disposed on a layer other than the gate electrode G1 of the first transistor T1 and the first and second capacitor electrodes CE1 and CE2. In one example of the present invention, the additional gate electrode T1_gate does not overlap the second and fourth node capacitor electrodes NCE2 and NCE4 in a plane.

[0137] A write scan line GWL, a compensation scan line GCL, an initialization scan line GIL, a first initialization voltage line VIL, and a horizontal voltage line H_VL1 are disposed on the fourth insulating layer 40. The write scan line GWL may correspond to the j-th write scan line (i.e., the first scan line) shown in FIG. 5, and the write scan line GWL is connected to the gate electrode G2 of the second transistor T2 through a contact hole that penetrates the second to fourth insulating layers 20, 30, and 40. The compensation scan line GCL may correspond to the j-th compensation scan line (i.e., the second scan line) shown in FIG. 5, and the compensation scan line GCL is connected to the gate electrodes G3-1 and G3-2 of the first and second sub-transistors T3-1 and T3-2 through a contact hole that penetrates the second to fourth insulating layers 20, 30, and 40. The initialization scan line GIL may correspond to the jth initialization scan line (i.e., the third scan line) shown in FIG. 5, and the initialization scan line GIL is connected to the gate electrode G4-2 of the fourth sub-transistor T4-2 through a contact hole penetrating the second to fourth insulating layers 20, 30, and 40.

[0138] The additional gate electrode T1_gate can be disposed on the write scan line GWL, the compensation scan line GCL, the initialization scan line GIL, and other layers.

[0139] The first initialization voltage line VIL is connected to the second electrode D4-2 of the fourth sub-transistor T4-2 through a contact hole that penetrates the first to fourth insulating layers 10, 20, 30, and 40, and the horizontal voltage wiring H_VL1 is connected to the second capacitor electrode CE2 through a contact hole that penetrates the third and fourth insulating layers 30 and 40.

[0140] First and second connecting electrodes CNE1 and CNE2 are further disposed on the fourth insulating layer 40. The first connecting electrode CNE1 is an electrode for connecting the first electrode S2 of the second transistor T2 to the data line DL, and the second connecting electrode CNE2 is an electrode for electrically connecting the connection signal line SCL to the anode AE ​​of the light emitting element ED.

[0141] The write scan line GWL, the compensation scan line GCL, the initialization scan line GIL, the first initialization voltage line VIL, the horizontal voltage line H_VL1, and the first and second connecting electrodes CNE1 and CNE2 may be part of the first data pattern layer SD1 shown in FIG. 9E.

[0142] The fifth insulating layer 50 is disposed to cover the write scan line GWL, the compensation scan line GCL, the initialization scan line GIL, the first initialization voltage line VIL, the horizontal voltage line H_VL1, and the first and second connecting electrodes CNE1 and CNE2. The vertical voltage line V_VL1, the data line DL, and the third connecting electrode CNE3 may be disposed on the fifth insulating layer 50.

[0143] The vertical voltage line V_VL1 is connected to the horizontal voltage line H_VL1 through a contact hole provided through the fifth insulating layer 50, and the data line DL is connected to the first connecting electrode CNE1 through a contact hole provided through the fifth insulating layer 50. The third connecting electrode CNE3 is connected to the second connecting electrode CNE2 through a contact hole provided through the fifth insulating layer 50.

[0144] The third connecting electrode CNE3 may be connected to the anode AE ​​of the light emitting element ED. The vertical voltage line V_VL1, the data line DL, and the third connecting electrode CNE3 may be part of the second data pattern layer SD2 shown in FIG.

[0145] A sixth insulating layer 60 covering the vertical voltage line V_VL1, the data line DL, and the third connecting electrode CNE3 is disposed on the fifth insulating layer 50, and a seventh insulating layer 70 is disposed on the sixth insulating layer 60. In this embodiment, each of the sixth and seventh insulating layers 60 and 70 may include a silicon oxide layer or a silicon nitride layer. Alternatively, one of the sixth and seventh insulating layers 60 and 70 may be omitted.

[0146] The device layer DP_ED is disposed on the circuit layer DP_CL. The device layer DP_ED may include a light-emitting element ED and a pixel definition layer PDL. The light-emitting element ED includes an anode AE, an emitting layer EL, and a cathode CE.

[0147] The pixel definition layer PDL may include an opening OP defined in correspondence with the light-emitting element ED. The opening OP exposes at least a portion of the anode AE ​​of the light-emitting element ED. The opening OP in the pixel definition layer PDL may define a light-emitting region. For example, a plurality of pixels PX (see FIG. 3) may be arranged regularly on the plane of the display panel DP (see FIG. 3). The region in which the plurality of pixels PX are arranged may be defined as a pixel region, and one pixel region may include a light-emitting region and a non-light-emitting region adjacent to the light-emitting region. The non-light-emitting region may surround the light-emitting region.

[0148] The light-emitting layer EL is disposed corresponding to an opening OP defined in the pixel definition layer PDL. In this embodiment, a patterned light-emitting layer EL is illustrated as an example, but the present invention is not limited thereto. A common light-emitting layer may be disposed in common to a plurality of pixels PX. Here, the common light-emitting layer may generate white light or blue light.

[0149] The cathode CE is disposed on the light-emitting layer EL and is shared by a plurality of pixels PX.

[0150] The display panel DP may further include an encapsulation layer that seals the device layer DP_ED. The encapsulation layer may include at least one organic film and at least one inorganic film. The inorganic film includes an inorganic material and can protect the device layer DP_ED from moisture / oxygen. The inorganic film may include, but is not limited to, a silicon nitride layer, a silicon oxynitride layer, a silicon oxide layer, a titanium oxide layer, an aluminum oxide layer, or the like. The organic film includes an organic material and can protect the device layer DP_ED from foreign substances such as dust particles.

[0151] FIG. 8 is a plan view showing a portion of a display panel according to an embodiment of the present invention.

[0152] 7 and 8, a plurality of pixel regions are defined on the base layer BL. The pixel regions may include a first pixel region PXA1 in which a first pixel (e.g., a red pixel) is disposed, a second pixel region PXA2 in which a second pixel (e.g., a green pixel) is disposed, and a third pixel region PXA3 in which a third pixel (e.g., a blue pixel) is disposed. The pixel regions are arranged in the order of the third pixel region PXA3, the first pixel region PXA1, and the second pixel region PXA2 in a first direction DR1.

[0153] A first pixel circuit unit is arranged in the first pixel region PXA1, a second pixel circuit unit is arranged in the second pixel region PXA2, and a third pixel circuit unit is arranged in the third pixel region PXA3. Each of the first to third pixel circuits includes eight transistors (i.e., first to eighth transistors T1 to T8) and five capacitors (i.e., a storage capacitor Cst, first and second node capacitors Cn1 and Cn2, and first and second boost capacitors Cbst1 and Cbst2). The first to third pixel circuits have the same circuit configuration and similar layout structures.

[0154] In one embodiment of the present invention, one additional gate electrode T1_gate is disposed in each of the first to third pixel regions PXA1, PXA2, and PXA3. The additional gate electrode T1_gate may correspond to the first node N1 shown in FIG. 5. The additional gate electrode T1_gate is used to form first and second boost capacitors Cbst1 and Cbst2. In one embodiment of the present invention, the second boost capacitor Cbst2 may include a first sub-boost capacitor Cbst21 and a second sub-boost capacitor Cbst22. The first sub-boost capacitor Cbst21 and the second sub-boost capacitor Cbst22 may be connected in series.

[0155] The first and second sub-light-emitting elements ED_R1 and ED_R2 (see FIG. 4B) are connected to the first pixel circuit section, the second light-emitting element ED_G (see FIG. 4B) is connected to the second pixel circuit section, and the third light-emitting element ED_B (see FIG. 4B) is connected to the third pixel circuit section.

[0156] 9A to 9G are plan views showing the layout of layers stacked in a display panel. Specifically, FIG. 9A is a plan view showing a semiconductor pattern layer disposed on a buffer layer, and FIG. 9B is a plan view showing a first gate pattern layer disposed on a first insulating layer and a semiconductor pattern layer. FIG. 9C is a plan view showing a second gate pattern layer disposed on a second insulating layer and a first gate pattern layer, and FIG. 9D is a plan view showing a third gate pattern layer disposed on a third insulating layer and a second gate pattern layer. FIG. 9E is a plan view showing a first data pattern layer disposed on a fourth insulating layer and a third gate pattern layer, and FIG. 9F is a plan view showing a second data pattern layer disposed on a fifth insulating layer and a first data pattern layer. FIG. 9G is a plan view showing an anode electrode layer disposed on a seventh insulating layer and a second data pattern layer.

[0157] 8 and 9A, a semiconductor pattern layer ACT is disposed on the buffer layer BFL. The semiconductor pattern layer ACT may include a silicon semiconductor. For example, the silicon semiconductor may include amorphous silicon, polycrystalline silicon, etc. For example, the semiconductor pattern layer ACT may include low-temperature polysilicon (LTPS).

[0158] The semiconductor pattern layer ACT includes semiconductor patterns of transistors (i.e., first to eighth transistors T1 to T8) included in each of the first to third pixel circuit units, and the semiconductor patterns may be connected to each other to form an integral shape.

[0159] The semiconductor pattern layer ACT includes a channel portion CH1 of the first transistor T1, a channel portion CH2 of the second transistor T2, a channel portion CH3-1 of the first sub-transistor T3-1, a channel portion CH3-2 of the second sub-transistor T3-2, and a first node capacitor electrode NCE1. The first node capacitor electrode NCE1 is disposed between the channel portion CH3-1 of the first sub-transistor T3-1 and the channel portion CH3-2 of the second sub-transistor T3-2, and may correspond to the first connecting node GN1 of FIG. 5.

[0160] The semiconductor pattern layer ACT further includes a channel portion CH4-1 of the third sub-transistor T4-1, a channel portion CH4-2 of the fourth sub-transistor T4-2, and a third node capacitor electrode NCE3. The third node capacitor electrode NCE3 is disposed between the channel portion CH4-1 of the third sub-transistor T4-1 and the channel portion CH4-2 of the fourth sub-transistor T4-2, and may correspond to the second coupling node GN2 in FIG. 5.

[0161] The semiconductor pattern layer ACT further includes a channel portion CH5 of a fifth transistor T5, a channel portion CH6 of a sixth transistor T6, a channel portion CH7 of a seventh transistor T7, and a channel portion CH8 of an eighth transistor T8.

[0162] 8 and 9B, a first insulating layer 10 may be disposed on the semiconductor pattern layer ACT, and a first gate pattern layer GAT1 may be disposed on the first insulating layer 10. The first gate pattern layer GAT1 may be a layer formed by patterning a first gate metal layer. The first gate pattern layer GAT1 may include a metal, an alloy, a conductive metal oxide, a transparent conductive material, or the like. For example, the first gate pattern layer GAT1 may include, but is not limited to, silver (Ag), a silver-containing alloy, molybdenum (Mo), a molybdenum-containing alloy, aluminum (Al), an aluminum-containing alloy, aluminum nitride (AlN), tungsten (W), tungsten nitride (WN), copper (Cu), indium tin oxide (ITO), indium zinc oxide (IZO), or the like.

[0163] The first gate pattern layer GAT1 may include gate electrodes of transistors (i.e., first to eighth transistors T1 to T8) included in each of the first to third pixel circuit units. The first gate pattern layer GAT1 and the semiconductor pattern layer ACT may form the first to eighth transistors T1 to T8 of each pixel circuit unit.

[0164] The first gate pattern layer GAT1 includes first to fourth sub-scan lines A_GIL, A_GCL, A_EML, and A_GBL, a sub-scan pattern A_GWP, and a first capacitor electrode CE1. Each of the first to fourth sub-scan lines A_GIL, A_GCL, A_EML, and A_GBL may extend in a first direction DR1 to overlap one or more pixel regions among the first to third pixel regions PXA1, PXA2, and PXA3.

[0165] The first auxiliary scan line A_GIL may include a gate electrode G4-1 of the third sub-transistor T4-1 overlapping with the channel portion CH4-1 of the third sub-transistor T4-1 and a gate electrode G4-2 of the fourth sub-transistor T4-2 overlapping with the channel portion CH4-2 of the fourth sub-transistor T4-2. The second auxiliary scan line A_GCL may include a gate electrode G3-1 of the first sub-transistor T3-1 overlapping with the channel portion CH3-1 of the first sub-transistor T3-1 and a gate electrode G3-2 of the second sub-transistor T3-2 overlapping with the channel portion CH3-2 of the second sub-transistor T3-2.

[0166] The auxiliary scan pattern A_GWP is provided in an Irish form and may include a gate electrode G2 of the second transistor T2 overlapping with the channel portion CH2 of the second transistor T2, and the first capacitor electrode CE1 may include a gate electrode G1 of the first transistor T1 overlapping with the channel portion CH1 of the first transistor T1.

[0167] The third sub-scan line A_EML may include a gate electrode G5 of the fifth transistor T5 overlapping with the channel portion CH5 of the fifth transistor T5 and a gate electrode G6 of the sixth transistor T6 overlapping with the channel portion CH6 of the sixth transistor T6. The fourth sub-scan line A_GBL may include a gate electrode G7 of the seventh transistor T7 overlapping with the channel portion CH7 of the seventh transistor T7 and a gate electrode G8 of the eighth transistor T8 overlapping with the channel portion CH8 of the eighth transistor T8.

[0168] 8 and 9C, a second insulating layer 20 may be disposed on the first insulating layer 10 to cover the first gate pattern layer GAT1. A second gate pattern layer GAT2 may be disposed on the second insulating layer 20. The second gate pattern layer GAT2 may be a layer formed by patterning a second gate metal layer. The second gate pattern layer GAT2 may include a metal, an alloy, a conductive metal oxide, a transparent conductive material, or the like.

[0169] The second gate pattern layer GAT2 may include a second capacitor electrode CE2, second and fourth node capacitor electrodes NCE2 and NCE4, a repair wiring RPL, and a second-first initialization voltage line VAIL_GB. The second capacitor electrode CE2 is disposed to overlap the first capacitor electrode CE1 on a plane. The first capacitor electrode CE1 and the second capacitor electrode CE2 may form a storage capacitor Cst (see FIG. 7) in each of the pixel regions PXA1 to PXA3.

[0170] The second node capacitor electrode NCE2 is branched from the second capacitor electrode CE2 and is arranged to overlap the first node capacitor electrode NCE1 on a plane. The first and second node capacitor electrodes NCE1 and NCE2 may form a first node capacitor Cn1 (see FIG. 7) in each of the pixel regions PXA1 to PXA3.

[0171] The fourth node capacitor electrode NCE4 is arranged in an Irish shape and overlaps the third node capacitor electrode NCE3 on a plane. The third and fourth node capacitor electrodes NCE3 and NCE4 may form a second node capacitor Cn2 (see FIG. 7) in each of the pixel regions PXA1 to PXA3.

[0172] The repair line RPL may be provided to repair lines (e.g., scan lines and emission control lines) provided in the display panel DP (see FIG. 3). The repair line RPL may extend in an extension direction (e.g., a first direction DR1) of the scan lines and emission control lines. When one of the scan lines and emission control lines is broken, the two portions of the broken line may be electrically connected through the repair line RPL by connecting the two portions of the broken line to an adjacent repair line RPL. In one example of the present invention, the repair line RPL and the broken line may be connected to each other in the non-display area NDA (see FIG. 3).

[0173] 5 may include a 2-1 initialization voltage line VAIL_GB connected to the second and third pixels and a 2-2 initialization voltage line VAIL_R (see FIG. 9D) connected to the first pixel. The 2-1 initialization voltage line VAIL_GB supplies the 2-1 initialization voltage to the second and third pixels, and the 2-2 initialization voltage line VAIL_R supplies the 2-2 initialization voltage to the first pixel. In one example, the 2-2 initialization voltage may have a different voltage level from the 2-1 initialization voltage. The 2-1 initialization voltage line VAIL_GB may be connected to second electrodes of seventh transistors T7 disposed in the second and third pixel areas PXA2 and PXA3, respectively.

[0174] 8 and 9D, a third insulating layer 30 may be disposed on the second insulating layer 20 to cover the second gate pattern layer GAT2. A third gate pattern layer GAT3 may be disposed on the third insulating layer 30. The third gate pattern layer GAT3 may include a metal, an alloy, a conductive metal oxide, a transparent conductive material, or the like.

[0175] The third gate pattern layer GAT3 includes an additional gate electrode T1_gate, an emission control wiring EML, a bias voltage line VBL, and a 2-2 initialization voltage line VAIL_R. The additional gate electrode T1_gate is arranged to overlap the first and second capacitor electrodes CE1 and CE2 in a plane. The additional gate electrode T1_gate is connected to the gate electrode G1 of the first transistor T1 through a first contact hole CNT1 and to the second electrode D3-1 of the first sub-transistor T3 (see FIG. 7) and the first electrode S4-1 of the third sub-transistor T4 (see FIG. 7) through a second contact hole CNT2.

[0176] The light-emission control line EML overlaps the third sub-scan line A_EML (see FIG. 9B) in a plane and is connected to the third sub-scan line A_EML through a contact hole. The light-emission control line EML can overlap the gate electrode G5 of the fifth transistor T5 and the gate electrode G6 of the sixth transistor T6 in a plane.

[0177] The bias voltage line VBL is connected to the first electrode of the eighth transistor T8 and can supply the bias voltage Vbias (see FIG. 5) to the eighth transistor T8. The 2-2 initialization voltage line VAIL_R is connected to the second electrode of the seventh transistor T2 arranged in the first pixel area PXA1 and can supply the 2-2 initialization voltage to the seventh transistor T7 of the first pixel.

[0178] 8 and 9E, a fourth insulating layer 40 may be disposed on the third insulating layer 30 to cover the third gate pattern layer GAT3. A first data pattern layer SD1 may be disposed on the fourth insulating layer 40. The first data pattern layer SD1 may be a layer formed by patterning a first data metal layer. The first data pattern layer SD1 may include a metal, an alloy, a conductive metal oxide, a transparent conductive material, or the like.

[0179] The first data pattern layer SD1 includes initialization scan lines GIL, compensation scan lines GCL, write scan lines GWL, black scan lines GBL, first initialization voltage lines VIL, and horizontal voltage lines H_VL1. The initialization scan lines GIL, compensation scan lines GCL, write scan lines GWL, black scan lines GBL, first initialization voltage lines VIL, and horizontal voltage lines H_VL1 may extend in a first direction DR1 and be spaced apart from each other in a second direction DR2.

[0180] The initialization scan line GIL overlaps the first auxiliary scan line A_GIL in the plane and is connected to the first auxiliary scan line A_GIL (see FIG. 9B) through a contact hole. The compensation scan line GCL overlaps the second auxiliary scan line A_GCL (see FIG. 9B) in the plane and is connected to the second auxiliary scan line A_GCL through a contact hole. The write scan line GWL overlaps the auxiliary scan pattern A_GWP in the plane and is connected to the auxiliary scan pattern A_GWP through a contact hole. The black scan line GBL overlaps the fourth auxiliary scan line A_GBL in the plane and is connected to the fourth auxiliary scan line A_GBL (see FIG. 9B) through a contact hole.

[0181] When the first to fourth auxiliary scan lines A_GIL to A_GBL are arranged in this manner, even if a break occurs in each of the initialization scan line GIL, the compensation scan line GCL, the light emission control line EML, and the black scan line GBL, signals can be supplied through the first to fourth auxiliary scan lines A_GIL to A_GBL, and as a result, pixel defects can be minimized.

[0182] The first initialization voltage line VIL is connected to the second electrode D4-2 of the fourth sub-transistor T4-2 and may supply the first initialization voltage Vint to the fourth sub-transistor T4. The horizontal voltage line H_VL1 may be included in the first driving voltage line VL1. The horizontal voltage line H_VL1 is connected to the second capacitor electrode CE2 (see FIG. 9C) and may supply the first driving voltage ELVDD to the second capacitor electrode CE2 of the storage capacitor Cst.

[0183] The first data pattern layer SD1 may include a plurality of connecting electrodes, which may include first and second connecting electrodes CNE1 and CNE2.

[0184] 8 and 9F, a fifth insulating layer 50 may be disposed on the fourth insulating layer 40 to cover the first data pattern layer SD1. A second data pattern layer SD2 may be disposed on the fifth insulating layer 50. The second data pattern layer SD2 may be a layer formed by patterning a second data metal layer. The second data pattern layer SD2 may include, for example, a metal, an alloy, a conductive metal oxide, a transparent conductive material, etc.

[0185] The second data pattern layer SD2 may include data lines DL, vertical voltage lines V_VL1, and dummy vertical lines EOAL.

[0186] The data line DL, the vertical voltage line V_VL1, and the dummy vertical line EOAL may extend in the second direction DR2 and be spaced apart from each other in the first direction DR1. The data line DL may be connected to the first electrode S2 (shown in FIG. 7) of the second transistor T2 through the first connecting electrode CNE1 (see FIGS. 7 and 9E). The data line DL may correspond to one of the data lines DL1 to DLi shown in FIG. 3.

[0187] The vertical voltage wiring V_VL1 may include a portion that overlaps the second capacitor electrode CE2 (see FIG. 9C) in a plan view. The vertical voltage wiring V_VL1 may be connected to the horizontal voltage wiring H_VL1 through a contact hole that penetrates the fifth insulating layer 50. The first driving voltage line VL1 (see FIG. 5) may be configured in a mesh shape on the display panel DP using the horizontal voltage wiring H_VL1 shown in FIG. 9E and the vertical voltage wiring V_VL1 shown in FIG. 9F. This prevents a voltage drop in the first driving voltage ELVDD (see FIG. 5) applied through the first driving voltage line VL1, and as a result, the first driving voltage line VL1 can supply a uniform first driving voltage ELVDD to the pixels PX. This reduces brightness deviation between pixels caused by the voltage drop issue of the first driving voltage ELVDD, resulting in an overall improvement in the image quality of the display panel DP.

[0188] The dummy vertical wiring EOAL may be connected to at least one of the first initialization voltage line VIL, the bias voltage line VBL, the second-first initialization voltage line VAIL_GB, and the second-second initialization voltage line VAIL_R. By connecting with the dummy vertical wiring EOAL, the first initialization voltage line VIL, the bias voltage line VBL, the second-first initialization voltage line VAIL_GB, and the second-second initialization voltage line VAIL_R may be provided in a mesh form on the display panel DP. The voltage drop phenomenon of the voltages applied to the first initialization voltage line VIL, the bias voltage line VBL, the second-first initialization voltage line VAIL_GB, and the second-second initialization voltage line VAIL_R may be improved. The dummy vertical wiring EOAL may also be used as the second driving voltage line VL2 (see FIG. 5).

[0189] The second data pattern layer 150 may further include a third connecting electrode CNE3. The third connecting electrode CNE3 may be provided in an aligned manner in each of the pixel regions PXA1 to PXA3 and may be connected to the connecting signal line SCL (see FIG. 7) through the second connecting electrode CNE2 (see FIGS. 7 and 9E).

[0190] 7 and 9G, a sixth insulating layer 60 may be disposed on the fifth insulating layer 50 to cover the second data pattern layer SD2. An anode electrode layer PXL may be disposed on the seventh insulating layer 70. The anode electrode layer PXL may include, for example, a metal, an alloy, a conductive metal oxide, a transparent conductive material, etc.

[0191] The anode electrode layer PXL may include a first anode R_AE of the first and second sub-light-emitting elements ED_R1 and ED_R2 (see FIG. 4B), a second anode G_AE of the second light-emitting element ED_G, and a third anode B_AE of the third light-emitting element ED_B. Each of the first to third anodes R_AE, G_AE, and B_AE may be arranged to overlap a corresponding third connecting electrode CNE3 on a plane. Each of the first to third anodes R_AE, G_AE, and B_AE may be electrically connected to the second connecting electrode CNE2 (see FIG. 7) and the connecting signal line SCL (see FIG. 7) through the corresponding third connecting electrode CNE3.

[0192] The anode electrode layer PXL is covered by a pixel definition layer PDL, and the pixel definition layer PDL is provided with openings OP (see FIG. 7) that expose the first to third anodes R_AE, G_AE, B_AE.

[0193] The first light-emitting sub-element ED_R1 further includes a first sub-light-emitting layer R_EL1 disposed on the first anode R_AE, the second light-emitting sub-element ED_R2 further includes a second sub-light-emitting layer R_EL2 disposed on the first anode R_AE, the second light-emitting element ED_G further includes a second light-emitting layer G_EL disposed on the second anode G_AE, and the third light-emitting element ED_B further includes a third light-emitting layer B_EL disposed on the third anode B_AE.

[0194] In one embodiment of the present invention, the first and second sub-light-emitting layers R_EL1 and R_EL2 are red light-emitting layers that emit red light, the second light-emitting layer G_EL is a green light-emitting layer that emits green light, and the third light-emitting layer B_EL is a blue light-emitting layer that emits blue light. Each of the first and second sub-light-emitting layers R_EL1 and R_EL2 may have a hexagonal shape, and each of the second and third light-emitting layers G_EL and B_EL may have an octagonal shape.

[0195] FIG. 10 is a block diagram of an electronic device according to one embodiment of the present invention.

[0196] 10, the electronic device 701 outputs various information within the operating system through a display module 740. When the processor 710 executes an application stored in the memory 720, the display module 740 provides application information to a user through a display panel 741.

[0197] The processor 710 acquires an external input through the input module 730 or the sensor module 761 and executes an application corresponding to the external input. For example, if a user selects a camera icon displayed on the display panel 741, the processor 710 acquires the user input through the input sensor 761-2 and activates the camera module 771. The processor 710 transmits image data corresponding to the captured image acquired through the camera module 771 to the display module 740. The display module 740 can display an image corresponding to the captured image on the display panel 741.

[0198] As another example, when personal information authentication is performed by the display module 740, the fingerprint sensor 761-1 acquires input fingerprint information as input data. The processor 710 compares the input data acquired through the fingerprint sensor 761-1 with authentication data stored in the memory 720 and executes an application according to the comparison result. The display module 740 can display information executed according to the logic of the application on the display panel 741.

[0199] As another example, when a music streaming icon displayed on the display module 740 is selected, the processor 710 acquires user input through the input sensor 761-2 and activates a music streaming application stored in the memory 720. When a music execution command is input in the music streaming application, the processor 710 activates the audio output module 763 to provide the user with audio information corresponding to the music execution command.

[0200] The above is a brief description of the operation of the electronic device 701. Below, a detailed description will be given of the configuration of the electronic device 701. Some of the components of the electronic device 701 described below may be integrated and provided as a single component, or one component may be provided as two or more separate components.

[0201] 10 , an electronic device 701 can communicate with an external electronic device 702 through a network (e.g., a short-range wireless communication network or a long-range wireless communication network). According to one embodiment, the electronic device 701 can include a processor 710, a memory 720, an input module 730, a display module 740, a power module 750, an internal module 760, and an external module 770. According to one embodiment, the electronic device 701 can omit at least one of the above components or can include one or more other components. According to one embodiment, some of the above components (e.g., the sensor module 761, the antenna module 762, or the acoustic output module 763) can be integrated into another component (e.g., the display module 740).

[0202] The processor 710 can execute software to control at least one other component (e.g., a hardware or software component) of the electronic device 701 coupled to the processor 710, and can perform various data processing or calculations. According to one embodiment, as at least part of the data processing or calculations, the processor 710 can store instructions or data received from other components (e.g., the input module 730, the sensor module 761, or the communication module 773) in the volatile memory 721, process the instructions or data stored in the volatile memory 721, and store the resulting data in the non-volatile memory 722.

[0203] The processor 710 may include a main processor 711 and an auxiliary processor 712. The main processor 711 may include one or more of a central processing unit (CPU) 711-1 or an application processor (AP). The main processor 711 may further include one or more of a graphics processing unit (GPU) 711-2, a communication processor (CP), and an image signal processor (ISP). The main processor 711 may further include a neural network processing unit (NPU) 711-3. The neural network processing unit is a processor specialized for processing artificial intelligence models, and the artificial intelligence models may be generated through machine learning. The artificial intelligence models may include multiple artificial neural network layers. The artificial neural network may be one of, but is not limited to, a deep neural network (DNN), a convolutional neural network (CNN), a recurrent neural network (RNN), a restricted Boltzmann machine (RBM), a deep belief network (DBN), a bidirectional recurrent deep neural network (BRDNN), a deep Q-network, or a combination of two or more of the above. The artificial intelligence model may include a software structure in addition to or mainly in addition to a hardware structure. At least two of the processing units and processors described above may be embodied in an integrated structure (e.g., a single chip) or each may be embodied in an independent structure (e.g., multiple chips).

[0204] The auxiliary processor 712 may include a drive controller 712-1. The drive controller 712-1 may include an interface conversion circuit and a timing control circuit. The drive controller 712-1 receives image signals from the main processor 711, converts the data format of the image signals to match the interface specifications with the display module 740, and outputs image data. The drive controller 712-1 may output various control signals required to drive the display module 740. The configuration of the drive controller 712-1 is substantially similar to that of the drive controller 100 shown in FIG. 3, so a detailed description thereof will be omitted.

[0205] The auxiliary processor 712 may further include a data conversion circuit 712-2, a gamma correction circuit 712-3, a rendering circuit 712-4, etc. The data conversion circuit 712-2 receives image data from the drive controller 712-1 and can compensate the image data so that an image is displayed at a desired brightness, or convert the image data to reduce power consumption or compensate for image lag, etc., depending on the characteristics of the electronic device 701 or user settings, etc. The gamma correction circuit 712-3 can convert the image data or a gamma reference voltage, etc., so that an image displayed on the electronic device 701 has desired gamma characteristics. The rendering circuit 712-4 receives image data from the drive controller 712-1 and can render the image data taking into account the pixel layout, etc., of the display panel 741 applied to the electronic device 701. At least one of the data conversion circuit 712-2, the gamma correction circuit 712-3, and the rendering circuit 712-4 may be integrated into another component (e.g., the main processor 711 or the controller 712-1). At least one of the data conversion circuit 712-2, the gamma correction circuit 712-3, and the rendering circuit 712-4 may be integrated into a data driver 743, which will be described later.

[0206] The memory 720 may store various data used by at least one component (e.g., the processor 710 or the sensor module 761) of the electronic device 701 and input or output data for associated instructions. The memory 720 may include at least one of a volatile memory 721 and a non-volatile memory 722.

[0207] The input module 730 can receive instructions or data for use by components of the electronic device 701 (e.g., the processor 710, the sensor module 761, or the acoustic output module 763) from outside the electronic device 701 (e.g., from a user or an external electronic device 702).

[0208] The input module 730 may include a first input module 731 through which commands or data are input from a user, and a second input module 732 through which commands or data are input from the external electronic device 702. The first input module 731 may include a microphone, a mouse, a keyboard, keys (e.g., buttons), or a pen (e.g., a passive pen or an active pen). The second input module 732 may support a specified protocol that can be connected to the external electronic device 702 via a wired or wireless connection. According to an embodiment, the second input module 732 may include a high definition multimedia interface (HDMI), a universal serial bus (USB), an SD card interface, or an audio interface. The second input module 732 may include a connector that can be physically connected to the external electronic device 702, such as an HDMI connector, a USB connector, an SD card connector, or an audio connector (e.g., a headset connector).

[0209] The display module 740 provides visual information to a user. The display module 740 may include a display panel 741, a scan driver 742, and a data driver 743. The display module 740 may further include a window, a chassis, and a bracket for protecting the display panel 741. The display module 740 may further include a light emitting driver and a voltage generator. The voltage generator may output various voltages (e.g., first and second driving voltages ELVDD and ELVSS (see FIG. 3)) required to drive the display panel 741. The configurations of the display panel 741, the scan driver 742, the data driver 743, and the voltage generator are substantially similar to the display panel DP, the scan driving circuit 300, the source driving circuit 200, and the voltage generator 400 shown in FIG. 3, and therefore detailed description thereof will be omitted.

[0210] The power supply module 750 supplies power to the components of the electronic device 701. The power supply module 750 may include a battery that charges a power supply voltage. The battery may include a non-rechargeable primary battery, a rechargeable secondary battery, or a fuel cell. The power supply module 750 may include a power management integrated circuit (PMIC). The PMIC supplies optimized power to each of the modules described above and below. The power supply module 750 may include a wireless power transmitting / receiving member electrically connected to the battery. The wireless power transmitting / receiving member may include a plurality of antenna radiators in the form of coils.

[0211] The electronic device 701 may further include an internal module 760 and an external module 770. The internal module 760 may include a sensor module 761, an antenna module 762, and an acoustic output module 763. The external module 770 may include a camera module 771, a light module 772, and a communication module 773.

[0212] The sensor module 761 can sense input from the user's body or input from a pen in the first input module 731 and generate an electrical signal or data value corresponding to the input. The sensor module 761 can include at least one of a fingerprint sensor 761-1, an input sensor 761-2, and a digitizer 761-3.

[0213] The fingerprint sensor 761-1 can generate a data value corresponding to a user's fingerprint and can include either an optical or capacitive fingerprint sensor.

[0214] The input sensor 761-2 can generate data values ​​corresponding to coordinate information of input by the user's body or pen. The input sensor 761-2 generates a data value representing the amount of capacitance change due to the input. The input sensor 761-2 can sense input by a passive pen or can send and receive data to and from an active pen.

[0215] The input sensor 761-2 may measure a biological signal such as blood pressure, water content, or body fat. For example, when a user touches a body part to the sensor layer or sensing panel and does not move for a certain period of time, the input sensor 761-2 can sense the biological signal based on a change in an electric field caused by the body part and output information desired by the user to the display module 740.

[0216] The digitizer 761-3 can generate data values ​​corresponding to the coordinate information of the input by the pen. The digitizer 761-3 converts the amount of electromagnetic change caused by the input into data values. The digitizer 761-3 can sense input by a passive pen or can send and receive data to and from an active pen.

[0217] At least one of the fingerprint sensor 761-1, the input sensor 761-2, and the digitizer 761-3 may be implemented as a sensor layer formed on the display panel 741 through a continuous process. The fingerprint sensor 761-1, the input sensor 761-2, and the digitizer 761-3 may be disposed on the upper side of the display panel 741, and any one of the fingerprint sensor 761-1, the input sensor 761-2, and the digitizer 761-3, for example, the digitizer 761-3, may be disposed on the lower side of the display panel 741.

[0218] At least two of the fingerprint sensor 761-1, the input sensor 761-2, and the digitizer 761-3 may be formed to be integrated into one sensing panel through the same process. When integrated into one sensing panel, the sensing panel may be disposed between the display panel 741 and a window disposed above the display panel 741. According to one embodiment, the sensing panel may be disposed on the window, and the position of the sensing panel is not particularly limited.

[0219] At least one of the fingerprint sensor 761-1, the input sensor 761-2, and the digitizer 761-3 may be embedded in the display panel 741. That is, at least one of the fingerprint sensor 761-1, the input sensor 761-2, and the digitizer 761-3 may be formed simultaneously through the process of forming elements (e.g., light-emitting elements, transistors, etc.) included in the display panel 741.

[0220] Additionally, the sensor module 761 may generate an electrical signal or a data value corresponding to an internal state or an external state of the electronic device 701. The sensor module 761 may further include, for example, a gesture sensor, a gyro sensor, a barometric pressure sensor, a magnetic sensor, an acceleration sensor, a grip sensor, a proximity sensor, a color sensor, an IR (infrared) sensor, a biometric sensor, a temperature sensor, a humidity sensor, or an illuminance sensor.

[0221] The antenna module 762 may include one or more antennas for transmitting or receiving signals or power to or from an external device. According to an embodiment, the communication module 773 may transmit or receive signals to or from an external electronic device through an antenna compatible with a communication method. The antenna pattern of the antenna module 762 may be integrated into one component of the display module 740 (e.g., the display panel 741) or the input sensor 761-2.

[0222] The audio output module 763 may include a speaker for general purposes, such as multimedia playback or recording playback, and a receiver for receiving phone calls, as a device for outputting audio signals to the outside of the electronic device 701. According to an embodiment, the receiver may be formed integrally with the speaker or separately. The audio output pattern of the audio output module 763 may be integrated into the display module 740.

[0223] The camera module 771 can capture still images and videos. According to an embodiment, the camera module 771 can include one or more lenses, image sensors, or image signal processors. The camera module 771 can further include an infrared camera that can measure the presence or absence of a user, the user's position, the user's line of sight, etc.

[0224] The light module 772 can provide light. The light module 772 can include a light emitting diode or a xenon lamp. The light module 772 can operate in conjunction with the camera module 771 or can operate independently.

[0225] The communication module 773 may assist in establishing a wired or wireless communication channel between the electronic device 701 and the external electronic device 702 and communicating through the established communication channel. The communication module 773 may include any one or all of a wireless communication module, such as a cellular communication module, a short-range wireless communication module, or a global navigation satellite system (GNSS) communication module, and a wired communication module, such as a local area network (LAN) communication module or a power line communication module. The communication module 773 may communicate with the external electronic device 702 through a short-range communication network, such as Bluetooth, WiFi Direct, or infrared data association (IrDA), or a long-range communication network, such as a cellular network, the Internet, or a computer network (e.g., a LAN or WAN). The various types of communication modules 773 described above may be implemented on a single chip, or may each be implemented on a separate chip.

[0226] The input module 730 , sensor module 761 , camera module 771 , etc. may be utilized in conjunction with the processor 710 to control the operation of the display module 740 .

[0227] The processor 710 outputs commands or data to the display module 740, the audio output module 763, the camera module 771, or the light module 772 based on input data received from the input module 730. For example, the processor 710 may generate image data in response to input data applied through a mouse, an active pen, or the like, and output the image data to the display module 740, or may generate command data in response to the input data and output the command data to the camera module 771 or the light module 772. If no input data is received from the input module 730 for a certain period of time, the processor 710 may switch the operation mode of the electronic device 701 to a low-power mode or a sleep mode to reduce power consumption by the electronic device 701.

[0228] The processor 710 outputs commands or data to the display module 740, the audio output module 763, the camera module 771, or the light module 772 based on the sensing data received from the sensor module 761. For example, the processor 710 may compare authentication data applied by the fingerprint sensor 761-1 with authentication data stored in the memory 720 and then execute an application according to the comparison result. The processor 710 may execute commands or output corresponding image data to the display module 740 based on sensing data sensed by the input sensor 761-2 or the digitizer 761-3. If the sensor module 761 includes a temperature sensor, the processor 710 may receive temperature data on the measured temperature from the sensor module 761 and further perform brightness correction, etc. on the image data based on the temperature data.

[0229] The processor 710 can receive measurement data on the presence or absence of a user, the user's position, the user's line of sight, etc. from the camera module 771. The processor 710 can further perform brightness correction, etc. on the image data based on the measurement data. For example, the processor 710, which has determined the presence or absence of a user through input from the camera module 771, can output image data, the brightness of which has been corrected through the data conversion circuit 712-2 or the gamma correction circuit 712-3, to the display module 740.

[0230] Some of the components may be connected to each other via a peripheral communication method, such as a bus, a general purpose input / output (GPIO), a serial peripheral interface (SPI), a mobile industry processor interface (MIPI), or an ultra path interconnect (UPI) link, to exchange signals (e.g., commands or data). The processor 710 may communicate with the display module 740 via a mutually agreed-upon interface, and may use, for example, any one of the above-mentioned communication methods, but is not limited to the above-mentioned communication methods.

[0231] The electronic device 701 according to various embodiments disclosed herein can be a device of various forms. The electronic device 701 can include, for example, at least one of a portable communication device (e.g., a smartphone), a computing device, a portable multimedia device, a portable medical device, a camera, a wearable device, or a consumer electronic device. The electronic device 701 according to embodiments of this document is not limited to the aforementioned devices.

[0232] (effect) Although the present invention has been described above with reference to preferred embodiments, it will be understood by those skilled in the art or those with ordinary knowledge in the art that various modifications and changes can be made to the present invention without departing from the spirit and scope of the present invention as defined in the claims below. Therefore, the technical scope of the present invention should not be limited to the contents described in the detailed description of the specification, but should be determined by the claims.

[0233] According to a preferred specific embodiment, it is as follows:

[0234] The background and issues of this case are as follows (i) to (iv).

[0235] (i) Display panels in which light-emitting display elements (LEDs) such as organic light-emitting display elements (OLEDs) or sub-pixels are arranged, and pixel circuits are arranged for each light-emitting display element (LED) or each sub-pixel, are widely used.

[0236] (ii) In each pixel circuit, a data signal for each subpixel is written to the node (N1) of the gate electrode of the driving transistor (T1) during the data write period (AP3). Prior to this, an initialization period (AP1) is performed to initialize this node (N1), and after this, a compensation period (AP2) is performed to initialize the anode of the light-emitting element (ED) and the like (see, for example, Figures 6A and 6B of the present application).

[0237] (iii) To improve image quality, the write rate must be increased to a certain extent, and the length of the data write section (AP3) cannot be made too long.

[0238] (iv) If a voltage higher than the target voltage is applied in order to shorten the time it takes for the node (N1) to be written to reach a predetermined target voltage (in this specific example, the black data voltage), the power consumption will increase.

[0239] According to a specific preferred embodiment, A6 to A7 are set based on the following A1 to A4 or A1 to A5. Also, A8 to A10 are possible. (In particular, Figures 5, 6A, and 6B of the present application, and Figure 14 of Patent Document 1, etc.)

[0240] A1 A storage capacitor Cst is provided between a node (first node N1) of the gate electrode of the driving transistor T1 and a driving voltage power supply (first driving voltage ELVDD).

[0241] A2 The node (second node N2) of the input electrode of the drive transistor (T1) is connected to the output electrode of the write transistor (T2).

[0242] A3 The node (third node N3) of the output electrode of the driving transistor (T1) is connected to the "first node N1" via a compensation transistor ("third transistor T3").

[0243] A4 "first node N1" is connected to the initialization voltage line (VIL) via an initialization transistor ("fourth transistor T4").

[0244] A5 The data write period (AP3) starts after the start of the compensation period (AP2) and ends after the end of the compensation period (AP2) or simultaneously with the end of the compensation period (AP2) (FIGS. 6A and 6B).

[0245] A6: A first boost capacitor (Cbst1) is provided between the 'first node N1' and the gate electrode of the write transistor (T2). At the start of the data write period (AP3), "the potential of the first node N1 can be boosted primarily by the coupling phenomenon" (

[0111] of the present application).

[0246] A7: A second boost capacitor (Cbst2) is provided between the first node N1 and the third node N3. At the end of the data write period (AP3) and the end of the compensation period (AP2), "the potential of the first node N1 can be boosted a second time by the coupling phenomenon." (Applicant's

[0112] )

[0247] A8: The compensation transistor ("third transistor T3") is connected in series with two sub-transistors (T3-1, T3-2), and the intermediate node (GN1) of these sub-transistors (T3-1, T3-2) is connected to the drive voltage power supply (first drive voltage ELVDD) via the "first node capacitor Cn1."

[0248] A9: The initialization transistor ("fourth transistor T4") is connected in series with two sub-transistors (T4-1, T4-2), and the intermediate node (GN2) of these sub-transistors (T4-1, T4-2) is connected to the initialization voltage line (VIL) via the "second node capacitor Cn2".

[0249] A bias signal can be applied to the second node N2 from the bias voltage line (Vbias) through a transistor (eighth transistor T8) that is turned on in response to the black scan signal GBj. [Explanation of symbols]

[0250] Cbst1, Cbst2 boost capacitors CE1, CE2 capacitor electrodes Cn1, Cn2 node capacitors CNE1, CNE2 connection electrode Cst storage capacitor DP display panel ED light emitting element N1 to N3 nodes GN1, GN2 combined node NCE1~NCE4 Node capacitor electrodes PX pixels T1~T8 transistors VL1, VL2 drive voltage lines

Claims

1. a display panel including pixels; The pixel is A light-emitting element; a first transistor connected between the light emitting device and a first driving voltage line and operating in response to a potential of a first node; a second transistor connected between the data line and the first electrode of the first transistor and receiving a first scan signal through a first scan line; a third transistor connected between the first node and the second electrode of the first transistor and receiving a second scan signal through a second scan line; a fourth transistor connected between the first node and a first initialization voltage line and receiving a third scan signal through a third scan line; a storage capacitor connected between the first node and the first driving voltage line; a first boost capacitor connected between the first node and the first scan line; a second boost capacitor connected between the first node and the second scan line.

2. The second boost capacitor 2. The display device of claim 1, comprising a first sub-boost capacitor and a second sub-boost capacitor connected in series between the first node and the second scan line.

3. The third transistor is a first sub-transistor connected between the first node and a first coupling node and receiving the second scan signal through the second scan line; 2. The display device of claim 1, further comprising: a second sub-transistor connected between the first coupling node and the second electrode of the first transistor and configured to receive the second scan signal through the second scan line.

4. The pixel is 4. The display device of claim 3, further comprising a first node capacitor connected between the first coupling node and the first driving voltage line.

5. The fourth transistor is a third sub-transistor connected between the first node and the second coupling node and receiving the third scan signal through the third scan line; 2. The display device of claim 1, further comprising: a fourth sub-transistor connected between the second coupling node and the first initialization voltage line and receiving the third scan signal through the third scan line.

6. The pixel is 6. The display device of claim 5, further comprising a second node capacitor connected between the second coupling node and the first initialization voltage line.

7. The first scan signal is activated during a data write period, The second scan signal is activated during a compensation period, the data write section and the compensation section overlap, each of the data write section and the compensation section is a low level section; The display device of claim 1 , wherein the rising point of the compensation period is the same as or follows the rising point of the data writing period.

8. The pixel is a fifth transistor connected between the first electrode of the first transistor and the first driving voltage line and receiving a light emitting control signal through a light emitting control line; a sixth transistor connected between the second electrode of the first transistor and the light emitting device and receiving the light emitting control signal through the light emitting control line; a seventh transistor connected between the light emitting device and a second initialization voltage line and receiving a fourth scan signal through a fourth scan line; an eighth transistor connected between the first electrode of the first transistor and a bias voltage line and receiving the fourth scan signal through the fourth scan line; The display device according to claim 1 , wherein each of the first to eighth transistors is a LTPS transistor.

9. an element layer including a light-emitting element; a circuit layer including a pixel circuit unit connected to the light emitting device, The circuit layer comprises: a first transistor including a gate electrode coupled to a first node, a first electrode coupled to a second node, and a second electrode coupled to a third node; a second transistor including a gate electrode connected to a first scan line, a first electrode connected to a data line, and a second electrode connected to the second node; a third transistor including a gate electrode connected to a second scan line, a first electrode connected to the third node, and a second electrode connected to the first node; a fourth transistor including a gate electrode connected to a third scan line, a first electrode connected to the first node, and a second electrode connected to a first initialization voltage line; a first capacitor electrode extending from the gate electrode of the first transistor; a second capacitor electrode facing the first capacitor electrode to form a storage capacitor and connected to a first driving voltage line; an additional gate electrode connected to the gate electrode of the first transistor and overlapping the first scan line to form a first boost capacitor; The display device, wherein the additional gate electrode is disposed on a layer different from the gate electrode of the first transistor, the second capacitor electrode, and the first scan line.

10. The circuit layer comprises: a first insulating layer; a first gate pattern layer disposed on the first insulating layer, the first gate pattern layer including the gate electrodes of the first to fourth transistors and the first capacitor electrode; a second insulating layer covering the first gate pattern layer; a second gate pattern layer disposed on the second insulating layer and including the second capacitor electrode; a third insulating layer covering the second gate pattern layer; The display device of claim 9 , further comprising: a third gate pattern layer disposed on the third insulating layer and including the additional gate electrode.

11. The circuit layer comprises: further comprising an auxiliary scan line connected to the second scan line through two or more contact holes; The display device of claim 10 , wherein the auxiliary scan line is disposed on the first insulating layer and is included in the first gate pattern layer.

12. The circuit layer comprises: a fourth insulating layer covering the third gate pattern layer; a first data pattern layer disposed on the fourth insulating layer and including the first to third scan lines and horizontal voltage wirings; 12. The display device of claim 11, wherein the additional gate electrode overlaps the second scan line to form a first sub-boost capacitor and overlaps the auxiliary scan line to form a second sub-boost capacitor.

13. The circuit layer comprises: a fifth insulating layer covering the first data pattern layer; a second data pattern layer disposed on the fifth insulating layer, the second data pattern layer including the data wiring and the vertical voltage wiring; The display device of claim 12 , wherein the vertical voltage wiring is connected to the horizontal voltage wiring to form the first driving voltage line.

14. The third transistor is a first sub-transistor including a gate electrode connected to the second scan line, a first electrode connected to a first junction node, and a second electrode connected to the first node; 10. The display device of claim 9, further comprising: a second sub-transistor including a gate electrode connected to the second scan line, a first electrode connected to the third node, and a second electrode connected to the first junction node.

15. The circuit layer comprises: a semiconductor pattern layer including channel portions of the first to fourth transistors and the first and second electrodes; The display device of claim 14 , wherein the semiconductor pattern layer further comprises a first node capacitor electrode corresponding to the first coupling node.

16. The circuit layer comprises: a first insulating layer covering the semiconductor pattern layer; a first gate pattern layer disposed on the first insulating layer, the first gate pattern layer including the gate electrodes of the first to fourth transistors and the first capacitor electrode; a second insulating layer covering the first gate pattern layer; a second gate pattern layer disposed on the second insulating layer, the second gate pattern layer including the second capacitor electrode and a second node capacitor electrode branched from the second capacitor electrode and overlapping the first node capacitor electrode; a third insulating layer covering the second gate pattern layer; a third gate pattern layer disposed on the third insulating layer and including the additional gate electrode; The display device of claim 15 , wherein the additional gate electrode does not overlap the second node capacitor electrode in a plane.

17. The fourth transistor is a third sub-transistor including a gate electrode connected to the third scan line, a first electrode connected to the first node, and a second electrode connected to a second junction node; and a fourth sub-transistor including a gate electrode connected to the third scan line, a first electrode connected to the first initialization voltage line, and a second electrode connected to the second coupling node.

18. The circuit layer comprises: a semiconductor pattern layer including channel portions of the first to fourth transistors and the first and second electrodes; The display device of claim 17, wherein the semiconductor pattern layer further comprises a third node capacitor electrode corresponding to the second coupling node.

19. The circuit layer comprises: a first insulating layer covering the semiconductor pattern layer; a first gate pattern layer disposed on the first insulating layer, the first gate pattern layer including the gate electrodes of the first to fourth transistors and the first capacitor electrode; a second insulating layer covering the first gate pattern layer; a second gate pattern layer disposed on the second insulating layer, the second gate pattern layer including a fourth node capacitor electrode overlapping the third node capacitor electrode and the second capacitor electrode; a third insulating layer covering the second gate pattern layer; a third gate pattern layer disposed on the third insulating layer and including the additional gate electrode; The display device of claim 18 , wherein the additional gate electrode does not overlap the fourth node capacitor electrode in a plane.

20. a display panel including pixels; a panel driver that drives the display panel; a main processor for providing an image signal to the panel driver; The pixel is A light-emitting element; a first transistor connected between the light emitting device and a first driving voltage line and operating in response to a potential of a first node; a second transistor connected between the data line and the first electrode of the first transistor and receiving a first scan signal through a first scan line; a third transistor connected between the first node and the second electrode of the first transistor and receiving a second scan signal through a second scan line; a fourth transistor connected between the first node and a first initialization voltage line and receiving a third scan signal through a third scan line; a storage capacitor connected between the first node and the first driving voltage line; a first boost capacitor connected between the first node and the first scan line; a second boost capacitor coupled between the first node and the second scan line.

Images