Transistor

Abstract

To provide a transistor having small parasitic capacitance. A transistor with high frequency characteristics is provided. A semiconductor device including the transistor is provided.SOLUTION: An oxide semiconductor, a first conductor, a second conductor, a third conductor, a first insulator, and a second insulator, the first conductor includes a first region where the first conductor and the oxide semiconductor overlap with each other with the first insulator therebetween, a second region where the first conductor and the second conductor overlap with each other with the first insulator and the second insulator therebetween, and a third region where the first conductor and the third conductor overlap with each other with the first insulator and the second insulator therebetween. The oxide semiconductor includes a fourth region where the oxide semiconductor is in contact with the second conductor and a fifth region where the oxide semiconductor is in contact with the third conductor.SELECTED DRAWING: Figure 1

Description

[Technical Field]

[0001] The present invention relates to, for example, a transistor and a semiconductor device, and a method for manufacturing the same. Alternatively, the present invention may be applied to, for example, a display device, a light-emitting device, a lighting device, a power storage device, a storage device, a processor, or a display device, a liquid crystal display device, a light-emitting device, a storage device, The present invention relates to a method for manufacturing an electronic device, a semiconductor device, a display device, a liquid crystal display device, and a light-emitting device. The present invention relates to a memory device and a method for driving an electronic device.

[0002] Note that one embodiment of the present invention is not limited to the above technical fields. The technical field of one aspect relates to an article, a method, or a manufacturing method. One aspect of the present invention is a process, machine, manufacture, or composition. It concerns the matter of matter.

[0003] In this specification and the like, a semiconductor device is a device that can function by utilizing semiconductor characteristics. This refers to a general category of devices, including display devices, light-emitting devices, lighting devices, electro-optical devices, semiconductor circuits, and electronic devices. may have semiconductor devices. [Background technology]

[0004] In recent years, transistors using oxide semiconductors have been attracting attention. Since it can be deposited by a deposition method, it is possible to form semiconductors for transistors that constitute large display devices. In addition, a transistor using an oxide semiconductor can be used in a semiconductor device that uses amorphous silicon. It is possible to improve and use some of the production equipment for transistors using Another benefit is reduced investment.

[0005] Furthermore, a transistor including an oxide semiconductor has an extremely low leakage current in an off state. For example, it is known that the leakage current of a transistor using an oxide semiconductor is low. A low-power CPU that utilizes this characteristic has been disclosed (see Patent Document 1). . [Prior art documents] [Patent documents]

[0006] [Patent Document 1] Japanese Patent Application Laid-Open No. 2012-257187 Summary of the Invention [Problem to be solved by the invention]

[0007] It is an object of the present invention to provide a transistor having small parasitic capacitance. Another object of the present invention is to provide a transistor having good electrical characteristics. Another object of the present invention is to provide a transistor having stable electrical characteristics. Another object of the present invention is to provide a transistor with a small current when off. Another object of the present invention is to provide a novel transistor. Another object is to provide a semiconductor device including the transistor. Another object is to provide a semiconductor device with high operating speed. Another object of the present invention is to provide a semiconductor device. Another object of the present invention is to provide an electronic device including the semiconductor device or the module. One of our goals is to provide the following.

[0008] The description of these problems does not preclude the existence of other problems. It is not necessary for the present invention to solve all of these problems. The above will be made clear from the description, drawings, claims, etc. It is possible to extract other issues from the descriptions in the patent, claims, etc. [Means for solving the problem]

[0009] (1) One embodiment of the present invention is a semiconductor device including an oxide semiconductor, a first conductor, a second conductor, and a third conductor. The first conductor has a first region and a second region. The first region has a first conductive layer through a first insulator and a third region. the second region has a region where the first insulator and the second oxide semiconductor overlap each other; The first conductor and the second conductor have an overlapping region with the insulator interposed therebetween, and the third region The region is formed by connecting the first conductor and the third conductor to each other via the first insulator and the second insulator. the oxide semiconductor has a fourth region and a fifth region, and the fourth region The fifth region has a region where the oxide semiconductor and the second conductor are in contact with each other, and the fifth region has a region where the oxide semiconductor and the second conductor are in contact with each other. This is a transistor having a region where the semiconductor and the third conductor are in contact with each other.

[0010] (2) Alternatively, one embodiment of the present invention is a semiconductor device including a p-channel transistor and an n-channel transistor. and one of the source and drain of the p-channel transistor is an n-channel It is electrically connected to either the source or drain of a p-channel transistor. The gate of the n-channel transistor is electrically connected to the gate of the p-channel transistor. n-channel transistors have silicon in the channel formation region, and n-channel transistors The semiconductor device is the transistor described in (1).

[0011] (3) Alternatively, in one embodiment of the present invention, the p-channel transistor has a top crystal plane of (11 The semiconductor device according to (2) is provided on a silicon substrate having a surface region of (0).

[0012] (4) Alternatively, in one embodiment of the present invention, a channel formation region of a p-channel transistor is The impurity concentration that gives n-type conductivity increases toward the surface. or (3).

[0013] (5) Alternatively, in one embodiment of the present invention, the gate of a p-channel transistor has a work function of 4 The semiconductor device according to any one of (2) to (4) has a conductor having a conductivity of 0.5 eV or more. .

[0014] (6) Alternatively, one embodiment of the present invention is any one of (2) to (5) above, in which the oxide semiconductor contains indium. The semiconductor device according to any one of the above items.

[0015] (7) Alternatively, in one embodiment of the present invention, the oxide semiconductor includes a first oxide semiconductor layer and a second oxide semiconductor layer. a first oxide semiconductor layer and a second oxide semiconductor layer; The oxide semiconductor layer and the third oxide semiconductor layer have overlapping regions (2) to (6). ) is a semiconductor device according to any one of the preceding claims.

[0016] In the semiconductor device according to one embodiment of the present invention, the oxide semiconductor may be replaced with another semiconductor. It's okay. [Effects of the Invention]

[0017] It is possible to provide a transistor with small parasitic capacitance. Alternatively, a transistor having good electrical characteristics can be provided. Alternatively, a transistor with stable electrical characteristics can be provided. Alternatively, a transistor with a small current when turned off can be provided. A transistor can be provided. Alternatively, a semiconductor device having the transistor can be provided. Alternatively, a semiconductor device with high operating speed can be provided. A novel semiconductor device can be provided. Alternatively, an electronic device having the semiconductor device or the module can be provided. can be provided.

[0018] The description of these effects does not preclude the existence of other effects. An embodiment does not necessarily have all of these effects. Effects other than these may be included in the description, This becomes clear from the description, drawings, claims, etc. From any description, it is possible to extract effects other than these. [Brief explanation of the drawings]

[0019] [Figure 1] 1A and 1B are a top view and a cross-sectional view illustrating a transistor according to one embodiment of the present invention. [Figure 2] FIG. 1 is a cross-sectional view illustrating a part of a transistor according to one embodiment of the present invention. [Figure 3] 1A and 1B are a cross-sectional view and a diagram illustrating a band structure of a transistor according to one embodiment of the present invention. [Figure 4] FIG. 1 is a cross-sectional view illustrating a transistor according to one embodiment of the present invention. [Figure 5]1A to 1C are cross-sectional views illustrating a method for manufacturing a transistor according to one embodiment of the present invention. [Figure 6] 1A to 1C are cross-sectional views illustrating a method for manufacturing a transistor according to one embodiment of the present invention. [Figure 7] 1A to 1C are cross-sectional views illustrating a method for manufacturing a transistor according to one embodiment of the present invention. [Figure 8] 1A to 1C are cross-sectional views illustrating a method for manufacturing a transistor according to one embodiment of the present invention. [Figure 9] 1A and 1B are top views and cross-sectional views illustrating a method for manufacturing a transistor according to one embodiment of the present invention. [Figure 10] FIG. 1 is a cross-sectional view illustrating a transistor according to one embodiment of the present invention. [Figure 11] 1A to 1C are cross-sectional views illustrating a method for manufacturing a transistor according to one embodiment of the present invention. [Figure 12] 1A to 1C are cross-sectional views illustrating a method for manufacturing a transistor according to one embodiment of the present invention. [Figure 13] 1A to 1C are cross-sectional views illustrating a method for manufacturing a transistor according to one embodiment of the present invention. [Figure 14] FIG. 1 is a circuit diagram of a semiconductor device according to one embodiment of the present invention. [Figure 15] FIG. 1 is a cross-sectional view illustrating a semiconductor device according to one embodiment of the present invention. [Figure 16] FIG. 1 is a cross-sectional view illustrating a semiconductor device according to one embodiment of the present invention. [Figure 17] FIG. 1 is a cross-sectional view illustrating a semiconductor device according to one embodiment of the present invention. [Figure 18] FIG. 1 is a circuit diagram of a memory device according to one embodiment of the present invention. [Figure 19] FIG. 2 is a block diagram illustrating a CPU according to an embodiment of the present invention. [Figure 20] FIG. 10 is a circuit diagram of a memory element according to one embodiment of the present invention. [Figure 21] 1A and 1B are a top view and a circuit diagram of a display device according to one embodiment of the present invention. [Figure 22] 1A to 1C are diagrams illustrating electronic devices according to one embodiment of the present invention. DETAILED DESCRIPTION OF THE INVENTION

[0020] The embodiments of the present invention will be described in detail with reference to the drawings. The present invention is not limited to the above, and various modifications in form and details can be easily made by those skilled in the art. It is understood that the present invention should not be construed as being limited to the description of the following embodiments. In explaining the configuration of the invention using the drawings, the same symbols are used in different The hatch pattern is used in common between drawings. However, there are cases where no particular symbol is attached.

[0021] In the drawings, the size, thickness of the film (layer), or area is exaggerated for clarity. There may be cases where this is the case.

[0022] In this specification, the shape of an object may be expressed as, for example, a "diameter," a "particle size," a "size," or a "diameter." When specifying the size or width, it is the length of one side of the smallest cube that the object can fit into, or can be read as the equivalent circle diameter in a cross section of an object. refers to the diameter of a perfect circle whose area is equal to the cross section of an object.

[0023] Note that the voltage is the difference between a certain potential and a reference potential (for example, ground potential (GND) or source potential). Therefore, voltage can be replaced with potential. .

[0024] The ordinal numbers such as 1st and 2nd are used for convenience and do not represent the order of processes or stacking. Therefore, for example, "the first" should not be replaced with "the second" or "the third" In addition, the ordinal numbers described in this specification and the like can be replaced with the ordinal numbers. , the ordinal numbers used to identify an aspect of the present invention may not match.

[0025] Even when written as "semiconductor," if the conductivity is sufficiently low, it may be written as "insulator." In addition, the boundary between "semiconductor" and "insulator" is vague, and Therefore, the term "semiconductor" as used herein may be used interchangeably with "insulator." Similarly, the term "insulator" used herein can be interpreted as "semiconductor." " can sometimes be rephrased as ".

[0026] Also, even if a material is written as a "semiconductor," if the material has a sufficiently high conductivity, it may be written as a "conductor." In addition, the boundary between "semiconductor" and "conductor" is vague, and Therefore, the term "semiconductor" as used herein may be used interchangeably with "conductor." Similarly, the term "conductor" used in this specification can be used to refer to a "semiconductor." " can sometimes be rephrased as ".

[0027] The impurities in a semiconductor refer to, for example, substances other than the main components that make up the semiconductor. For example, the concentration Elements with a concentration of less than 0.1 atomic percent are considered impurities. The formation of DOS (Density of State) in the body and the carrier mobility The semiconductor may become an oxide semiconductor, and the crystallinity may decrease. In the case of a semiconductor, impurities that change the properties of the semiconductor include, for example, elements of Group 1 and Group 2. These include elements, group 14 elements, group 15 elements, and transition metals other than the main component, in particular, for example, Hydrogen (also found in water), lithium, sodium, silicon, boron, phosphorus, carbon, nitrogen In the case of oxide semiconductors, for example, oxygen vacancies are formed due to the inclusion of impurities such as hydrogen. In addition, if the semiconductor is a silicon film, there may be some defects that change the properties of the semiconductor. The pure substances include, for example, oxygen, Group 1 elements excluding hydrogen, Group 2 elements, Group 13 elements, and Group 1 elements. Group 5 elements, etc.

[0028] In this specification, when it is stated that A has a region of concentration B, for example, If the concentration in the entire depth direction in the region where A is present is B, then the concentration in the depth direction in the region where A is present is If the average concentration is B, and the median concentration in the depth direction in a region of A is B, In this case, if the maximum concentration in the depth direction in a region where A is present is B, If the minimum concentration in the depth direction is B, the concentration in the depth direction in a region of A is When the value is B, the concentration in the area where the most likely value of A itself can be obtained by measurement is B. Including cases where

[0029] In this specification, A has an area of ​​size B, length B, thickness B, width B or distance B. When describing "to be" in a certain area of ​​A, for example, the overall size, length, thickness, width, or the size, length, thickness, width, or distance of an area of ​​A if the distance is B If the average value of is B, then the size, length, thickness, width, or distance of a certain area of ​​A If the median is B, then the maximum size, length, thickness, width, or distance in a region of A The minimum size, length, thickness, width, or distance in a region of A when the maximum value is B If the value is B, then the convergence value of size, length, thickness, width, or distance in a region of A When B is the size, length, and thickness of the area where the value of A itself can be obtained by measurement This includes cases where the length, width, or distance is B.

[0030] Note that the channel length is, for example, the length of a semiconductor (or transistor) in a top view of a transistor. When the transistor is in the on state, the gate electrode overlaps with the semiconductor (the part where current flows). The source (source region or source voltage) in the region where the The distance between the source and drain (drain region or drain electrode) is In a transistor, the channel length does not necessarily have the same value in all regions. The channel length of each transistor may not be determined to a single value. In the document, the channel length is any one value, maximum value, The minimum or average value.

[0031] The channel width is the width of the semiconductor (or transistor) when it is in the on state. The region where the current flows and the gate electrode overlap, or the region where the channel is formed. The length of the part where the source and drain face each other in the region. In a transistor, the channel width does not necessarily have the same value in all regions. The channel width of each transistor may not be determined to be a single value. In the document, the channel width is defined as any one value, maximum value, or The minimum or average value.

[0032] Depending on the structure of the transistor, the channel in the region where the channel is actually formed may be The effective channel width (hereinafter referred to as the effective channel width) and the The channel width (hereinafter referred to as apparent channel width) may differ from the actual channel width. For example, In a transistor having a three-dimensional structure, the effective channel width is The apparent channel width becomes larger than that shown in For example, in a transistor with a fine, three-dimensional structure, The ratio of the channel region formed on the side of the semiconductor to the channel region formed In this case, the apparent channel width shown in the top view may be larger. The effective channel width where the channel is actually formed is larger than the actual channel width.

[0033] In the case of a transistor having a three-dimensional structure, the effective channel width is measured. For example, it may be difficult to estimate the effective channel width from the design value. In order to obtain this, it is necessary to assume that the shape of the semiconductor is known. If is not known accurately, it is difficult to accurately measure the effective channel width.

[0034] Therefore, in this specification, in a top view of a transistor, a semiconductor and a gate electrode are not mutually connected. The apparent length of the overlapping area where the source and drain face each other The channel width of the In this specification, it is sometimes referred to as "channel width." In some cases, it may refer to the enclosed channel width or apparent channel width. In this specification, when simply referred to as a channel width, it may refer to an effective channel width. The channel length, channel width, effective channel width, apparent channel width, and enclosure The width of the embedded channel can be determined by taking a cross-sectional TEM image and analyzing the image. The value can be determined by

[0035] The field effect mobility of the transistor and the current value per channel width are calculated. In this case, the effective channel width is calculated using the enclosed channel width. The value may differ from that calculated using the channel width.

[0036] In this specification, when it is stated that A has a shape that protrudes more than B, it is not limited to a top view. In the cross-sectional view, at least one end of A is located outside at least one end of B. Therefore, it may be stated that A has a shape that protrudes more than B. For example, in the top view, one end of A is outside one end of B. It can be read as having.

[0037] In this specification, "parallel" means that two straight lines are at an angle of -10° or more and 10° or less. Therefore, it includes the case where the angle is between -5° and 5°. "Perpendicular" means that two straight lines are arranged at an angle of 80° or more and 100° or less. Therefore, it also includes cases where the angle is between 85° and 95°.

[0038] In this specification, when the crystal is a trigonal or rhombohedral crystal, it is expressed as a hexagonal crystal system. .

[0039] <Transistor structure> The structure of a transistor according to one embodiment of the present invention will be described below.

[0040] <Transistor structure 1> 1A and 1B are top views and diagrams of a transistor 490 according to one embodiment of the present invention. 1(A) is a top view, and FIG. 1(B) is a cross-sectional view of the device shown in FIG. 1(A). A1-A2 and a cross-sectional view corresponding to the dashed line A3-A4. In the plan view, some elements are omitted for clarity of illustration.

[0041] In FIG. 1B, a transistor 490 includes an insulator 401 and an insulator 402 on a substrate 400. 402 on the insulator 402, the semiconductor 406 on the insulator 402, and the upper surface of the semiconductor 406. Conductor 416a and conductor 416b having a region in contact with the side surface, and conductor 416a and and an opening that contacts the upper surface of the conductor 416b and reaches the conductor 416a, and an insulator 410 having an opening that reaches the conductor 416a; and a conductor 424a that contacts the conductor 416b through the opening of the insulator 410. the insulator 412 in contact with the upper surface of the semiconductor 406; The conductor 404 is disposed on the insulator 410 and the insulator 412 is disposed on the conductor 404. 08 and has.

[0042] Note that the transistor 490 does not necessarily have to include the insulator 401. The transistor 490 may not have the insulator 402. The transistor 490 may not have the insulator 408. The transistor 490 may not include the conductor 424a. In some cases, the conductor 424b may not be included.

[0043] In FIG. 1B, the conductor 424a is on the insulator 408 of the transistor 490. an insulator 418 having an opening and an opening reaching the conductor 424b; The conductor 426a is in contact with the conductor 424a through the opening, and the insulator 418 is in contact with the conductor 426a through the opening. and conductor 426b in contact with conductor 424b.

[0044] In the transistor 490, the conductor 404 functions as a gate electrode. The insulator 412 functions as a gate insulator. 416b functions as a source electrode and a drain electrode. The resistance of the semiconductor 406 can be controlled by applying a potential to the conductive layer 404. The potential applied to the conductor 404 controls the conduction / non-conduction between the conductor 416a and the conductor 416b. Conduction can be controlled.

[0045] The conductor 404 of the transistor 490 is electrically connected to the conductor 404 via an insulator 410. The area where the conductor 404 and the conductor 416a overlap each other and the area where the conductor 404 and the conductor 416 are connected via the insulator 410 are connected to each other. The transistor 490 has a region where the conductors 404 and 4b overlap each other. 16a, and between the conductor 404 and the conductor 416b, respectively. Therefore, the transistor 490 has a frequency characteristic This results in a high-performance transistor.

[0046] As shown in FIG. 1B, the side surface of the semiconductor 406 is covered with the conductor 416a and the conductor 416b. In addition, the electric field of the conductor 404, which functions as a gate electrode, The electric field of the gate electrode electrically surrounds the semiconductor. The surrounding transistor structure is called the surrounded channel (s-chan This is called a nel structure. Therefore, a channel is formed in the entire (bulk) of the semiconductor 406. In the s-channel structure, a large current flows between the source and drain of the transistor. This allows the current (on-state current) to flow when the semiconductor is conducting. Since 406 is surrounded by the electric field of the conductor 404, the current (O The current (f) can be reduced.

[0047] The transistor 490 has a function of blocking impurities such as hydrogen and oxygen. By surrounding the transistor 490 with an insulator, the electrical characteristics of the transistor 490 can be stabilized. For example, the insulator 401 has a function of blocking impurities such as hydrogen and oxygen. An insulator may be used. In addition, as the insulator 408, a material that blocks impurities such as hydrogen and oxygen may be used. An insulator having a blocking function may be used.

[0048] Examples of insulators that have the function of blocking impurities such as hydrogen and oxygen include boron. element, carbon, nitrogen, oxygen, fluorine, magnesium, aluminum, silicon, phosphorus, chlorine, Argon, Gallium, Germanium, Yttrium, Zirconium, Lanthanum, Neodymium Insulators containing hafnium or tantalum may be used in single or multilayer configurations.

[0049] For example, the insulator 401 may be aluminum oxide, magnesium oxide, or silicon nitride oxide. silicon nitride, gallium oxide, germanium oxide, yttrium oxide, zirconium oxide lanthanum oxide, neodymium oxide, hafnium oxide or tantalum oxide may be used. It is preferable that the insulator 401 contains aluminum oxide or silicon nitride. For example, the insulator 401 may comprise aluminum oxide or silicon nitride, which may result in a semiconductor. It is possible to prevent impurities such as hydrogen from being mixed into 406. The insulating layer 401 has aluminum oxide or silicon nitride, which reduces outward diffusion of oxygen. can be reduced.

[0050] The insulator 408 may be, for example, aluminum oxide, magnesium oxide, or nitride oxide. Silicon, silicon nitride, gallium oxide, germanium oxide, yttrium oxide, dioxide tantalum oxide, lanthanum oxide, neodymium oxide, hafnium oxide, or tantalum oxide may be used. The insulator 408 preferably comprises aluminum oxide or silicon nitride. For example, the insulator 408 may comprise aluminum oxide or silicon nitride. It is possible to prevent impurities such as hydrogen from being mixed into the semiconductor 406. For example, the insulator 408 may comprise aluminum oxide or silicon nitride, which may reduce the outward diffusion of oxygen. This can reduce dispersion.

[0051] The insulator 402 may be, for example, boron, carbon, nitrogen, oxygen, fluorine, magnesium, or aluminum. Aluminum, silicon, phosphorus, chlorine, argon, gallium, germanium, yttrium , zirconium, lanthanum, neodymium, hafnium or tantalum, For example, the insulator 402 may be made of aluminum oxide, aluminum oxide, or aluminum alloy. magnesium oxide, silicon oxide, silicon oxynitride, silicon nitride oxide, silicon nitride, Gallium oxide, germanium oxide, yttrium oxide, zirconium oxide, lanthanum oxide , neodymium oxide, hafnium oxide or tantalum oxide may be used.

[0052] The insulator 402 may have the role of preventing diffusion of impurities from the substrate 400. When the semiconductor 406 is an oxide semiconductor, the insulator 402 supplies oxygen to the semiconductor 406. It can play a role in

[0053] The conductor 416a and the conductor 416b may include, for example, boron, nitrogen, oxygen, fluorine, Silicon, phosphorus, aluminum, titanium, chromium, manganese, cobalt, nickel, copper, Zinc, gallium, yttrium, zirconium, molybdenum, ruthenium, silver, indium Conductors containing one or more of aluminum, tin, tantalum and tungsten are used in a single layer or multilayer. For example, alloys or compounds may be used, and conductors containing aluminum, copper, Conductors containing copper and manganese, conductors containing indium, tin and oxygen Alternatively, a conductor containing titanium and nitrogen may be used.

[0054] The offset region and the offset region are determined by the shape of the ends of the conductors 416a and 416b. - It is possible to create a burlap area.

[0055] The cross-sectional views shown in FIGS. 2A and 2B show that the semiconductor 416a is The angle between the top surface of 06 and the side surface of the conductor 416a is θa, and the end of the conductor 416b 4, the angle formed between the top surface of the semiconductor 406 and the side surface of the conductor 416b is θb. At the end of the conductor 416a and the end of the conductor 416b, θa and θ If b has a range, the angles θa and θb are their mean, median, minimum or maximum values. It shall indicate either of the following.

[0056] In FIG. 2A, the angle θa is large, and the approach of the conductor 416a is greater than the thickness of the insulator 412. Since the amount of projection is small, an offset region Loffa is formed. Similarly, in FIG. 2(A), , the angle θb is large, and the amount of protrusion of the conductor 416b is smaller than the thickness of the insulator 412. Therefore, an offset region Loffb is formed. For example, θa is equal to or greater than 60° and less than 90°. For example, θb may be set to be equal to or greater than 60° and less than 90°. a and Loffb may be the same size or different sizes. For example, Loffa By making Loffb and Loffb equal in size, a semiconductor device having a plurality of transistors 490 can be realized. It is possible to reduce the variations in electrical properties and shape in the By making fb different in size, the electric field concentration occurs in a specific area, which causes a transistor. This may reduce the deterioration of the star 490.

[0057] On the other hand, in FIG. 2B, the angle θa is small, and the thickness of the conductor 416a is larger than the thickness of the insulator 412. Since the amount of protrusion of is large, an overlap area Lova is formed. In B), the angle θb is small, and the amount of protrusion of the conductor 416b is greater than the thickness of the insulator 412. For example, θa is 15° or more, and θb is 6° or more. It is sufficient to set the angle θb to less than 0°, or 20° or more and less than 50°. It is sufficient to set the angle to less than 60°, or 20° or more and less than 50°. For example, if you want to make Lova and Lovb the same size, you can make them different sizes. By adjusting the size, the electrical characteristics and shape of a semiconductor device having a plurality of transistors 490 can be improved. In addition, by making Lova and Lovb different sizes, This reduces the degradation of the transistor 490 due to the concentration of electric field in a specific region. It may be possible.

[0058] It should be noted that even if transistor 490 has both an overlap region and an offset region, For example, by having Lova and Loffb, the on-current can be increased, and This can reduce the deterioration of the transistor 490 due to the electric field concentration in a specific region. This may be possible.

[0059] In the cross-sectional view shown in FIG. 2C, the top surface of the semiconductor 406 and the conductor 416a are in contact with each other at the end of the conductor 416a. The angle formed by the side of the conductor 416a and the semiconductor at the end of the conductor 416b is approximately perpendicular. The angle formed between the top surface of 406 and the side surface of conductor 416b is approximately perpendicular. , the thickness of the insulator 412 is the size of the offset region (Loffa and Loff in FIG. 2(C)). It is written as fb.)

[0060] In the cross-sectional view shown in FIG. 2D, the end of the conductor 416a has a curved surface, and the end of the conductor 416b has a curved surface. The end portions of the conductors 416a and 416b have curved surfaces. This can reduce the electric field concentration at the ends of the conductor 416a and the conductor 416b. Therefore, deterioration of the transistor 490 due to electric field concentration may occur. It may be possible to reduce

[0061] The insulator 410 may be, for example, boron, carbon, nitrogen, oxygen, fluorine, magnesium, or aluminum. Aluminum, silicon, phosphorus, chlorine, argon, gallium, germanium, yttrium , zirconium, lanthanum, neodymium, hafnium or tantalum, For example, the insulator 410 may be made of aluminum oxide, aluminum alloy, or aluminum alloys. magnesium oxide, silicon oxide, silicon oxynitride, silicon nitride oxide, silicon nitride, Gallium oxide, germanium oxide, yttrium oxide, zirconium oxide, lanthanum oxide , neodymium oxide, hafnium oxide or tantalum oxide may be used.

[0062] It is preferable that the insulator 410 has a low relative dielectric constant. 410 is silicon oxide, silicon oxynitride, silicon nitride oxide, silicon nitride or resin Alternatively, the insulator 410 may be made of silicon oxide or oxynitride. It is preferable that the insulating film has a laminated structure of silicon and resin. Silicon is thermally stable, so by combining it with resin, it becomes thermally stable and has a low dielectric constant. The resin can be, for example, polyester, polyolefin, or the like. Fins, polyamide (nylon, aramid, etc.), polyimide, polycarbonate or Acrylic and others.

[0063] The insulator 412 may be, for example, boron, carbon, nitrogen, oxygen, fluorine, magnesium, or aluminum. Aluminum, silicon, phosphorus, chlorine, argon, gallium, germanium, yttrium , zirconium, lanthanum, neodymium, hafnium or tantalum, For example, the insulator 412 may be made of aluminum oxide, aluminum alloy, or aluminum alloys. magnesium oxide, silicon oxide, silicon oxynitride, silicon nitride oxide, silicon nitride, Gallium oxide, germanium oxide, yttrium oxide, zirconium oxide, lanthanum oxide , neodymium oxide, hafnium oxide or tantalum oxide may be used.

[0064] It is preferable that the insulator 412 has a high relative dielectric constant. 412 is a composite of gallium oxide, hafnium oxide, and oxides with aluminum and hafnium. oxide nitrides with aluminum and hafnium, oxide nitrides with silicon and hafnium It is preferred to have an oxide containing silicon and hafnium, or an oxynitride containing silicon and hafnium. Alternatively, the insulator 412 may be a material selected from the group consisting of silicon oxide or silicon oxynitride and a material having a dielectric constant of 0.1 to 0.2. It is preferable to have a laminated structure of silicon oxide and silicon oxynitride. Since SiO2 is thermally stable, it can be used in combination with an insulator with a high dielectric constant. For example, aluminum oxide, gallium oxide, By having hafnium or hafnium oxide on the semiconductor 406 side, silicon oxide or oxynitride can be formed. The silicon contained in the silicon oxide can be prevented from being mixed into the semiconductor 406. In addition, for example, by having silicon oxide or silicon oxynitride on the semiconductor 406 side, , aluminum oxide, gallium oxide or hafnium oxide, and silicon oxide or nitroxide In some cases, trap centers are formed at the interface between the silicon dioxide and the silicon dioxide. By capturing electrons, the threshold voltage of the transistor can be shifted in the positive direction. It may be possible.

[0065] The conductor 404 may be, for example, boron, nitrogen, oxygen, fluorine, silicon, phosphorus, or aluminum. Sodium, titanium, chromium, manganese, cobalt, nickel, copper, zinc, gallium, yttrium Sodium, zirconium, molybdenum, ruthenium, silver, indium, tin, tantalum and A conductor containing one or more of tungsten and silicon may be used in a single layer or a multilayer. Conductors that may be alloys or compounds include aluminum-containing conductors, copper- and titanium-containing conductors, and the like. conductors containing copper and manganese, conductors containing indium, tin and oxygen, or thiamin Conductors containing titanium and nitrogen may also be used.

[0066] The conductor 424a and the conductor 424b may include, for example, boron, nitrogen, oxygen, fluorine, Silicon, phosphorus, aluminum, titanium, chromium, manganese, cobalt, nickel, copper, Zinc, gallium, yttrium, zirconium, molybdenum, ruthenium, silver, indium Conductors containing one or more of aluminum, tin, tantalum and tungsten are used in a single layer or multilayer. For example, alloys or compounds may be used, and conductors containing aluminum, copper, Conductors containing copper and manganese, conductors containing indium, tin and oxygen Alternatively, a conductor containing titanium and nitrogen may be used.

[0067] The conductor 426a and the conductor 426b may include, for example, boron, nitrogen, oxygen, fluorine, Silicon, phosphorus, aluminum, titanium, chromium, manganese, cobalt, nickel, copper, Zinc, gallium, yttrium, zirconium, molybdenum, ruthenium, silver, indium Conductors containing one or more of aluminum, tin, tantalum and tungsten are used in a single layer or multilayer. For example, alloys or compounds may be used, and conductors containing aluminum, copper, Conductors containing copper and manganese, conductors containing indium, tin and oxygen Alternatively, a conductor containing titanium and nitrogen may be used.

[0068] The insulator 418 may be, for example, boron, carbon, nitrogen, oxygen, fluorine, magnesium, or aluminum. Aluminum, silicon, phosphorus, chlorine, argon, gallium, germanium, yttrium , zirconium, lanthanum, neodymium, hafnium or tantalum, For example, the insulator 418 may be aluminum oxide, aluminum oxide, or aluminum alloy. magnesium oxide, silicon oxide, silicon oxynitride, silicon nitride oxide, silicon nitride, Gallium oxide, germanium oxide, yttrium oxide, zirconium oxide, lanthanum oxide , neodymium oxide, hafnium oxide or tantalum oxide may be used.

[0069] It is preferable that the insulator 418 has a low dielectric constant. 418 is silicon oxide, silicon oxynitride, silicon nitride oxide, silicon nitride or resin Alternatively, the insulator 418 may be made of silicon oxide or oxynitride. It is preferable that the insulating film has a laminated structure of silicon and resin. Silicon is thermally stable, so by combining it with resin, it becomes thermally stable and has a low dielectric constant. The resin can be, for example, polyester, polyolefin, or the like. Fins, polyamide (nylon, aramid, etc.), polyimide, polycarbonate or Acrylic and others.

[0070] The semiconductor 406 is preferably an oxide semiconductor. (including silicon), germanium, silicon germanium, silicon carbide, gallium arsenide, Using aluminum gallium arsenide, indium phosphide, gallium nitride, or organic semiconductors There are cases where this is acceptable.

[0071] The structure of an oxide semiconductor will be described below.

[0072] Oxide semiconductors are roughly classified into non-single-crystal oxide semiconductors and single-crystal oxide semiconductors. Oxide semiconductors are CAAC-OS (C Axis Aligned Crystalline Polycrystalline Oxide Semiconductor, Microcrystalline Oxide Semiconductor These include amorphous semiconductors and amorphous oxide semiconductors.

[0073] First, let me explain about CAAC-OS.

[0074] CAAC-OS is one of oxide semiconductors having multiple crystal parts aligned along the c-axis.

[0075] Transmission Electron Microscope (TEM) The CAAC-OS bright-field image and diffraction pattern were analyzed by the IR scope. By observing the high-resolution TEM image, multiple crystalline regions can be identified. On the other hand, high-resolution TEM images also clearly show the boundaries between crystalline parts, i.e., grain boundaries (grain bows). Therefore, CAAC-OS is not able to confirm the grain size. It can be said that the decrease in electron mobility due to magnetic fields is unlikely to occur.

[0076] When a high-resolution TEM image of a cross section of CAAC-OS is observed from a direction roughly parallel to the sample surface, It can be seen that the metal atoms are arranged in layers in the crystalline part. Each layer of metal atoms is The shape reflects the unevenness of the surface on which the CAAC-OS film is formed (also called the surface on which it is formed) or the top surface. The CAAC-OS has a shape similar to that of a crystalline silicon nanotube, and is arranged parallel to the surface on which the CAAC-OS is formed or the upper surface.

[0077] On the other hand, a high-resolution TEM image of the CAAC-OS plane was observed from a direction roughly perpendicular to the sample surface. It was confirmed that the metal atoms in the crystals were arranged in a triangular or hexagonal shape. However, there is no regularity in the arrangement of metal atoms between different crystal parts.

[0078] For CAAC-OS, X-ray diffraction (XRD) equipment For example, the structure of CAAC-OS with InGaZnO4 crystals was analyzed using In the out-of-plane analysis, a peak appears at a diffraction angle (2θ) of approximately 31°. This peak is attributed to the (009) plane of the InGaZnO4 crystal. Therefore, the CAAC-OS crystal has a c-axis orientation, and the c-axis is approximately perpendicular to the surface on which the CAAC-OS is formed or the upper surface. It can be seen that it is facing the right direction.

[0079] In addition, the out-of-plane method of CAAC-OS with InGaZnO4 crystals In the analysis using the method, in addition to the peak at 2θ around 31°, a peak also appears at 2θ around 36°. The peak at 2θ around 36° is due to the presence of a part of the CAAC-OS that has c-axis orientation. This indicates that the CAAC-OS contains crystals that are not crystallized. and preferably does not exhibit a peak at 2θ of around 36°.

[0080] CAAC-OS is an oxide semiconductor with a low concentration of impurities. The impurities are hydrogen, carbon, and silicon. Elements other than the main components of oxide semiconductors, such as silicon and transition metal elements. The elements that bond with oxygen more strongly than the metal elements that make up the oxide semiconductor are By removing oxygen from the oxide semiconductor, the atomic arrangement of the oxide semiconductor is disturbed, which causes a decrease in crystallinity. In addition, heavy metals such as iron and nickel, argon, and carbon dioxide have atomic radii (or molecular radii). Because of their large radius, when they are contained inside an oxide semiconductor, they disrupt the atomic arrangement of the oxide semiconductor. Impurities contained in an oxide semiconductor can cause a decrease in crystallinity. This may be a source of loops or carriers.

[0081] In addition, the CAAC-OS is an oxide semiconductor with a low density of defect states. Oxygen vacancies in the body act as carrier traps or trap hydrogen, which can increase the carrier It can be a source of odor.

[0082] Low impurity concentration and low defect level density (low oxygen vacancies) are called high purity intrinsic or A highly purified or substantially highly purified intrinsic oxide semiconductor is Since there are fewer carrier generation sources, the carrier density can be reduced. The transistor using the oxide semiconductor has electrical characteristics such as a negative threshold voltage ( It is also called marion.) It is rare for it to become high purity genuine or substantially high purity genuine. Oxide semiconductors are highly conductive and have few carrier traps. Such a transistor has little fluctuation in electrical characteristics and is highly reliable. However, it takes a long time for the charges trapped in the carrier traps of the oxide semiconductor to be released. Therefore, the impurity concentration is high and defects are generated. A transistor using an oxide semiconductor with a high density of states may have unstable electrical characteristics. do.

[0083] In addition, transistors using CAAC-OS show changes in their electrical characteristics when irradiated with visible light or ultraviolet light. The fluctuation is small.

[0084] Next, a microcrystalline oxide semiconductor will be described.

[0085] Microcrystalline oxide semiconductors are regions where crystals can be confirmed in high-resolution TEM images. The microcrystalline oxide semiconductor has a region in which no clear crystal part can be identified. The crystal part contained in the crystal is 1 nm or more and 100 nm or less, or 1 nm or more and 10 nm or less. In particular, microcrystals of 1 nm to 10 nm or 1 nm to 3 nm are often present. The oxide semiconductor having nanocrystals (nc) is called nc-OS. (nanocrystalline oxide semiconductor) In addition, the grain boundaries of nc-OS cannot be clearly identified in high-resolution TEM images. There are cases where this happens.

[0086] nc-OS is a material that can be used in microscopic areas (e.g., areas between 1 nm and 10 nm, especially areas between 1 nm and 3 nm). The atomic arrangement is periodic in the region of less than 100 nm. There is no regularity in the crystal orientation between the individual regions. Therefore, no orientation is observed throughout the film. Therefore, depending on the analytical method, nc-OS may be indistinguishable from amorphous oxide semiconductors. For example, an XRD device using X-rays with a diameter larger than the crystal part is used for nc-OS. When structural analysis is performed using the out-of-plane method, peaks indicating crystal planes are observed. In addition, for nc-OS, the probe diameter (e.g., 5 mm) is larger than the crystalline part. When electron diffraction (also called selected area electron diffraction) is performed using an electron beam with a wavelength of 0 nm or more, halo On the other hand, the size of the crystalline part is smaller than that of nc-OS. When nanobeam electron diffraction is performed using an electron beam with a probe diameter close to or smaller than the crystal part, In addition, when nanobeam electron diffraction is performed on nc-OS, a circular spot is observed. In some cases, a bright area (ring-shaped) may be observed. When nanobeam electron diffraction is performed, multiple spots may be observed within a ring-shaped region. do.

[0087] The nc-OS is an oxide semiconductor with higher order than an amorphous oxide semiconductor. The nc-OS has a lower density of defect states than amorphous oxide semiconductors. In the case of nc-OS, there is no regularity in the crystal orientation between different crystal parts. The defect level density is higher than that of C-OS.

[0088] Next, the amorphous oxide semiconductor will be described.

[0089] Amorphous oxide semiconductors are oxides in which the atomic arrangement in the film is irregular and there are no crystalline parts. An example is an oxide semiconductor that has an amorphous state, such as quartz.

[0090] In amorphous oxide semiconductors, no crystalline parts can be observed in high-resolution TEM images.

[0091] When structural analysis is performed on amorphous oxide semiconductors using an XRD device, out-of-plane In the analysis by the ane method, no peaks indicating crystal planes are detected. When electron diffraction is performed on the amorphous oxide semiconductor, a halo pattern is observed. However, when nanobeam electron diffraction is performed, no spots are observed, and a halo pattern is observed. can be.

[0092] Note that the oxide semiconductor has a structure exhibiting physical properties between those of the nc-OS and the amorphous oxide semiconductor. An oxide semiconductor having such a structure is particularly called an amorphous-like oxide semiconductor. (amorphous-like OS:amorphous-like Oxide It is called a semiconductor.

[0093] Amorphous-like OS appears as voids in high-resolution TEM images. In addition, crystals may be clearly observed in high-resolution TEM images. There are areas where crystals can be seen and areas where crystals cannot be seen. The house-like OS crystallizes under the small amount of electron irradiation, which is the same level as observed by TEM. On the other hand, if the nc-OS is of good quality, the TE Crystallization due to the minute amount of electron irradiation observed by M is hardly observed.

[0094] The size of the crystalline parts of amorphous-like OS and nc-OS was measured. This can be done using high-resolution TEM images. For example, InGaZnO4 crystals have a layered structure. It has a structure with two Ga-Zn-O layers between In-O layers. The unit cell of the crystal has three In-O layers and six Ga-Zn-O layers, for a total of nine layers. It has a layered structure in the c-axis direction. Therefore, the spacing between adjacent layers is ( 009) plane lattice spacing (also called d value), and from crystal structure analysis, this value Therefore, focusing on the lattice fringes in high-resolution TEM images, In the area where the lattice spacing is 0.28 nm or more and 0.30 nm or less, The fringes correspond to the ab plane of the InGaZnO4 crystal.

[0095] The oxide semiconductor may be, for example, an amorphous oxide semiconductor or an amorphous-like A stacked film containing two or more of an OS, a microcrystalline oxide semiconductor, and a CAAC-OS good.

[0096] FIG. 3A is an enlarged cross-sectional view of a portion of the transistor 490. The conductor 406 is made up of a semiconductor layer 406a, a semiconductor layer 406b, and a semiconductor layer 406c in this order. This shows a case where a laminated film is laminated on the substrate.

[0097] Regarding semiconductors applicable to the semiconductor layer 406a, the semiconductor layer 406b, the semiconductor layer 406c, etc. I will explain.

[0098] The semiconductor layer 406b is, for example, an oxide semiconductor containing indium. For example, when indium is contained, the carrier mobility (electron mobility) increases. The conductor layer 406b preferably contains the element M. The element M is preferably aluminum, gallium, or the like. Other elements that can be used for M include sodium, yttrium, and tin. are boron, silicon, titanium, iron, nickel, germanium, yttrium, and zirconia. Smoke, molybdenum, lanthanum, cerium, neodymium, hafnium, tantalum, tungste However, there are cases where the element M can be a combination of multiple elements mentioned above. The element M is, for example, an element that has a high bond energy with oxygen. The element M is an element having a higher bond energy than indium. Alternatively, the element M may be, for example, an oxide. It is an element that has the function of widening the energy gap of a semiconductor. 6b preferably contains zinc. When an oxide semiconductor contains zinc, it tends to be easily crystallized. There is.

[0099] However, the semiconductor layer 406b is not limited to an oxide semiconductor containing indium. 406b is an insulator, such as zinc tin oxide, gallium tin oxide, or gallium oxide. oxide semiconductors containing zinc but not containing gallium, oxide semiconductors containing tin, It may also be a compound semiconductor.

[0100] The semiconductor layer 406b is made of, for example, an oxide with a large energy gap. The energy gap of O6b is, for example, 2.5 eV or more and 4.2 eV or less, preferably 2 The value is preferably 0.8 eV or more and 3.8 eV or less, and more preferably 3 eV or more and 3.5 eV or less.

[0101] For example, the semiconductor layer 406a and the semiconductor layer 406c are formed by the oxygen constituting the semiconductor layer 406b. The semiconductor layer 40 is an oxide semiconductor composed of one or more elements other than the above. The semiconductor layer 406a and the semiconductor layer 6b are formed from one or more elements other than oxygen. Since the conductor layer 406c is formed, the interface between the semiconductor layer 406a and the semiconductor layer 406b and An interface state is unlikely to be formed at the interface between the semiconductor layer 406b and the semiconductor layer 406c.

[0102] When the semiconductor layer 406a, the semiconductor layer 406b, and the semiconductor layer 406c contain indium When the semiconductor layer 406a is an In-M-Zn oxide, In and When the sum of M is 100 atomic %, In is preferably less than 50 atomic %. M is 50 atomic % or more, more preferably In is less than 25 atomic %, and M is 7 When the semiconductor layer 406b is an In-M-Zn oxide, When the sum of In and M is 100 atomic %, In is preferably 25 atomic %. c% or more, M is less than 75 atomic %, and more preferably In is 34 atomic % or more. In addition, the semiconductor layer 406c is made of In-M-Zn oxide. When the sum of In and M is 100 atomic %, preferably In is 50 atomic %, M is 50 atomic % or more, and more preferably In is 25 atomic % or more. The semiconductor layer 406c is made of a semiconductor The same oxide as that of layer 406a may be used.

[0103] The semiconductor layer 406b has a larger electron affinity than the semiconductor layer 406a and the semiconductor layer 406c. For example, the semiconductor layer 406b is made of a thin oxide. The electron affinity is 0.07 eV or more and 1.3 eV or less, preferably 0.1 eV or less, than 406c. An oxide having a larger valence of 0.7 eV or less, more preferably 0.15 eV or more and 0.4 eV or less, is used. The electron affinity is the energy difference between the vacuum level and the bottom of the conduction band.

[0104] Indium gallium oxide has a small electron affinity and a high oxygen blocking property. Therefore, the semiconductor layer 406c preferably contains indium gallium oxide. The atomic ratio [Ga / (In+Ga)] is, for example, 70% or more, preferably 80% or more, and More preferably, it is 90% or more.

[0105] However, even if the semiconductor layer 406a and / or the semiconductor layer 406c is made of gallium oxide, For example, when gallium oxide is used for the semiconductor layer 406c, the conductor 416a Alternatively, the leakage current occurring between the conductor 416b and the conductor 404 can be reduced. That is, the off-state current of the transistor 490 can be reduced.

[0106] At this time, when a gate voltage is applied, the semiconductor layer 406a, the semiconductor layer 406b, and the semiconductor layer 4 A channel is formed in the semiconductor layer 406b having a large electron affinity among the semiconductor layers 406a and 406b.

[0107] The band structure corresponding to the dashed line E1-E2 shown in FIG. 3(A) is shown in FIG. 3(B). B) shows the vacuum level (denoted as vacuum level), the energy of the bottom of the conduction band of each layer, The energy at the top of the valence band (denoted as Ev) is shown.

[0108] Here, between the semiconductor layer 406a and the semiconductor layer 406b, there is a semiconductor layer 406a and a semiconductor layer 406b. In some cases, the semiconductor layer 406b and the semiconductor layer 406c are mixed. There may be a mixed region of the semiconductor layer 406b and the semiconductor layer 406c between them. The interface state density is low in the overlap region. The stack of the semiconductor layer 406c and the semiconductor layer 406d has a structure in which energy is continuously distributed near the interfaces of the semiconductor layer 406c and the semiconductor layer 406d. This results in a band structure that changes (also called a continuous junction).

[0109] At this time, the electrons are not in the semiconductor layer 406a and the semiconductor layer 406c but in the semiconductor layer 4 Therefore, the electrons move mainly through the semiconductor layer 406a and the semiconductor layer 406b. Interface state density at the interface, the interface between the semiconductor layer 406b and the semiconductor layer 406c By lowering the level density, the movement of electrons in the semiconductor layer 406b is inhibited. Therefore, the on-state current of the transistor 490 can be increased.

[0110] Note that when the transistor 490 has an s-channel structure, the semiconductor layer 406b Therefore, the thicker the semiconductor layer 406b, the larger the channel region. That is, the thicker the semiconductor layer 406b, the higher the on-state current of the transistor 490. For example, it can be 20 nm or more, preferably 40 nm or more, and more preferably a semiconductor layer 406b having a region with a thickness of 60 nm or more, more preferably 100 nm or more; However, productivity of a semiconductor device including the transistor 490 may decrease. Therefore, for example, it is 300 nm or less, preferably 200 nm or less, and more preferably 15 The semiconductor layer 406b may have a region with a thickness of 0 nm or less.

[0111] In order to increase the on-state current of the transistor 490, the thickness of the semiconductor layer 406c is small. For example, it is less than 10 nm, preferably 5 nm or less, and more preferably 3 The semiconductor layer 406c may have a region of 100 nm or less. The semiconductor layer 406b in which the channel is formed is doped with elements other than oxygen (water) that constitute the adjacent insulator. It has the function of blocking the penetration of elements such as silicon and silicon dioxide. It is preferable that 406c has a certain thickness. For example, it is preferable that it is 0.3 nm or more. a semiconductor layer 406c having a region with a thickness of at least 1 nm, more preferably at least 2 nm; The semiconductor layer 406c may be formed by the outward diffusion of oxygen released from the insulator 402 or the like. In order to suppress diffusion, it is preferable that the material has oxygen blocking properties.

[0112] In order to increase reliability, the semiconductor layer 406a is thick and the semiconductor layer 406c is thin. For example, it is preferably 10 nm or more, more preferably 20 nm or more, and even more preferably 40 If the semiconductor layer 406a has a region with a thickness of 60 nm or more, more preferably 60 nm or more, By increasing the thickness of the semiconductor layer 406a, the adjacent insulator and the semiconductor layer 406a The distance from the interface with the semiconductor layer 406b where the channel is formed can be increased. However, productivity of a semiconductor device having the transistor 490 may decrease. For example, the thickness is 200 nm or less, preferably 120 nm or less, and more preferably 80 nm or less. The semiconductor layer 406a may have the above-mentioned region.

[0113] For example, silicon in an oxide semiconductor can act as a carrier trap or a carrier generation source. Therefore, the lower the silicon concentration of the semiconductor layer 406b, the more preferable. The layer 406b and the semiconductor layer 406a are separated by, for example, secondary ion mass spectroscopy (SIMS). Secondary Ion Mass Spectrometry (1×1) 0 19 atoms / cm 3 Less than 5 x 10 18 atoms / cm 3 Less than, more Preferably 2 x 1018 atoms / cm 3 The silicon concentration is less than 1000 .mu.m. In addition, a 1×10 19 atoms / cm 3 Less than 5 x 10 18 atoms / cm 3 Less than, even more preferred Or 2 x 10 18 atoms / cm 3 The silicon concentration is less than 1000 .mu.m.

[0114] The semiconductor layer 406b has a SIMS value of 2×10 20 atoms / cm 3 below, Preferably 5 x 10 19 atoms / cm 3 Less than 1×10, more preferably 19 atom s / cm 3 Less than 5 × 10, more preferably 18 atoms / cm 3 The hydrogen concentration is as follows: In order to reduce the hydrogen concentration in the semiconductor layer 406b, It is preferable to reduce the hydrogen concentration in the semiconductor layer 406a and the semiconductor layer 406c. The conductor layer 406c has a SIMS value of 2×10 20 atoms / cm 3 The following is preferably is 5 x 10 19 atoms / cm 3 Less than 1×10, more preferably 19 atoms / cm 3 Less than 5 × 10, more preferably 18 atoms / cm 3 The region with the following hydrogen concentration In order to reduce the nitrogen concentration in the semiconductor layer 406b, It is preferable to reduce the nitrogen concentration in the semiconductor layer 406c. In S, 5 x 10 19 atoms / cm 3 Less than 5 x 10 18 atoms / cm 3 Less than 1×10, more preferably 18 atoms / cm 3 More preferably, 5×10 17 atoms / cm 3 The semiconductor layer 406a has a region with the following nitrogen concentration: The semiconductor layer 406c has a SIMS resolution of 5×10 19 atoms / cm 3 less than, Preferably 5 x 10 18 atoms / cm 3 Less than 1×10, more preferably 18 atom s / cm 3 Less than 5 × 10, more preferably 17 atoms / cm 3 The nitrogen concentration is as follows: It has an area.

[0115] Note that when copper is mixed into an oxide semiconductor, electron traps may be generated. The flip-flop may shift the threshold voltage of the transistor in the positive direction. The copper concentration on the surface or inside of the semiconductor layer 406b is preferably as low as possible. Layer 406b, copper concentration 1×10 19 atoms / cm 3 Below, 5 x 10 18 atoms / cm 3 or less, or 1 x 10 18 atoms / cm 3 It is preferable to have a region where: .

[0116] The above-mentioned three-layer structure is an example. For example, a semiconductor layer 406a or a semiconductor layer 406c may be omitted. Alternatively, a two-layer structure may be used. 406c, a semiconductor layer 406a, a semiconductor layer 406b, and a semiconductor layer 406c are provided above or below the semiconductor layer 406a, a semiconductor layer 406b, and a semiconductor layer 406c. Alternatively, a four-layer structure may be used, which includes any one of the semiconductors exemplified above. Above layer 406a, below semiconductor layer 406a, above semiconductor layer 406c, below semiconductor layer 406c The semiconductor layer 406a, the semiconductor layer 406b, and the semiconductor layer 406c are disposed in two or more places. It may also be an n-layer structure (n is an integer of 5 or more) having one of the semiconductors exemplified above. do not have.

[0117] The substrate 400 may be, for example, an insulating substrate, a semiconductor substrate, or a conductive substrate. Examples of insulating substrates include glass substrates, quartz substrates, sapphire substrates, and stabilized zirconia substrates. There are various substrates, such as zirconia substrates (yttria-stabilized zirconia substrates), and resin substrates. The substrate may be, for example, a single semiconductor substrate such as silicon or germanium, or a silicon carbide substrate. Silicon, silicon germanium, gallium arsenide, indium phosphide, zinc oxide, gallium oxide Furthermore, there are compound semiconductor substrates such as silicon. A semiconductor substrate having such a structure, for example, an SOI (Silicon On Insulator) substrate Conductive substrates include graphite substrates, metal substrates, alloy substrates, and conductive resin substrates. Alternatively, there are substrates having metal nitrides, substrates having metal oxides, etc. The substrates include a substrate in which a conductor or a semiconductor is provided on an insulating substrate, a substrate in which a conductor or an insulator is provided on a semiconductor substrate, and There are substrates provided with an edge, and substrates in which a semiconductor or an insulator is provided on a conductive substrate. Alternatively, a substrate having an element provided thereon may be used. Examples of the elements include capacitance elements, resistance elements, switch elements, light-emitting elements, and memory elements.

[0118] A flexible substrate may be used as the substrate 400. The method of providing a transistor is to fabricate a transistor on a non-flexible substrate and then Alternatively, the resistor may be peeled off and transferred to a flexible substrate 400. A peeling layer may be provided between the non-flexible substrate and the transistor. Alternatively, a sheet, film, or foil made of woven fibers may be used. The substrate 400 may be stretchable. Also, the substrate 400 may be designed to retain its original shape when the bending or pulling is stopped. The substrate 4 may have a property of returning to its original shape, or may have a property of not returning to its original shape. 00 is, for example, 5 μm or more and 700 μm or less, preferably 10 μm or more and 500 μm or less, More preferably, the substrate 400 has a region with a thickness of 15 μm or more and 300 μm or less. By thinning the transistor 490, the weight of the semiconductor device including the transistor 490 can be reduced. By making the substrate 400 thin, it is possible to make it stretchable or foldable even when glass or the like is used. It may have the property of returning to its original shape when bending or pulling is stopped. As a result, it is possible to reduce the impact that is applied to the semiconductor device on the substrate 400. Therefore, a robust semiconductor device can be provided.

[0119] The substrate 400, which is a flexible substrate, may be made of, for example, metal, alloy, resin, glass, or The substrate 400, which is a flexible substrate, can be made of a material having a linear expansion coefficient of 1000 kJ / cm. The lower the coefficient of thermal expansion, the more preferable it is because deformation due to the environment is suppressed. For example, the linear expansion coefficient is 1×10 -3 / K or less, 5×10 -5 / K or less, or 1×1 0 -5 The resin may be, for example, polyester, poly Olefin, polyamide (nylon, aramid, etc.), polyimide, polycarbonate, Acrylic, etc. In particular, aramid has a low linear expansion coefficient, making it suitable for flexible substrates. 400 is suitable.

[0120] Note that the transistor 490 has the structure shown in the cross-sectional view of FIG. 4(A) or FIG. 4(B). FIG. 4A shows the structure in which the conductor 413 is provided under the insulator 402, which is different from the structure shown in FIG. 4B, the conductor 413 is electrically connected to the conductor 404. This differs from Figure 4(A).

[0121] The conductor 413 serves as a second gate electrode (also referred to as a backgate electrode) of the transistor 490. For example, the conductor 413 may be connected to a source electrode having a voltage lower or higher than that of the source electrode. A voltage is applied to the transistor 490 to change the threshold voltage in the positive or negative direction. For example, the threshold voltage of the transistor 490 may be changed in a positive direction. By this, even if the gate voltage is 0V, the transistor 490 is in a non-conducting state (off state). In this case, a normally-off state can be realized. It may be variable or fixed.

[0122] The conductor 413 may be, for example, boron, nitrogen, oxygen, fluorine, silicon, phosphorus, or aluminum. Sodium, titanium, chromium, manganese, cobalt, nickel, copper, zinc, gallium, yttrium Sodium, zirconium, molybdenum, ruthenium, silver, indium, tin, tantalum and A conductor containing one or more of tungsten and silicon may be used in a single layer or a multilayer. Conductors that may be alloys or compounds include aluminum-containing conductors, copper- and titanium-containing conductors, and the like. conductors containing copper and manganese, conductors containing indium, tin and oxygen, or thiamin Conductors containing titanium and nitrogen may also be used.

[0123] <Method for fabricating transistor structure 1> A method for manufacturing the transistor 490 shown in FIG. 1 will be described below.

[0124] First, a substrate 400 is prepared.

[0125] Next, the insulator 401 is formed. The insulator 401 can be formed by a sputtering method, a chemical vapor deposition method, or the like. Chemical Vapor Deposition (CVD), molecular beam epitaxy Molecular Beam Epitaxy (MBE) or pulsed laser Pulsed Laser Deposition (PLD), atomic layer deposition ( This can be done using methods such as ALD (Atomic Layer Deposition). can.

[0126] The CVD method is a plasma CVD (PECVD) method that uses plasma. enhanced CVD method, thermal CVD (TCVD) D) method, and photo-CVD (Photo CVD) method, which uses light. Depending on the source gas, metal CVD (MCVD) and metal organic CVD ( MOCVD (Metal Organic CVD) method.

[0127] The plasma CVD method can produce high-quality films at relatively low temperatures. This is a film formation method that can reduce plasma damage to the processed object because it does not use a plasma. For example, wiring, electrodes, elements (transistors, capacitors, etc.) included in a semiconductor device These may become charged up by receiving electric charges from the plasma. The accumulated charge can destroy the wiring, electrodes, elements, etc. contained in the semiconductor device. On the other hand, in the case of thermal CVD, which does not use plasma, such plasma damage is small. In addition, in the thermal CVD method, Since the plasma damage is small, a film with few defects can be obtained.

[0128] The ALD method is also a film formation method that can reduce plasma damage to the workpiece. In addition, the ALD method also produces films with fewer defects because plasma damage during film formation is minimal. can be done.

[0129] The CVD and ALD methods are film formation methods in which particles emitted from a target are deposited. Unlike the conventional method, this is a film formation method in which a film is formed by a reaction on the surface of the object to be treated. This is a film forming method that is less affected by the shape of the workpiece and has good step coverage. The ALD method has excellent step coverage and thickness uniformity, making it suitable for the production of thin films with high aspect ratios. It is suitable for coating the surface of high openings. However, the ALD method has a relatively low film formation rate. Because the deposition rate is slow, it cannot be used in combination with other deposition methods such as CVD, which has a high deposition rate. In some cases this may be preferable.

[0130] In the CVD and ALD methods, the composition of the resulting film can be controlled by the flow rate ratio of the source gases. For example, in the CVD and ALD methods, the flow rate ratio of the source gases can be adjusted to any desired value. In addition, for example, in the CVD method and the ALD method, it is possible to form a film having a composition. By changing the flow rate ratio of the source gases while When forming a film while changing the flow rate ratio of the source gases, multiple film forming chambers can be used. Compared to forming a film by hand, the time required for film formation is shortened by the time required for transport and pressure adjustment. Therefore, the productivity of the semiconductor device can be increased in some cases.

[0131] Next, the insulator 402 is formed (see FIG. 5A). The insulator 402 is formed by sputtering. This can be done using a laser deposition method, a CVD method, an MBE method, a PLD method, an ALD method, or the like. .

[0132] Next, a process for adding oxygen to the insulator 402 may be performed. For example, ion implantation, plasma treatment, etc. are used. The oxygen removed becomes excess oxygen.

[0133] Next, a semiconductor film is formed. The semiconductor film can be formed by a sputtering method, a CVD method, an MBE method, or the like. This can be done using a PLD method, an ALD method, or the like.

[0134] Next, a process for adding oxygen to the semiconductor may be performed. For example, there are ion implantation methods, plasma treatment methods, etc. The oxygen added to the semiconductor is When the semiconductor is a stacked film, the semiconductor layer 406a in FIG. It is preferable to carry out a treatment for adding oxygen to the layer corresponding to the semiconductor to be formed.

[0135] Next, first heat treatment is preferably performed at a temperature of 250° C. or higher and 650° C. or lower. , preferably 450°C or higher and 600°C or lower, and more preferably 520°C or higher and 570°C or lower. The first heat treatment is carried out in an inert gas atmosphere or an oxidizing gas atmosphere containing 10 ppm or more of an oxidizing gas. The first heat treatment is carried out in an atmosphere containing 1% or more or 10% or more of HCl. Alternatively, the first heat treatment may be performed in an inert gas atmosphere, followed by desorbed oxygen. To compensate for this, heating is performed in an atmosphere containing oxidizing gases of 10 ppm or more, 1% or more, or 10% or more. The first heat treatment can be performed to improve the crystallinity of the semiconductor and to remove hydrogen or It can remove impurities such as water.

[0136] Next, the semiconductor is processed by photolithography or the like to form the semiconductor 406 (FIG. 5(B). When the semiconductor 406 is formed, the insulator 402 is also etched. In other words, the insulator 402 may be thin in the area in contact with the semiconductor 406. The shape may have a protrusion.

[0137] Next, a conductive film is formed. The conductive film can be formed by a sputtering method, a CVD method, an MBE method, or the like. This can be done using a PLD method, an ALD method, or the like.

[0138] Next, the conductor is processed by photolithography or the like to form the conductor 416 (FIG. 6(A). Note that the conductor 416 covers the semiconductor 406.

[0139] In the photolithography method, first, the resist is exposed to light through a photomask. The exposed area is then removed or left behind using a developer to form a resist mask. Next, a conductor, a semiconductor, or an insulator is formed by etching through the resist mask. It is possible to process the edges and other parts into the desired shape. For example, KrF excimer laser light, Ar F excimer laser light, EUV (Extreme Ultraviolet) light, etc. A resist mask can be formed by exposing the resist to light. It is also possible to use a liquid immersion technique in which a liquid (for example, water) is filled between the lens and the substrate before exposure. Instead of the light, an electron beam or an ion beam may be used. When a beam is used, a photomask is not required. dry etching such as ashing or / and wet etching. It is possible.

[0140] Next, the insulator 438 is deposited (see FIG. 6B). The insulator 438 is deposited by sputtering. This can be done using a laser deposition method, a CVD method, an MBE method, a PLD method, an ALD method, or the like. The insulator 438 can be formed by a spin coating method, a dipping method, a droplet discharging method (inkjet method), or the like. printing method (screen printing, offset printing, etc.), doctor knife method, This can be done using a roll coater method, a curtain coater method, or the like.

[0141] The insulator 438 is formed to have a flat top surface. For example, the insulator 438 is formed by The top surface may be flat immediately after deposition. Alternatively, for example, the insulator 438 may be formed on a substrate. By removing the insulator from the top surface so that it is parallel to the reference surface such as the back surface of the plate, flatness is achieved. Such a process is called a planarization process. Polishing (CMP: Chemical Mechanical Polishing) processing, However, the upper surface of the insulator 438 does not need to be flat. It's okay.

[0142] Next, the insulator 438 is processed by photolithography or the like, and is later formed into the conductor 416a. and an opening that reaches what will later become conductor 416b. An insulator 439 is formed.

[0143] Next, a conductive film is formed. The conductive film can be formed by a sputtering method, a CVD method, an MBE method, or the like. The conductive material can be formed by the opening of the insulator 439. Therefore, it is preferable to use the CVD method (especially the MCVD method). In addition, in order to improve the adhesion of the conductor formed by the CVD method, it is necessary to form the conductor by the ALD method or the like. It may be preferable to form a laminated film of a deposited conductor and a conductor deposited by CVD. For example, a laminated film in which titanium nitride and tungsten are deposited in this order may be used. .

[0144] Next, the conductor is placed parallel to the reference surface such as the back surface of the substrate so that the conductor remains only in the opening of the insulator 439. The conductor is removed from the upper surface so that a part of the upper surface of the conductor is exposed through the opening of the insulator 439. At this time, the conductor exposed from the opening of the insulator 439 is , and are referred to as conductor 424a and conductor 424b, respectively (see FIG. 7A).

[0145] Next, the insulator 439 is processed by photolithography or the like to form the insulator 410. do.

[0146] Next, the conductor 416 is processed by photolithography or the like to form the conductors 416a and The conductor 416b is formed (see FIG. 7B). The processing of 416 may be performed during the process using a common photolithography method. By sharing the lithography process, the number of steps can be reduced. Therefore, the productivity of a semiconductor device including the transistor 490 can be increased. The insulator 439 and the conductor 416 are processed by different photolithography methods. It is also possible to carry out the process using different photolithography methods. , it may be easier to give each of them an independent shape.

[0147] At this time, the semiconductor 406 is exposed.

[0148] Next, an insulator film is formed. The insulator film can be formed by a sputtering method, a CVD method, an MBE method, or the like. The insulator can be formed by using a PLD method, an ALD method, or the like. A film is formed with a uniform thickness on the side and bottom surfaces of the openings formed in 416a and conductor 416b. Therefore, it is preferable to use the ALD method.

[0149] Next, a conductive film is formed. The conductive film can be formed by a sputtering method, a CVD method, an MBE method, or the like. The conductive material can be formed on the insulator 410 or the like. Therefore, the CVD method (especially the MCVD method) is used. In addition, in order to improve the adhesion of the conductor formed by the CVD method, it is preferable to use ALD. It is preferable to form a laminated film of a conductor formed by a method such as a CVD method and a conductor formed by a CVD method. For example, a laminated film in which titanium nitride and tungsten are deposited in this order may be used. Just use

[0150] Next, the conductor is processed by photolithography or the like to form the conductor 404 .

[0151] Next, the insulator is processed by photolithography or the like to form the insulator 412 (FIG. 8(A).) The conductor and insulator are processed using a common photolithography. It may be performed during the process using the photolithography method. Therefore, the number of steps can be reduced. The productivity of the device can be increased. Alternatively, the processing of the conductor and the processing of the insulator can be performed in different ways. It is also possible to carry out a process using a different photolithography method. By processing them in this way, it may be easier to create independent shapes. In addition, although an example in which the insulator 412 is formed by processing an insulator is shown here, The transistor according to the present embodiment is not limited to this. In some cases, the insulator 412 may be used without being processed.

[0152] Next, an insulator that will become the insulator 408 is formed. This can be done using methods such as CVD, MBE, PLD, and ALD. Cut.

[0153] At some timing after the formation of the insulator that will become the insulator 408, a second heat treatment is performed. By the second heat treatment, excess silicon contained in the insulator 402 or the like can be removed. Since oxygen moves to the semiconductor 406, defects (oxygen vacancies) in the semiconductor 406 are reduced. The second heat treatment is performed to convert excess oxygen (oxygen) in the insulator 402 into the semiconductor 406. For example, the description of the first heat treatment may be referred to. Alternatively, the second heat treatment is preferably performed at a temperature lower than that of the first heat treatment. The temperature difference between the first heat treatment and the second heat treatment is, for example, 20°C or more and 150°C or less, preferably 4°C or less. The temperature is set to 0° C. or higher and 100° C. or lower. This allows excess oxygen (oxygen) to be released from the insulator 402. The second heat treatment can suppress the release of the fluorine. In some cases, this can be achieved by heating during film formation, and therefore this step may not be necessary.

[0154] Next, an insulator that will become the insulator 418 is formed. This can be done using methods such as CVD, MBE, PLD, and ALD. Cut.

[0155] Next, the insulator that will become the insulator 418 is processed by photolithography or the like to form the insulator 4 Form 18.

[0156] Next, the insulator that will become the insulator 408 is processed by photolithography or the like to form the insulator 4 08. Note that the processing of the insulator that will become the insulator 418 and the processing of the insulator that will become the insulator 408 are performed. The processing of the first and second layers may be performed in a common photolithography process. By standardizing the steps using the lithography method, the number of steps can be reduced. Therefore, productivity of a semiconductor device including the transistor 490 can be increased. The processing of the insulator that will become the insulator 418 and the processing of the insulator that will become the insulator 408 are performed using different photolithography techniques. It may be performed by a lithography process. By processing the parts in this way, it may be easier to create independent shapes for each part.

[0157] At this time, the conductors 424a and 424b are exposed.

[0158] Next, a conductive film is formed. The conductive film can be formed by a sputtering method, a CVD method, an MBE method, or the like. This can be done using a PLD method, an ALD method, or the like.

[0159] Next, the conductor is processed by photolithography or the like to form the conductor 426a and the conductor 426b is formed (see FIG. 8(B)).

[0160] In the above manner, the transistor 490 shown in FIG. 1 can be manufactured.

[0161] The transistor 490 determines the size of the offset region or overlap region of each layer. It can be controlled by the thickness and shape. The size of the offset area or overlap area must be smaller than the minimum processing dimension. This makes it easier to miniaturize transistors. In addition, the parasitic capacitance is small, A transistor with high frequency characteristics can be obtained.

[0162] <Transistor structure 2> Hereinafter, a transistor having a different structure from the transistor 490 shown in FIG. 1 etc. will be described. 9(A) and 9(B) are diagrams illustrating a transceiver according to an embodiment of the present invention. 9A and 9B are a top view and a cross-sectional view of the resistor 590. FIG. 9A is a top view. FIG. 9B is a cross-sectional view of the resistor 590. 9(A) and 9(B) are cross-sectional views corresponding to the dashed dotted lines B1-B2 and B3-B4 shown in FIG. In the top view of FIG. 9(A), some elements are omitted for clarity. do.

[0163] In FIG. 9B, a transistor 590 includes an insulator 501 and an insulator 502 on a substrate 500. The insulator 502 on the insulating layer 501, the semiconductor 506 on the insulating layer 502, and the semiconductor 506 are in contact with the upper surface of the insulating layer 502. Conductor 516a and conductor 516b have a region where the conductor 516a and conductor 516b are connected. an insulator 510 in contact with the upper surface of the semiconductor 506; an insulator 512 in contact with the upper surface of the semiconductor 506; A conductor 504 is disposed on a semiconductor 506 via an insulator 512, and a conductor 504 is disposed on an insulator 510 and a conductor 506 is disposed on the insulator 510. and an insulator 508 on the conductive material 504.

[0164] Note that the transistor 590 does not necessarily have to include the insulator 501. The transistor 590 may not have the insulator 502. The resistor 590 may not have the insulator 508 .

[0165] In FIG. 9B, the transistor 590 has an insulator 518 over the insulator 508 . The insulators 518, 508, and 510 have openings that reach the conductor 516a. In addition, the insulator 518, the insulator 508, and the insulator 510 have a conductor 516b. The openings in the insulators 518, 508, and 510 also extend to the The conductor 524a is in contact with the conductor 516a through the insulator 518, the insulator 508, and the and a conductor 524b that contacts the conductor 516b through the opening of the insulator 510, and a conductor 524b that contacts the conductor 516b through the opening of the insulator 510. A conductor 526a is disposed in contact with conductor 4a, and a conductor 526b is disposed in contact with conductor 524b.

[0166] In the transistor 590, the conductor 504 functions as a gate electrode. The insulator 512 functions as a gate insulator. 516b functions as a source electrode and a drain electrode. The resistance of the semiconductor 506 can be controlled by applying a potential to the conductive layer 504. The potential applied to the conductor 504 controls the conduction / non-conduction between the conductor 516a and the conductor 516b. Conduction can be controlled.

[0167] The conductor 504 of the transistor 590 is electrically connected to the conductor 504 via the insulator 510. The area where the conductor 504 and the conductor 516a overlap each other and the area where the conductor 504 and the conductor 516 are connected via the insulator 510 are connected to each other. The transistor 590 has a region where the conductors 504 and 5b overlap each other. 16a, and between the conductor 504 and the conductor 516b, respectively. Therefore, the transistor 590 has a frequency characteristic This results in a high-performance transistor.

[0168] As shown in FIG. 9B, the electric field of the conductor 504 electrically surrounds the semiconductor 506. In other words, it has an s-channel structure. In addition, the off-state current of the transistor can be reduced. In addition, since the conductor 516a and the conductor 516b do not contact the side surfaces of the semiconductor 506, Therefore, the effect of the electric field of the conductor 504 surrounding the semiconductor 506 becomes stronger. The transistor 590 has a structure that makes it easier to take advantage of the s-channel structure than the transistor 490. It is made of

[0169] The transistor 590 has a function of blocking impurities such as hydrogen and oxygen. By surrounding the transistor 590 with an insulator, the electrical characteristics of the transistor 590 can be stabilized. For example, the insulator 501 has a function of blocking impurities such as hydrogen and oxygen. An insulator may be used. In addition, as the insulator 508, a material that blocks impurities such as hydrogen and oxygen may be used. An insulator having a blocking function may be used.

[0170] For the substrate 500, please refer to the description of the substrate 400. For the insulator 502, refer to the description of the insulator 401. For the semiconductor 506, please refer to the description of the semiconductor 406. For the conductor 516a, refer to the description of the conductor 416a. For 516b, refer to the description of the conductor 416b. For details, please refer to the description of the insulator 412. For the insulator 508, please refer to the description of the insulator 404. For the insulator 518, please refer to the description of the insulator 418. For the conductor 524a, see the description of the conductor 424a. For the conductor 524b, refer to the description of the conductor 424b. For the conductor 526a, refer to the description of the conductor 426a. For 526b, refer to the description of conductor 426b.

[0171] Note that the transistor 590 has the structure shown in the cross-sectional view of FIG. 10(A) or FIG. 10(B). 10(A) shows that the conductor 513 is located under the insulator 502, which is different from the structure shown in FIG. 10B, the conductor 513 is electrically connected to the conductor 504. The difference from FIG. 10(A) is that it is connected to

[0172] The conductor 513 is a second gate electrode (also referred to as a back gate electrode) of the transistor 590. For example, the conductor 513 may be connected to a source electrode having a voltage lower or higher than that of the source electrode. A voltage is applied to the transistor 590 to change the threshold voltage in the positive or negative direction. For example, the threshold voltage of the transistor 590 may be changed in a positive direction. By this, even if the gate voltage is 0V, the transistor 590 is in a non-conducting state (off state). In addition, the voltage applied to the conductor 513 is It may be variable or fixed.

[0173] For the conductor 513, refer to the description of the conductor 413.

[0174] <Method for fabricating transistor structure 2> A method for manufacturing the transistor 590 shown in FIGS.

[0175] First, a substrate 500 is prepared.

[0176] Next, the insulator 501 is formed. The insulator 501 can be formed by a sputtering method, a CVD method, or the like. This can be done using the MBE method, PLD method, ALD method, or the like.

[0177] Next, an insulator 502 is formed (see FIG. 11(A)). The insulator 502 is formed by sputtering. The deposition can be performed by a deposition method, a CVD method, an MBE method, a PLD method, an ALD method, or the like. do.

[0178] Next, a process for adding oxygen to the insulator 502 may be performed. For example, ion implantation, plasma treatment, etc. are used. The oxygen removed becomes excess oxygen.

[0179] Next, a semiconductor film is formed. The semiconductor film can be formed by a sputtering method, a CVD method, an MBE method, or the like. This can be done using a PLD method, an ALD method, or the like.

[0180] Next, a process for adding oxygen to the semiconductor may be performed. For example, there are ion implantation methods, plasma treatment methods, etc. The oxygen added to the semiconductor is When the semiconductor is a stacked film, the semiconductor layer 406a in FIG. It is preferable to carry out a treatment for adding oxygen to the layer corresponding to the semiconductor to be formed.

[0181] Next, first heat treatment is preferably performed at a temperature of 250° C. or higher and 650° C. or lower. , preferably 450°C or higher and 600°C or lower, and more preferably 520°C or higher and 570°C or lower. The first heat treatment is carried out in an inert gas atmosphere or an oxidizing gas atmosphere containing 10 ppm or more of an oxidizing gas. The first heat treatment is carried out in an atmosphere containing 1% or more or 10% or more of HCl. Alternatively, the first heat treatment may be performed in an inert gas atmosphere, followed by desorbed oxygen. To compensate for this, heating is performed in an atmosphere containing oxidizing gases of 10 ppm or more, 1% or more, or 10% or more. The first heat treatment can be performed to improve the crystallinity of the semiconductor and to remove hydrogen or It can remove impurities such as water.

[0182] Next, a conductive film is formed. The conductive film can be formed by a sputtering method, a CVD method, an MBE method, or the like. This can be done using a PLD method, an ALD method, or the like.

[0183] Next, the conductor is processed by photolithography or the like to form the conductor 516 .

[0184] Next, the semiconductor is etched through the conductor 516 to form the semiconductor 506 (FIG. 11( When the semiconductor 506 is formed, the insulator 502 is also etched, and a part of the insulator 502 is also etched. That is, the insulator 502 may have a protrusion in the area in contact with the semiconductor 506. The shape may have the following characteristics.

[0185] Next, the insulator 538 is formed (see FIG. 12A). The deposition can be performed by a deposition method, a CVD method, an MBE method, a PLD method, an ALD method, or the like. The insulator 538 can be formed by a spin coating method, a dipping method, a droplet discharging method (inkjet method), or the like. Jet method, printing method (screen printing, offset printing, etc.), doctor knife method, This can be done using a roll coater method or a curtain coater method.

[0186] The insulator 538 may have a flat upper surface.

[0187] Next, the insulator 538 is processed by photolithography or the like to form an insulator 539. do.

[0188] Next, the conductor 516 is processed by photolithography or the like to form the conductors 516a and The conductor 516b is formed (see FIG. 12B). The processing of the body 516 may be performed in a common photolithography process. By sharing the photolithography process, the number of steps can be reduced. Therefore, the productivity of a semiconductor device including the transistor 590 can be increased. Alternatively, the insulator 538 and the conductor 516 may be processed by different photolithography methods. It is also possible to carry out the process by using a different photolithography method. This may make it easier to give each part an independent shape.

[0189] At this time, the semiconductor 506 is exposed.

[0190] Next, an insulator film is formed. The insulator film can be formed by a sputtering method, a CVD method, an MBE method, or the like. The insulator can be formed by a PLD method, an ALD method, or the like. A film is formed with a uniform thickness on the side and bottom surfaces of the openings formed in 516a and conductor 516b. Therefore, it is preferable to use the ALD method.

[0191] Next, a conductive film is formed. The conductive film can be formed by a sputtering method, a CVD method, an MBE method, or the like. The deposition can be performed by using a PLD method, an ALD method, etc. The conductor is formed on an insulator 539, etc. Therefore, the CVD method (especially the MCVD method) is used. In addition, in order to improve the adhesion of the conductor formed by the CVD method, it is preferable to use ALD. It is preferable to form a laminated film of a conductor formed by a method such as a CVD method and a conductor formed by a CVD method. For example, a laminated film in which titanium nitride and tungsten are deposited in this order may be used. Just use

[0192] Next, the conductor is processed by photolithography or the like to form the conductor 504 .

[0193] Next, the insulator is processed by photolithography or the like to form the insulator 512 (FIG. 13(A).) It should be noted that the conductor and insulator are processed using a common photolithography. It may be performed during the photolithography process. Therefore, the number of steps can be reduced. The productivity of the device can be increased. It is also possible to carry out the process using a different photolithography method. When processing by the method makes it easier to create independent shapes In addition, although an example in which the insulator 512 is formed by processing an insulator is shown here, The transistor according to one embodiment of the present invention is not limited to this. In some cases, it may be used as is without processing into the insulator 512.

[0194] Next, an insulator that will become the insulator 508 is formed. This can be done using methods such as CVD, MBE, PLD, and ALD. Cut.

[0195] At some timing after the formation of the insulator that will become the insulator 508, a second heat treatment is performed. By performing the second heat treatment, the excess contained in the insulator 502 and the like can be removed. Since oxygen moves to the semiconductor 506, defects (oxygen vacancies) in the semiconductor 506 are reduced. The second heat treatment is performed to convert excess oxygen (oxygen) in the insulator 502 into the semiconductor 506. For example, the description of the first heat treatment may be referred to. Alternatively, the second heat treatment is preferably performed at a temperature lower than that of the first heat treatment. The temperature difference between the first heat treatment and the second heat treatment is, for example, 20° C. or more and 150° C. or less, preferably The temperature is set to 40° C. or higher and 100° C. or lower. This allows excess oxygen (oxygen) to be released from the insulator 502. The second heat treatment can suppress the release of the In some cases, this can be achieved by heating during film formation, and therefore this step may not be necessary.

[0196] Next, an insulator that will become the insulator 518 is formed. This can be done using methods such as CVD, MBE, PLD, and ALD. Cut.

[0197] Next, the insulator that will become the insulator 518 is processed by photolithography or the like to form the insulator 5 Form 18.

[0198] Next, the insulator that will become the insulator 508 is processed by photolithography or the like to form the insulator 5 08. Note that the processing of the insulator that will become the insulator 518 and the processing of the insulator that will become the insulator 508 are performed. The processing of the first and second layers may be performed in a common photolithography process. By standardizing the steps using the lithography method, the number of steps can be reduced. This can increase the productivity of a semiconductor device including the transistor 590. The processing of the insulator that will become the insulator 518 and the processing of the insulator that will become the insulator 508 are performed using different photolithography techniques. It may be performed by a lithography process. By processing the parts in this way, it may be easier to create independent shapes for each part.

[0199] Next, the insulator 539 is processed by photolithography or the like to form the insulator 510. In addition, the processing of the insulator that will become the insulator 518 and the processing of the insulator that will become the insulator 508 are performed. The processing of the edge 539 may be performed during a common photolithography process. By standardizing the photolithography process, the number of steps can be reduced. Therefore, the productivity of a semiconductor device including the transistor 590 can be increased. Alternatively, the processing of the insulator that will become the insulator 518, the processing of the insulator that will become the insulator 508, and the insulating The processing of the body 539 may be performed by a different photolithography process. By processing the parts using a photolithography process, each part can be made into an independent shape. It may be easier to get angry.

[0200] At this time, the conductors 516a and 516b are exposed.

[0201] Next, a conductive film is formed. The conductive film can be formed by a sputtering method, a CVD method, an MBE method, or the like. The conductive layer can be formed by a PLD method, an ALD method, or the like. The film is formed so as to fill the openings of the insulating material 508 and the insulating material 510. It is preferable to use the MCVD method. In order to achieve this, we have developed a method for stacking a conductor film formed by the ALD method and a conductor film formed by the CVD method. It may be preferable to form a layer film. For example, titanium nitride and tungsten may be formed in this order. A laminated film or the like may be used.

[0202] Next, the insulator 518, the insulator 508, and the insulator 510 are cut so that the conductors remain only in the openings. The conductor is removed from the top surface so that it is parallel to the reference surface such as the back surface of the board. 518, insulator 508, and insulator 510 are exposed only through the openings. At this time, the insulating material 518, the insulating material 508, and the insulating material 510 are exposed to the openings. The exposed conductors are referred to as conductor 524a and conductor 524b, respectively.

[0203] Next, a conductive film is formed. The conductive film can be formed by a sputtering method, a CVD method, an MBE method, or the like. This can be done using a PLD method, an ALD method, or the like.

[0204] Next, the conductor is processed by photolithography or the like to form the conductor 526a and the conductor 526b is formed (see FIG. 13(B)).

[0205] In the above manner, the transistor 590 shown in FIG. 9 can be manufactured.

[0206] The transistor 590 determines the size of the offset region or overlap region of each layer. It can be controlled by the thickness and shape. The size of the offset area or overlap area must be smaller than the minimum processing dimension. This makes it easier to miniaturize transistors. In addition, the parasitic capacitance is small, A transistor with high frequency characteristics can be obtained.

[0207] <Semiconductor device> Hereinafter, a semiconductor device according to one embodiment of the present invention will be described as an example.

[0208] <Circuit> An example of a circuit including a transistor according to one embodiment of the present invention will be described below.

[0209] [CMOS inverter] The circuit diagram shown in FIG. 14A includes a p-channel transistor 2200 and an n-channel transistor 2201. Transistor 2100 is connected in series and each gate is connected, so-called CMO The configuration of the S inverter is shown.

[0210] <Structure of semiconductor device> 15 is a cross-sectional view of the semiconductor device corresponding to FIG. 14(A). The transistor 2200 and the transistor 21 arranged above the transistor 2200 are 00. Note that the transistor 2100 may be the transistor 49 shown in FIG. However, the semiconductor device according to one embodiment of the present invention is not limited to this example. For example, the transistor 490 shown in FIG. 9, the transistor 490 shown in FIG. 9, the transistor 590 shown in FIG. 10(A), 590 or the transistor 590 shown in FIG. 10B, and the like. Therefore, the transistor 2100 may be used as the transistor described above. Please refer to the description of Zista.

[0211] A transistor 2200 shown in FIG. 15 is a transistor using a semiconductor substrate 450 . The transistor 2200 includes a region 474a in the semiconductor substrate 450 and a region 474b in the semiconductor substrate 450. Region 474b, region 470 in semiconductor substrate 450, insulator 462, and conductor 454. , the transistor 2200 may not have the region 470. be.

[0212] In transistor 2200, regions 474a and 474b are source and drain regions. The region 470 functions as a drain region. The region 470 also functions to control the threshold voltage. The insulator 462 also functions as a gate insulator. The conductor 454 functions as a gate electrode. Therefore, the resistance of the channel formation region can be controlled. The conduction / non-conduction between the region 474a and the region 474b can be controlled by the potential. Cut.

[0213] The semiconductor substrate 450 may be, for example, a single semiconductor substrate such as silicon or germanium, or or silicon carbide, silicon germanium, gallium arsenide, indium phosphide, zinc oxide A compound semiconductor substrate such as gallium oxide may be used. A single crystal silicon substrate is used as 50 .

[0214] The semiconductor substrate 450 is a semiconductor substrate containing impurities that impart n-type conductivity. The semiconductor substrate 450 is a semiconductor substrate containing impurities that impart p-type conductivity. In this case, the region that will become the transistor 2200 is given n-type conductivity. Alternatively, even if the semiconductor substrate 450 is an i-type, It's okay.

[0215] The upper surface of the semiconductor substrate 450 preferably has a (110) surface. The ON characteristics of the transistor 2200 can be improved.

[0216] Regions 474a and 474b are regions containing impurities that impart p-type conductivity. In this way, transistor 2200 constitutes a p-channel transistor.

[0217] The region 470 has an impurity concentration that imparts n-type conductivity to the semiconductor substrate 450 or the well. That is, by having region 470, the threshold of transistor 2200 is Therefore, the work function of the conductor 454 can be changed in the negative direction. Even when a highly conductive material is used, it is easy to obtain normally-off electrical characteristics. Conductors often have higher heat resistance than conductors with low work functions, which allows for greater flexibility in subsequent processes. This may increase the performance of the semiconductor device.

[0218] Note that transistor 2200 is separated from adjacent transistors by regions 460 and the like. The region 460 is an insulating region.

[0219] The semiconductor device shown in FIG. 15 includes an insulator 464, an insulator 466, an insulator 468, and a conductor. 480a, conductor 480b, conductor 480c, conductor 478a, and conductor 478b , conductor 478c, conductor 476a, conductor 476b, conductor 416c, and conductor The conductive body 424c and the conductive body 426c.

[0220] The insulator 464 is disposed on the transistor 2200. The insulator 466 is disposed on the insulator 464. 64. Insulator 468 is disposed on insulator 466. The stalk 2100 and the conductor 416c are disposed on the insulator 468.

[0221] The insulator 464 has an opening that reaches the region 474a, an opening that reaches the region 474b, and a conductive The openings have openings that reach the conductor 454. The openings also have conductors 480a, 480b, and 480c, respectively. The conductive material 480b or the conductive material 480c is embedded therein.

[0222] In addition, the insulator 466 has an opening that reaches the conductor 480a and an opening that reaches the conductor 480b. The openings each have a portion that is in contact with the conductor 480c, and an opening that reaches the conductor 480c. 478a, conductor 478b or conductor 478c is embedded therein.

[0223] In addition, the insulator 468 has an opening that reaches the conductor 478b and an opening that reaches the conductor 478c. The openings are filled with a conductor 476a or a conductor 476b. It's embedded.

[0224] The conductor 476a is in contact with the conductor 416b of the transistor 2100. 6b contacts the conductor 416c.

[0225] The insulator 410 has an opening that reaches the conductor 416c. 24c is embedded.

[0226] Insulator 418 and insulator 408 have openings that reach conductor 424c and conductor 404. The conductor 424c and the conductor 404 have openings that reach the respective openings. Electrical connection is made via the opening by conductor 426c.

[0227] The semiconductor device shown in FIG. 16 is the same as the transistor 2200 of the semiconductor device shown in FIG. The only difference is the structure. Therefore, the semiconductor device shown in FIG. Please refer to the description of the semiconductor device. Specifically, the semiconductor device shown in FIG. The transistor 2200 is a Fin type. This increases the effective channel width, improving the on-state characteristics of the transistor 2200. In addition, the contribution of the electric field of the gate electrode can be increased, The off characteristics of the transistor 2200 can be improved.

[0228] 17 is a circuit diagram of the semiconductor device shown in FIG. 15. The only difference is the structure. Therefore, the semiconductor device shown in FIG. Please refer to the description of the semiconductor device. Specifically, the semiconductor device shown in FIG. 17 shows the case where the semiconductor device 200 is provided on an SOI substrate. The structure shown is one in which the region 456 is separated from the semiconductor substrate 450. Therefore, punch-through current and the like can be reduced, and the transistor 2200 is turned off. The insulator 452 insulates a part of the semiconductor substrate 450. For example, the insulator 452 can be formed by densifying silicon oxide. Recons can be used.

[0229] The semiconductor devices shown in FIGS. 15, 16 and 17 are p-channel transistors formed on a semiconductor substrate. The device occupancy is The area can be reduced, that is, the integration degree of the semiconductor device can be increased. The n-channel transistor and the p-channel transistor are formed on the same semiconductor substrate. Since the process can be simplified compared to when the semiconductor device is manufactured by the conventional method, the productivity of the semiconductor device can be improved. Furthermore, the yield of the semiconductor device can be increased. The channel transistor has an LDD (Lightly Doped Drain) region, In some cases, complex processes such as shallow trench structures and distortion design can be omitted. Compared to fabricating a channel transistor using a semiconductor substrate, productivity and yield are improved. It may be possible to increase retention.

[0230] [CMOS analog switch] The circuit diagram shown in FIG. 14B is that of the transistor 2100 and the transistor 2200. The figure shows a configuration in which the source and drain of each transistor are connected. It can function as a so-called CMOS analog switch.

[0231] [Example of storage device] A transistor according to one embodiment of the present invention is used to retain stored contents even when power is not supplied. An example of a semiconductor device (memory device) that can be stored and has no limit on the number of times it can be written is shown in FIG. Shown below.

[0232] The semiconductor device shown in FIG. 18A includes a transistor 3200 using a first semiconductor and a second The semiconductor device includes a transistor 3300 and a capacitor 3400. The transistor 3300 can be any of the transistors described above.

[0233] The transistor 3300 is a transistor including an oxide semiconductor. The low off-state current of 00 allows the stored contents to remain in a specific node of the semiconductor device for a long period of time. This means that no refresh operation is required or that This makes it possible to reduce the frequency of flash operations to a minimum, resulting in a semiconductor device with low power consumption. This becomes:

[0234] In FIG. 18A, a first wiring 3001 is electrically connected to the source of a transistor 3200. The second wiring 3002 is electrically connected to the drain of the transistor 3200. The third wiring 3003 is electrically connected to one of the source and drain of the transistor 3300. The fourth wiring 3004 is electrically connected to the gate of the transistor 3300. The gate of the transistor 3200 and the source of the transistor 3300 are connected to each other. The other of the drains is electrically connected to one of the electrodes of the capacitor 3400 and is connected to the fifth wiring 30 05 is electrically connected to the other electrode of the capacitor 3400 .

[0235] The semiconductor device illustrated in FIG. 18A can hold the potential of the gate of the transistor 3200. This property makes it possible to write, store, and read information, as shown below. do.

[0236] Writing and holding of information will be described. First, the potential of the fourth wiring 3004 is changed by a transistor. The transistor 3300 is set to a potential at which it becomes conductive, thereby making the transistor 3300 conductive. As a result, the potential of the third wiring 3003 is applied to the gate of the transistor 3200 and the capacitor The voltage is applied to a node FG electrically connected to one of the electrodes of the capacitor 3400. A predetermined charge is applied to the gate of the register 3200 (write). Charges that give two potential levels (hereinafter referred to as low-level charge and high-level charge) Then, the potential of the fourth wiring 3004 is applied to the transistor. The transistor 3300 is set to a potential at which it is in a non-conductive state, thereby making the transistor 3300 in a non-conductive state. As a result, the charge is held at the node FG (retention).

[0237] Since the off-state current of the transistor 3300 is extremely small, the charge of the node FG is maintained for a long period of time. It is held as such.

[0238] Next, the reading of information will be described. A predetermined potential (constant potential) is applied to the first wiring 3001. In this state, when an appropriate potential (read potential) is applied to the fifth wiring 3005, 3002 takes a potential according to the amount of charge held in the node FG. If 3200 is an n-channel type, a high level charge is applied to the gate of transistor 3200. The apparent threshold voltage V th_H is the transistor 3200 Apparent threshold voltage V when low-level charge is applied to the gate th_L Yo Here, the apparent threshold voltage is the voltage at which the transistor 3200 is This refers to the potential of the fifth wiring 3005 required to make it "conductive." The potential of the fifth wiring 3005 is V th_H and V th_L By setting the potential V0 between For example, in a write operation, the charge applied to node FG can be determined. When a high level charge is applied to the fifth wiring 3005, the potential of the fifth wiring 3005 becomes V0 (> V th_H ), transistor 3200 is in a "conducting state." Meanwhile, node FG When a low level charge is applied to the fifth wiring 3005, the potential of the fifth wiring 3005 becomes V0 ( <V th_L ), transistor 3200 remains in a "non-conducting state." By determining the potential of the second wiring 3002, the data stored in the node FG is read. You can put it out.

[0239] When memory cells are arranged in an array, the information of the desired memory cell is read. In order to prevent the information of other memory cells from being read, A potential at which transistor 3200 is in a "non-conducting state" regardless of the charge applied to FG. , that is, V th_H A lower potential may be applied to the fifth wiring 3005. The potential at which transistor 3200 is in a "conducting state" regardless of the charge applied to the FG. , that is, V th_L A higher potential may be applied to the fifth wiring 3005 .

[0240] The semiconductor device shown in FIG. 18B differs from the semiconductor device shown in FIG. 18A in that it does not include the transistor 3200. In this case, the operation is the same as that of the semiconductor device shown in FIG. This makes it possible to write and retain information.

[0241] The reading of data from the semiconductor device shown in FIG. When the capacitor 3300 is brought into a conductive state, the third wiring 3003 and the capacitor element 3400, which are in a floating state, The third wiring 3003 and the capacitor 3400 are electrically connected to each other, and charge is redistributed between the third wiring 3003 and the capacitor 3400. As a result, the potential of the third wiring 3003 changes. The amount of change in the potential of the third wiring 3003 is determined by the capacitance The potential of one of the electrodes of the element 3400 (or the charge stored in the capacitor element 3400) , take different values.

[0242] For example, the potential of one electrode of the capacitor 3400 is V, the capacitance of the capacitor 3400 is C, and the third The capacitance component of the third wiring 3003 before the charge is redistributed is CB. If the potential is VB0, the potential of the third wiring 3003 after the charge is redistributed is (CB× Therefore, the state of the memory cell is If the potential of one of the 3400 electrodes takes two states, V1 and V0 (V1>V0), then: The potential of the third wiring 3003 when the potential V1 is maintained (=(CB×VB0+CV1) / (CB+C)) is the potential (=(C It can be seen that this is higher than B×VB0+CV0) / (CB+C)).

[0243] Then, the potential of the third wiring 3003 is compared with a predetermined potential, thereby reading out information. can be done.

[0244] In this case, the transistor to which the first semiconductor is applied is used in a drive circuit for driving the memory cell. A transistor to which a second semiconductor is applied is used as the transistor 3300. The structure may be such that the electrodes are stacked on the drive circuit.

[0245] The semiconductor device described above is a transistor using an oxide semiconductor and having extremely low off-state current. By applying this, it is possible to retain the memory contents for a long period of time. Refresh operations are no longer necessary, or the frequency of refresh operations can be reduced significantly. Therefore, a semiconductor device with low power consumption can be realized. Even if there is no potential (however, it is preferable that the potential is fixed), It is possible to retain the stored contents.

[0246] Furthermore, since the semiconductor device does not require a high voltage to write information, deterioration of the elements does not occur. For example, unlike conventional nonvolatile memory, injection of electrons into the floating gate Since electrons are not introduced or extracted from the floating gate, there is no risk of insulator degradation. That is, the semiconductor device according to one embodiment of the present invention does not cause the above problem. There is no limit to the number of times it can be rewritten, which is a problem with semiconductors, and reliability has been dramatically improved. Furthermore, information can be written depending on whether the transistor is conductive or non-conductive. This allows for high-speed operation.

[0247] <cpu> The following describes a CPU including semiconductor devices such as the above-mentioned transistors and the above-mentioned memory devices. and explain.

[0248] FIG. 19 is a block diagram showing the configuration of an example of a CPU that uses the above-mentioned transistor in part. be.

[0249] The CPU shown in FIG. 19 includes an ALU 1191 (ALU: Arithmetic) on a board 1190. ic logic unit, arithmetic circuit), ALU controller 1192, instruction tion decoder 1193, interrupt controller 1194, timing controller 1195, register 1196, register controller 1197, bus interface 1 198, rewritable ROM 1199, and ROM interface 1189 The substrate 1190 may be a semiconductor substrate, an SOI substrate, a glass substrate, or the like. 199 and the ROM interface 1189 may be provided on separate chips. The CPU shown in Figure 19 is merely an example of a simplified configuration. There are various configurations depending on the application. For example, the CPU or arithmetic circuit shown in Figure 19 A configuration including the above is considered as one core, and multiple cores are included, and each core operates in parallel. The number of bits that the CPU can handle in the internal arithmetic circuit and data bus is For example, it can be 8 bits, 16 bits, 32 bits, 64 bits, etc.

[0250] The instructions input to the CPU via the bus interface 1198 are After being input to the decoder 1193 and decoded, the ALU controller 1192 Rupture controller 1194, register controller 1197, timing controller It is entered into 1195.

[0251] ALU controller 1192, interrupt controller 1194, register controller The timing controller 1197 and the timing controller 1195 control various Specifically, the ALU controller 1192 controls the operation of the ALU 1191. The interrupt controller 1194 also generates signals for the CPU program. During system execution, interrupt requests from external I / O devices and peripheral circuits are handled according to their priority and mask. The register controller 1197 determines the address of the register 1196 and processes it. It generates a response and reads or writes to register 1196 depending on the state of the CPU.

[0252] The timing controller 1195 controls the ALU 1191 and the ALU controller 119 2, an instruction decoder 1193, an interrupt controller 1194, and It generates a signal to control the timing of the operation of the register controller 1197. The timing controller 1195 generates an internal clock signal based on the reference clock signal. The internal clock generator supplies an internal clock signal to the various circuits.

[0253] In the CPU shown in FIG. 19, a register 1196 is provided with a memory cell. The above-mentioned transistors and memory devices can be used as the memory cells of 1196. do.

[0254] In the CPU shown in FIG. 19, the register controller 1197 receives the data from the ALU 1191. According to the instruction, the holding operation is selected in the register 1196. That is, the register 1196 In the memory cell of the Select whether to hold data by flip-flop. If the power supply voltage is set to 0, the power supply voltage is supplied to the memory cells in the register 1196. If data retention in the capacitor is selected, the data is rewritten to the capacitor. This allows the supply of power supply voltage to the memory cells in the register 1196 to be stopped.

[0255] FIG. 20 is a circuit diagram of an example storage element 1200 that can be used as the register 1196. The memory element 1200 includes a circuit 1201 in which stored data is volatilized when the power is cut off, and a circuit 1202 in which stored data is volatilized when the power is cut off. A circuit 1202 that prevents stored data from volatilizing when turned off, a switch 1203, and a switch 1204. , a logic element 1206, a capacitor 1207, and a circuit 1220 having a selection function. The circuit 1202 includes a capacitor 1208, a transistor 1209, and a transistor 1210. 10. The memory element 1200 may include a diode, a resistor, It may further include other elements such as an inductor.

[0256] Here, the above-described memory device can be used for the circuit 1202. When the supply of power supply voltage to the ND (0V) or a potential that turns off the transistor 1209 is continuously input. For example, the gate of the transistor 1209 is configured to be grounded via a load such as a resistor. .

[0257] The switch 1203 uses a transistor 1213 of one conductivity type (for example, n-channel type). The switch 1204 is configured as a transistor of a conductivity type opposite to the one conductivity type (for example, a p-channel type). An example using a transistor 1214 is shown. Here, the first terminal of the switch 1203 The input corresponds to one of the source and drain of the transistor 1213, and the second input of the switch 1203. The terminal of corresponds to the other of the source and drain of the transistor 1213, and the switch 1203 A control signal RD input to the gate of the transistor 1213 switches the first terminal and the second terminal Conduction or non-conduction between the terminals (i.e., the conducting or non-conducting state of transistor 1213) The first terminal of the switch 1204 is connected to the source and drain of the transistor 1214. The second terminal of the switch 1204 corresponds to one of the drains of the transistor 1214. The switch 1204 is connected to the gate of the transistor 1214. The control signal RD input to the first terminal determines whether or not the first terminal is electrically connected to the second terminal. The conducting or non-conducting state of transistor 1214 is selected.

[0258] One of the source and drain of the transistor 1209 is connected to a pair of electrodes of the capacitor 1208. The connection point is electrically connected to one of the gate electrodes of the transistor 1210 and the gate of the transistor 1210. The node M2 ​​is connected to the source or drain of the transistor 1210. The other is electrically connected to a wiring (for example, a GND line) that can supply 1203 (one of the source and drain of the transistor 1213) The second terminal of the switch 1203 (the source and drain of the transistor 1213) is connected to the The other terminal of the switch 1204 (one of the source and drain terminals of the transistor 1214) The second terminal of the switch 1204 (the source of the transistor 1214) is electrically connected to the The other of the source and drain terminals is electrically connected to the wiring that can supply the power supply potential VDD. The second terminal of the switch 1203 (the other of the source and drain of the transistor 1213) ) and the first terminal of the switch 1204 (one of the source and drain of the transistor 1214) ), an input terminal of the logic element 1206, and one of a pair of electrodes of the capacitor 1207. are electrically connected. Here, the connection point is referred to as node M1. The other of the electrodes may be configured to have a constant potential input thereto. It can be configured so that a power supply potential (GND, etc.) or a high power supply potential (VDD, etc.) is input. The other of the pair of electrodes of the capacitor 1207 is connected to a line that can supply a low power supply potential. The other of the pair of electrodes of the capacitor 1208 is electrically connected to a line (for example, a GND line). For example, a low power supply potential (such as GND) can be input. ) or a high power supply potential (such as VDD) can be input to the capacitor element 120. The other of the pair of electrodes 8 is connected to a wiring (e.g., GND) that can supply a low power supply potential. The power supply is electrically connected to the power supply line.

[0259] The capacitors 1207 and 1208 are used to reduce the parasitic capacitance of transistors and wirings. It is possible to omit it by actively using it.

[0260] A control signal WE is input to the gate of the transistor 1209. The switch 1204 is connected between the first terminal and the second terminal by a control signal RD that is different from the control signal WE. The conduction or non-conduction state between the first and second terminals of one switch is selected. When the terminals of one switch are in a conductive state, the first and second terminals of the other switch are in a non-conductive state. This becomes:

[0261] The other of the source and drain of the transistor 1209 is connected to a data line held in the circuit 1201. In FIG. 20, the signal output from the circuit 1201 is The example shown is input to the other of the source and drain of the switch 1203. The signal output from the second terminal (the other of the source and drain of the transistor 1213) is The logic value is inverted by the logic element 1206 to become an inverted signal, and is output via the circuit 1220. and input to the circuit 1201.

[0262] In FIG. 20, the second terminal of the switch 1203 (the source and drain of the transistor 1213) The signal output from the other of the two trains is routed through logic element 1206 and circuit 1220. The example shown is an input to the circuit 1201, but is not limited to this. The signal output from the other of the source and drain of the transistor 1213 is inverted. For example, the following may be included in the circuit 1201: When there is a node that holds a signal whose logical value is the inverse of the signal input from the input terminal The second terminal of the switch 1203 (the other of the source and drain of the transistor 1213) A signal output from the node can be input to the node.

[0263] In addition, in FIG. 20, among the transistors used in the memory element 1200, The transistors other than the transistor 1209 are made of a film or a substrate 119 made of a semiconductor other than an oxide semiconductor. For example, a transistor in which a channel is formed in a silicon film or The transistor may have a channel formed in a silicon substrate. All transistors used in 1200 are transistors whose channels are formed of oxide semiconductors. Alternatively, the memory element 1200 may include other elements in addition to the transistor 1209. The other transistors may include a transistor in which the channel is formed of an oxide semiconductor. The transistor has a channel formed in a layer or substrate 1190 made of a semiconductor other than an oxide semiconductor. It may also be a transistor.

[0264] For example, a flip-flop circuit can be used as the circuit 1201 in FIG. The logic element 1206 may be, for example, an inverter or a clocked inverter. It is possible.

[0265] In the semiconductor device according to one embodiment of the present invention, while power supply voltage is not supplied to the memory element 1200, The data stored in the circuit 1201 is transferred to the capacitor 1208 in the circuit 1202. It can be held by

[0266] In addition, a transistor in which a channel is formed in an oxide semiconductor has an extremely small off-state current. For example, the off-state current of a transistor in which a channel is formed in an oxide semiconductor is The off-state current is significantly lower than that of transistors whose channels are formed in silicon. By using this transistor as the transistor 1209, the memory element 120 The signal held in the capacitor 1208 is maintained for a long period of time even when power supply voltage is not supplied to the capacitor 1208. In this way, the storage element 1200 maintains its stored contents (data) even when the supply of power supply voltage is stopped. ) can be held.

[0267] Furthermore, by providing the switches 1203 and 1204, the precharge operation Since the memory element is characterized by performing the above operation, after the power supply voltage is restarted, the circuit 1201 This reduces the time required to restore the original data.

[0268] In the circuit 1202, the signal held by the capacitor 1208 is Therefore, the supply of the power supply voltage to the memory element 1200 is resumed. After that, the signal held by the capacitor element 1208 is transferred to the state ( The signal can be converted into a conducting state or a non-conducting state and read out from the circuit 1202. Therefore, even if the potential corresponding to the signal held in the capacitor element 1208 fluctuates slightly, the original signal It is possible to read out the number accurately.

[0269] Such a storage element 1200 may be used as a register or cache memory of a processor. By using it in a storage device, it is possible to prevent the loss of data in the storage device due to a power supply interruption. In addition, after the supply of power voltage is resumed, the state before the power supply was stopped can be restored in a short time. Therefore, the entire processor, or one or more components of the processor, can stop power supply for a short time in multiple logic circuits, reducing power consumption. It can be suppressed.

[0270] Although the storage element 1200 has been described as being used in a CPU, the storage element 1200 can also be used in a DSP ( Digital Signal Processor), custom LSI, PLD (Pr LSIs such as programmable logic devices, RF-IDs (Radio Frequency Identification It can also be applied to RF Frequency Identification.

[0271] <Display device> A configuration example of a display device according to one embodiment of the present invention will be described below.

[0272] [Configuration example] FIG. 21A shows a top view of a display device according to one embodiment of the present invention. In the display device according to one embodiment of the present invention, a pixel circuit is provided in which a liquid crystal element is used for a pixel. 21C shows a display device according to one embodiment of the present invention in which an organic EL element is used in a pixel. 1 shows a pixel circuit when the pixel circuit is used.

[0273] The transistor used in the pixel can be any of the above-described transistors. An example using an n-channel transistor is shown. A transistor manufactured through one process may be used as a driver circuit. By using the above-mentioned transistors in the element and the driving circuit, high display quality and / or This results in a highly reliable display device.

[0274] An example of an active matrix display device is shown in FIG. On the top, there are a pixel section 5001, a first scanning line driving circuit 5002, a second scanning line driving circuit 5003, and a 3, a signal line driver circuit 5004 is disposed. The pixel portion 5001 receives signals through a plurality of signal lines. The first scanning line driver circuit 5004 is electrically connected to the first scanning line driver circuit 5005 and is driven by a plurality of scanning lines. The scanning line driver circuit 5002 and the second scanning line driver circuit 5003 are electrically connected. Pixels each having a display element are arranged in the areas separated by the signal lines. In addition, the substrate 5000 of the display device is made of FPC (Flexible Printed Circuit). A timing control circuit (also called a controller or control IC) is connected to the The power supply is electrically connected to the power supply.

[0275] The first scanning line driver circuit 5002, the second scanning line driver circuit 5003 and the signal line driver circuit 5 004 is formed on the same substrate 5000 as the pixel portion 5001. The cost of manufacturing the display device can be reduced compared to when the display device is manufactured by using a drive circuit. If a separate operating circuit is created, the number of connections between the wiring will increase. By providing a driver circuit in the and / or yield can be improved.

[0276] [Liquid crystal display device] An example of the circuit configuration of a pixel is shown in FIG. 21(B). 1 shows a pixel circuit that can be applied to a pixel such as a liquid crystal display (LCD).

[0277] This pixel circuit can be applied to a configuration in which one pixel has multiple pixel electrodes. The electrodes are connected to different transistors, and each transistor can be driven by a different gate signal. This allows the individual pixel electrodes of the multi-domain designed pixels to The signals applied to the electrodes can be controlled independently.

[0278] The scanning line 5012 of the transistor 5016 and the scanning line 5013 of the transistor 5017 , are separated so that different gate signals can be applied. is commonly used in the transistor 5016 and the transistor 5017. The above-described transistors can be used as the capacitor 5016 and the transistor 5017 as appropriate. This provides a liquid crystal display device with high display quality and / or high reliability. can be done.

[0279] The transistor 5016 is electrically connected to a first pixel electrode. The second pixel electrode is electrically connected to the first pixel electrode 017. The shapes of the first pixel electrode and the second pixel electrode are not particularly limited. For example, the first pixel electrode may be V-shaped.

[0280] The gate electrode of the transistor 5016 is electrically connected to the scanning line 5012. The gate electrode of 5017 is electrically connected to the scanning line 5013. By applying different gate signals to the scan line 5013, the transistors 5016 and 5017 By varying the operation timing of the two, the orientation of the liquid crystal can be controlled.

[0281] Also, a capacitance line 5010, a gate insulator acting as a dielectric, and a first pixel electrode or A capacitor element may be formed by a capacitor electrode electrically connected to the second pixel electrode.

[0282] The multi-domain structure has a first liquid crystal element 5018 and a second liquid crystal element 5019 in one pixel. The first liquid crystal element 5018 is composed of a first pixel electrode, a counter electrode, and a liquid crystal layer therebetween. The second liquid crystal element 5019 is composed of a second pixel electrode, a counter electrode, and a liquid crystal layer therebetween. do.

[0283] Note that a display device according to one embodiment of the present invention is not limited to the pixel circuit shown in FIG. For example, if a switch, a resistor, a capacitor, a transistor, etc. are newly added to the pixel circuit shown in FIG. 21(B), Additional components such as sensors, logic circuits, etc. may be added.

[0284] [Organic EL display device] Another example of the circuit configuration of a pixel is shown in Figure 21(C). 1 shows the pixel structure of the device.

[0285] When a voltage is applied to the light-emitting element, the organic EL element generates a pair of electrodes. Electrons are injected from one electrode and holes are injected from the other electrode into a layer containing a light-emitting organic compound, An electric current flows, and the electrons and holes recombine to form light-emitting organic compounds. An excited state is formed, and light is emitted when the excited state returns to the ground state. Therefore, such a light-emitting element is called a current-excited light-emitting element.

[0286] FIG. 21C is a diagram showing an example of a pixel circuit. Here, one pixel has an n-channel type An example using two transistors will be shown. Note that the n-channel transistors are The pixel circuit is suitable for digital time gray scale driving. It can be used.

[0287] Regarding the configuration of applicable pixel circuits and pixel operation when digital time gray scale driving is applied, and explain.

[0288] The pixel 5020 includes a switching transistor 5021, a driving transistor 5022, The switching transistor 502 includes a light-emitting element 5024 and a capacitor element 5023. 1, the gate electrode is connected to the scanning line 5026, and the first electrode (the source electrode, the drain electrode) The first electrode (the other of the source and drain electrodes) is connected to a signal line 5025, and the second electrode (the other of the source and drain electrodes) is connected to a drive The gate electrode of the driving transistor 5022 is connected to the gate electrode of the driving transistor 5022. The gate electrode is connected to a power supply line 5027 via a capacitor element 5023, and the first electrode is connected to a power supply line 5026. The second electrode is connected to the first electrode (pixel electrode) of the light-emitting element 5024. The second electrode of the light emitting element 5024 corresponds to the common electrode 5028. are electrically connected to a common potential line formed on the same substrate.

[0289] The switching transistor 5021 and the driving transistor 5022 are the transistors described above. This allows for high quality and / or reliable display. This will result in a high-performance organic EL display device.

[0290] The potential of the second electrode (common electrode 5028) of the light emitting element 5024 is set to a low power supply potential. The low power supply potential is a potential lower than the high power supply potential supplied to the power supply line 5027, for example. GND, 0V, etc. can be set as the low power supply potential. The high and low power supply potentials are set so that the potential difference is equal to or greater than the threshold voltage of the light-emitting element. By applying a voltage to the transistor 5024, a current flows through the light emitting element 5024, causing it to emit light. The forward voltage of the light emitting element 5024 refers to the voltage required to achieve a desired luminance, and is at least Both include forward threshold voltage.

[0291] The capacitor 5023 is substituted for the gate capacitance of the driving transistor 5022. The gate capacitance of the driving transistor 5022 can be omitted. A capacitance may be formed between the capacitor formation region and the gate electrode.

[0292] Next, a description will be given of the signal input to the driving transistor 5022. Voltage input voltage driving In this case, the driving transistor 5022 is in either an on or off state. The video signal is input to the driving transistor 5022. In order to operate the inverter 2 in the linear region, a voltage higher than the voltage of the power supply line 5027 is applied to the driving transformer. The signal line 5025 is connected to the gate electrode of the transistor 5022. A voltage equal to or greater than the threshold voltage Vth of the transistor 5022 is applied.

[0293] When analog gradation driving is performed, the gate electrode of the driving transistor 5022 is connected to the light emitting element 50 24 plus the threshold voltage Vth of the driving transistor 5022. A voltage is applied to the video signal so that the driving transistor 5022 operates in the saturation region. A signal is inputted to cause a current to flow through the light emitting element 5024. Also, the driving transistor 5022 is saturated. In order to operate the driving transistor 5022 in the above-mentioned range, the potential of the power supply line 5027 is set to the gate By making the video signal analog, the video signal is applied to the light emitting element 5024. A current corresponding to the signal flows, and analog gradation driving can be performed.

[0294] Note that the display device according to one embodiment of the present invention is not limited to the pixel configuration shown in FIG. For example, the pixel circuit shown in FIG. 21(C) may include a switch, a resistor, a capacitor, a sensor, a transistor, and a A resistor or a logic circuit may be added.

[0295] When the above-described transistor is applied to the circuit illustrated in FIG. 21, the source electrode ( The drain electrode (first electrode) is electrically connected to the high potential side, and the drain electrode (second electrode) is electrically connected to the low potential side. Furthermore, the potential of the first gate electrode is controlled by a control circuit or the like, and the potential of the second gate electrode is controlled by a control circuit or the like. The potentials given above, such as a potential lower than the potential given to the source electrode, can be input to the electrode. It can be said that it is completed.

[0296] <Electronic equipment> A semiconductor device according to one aspect of the present invention includes a display device, a personal computer, and a recording medium. Image playback devices (typically DVD: Digital Versatile Disc) (Devices having a display that can play back recording media such as DVDs and display the images) In addition, electronic devices in which the semiconductor device according to one embodiment of the present invention can be used are Mobile phones, portable game consoles, portable data terminals, e-book terminals, video cameras , cameras such as digital still cameras, goggle-type displays (head-mounted displays) Ray), navigation systems, sound reproduction devices (car audio, digital audio players, etc.), copiers, facsimiles, printers, printer-combined machines, automated teller machines Examples of such electronic devices include ATMs and vending machines. vinegar.

[0297] FIG. 22A shows a portable game machine, which includes a housing 901, a housing 902, a display unit 903, and a display unit 904, microphone 905, speaker 906, operation keys 907, stylus 908 The portable game machine shown in FIG. 22A has two display units 903 and a display However, the number of display units that the portable game machine has is not limited to this. .

[0298] FIG. 22(B) shows a portable data terminal, which includes a first housing 911, a second housing 912, a first display unit 9 13, a second display unit 914, a connection unit 915, operation keys 916, etc. The first display unit 911 is provided in the first housing 911, and the second display unit 914 is provided in the second housing 912. The first housing 911 and the second housing 912 are connected by a connection part 915. The angle between the first housing 911 and the second housing 912 can be changed by the connecting portion 915. The image on the first display unit 913 is transmitted between the first housing 911 and the second housing 912 at the connection unit 915. 12. Also, the first display unit 913 and a display having a function as a position input device added to at least one of the first display unit 914 and the second display unit 915. The function as a position input device can be achieved by touching the display device. Alternatively, the function as a position input device can be added by providing a touch panel. By providing a photoelectric conversion element, also called a photosensor, in the pixel portion of the display device, It is possible.

[0299] FIG. 22C shows a notebook personal computer, which includes a housing 921, a display unit 922, a keyboard, and a keyboard. The computer has a keyboard 923, a pointing device 924, and the like.

[0300] FIG. 22(D) shows an electric refrigerator-freezer, which includes a housing 931, a refrigerator compartment door 932, and a freezer compartment door 93. He holds the third prize.

[0301] FIG. 22(E) shows a video camera, which includes a first housing 941, a second housing 942, a display unit 943, The operation key 944, the lens 945, the connection part 946, etc. 945 is provided in the first housing 941, and the display unit 943 is provided in the second housing 942. The first housing 941 and the second housing 942 are connected by a connecting portion 946. The angle between the first housing 941 and the second housing 942 can be changed by the connecting portion 946. The image on the display unit 943 is transmitted between the first housing 941 and the second housing 94 at the connection unit 946. 2.

[0302] FIG. 22(F) shows a standard automobile, which includes a body 951, wheels 952, a dashboard 953, and a rear view mirror. It has Ito 954 etc. [Explanation of symbols]

[0303] 400 boards 401 Insulator 402 Insulator 404 Conductors 406 Semiconductors 406a Semiconductor layer 406b Semiconductor layer 406c Semiconductor layer 408 Insulator 410 Insulator 412 Insulator 413 Conductors 416 Conductors 416a Conductor 416b Electric conductor 416c Conductor 418 Insulator 424a Conductor 424b Conductor 424c conductor 426a Conductors 426b Conductor 426c Conductor 438 Insulator 439 Insulator 450 Semiconductor Substrate 452 Insulator 454 Conductors 456 areas 460 areas 462 Insulator 464 Insulator 466 Insulator 468 Insulator 470 areas 474a area 474b area 476a Conductors 476b Conductor 478a Conductor 478b Conductor 478c Conductor 480a Conductor 480b Conductor 480c conductor 490 transistors 500 boards 501 Insulator 502 Insulator 504 Conductors 506 Semiconductors 508 Insulator 510 Insulator 512 Insulator 513 Conductors 516 Conductors 516a Conductor 516b Conductor 518 Insulator 524a Conductors 524b Conductor 526a Conductors 526b Conductor 538 Insulator 539 Insulator 590 transistors 901 Case 902 Case 903 Display section 904 Display section 905 Microphone 906 Speaker 907 Operation Key 908 Stylus 911 chassis 912 Case 913 Display section 914 Display section 915 Connection 916 Operation Key 921 Case 922 Display section 923 keyboard 924 Pointing Device 931 Case 932 Refrigerator door 933 Freezer door 941 Case 942 Case 943 Display section 944 Operation Key 945 lens 946 Connection 951 body 952 wheels 953 Dashboard 954 Light 1189 ROM interface 1190 PCB 1191 ALU 1192 ALU controller 1193 Instruction Decoder 1194 Interrupt Controller 1195 Timing Controller 1196 registers 1197 Register Controller 1198 Bus Interface 1199 ROM 1200 memory elements 1201 Circuit 1202 Circuit 1203 Switch 1204 Switch 1206 Logic Elements 1207 Capacitor element 1208 Capacitor 1209 Transistor 1210 transistor 1213 Transistor 1214 transistor 1220 circuits 2100 transistors 2200 transistors 3001 Wiring 3002 Wiring 3003 Wiring 3004 Wiring 3005 Wiring 3200 transistors 3300 transistors 3400 Capacitor 5000 boards 5001 Pixel unit 5002 Scanning line driver circuit 5003 Scanning line driver circuit 5004 Signal line driver circuit 5010 Capacitance Line 5012 scan lines 5013 scan lines 5014 Signal line 5016 Transistor 5017 Transistor 5018 Liquid crystal element 5019 Liquid crystal element 5020 pixels 5021 Switching transistor 5022 Drive transistor 5023 Capacitor element 5024 Light-emitting element 5025 signal line 5026 scan lines 5027 Power line 5028 Common electrode< / cpu>

Claims

[Claim 1] an oxide semiconductor, a first conductor, a second conductor, a third conductor, a first insulator, and a second insulator; the first conductor has a first region, a second region, and a third region; the first region has a region where the first conductor and the oxide semiconductor overlap with each other with the first insulator interposed therebetween; the second region has a region where the first conductor and the second conductor overlap each other via the first insulator and the second insulator, the third region has a region where the first conductor and the third conductor overlap with each other via the first insulator and the second insulator, the oxide semiconductor has a fourth region and a fifth region, the fourth region has a region where the oxide semiconductor and the second conductor are in contact with each other, the fifth region has a region where the oxide semiconductor and the third conductor are in contact with each other.

Images