Semiconductor device

Abstract

To provide a high-performance semiconductor device.SOLUTION: A semiconductor device includes a transistor, an insulating film over the transistor, an electrode, and a metal oxide over the insulating film, in which the transistor includes a first gate electrode, a first gate insulating film over the first gate electrode, an oxide over the first gate insulating film, a source electrode and a drain electrode electrically connected to the oxide, a second gate insulating film over the oxide, and a second gate electrode over the second gate insulating film. In the semiconductor device, the first gate insulating film is in contact with the insulating film, the thickness of the insulating film over the second gate electrode, the thickness of the insulating film over the source electrode, and the thickness of the insulating film over the drain electrode are substantially equal to one another, and the insulating film contains excess oxygen.SELECTED DRAWING: Figure 1

Description

[Technical Field]

[0001] One embodiment of the present invention relates to a semiconductor device and a method for driving the semiconductor device. One aspect of the present invention relates to an electronic device.

[0002] In this specification and the like, a semiconductor device is a device that can function by utilizing semiconductor characteristics. This refers to all types of equipment, including display devices (liquid crystal display devices, light-emitting display devices, etc.), projection devices, lighting devices, and Electro-optical devices, power storage devices, memory devices, semiconductor circuits, imaging devices, and electronic devices are all semiconductor devices. It may be said that the device has

[0003] Note that one embodiment of the present invention is not limited to the above technical fields. One aspect of the present invention relates to an article, a method, or a manufacturing method. is a process, machine, manufacture, or composition of matter. This concerns the [Background technology]

[0004] The technology of constructing a transistor using a semiconductor thin film is attracting attention. Widely used in electronic devices such as integrated circuits (ICs) and image display devices (also simply referred to as display devices) Silicon-based semiconductor materials are widely used as semiconductor thin films that can be applied to transistors. Although it is well known that oxide semiconductors are used for semiconductors, oxide semiconductors are attracting attention as other materials.

[0005] For example, zinc oxide or In-Ga-Zn oxide is used as an oxide semiconductor for the active layer. A technique for manufacturing a display device using such a transistor has been disclosed (Patent Document 1 and Patent Document 2). (See patent document 2).

[0006] In recent years, integrated circuits for memory devices have been fabricated using transistors containing oxide semiconductors. A technology for this has been disclosed (see Patent Document 3). transistors including an oxide semiconductor have also been used. [Prior art documents] [Patent documents]

[0007] [Patent Document 1] Japanese Patent Application Laid-Open No. 2007-123861 [Patent Document 2] Japanese Patent Application Laid-Open No. 2007-96055 [Patent Document 3] Japanese Patent Application Laid-Open No. 2011-119674 Summary of the Invention [Problem to be solved by the invention]

[0008] An object of one embodiment of the present invention is to provide a semiconductor device having favorable electrical characteristics. Another embodiment of the present invention provides a semiconductor device that can be miniaturized or highly integrated. Another object of one embodiment of the present invention is to provide a semiconductor device with high productivity. One of the challenges is to

[0009] One embodiment of the present invention is to provide a semiconductor device that can retain data for a long period of time. Another object of one embodiment of the present invention is to provide a semiconductor device having a high data writing speed. Another object of one embodiment of the present invention is to provide a semiconductor device having a high degree of design freedom. Another object of the present invention is to provide a body device that can reduce power consumption. Another object of the present invention is to provide a semiconductor device that can achieve the above object. One of the objects of the present invention is to provide a novel semiconductor device.

[0010] The description of these problems does not preclude the existence of other problems. It is not necessary for one embodiment to solve all of these problems. The subject matter will be self-evident from the description, drawings, claims, etc. It is possible to extract other issues from the drawings, claims, etc. [Means for solving the problem]

[0011] The semiconductor device has a circuit in which a plurality of elements are arranged at high density on the same substrate, and a In some cases, an element is stacked above the insulating film. For example, the above-mentioned elements may be formed on a silicon substrate. A transistor is disposed in which a part of the silicon substrate serves as a channel forming region, and the transistor A transistor having an oxide as a channel forming region is disposed above the insulating film. Furthermore, a wiring layer and a capacitance element are arranged above the transistor via an insulating film. In this way, by stacking and arranging multiple elements with insulating films in between, The device allows these elements to be arranged at high density per substrate area.

[0012] In order to make these multiple elements function, electrodes that electrically connect the upper and lower elements are required. The number of electrodes to be arranged depends on the density of elements in the semiconductor device, for example, For example, this depends on the density at which the transistors are arranged.

[0013] A transistor that uses an oxide as a channel formation region has an insulator near the channel formation region. The electrical characteristics vary depending on the area where the electrodes contact and the density at which the transistors are arranged. The density at which the transistors are arranged (transistor density) The term "transistor density" refers to the number of transistors per unit area. The density is 1 μm 2 is defined as the number of transistors per μm 2 or μ m -2 It can be expressed as:

[0014] According to one aspect of the present invention, the area where the electrode contacts the insulator near the channel forming region and the thickness By adjusting the transistor density, the semiconductor device has little effect on the transistor characteristics. It can be said that:

[0015] One embodiment of the present invention is a transistor, an insulating film over the transistor, an electrode, and a metal oxide film over the insulating film. A semiconductor device having a metal oxide, wherein a transistor includes a first gate electrode and a first A first gate insulating film on the gate electrode, an oxide on the first gate insulating film, and an electric a source electrode and a drain electrode which are electrically connected to each other; a second gate insulating film on the oxide; a second gate electrode on the second gate insulating film, the electrode having a region in contact with the insulating film; The first gate insulating film is in contact with the insulating film, and the thickness of the insulating film on the second gate electrode, the source voltage, The thickness of the insulating film on the top electrode and the thickness of the insulating film on the drain electrode are approximately equal. The film is a semiconductor device with excess oxygen.

[0016] In addition, the metal oxide has a function of suppressing oxygen permeation in the semiconductor device.

[0017] Metal oxides are semiconductor devices that contain aluminum and oxygen.

[0018] The oxide is a compound of In, an element M (M is Al, Ga, Y, or Sn), and Zn. The semiconductor device includes:

[0019] One embodiment of the present invention is a semiconductor device including a circuit, the circuit including a transistor and an electrode. It has multiple poles and the transistor density is 1 / μm 2 More than 2500 pieces / μm 2 The following semiconductor It is a body device.

[0020] In this circuit, the area where the electrode comes into contact with the insulating film is 0.035 μm 2 The semiconductor device preferably has the following characteristics.

[0021] In the semiconductor device, the insulating film preferably has a thickness of 40 nm or more.

[0022] One embodiment of the present invention is a semiconductor device including a plurality of the above-described semiconductor devices and having a region for dicing. It is a body wafer.

[0023] In one aspect of the present invention, a first insulator is formed, and a source electrode, a drain electrode, and a gate electrode are formed on the first insulator. A transistor having a channel formation region in an electrode and an oxide is formed, and Then, a second insulator is formed, and a third insulator is formed on the second insulator. By adding oxygen to the insulator and performing heat treatment, the oxygen is transferred to the oxide through the second insulator. The semiconductor device is then formed with an electrode that penetrates the second insulator and the third insulator and reaches the source electrode. A method for fabricating a semiconductor device.

[0024] The third insulator is formed by sputtering and contains aluminum and oxygen. The present invention relates to a method for manufacturing a semiconductor device including the above-mentioned method. [Effects of the Invention]

[0025] It is possible to provide a semiconductor device having good electrical characteristics. It is possible to provide a semiconductor device that can be integrated. can be provided.

[0026] Alternatively, a semiconductor device capable of retaining data for a long period of time can be provided. Alternatively, a semiconductor device with a high data writing speed can be provided. Alternatively, a semiconductor device that can reduce power consumption can be provided. A semiconductor device can be provided, or a novel semiconductor device can be provided.

[0027] The description of these effects does not preclude the existence of other effects. An embodiment does not necessarily have all of these effects. Effects other than these may be included in the description. The above is self-evident from the description, drawings, claims, etc. From the above descriptions, it is possible to extract other effects. [Brief explanation of the drawings]

[0028] [Figure 1] 1A and 1B are a top view and a cross-sectional view illustrating a transistor according to one embodiment of the present invention. [Figure 2] 1A and 1B are a top view and a cross-sectional view illustrating a transistor according to one embodiment of the present invention. [Figure 3] FIG. 10 is a perspective view illustrating the shape of an electrode according to one embodiment of the present invention. [Figure 4] Graphs showing the transistor density dependence of Vsh, the surface area of ​​contact between the electrode and the insulator, and the dependence of ΔVsh on the surface area of ​​contact between the electrode and the insulator are shown. [Figure 5] 10 is a graph showing the dependency of the amount of released oxygen on the thickness of a silicon oxynitride film and the dependency of ΔVsh on the thickness of a silicon oxynitride film. [Figure 6] 1A to 1C illustrate a method for manufacturing a transistor according to one embodiment of the present invention. [Figure 7] 1A to 1C illustrate a method for manufacturing a transistor according to one embodiment of the present invention. [Figure 8] 1A to 1C illustrate a method for manufacturing a transistor according to one embodiment of the present invention. [Figure 9] 1A to 1C illustrate a method for manufacturing a transistor according to one embodiment of the present invention. [Figure 10] 1A to 1C illustrate a method for manufacturing a transistor according to one embodiment of the present invention. [Figure 11] 1A to 1C illustrate a method for manufacturing a transistor according to one embodiment of the present invention. [Figure 12] 1A to 1C illustrate a method for manufacturing a transistor according to one embodiment of the present invention. [Figure 13] 1A to 1C illustrate a method for manufacturing a transistor according to one embodiment of the present invention. [Figure 14] 1A to 1C illustrate a method for manufacturing a transistor according to one embodiment of the present invention. [Figure 15] 1A to 1C illustrate a method for manufacturing a transistor according to one embodiment of the present invention. [Figure 16] FIG. 1 is a cross-sectional view of a semiconductor device according to one embodiment of the present invention. [Figure 17] FIG. 1 is a cross-sectional view of a semiconductor device according to one embodiment of the present invention. [Figure 18] FIG. 1 is a cross-sectional view of a memory cell array according to one embodiment of the present invention. [Figure 19] FIG. 1 is a cross-sectional view of a memory device according to one embodiment of the present invention. [Figure 20] FIG. 1 is a top view of a semiconductor wafer according to one embodiment of the present invention. [Figure 21] 1A and 1B are a flowchart and a schematic perspective view illustrating an example of a manufacturing process for an electronic component. [Figure 22] 1A to 1C are diagrams illustrating electronic devices according to one embodiment of the present invention. [Figure 23] FIG. 2 is a diagram illustrating the range of the atomic ratio of oxides according to the present invention. [Figure 24]Band diagram of oxide stacking structure. [Figure 25] 10 is a graph showing transistor characteristics of an example. [Figure 26] 10 is a graph showing transistor characteristics of an example. [Figure 27] 10 is a graph showing transistor characteristics of an example. [Figure 28] 10 is a graph showing transistor characteristics of an example. [Figure 29] 10 is a graph showing the Vbg dependency of ΔVsh in an example. [Figure 30] FIG. 1 shows the results of XRD analysis of the CAAC-OS of an example. [Figure 31] 10 is a graph showing transistor characteristics of an example. DETAILED DESCRIPTION OF THE INVENTION

[0029] Hereinafter, embodiments will be described with reference to the drawings. It is possible to implement the invention in various ways without departing from the spirit and scope of the invention. It will be readily apparent to those skilled in the art that various modifications may be made to the mode and details of the present invention. The present invention should not be construed as being limited to the description of the following embodiments.

[0030] Also, in the drawings, the size, thickness of layers, or areas are exaggerated for clarity. Therefore, the scale is not necessarily limited to that shown. The drawings are merely schematic illustrations, and are not limited to the shapes or values ​​shown in the drawings. In this case, the same reference numerals are used in common between different drawings to designate the same parts or parts having similar functions. In addition, when referring to the same function, the hatch pattern is used. In some cases, the same symbol is not attached.

[0031] In addition, in this specification and the like, ordinal numbers such as 1st, 2nd, etc. are used for convenience. It does not indicate the order of processes or stacking. For example, "first" may be changed to "second" "the" or "third" can be used as appropriate for explanation. The ordinal numbers listed in the specification do not match the ordinal numbers used to identify an aspect of the present invention. There are cases where this happens.

[0032] In addition, in this specification, the terms "above" and "below" that indicate the position of components are used to indicate the position of components. The positional relationship is used for convenience in describing the structure with reference to the drawings. The relationship between the two components changes depending on the direction in which each component is depicted. The terms are not limited to those used above, but can be rephrased appropriately depending on the situation.

[0033] In this specification and the like, a semiconductor device is a device that can function by utilizing semiconductor characteristics. Refers to devices in general, including semiconductor elements such as transistors, semiconductor circuits, arithmetic units, and memory The device is one aspect of a semiconductor device. Optical devices, power generation devices (including thin-film solar cells, organic thin-film solar cells, etc.), and electronic devices , may have semiconductor devices.

[0034] In this specification, a transistor includes a gate, a drain, and a source. It is an element having at least three terminals including a drain (drain terminal, drain Between the drain electrode and the source terminal A channel forming region is formed between the source and drain, and a current is applied between the source and drain through the channel forming region. In this specification and the like, the channel forming region is defined as This refers to the area where current mainly flows.

[0035] The functions of the source and drain may differ depending on whether transistors with different polarities are used or whether the circuit This may happen when the direction of the current changes during operation. In the specification, the terms source and drain may be used interchangeably. do.

[0036] In this specification and the like, a silicon oxynitride film is a film containing more oxygen than nitrogen as a component. The oxygen content is preferably 55 atomic % or more and 65 atomic % or less, and the nitrogen content is preferably 100 atomic % or less. is 1 atomic % or more and 20 atomic % or less, silicon is 25 atomic % or more and 35 atomic % or less, and hydrogen is 0. It refers to silicon nitride oxide contained in a concentration range of 1 atomic % to 10 atomic %. The film has a composition in which the nitrogen content is higher than the oxygen content, and preferably the nitrogen content is higher than the oxygen content. is 55 atomic % or more and 65 atomic % or less, oxygen is 1 atomic % or more and 20 atomic % or less, silicon is 25 atomic % or more and 35 atomic % or less, and hydrogen is contained in the concentration range of 0.1 atomic % or more and 10 atomic % or less. It refers to something that...

[0037] In addition, in this specification and the like, the terms "film" and "layer" are interchangeable. For example, the term "conductive layer" can be changed to the term "conductive film." Alternatively, for example, the term "insulating film" may be changed to "insulating layer" It may be possible to change the term to

[0038] Furthermore, unless otherwise specified, the transistors described in this specification and the like are field-effect transistors. In addition, unless otherwise specified, the transistors shown in this specification and the like are n The transistor is a channel type.

[0039] In this specification, "parallel" means that two straight lines are at an angle of -10° or more and 10° or less. Therefore, it includes cases where the angle is between -5° and 5°. "Almost parallel" means that the two lines are arranged at an angle of between -30° and 30°. "Perpendicular" means that two straight lines are arranged at an angle of 80° or more and 100° or less. Therefore, it also includes the case where the angle is between 85° and 95°. " refers to a state in which two straight lines are arranged at an angle of 60° or more and 120° or less.

[0040] In this specification, when the crystal is a trigonal or rhombohedral crystal, it is represented as a hexagonal crystal system. vinegar.

[0041] For example, in this specification, it is explicitly stated that X and Y are connected. In this case, X and Y are electrically connected, and X and Y are functionally connected. The case where X and Y are directly connected and the case where X and Y are directly connected are both considered to be disclosed in this specification. Therefore, it is not limited to predetermined connection relationships, for example, connection relationships shown in drawings or text. Connections other than those shown in the drawings or text are also included. Let's say.

[0042] Here, X and Y are the object (for example, a device, an element, a circuit, a wiring, an electrode, a terminal, a conductive film, layer, etc.).

[0043] An example of a direct connection between X and Y is a circuit that allows electrical connection between X and Y. The elements that function as When a diode, display element, light-emitting element, load, etc. is not connected between X and Y, and elements (e.g., switches, transistors, capacitors) that allow electrical connection between X and Y. without using any capacitors, inductors, resistors, diodes, display elements, light-emitting elements, loads, etc. In this case, X and Y are connected.

[0044] An example of the case where X and Y are electrically connected is The elements that function as One or more diodes, display elements, light-emitting elements, loads, etc.) are connected between X and Y. The switch has a function to control on / off. A switch can be in a conducting state (ON state) or a non-conducting state (OFF state) and allows current to flow. The switch has the function of controlling whether or not current flows. When X and Y are electrically connected, X This includes the case where Y is directly connected to Y.

[0045] An example of a case where X and Y are functionally connected is when the functional connection between X and Y is possible. Circuits that perform functions (e.g., logic circuits (inverters, NAND circuits, NOR circuits, etc.)), signal Conversion circuits (DA conversion circuits, AD conversion circuits, gamma correction circuits, etc.), potential level conversion circuits ( Power supply circuits (boost circuits, step-down circuits, etc.), level shifter circuits that change the signal potential level, etc. ), voltage sources, current sources, switching circuits, amplifier circuits (which can increase the signal amplitude or current amount, etc.) circuits, operational amplifiers, differential amplifier circuits, source follower circuits, buffer circuits, etc.), signal generation One or more circuits (synthesis circuit, memory circuit, control circuit, etc.) can be connected between X and Y. For example, even if another circuit is inserted between X and Y, the signal output from X If a signal is transmitted to Y, then X and Y are considered to be functionally connected. When X and Y are functionally connected, there are cases where X and Y are directly connected and cases where X and Y are functionally connected. This includes the case where Y is electrically connected.

[0046] If it is explicitly stated that X and Y are electrically connected, When X and Y are electrically connected (i.e., when there is another element or another circuit between X and Y), X and Y are functionally connected (i.e., X and Y are (When X and Y are functionally connected with another circuit between them) and (When X and Y are directly connected) (i.e., when X and Y are connected without any other element or circuit between them) In other words, it is assumed that the above is disclosed in the present specification. If it is explicitly stated that it is connected, The same contents as those in the above case are deemed to be disclosed in the present specification.

[0047] For example, if the source (or first terminal, etc.) of the transistor is connected to the The drain (or second terminal, etc.) of the transistor is electrically connected to X. It may be electrically connected to Y through Z2 (or not), or the source of the transistor may be The first terminal (or the first terminal, etc.) is directly connected to a part of Z1, and another part of Z1 is directly connected to X. The drain (or second terminal, etc.) of the transistor is directly connected to a part of Z2. When a part of Z2 is directly connected to Y, and another part of Z2 is directly connected to Y, it can be expressed as follows: It can be manifested.

[0048] For example, "X and Y and the source (or first terminal, etc.) and drain (or second terminal, etc.) of a transistor" 2 terminals) are electrically connected to each other, and X, the source (or The first terminal, etc.), the drain of the transistor (or the second terminal, etc.), and the Y are electrically connected in this order. "It is connected to the source (or The first terminal (or the drain of the transistor) is electrically connected to X, and the second terminal (or the drain of the transistor) is electrically connected to ) is electrically connected to Y, and X is the source (or first terminal, etc.) of the transistor, The drains (or second terminals, etc.) of the transistors, Y, are electrically connected in this order. Alternatively, "X is the source (or first terminal) of the transistor." and the drain (or second terminal, etc.) is electrically connected to Y, and X, The source (or first terminal, etc.) of a transistor, the drain (or second terminal, etc.) of a transistor, For example, Y is provided in this order. By specifying the order of connections in a circuit configuration using various representation methods, The source (or first terminal, etc.) and the drain (or second terminal, etc.) of the transistor are separated. The technical scope can be determined separately.

[0049] Alternatively, for example, "the source (or first terminal, etc.) of a transistor" ) is electrically connected to X through at least a first connection path, and the first connection path does not have a second connection path, and the second connection path is a The source (or first terminal, etc.) of the transistor and the drain (or second terminal, etc.) of the transistor The first connection path is a path via Z1, and the second connection path is a path between the transistor The drain (or second terminal, etc.) of the transistor is connected to Y via at least a third connection path. the third connection path does not have the second connection path, and the third connection path is electrically connected to the The connection path of this is the path via Z2. The source (or first terminal, etc.) of the resistor is connected to Z1 by at least the first connection path. and the first connection path does not have a second connection path. The second connection path has a connection path through a transistor, and the drain of the transistor The pin (or second terminal, etc.) is connected to Y via Z2 by at least a third connection path. The third connection path is electrically connected to the second connection path, and the third connection path does not have the second connection path. Alternatively, the source (or first terminal, etc.) of the transistor may be and X through Z1 by at least a first electrical path. The electrical path does not have a second electrical path, and the second electrical path is a transistor From the source (or first terminal, etc.) of the transistor to the drain (or second terminal, etc.) of the transistor The drain (or second terminal, etc.) of the transistor is an electrical path The third electrical path is electrically connected to Y through Z2, and the third electrical path does not have a fourth electrical path, and the fourth electrical path is The electrical connection from the input (or second terminal, etc.) to the source (or first terminal, etc.) of the transistor. Using the same expression as these examples, the circuit structure can be expressed as follows: By defining the connection path in the structure, the source (or first terminal) of the transistor The technical scope can be determined by distinguishing between the first terminal (or the first terminal, etc.) and the drain (or the second terminal, etc.). This can be done.

[0050] It should be noted that these expression methods are merely examples, and the present invention is not limited to these expression methods. X, Y, Z1, and Z2 are the objects (e.g., devices, elements, circuits, wiring, electrodes, terminals, conductive films) , layer, etc.).

[0051] Note that the circuit diagram shows independent components as if they are electrically connected to each other. Even if one component has the functions of multiple components, For example, when a part of the wiring also functions as an electrode, one conductive film functions as both the wiring and the electrode. Therefore, the present invention has the functions of both components, that is, the functions of a sensor and an electrode. The electrical connection is such that one conductive film has the functions of multiple components. If so, it will also be included in this category.

[0052] In this specification, the term "barrier film" refers to a film that prevents impurities such as hydrogen and oxygen from permeating. When the barrier film has conductivity, it is called a conductive barrier film. Sometimes I call.

[0053] In this specification, the term "metal oxide" refers to a metal in a broad sense. Metal oxides are oxides of the following: oxide insulators, oxide conductors (including transparent oxide conductors), ), oxide semiconductor (also called oxide semiconductor or simply OS) For example, when a metal oxide is used in the active layer of a transistor, the metal Oxides are sometimes called oxide semiconductors. When describing a transistor as an oxide or oxide semiconductor, In other words, it is a transistor having a body.

[0054] (Embodiment 1) A structure of a semiconductor device according to one embodiment of the present invention will be described below.

[0055] <Configuration Example 1 of Semiconductor Device> FIG. 1A is a top view of the semiconductor device. FIG. 1B is a top view of the semiconductor device shown in FIG. 1A. FIG. 1C is a cross-sectional view of the portion indicated by the dashed line A2. 4 is a cross-sectional view of the portion indicated by the dashed dotted line.

[0056] In FIG. 1B, A1-A2 indicates the channel length direction of a transistor included in the semiconductor device. 1C is a cross-sectional view of a semiconductor device, and A3-A4 in FIG. 1(A) is a cross-sectional view in the channel width direction. In the top view of FIG. 1(A), some elements are omitted for clarity. The illustration omits elements.

[0057] In FIGS. 1B and 1C, the transistors included in the semiconductor device are formed on a substrate 400. The oxide 401a is disposed on the oxide 401b on the oxide 401a. The transistor is made up of conductor 310a on oxide 401b, conductor 310b and insulator 301, The insulator 302 on the conductor 310a, the conductor 310b, and the insulator 301, and the insulator 302 on the insulator 301 are Insulator 303 on oxide 402, insulator 402 on insulator 303, and oxide 402 on insulator 402. The oxide 406a, the oxide 406b on the oxide 406a, and the area in contact with the top surface of the oxide 406b are The conductor 416a1 and the conductor 416a2 have a barrier film 41 7a1, a barrier film 417a2 on the conductor 416a2, the side of the conductor 416a1, the conductor The side surface of the body 416a2, the top surface of the barrier film 417a1, the top surface of the barrier film 417a2, and the oxide film an oxide 406c having a region in contact with the upper surface of the substrate 406b; and an insulator 406b on the oxide 406c. 12, and the top surface of the oxide 406b overlaps with the oxide 406c and the insulator 412. The insulator 301 has an opening, and Conductor 310a and conductor 310b are disposed within the openings.

[0058] On the transistor, there is an oxide 418, an insulator 415 on the oxide 418, and an insulator 41 5, an oxide 420 on the oxide 420, an oxide 422 on the oxide 420, and an insulator 41 on the oxide 422. 0 and are placed.

[0059] Further, the barrier film 417a1, the insulator 415, the oxide 420, the oxide 422 and the insulator An electrode 450 that passes through the body 410 and reaches the conductor 416a1, a barrier film 417a2, an insulator 415, oxide 420, oxide 422 and insulator 410 to reach conductor 416a2. An electrode 451 is disposed.

[0060] In FIG. 1B, the edge of the oxide 418, the edge of the insulator 412, and the oxide 406c The end portions of the barrier film 417a1 and the barrier film 417b are flush with each other in the channel length direction. The thickness of the insulator 415 on the oxide 418 that overlaps the conductor 404 is , the thickness of the insulator 415 on the barrier film 417a1 and the thickness of the insulator 41 on the barrier film 417a2 The thickness of the insulator 415 is approximately the same as that of the insulator 402. It has a region.

[0061] In the transistor, the conductor 404 functions as a first gate electrode. The body 404 may have a laminated structure of a conductor 404a and a conductor 404b. For example, a conductor 404a having a function of suppressing oxygen permeation may be formed as a film below a conductor 404b. This can prevent an increase in electrical resistance due to oxidation of the conductor 404b.

[0062] In addition, an oxide 418 is disposed so as to cover the conductor 404a and the conductor 404b. The oxide 418 is a metal oxide such as aluminum oxide that has the function of suppressing oxygen permeation. By using the oxide, oxygen from the outside is prevented from diffusing into the conductor 404b, and the conductor This can prevent an increase in electrical resistance due to oxidation of the body 404b.

[0063] Oxide 418 was deposited by atomic layer deposition (ALD). It is preferable to use a metal oxide film formed by the on method, for example, aluminum oxide. The insulator 412 functions as a first gate insulator.

[0064] The conductor 416a1 and the conductor 416a2 are connected to a source electrode and a drain electrode. The conductor 416a1 and the conductor 416a2 also function as a barrier to oxygen permeation. For example, a conductive material that suppresses oxygen permeation can be used. By forming a conductor having a function of forming a film on the upper layer, the conductor 416a1 and the conductor 416a2 This prevents the increase in electrical resistance due to oxidation of the conductor. , and can be measured using the two-terminal method.

[0065] The barrier film 417a1 and the barrier film 417a2 are also resistant to impurities such as hydrogen and water. The barrier film 417a1 has a function of suppressing the permeation of oxygen. The barrier film 417a2 prevents oxygen from diffusing into the conductor 416a1. a2 and prevents oxygen from diffusing into conductor 416a2.

[0066] In the transistor, the oxide 406b functions as a channel formation region. The transistor controls the resistance of the oxide 406b by applying a potential to the conductor 404. That is, the potential applied to the conductor 404 can cause the conductor 416a1 and the conductor 416a2.

[0067] As shown in FIG. 1C, the oxide 406c is formed on the oxide 406b in the channel width direction. Furthermore, a conductor 404 having a function of a first gate electrode is arranged to cover the entire surface of the gate electrode. The first insulating layer 412 covers the entire oxide 406b. Therefore, the electric potential of the conductor 404 which functions as the first gate electrode is The oxide 406b can be entirely surrounded electrically by the field. The structure of a transistor in which the channel formation region is electrically surrounded by an electric field is called surro This is called an unded channel (s-channel) structure. Since a channel can be formed across the entire 6b, a large current can flow between the source and drain. This allows the current (on-state current) to be increased during conduction. Since the conductor 404 is surrounded by the electric field of the conductor 404, the current (off current) when the conductor 404 is not conducting is It can be made smaller.

[0068] The transistor also includes a conductor 404 that functions as a first gate electrode and a source electrode. Conductor 416a1 and conductor 416a2 functioning as a source electrode or a drain electrode 2 and conductor 404 have an overlapping region, and are formed by conductor 416a1 and conductor 416a1. and a parasitic capacitance formed by the conductor 404 and the conductor 416a2. do.

[0069] The transistor is configured such that an insulator 41 is provided between the conductor 404 and the conductor 416a1. 2. In addition to the oxide 406c, the barrier film 417a1 is provided, thereby reducing the parasitic capacitance. Similarly, an insulating layer can be formed between the conductor 404 and the conductor 416a2. The barrier film 417a2 is included in addition to the body 412 and oxide 406c, so that the parasitic volume Therefore, the transistor has excellent frequency characteristics. It becomes ta.

[0070] Furthermore, by configuring the transistor as described above, when the transistor is in operation, for example, When a potential difference occurs between the conductor 404 and the conductor 416a1 or the conductor 416a2, The leakage current between the conductor 404 and the conductor 416a1 or the conductor 416a2 is reduced or or can be prevented.

[0071] The conductor 310 is provided in an opening formed in the insulator 301. The insulator 300 may have a laminated structure of a conductor 310a and a conductor 310b. A conductor 310a is formed in contact with the inner wall of the opening 1, and a conductor 310b is formed further inside. Here, the height of the upper surfaces of the conductors 310a and 310b and the height of the insulator 30 The height of the upper surface of the conductor 310 can be made to be approximately the same. The conductor 310 functions as a second gate electrode. The conductor 310 is a multilayer film containing a conductor having a function of suppressing oxygen permeation. For example, the conductor 310a may be a conductor having a function of suppressing oxygen permeation. This can prevent the electrical conductivity of the conductor 310b from decreasing due to oxidation.

[0072] The insulators 302, 303, and 402 function as a second gate insulating film. The threshold voltage of the transistor is controlled by the potential applied to the conductor 310. It is possible.

[0073] The oxide 420 is preferably a metal oxide film formed by sputtering. For example, it is preferable to use aluminum oxide. By this, oxygen is supplied to the insulator 415 through the surface where the oxide 420 and the insulator 415 contact. By supplying oxygen to the insulator 415, the insulator 415 can be in an oxygen-excess state. It contains more oxygen than meets the oxygen requirement. This oxygen is called excess oxygen. The excess oxygen can be removed by heat treatment or the like to form the insulator 415 and the insulator 415. The oxide 406b passes through the adjacent insulator 402 and forms a channel (channel formation 406a) and oxide 406b. The oxygen vacancies in the insulator 415 and the oxide 406b can be reduced. The insulator 402 is an insulating material that is more permeable to oxygen than the oxide 420 or the oxide 422. For example, silicon oxide or silicon oxynitride can be used.

[0074] The insulator 415 has a region in contact with the electrode 450 and the electrode 451. Excess oxygen diffuses through this region to electrodes 450 and 451, By oxidizing the electrode 451, the excess oxygen may be consumed and reduced. The surface area of ​​the region in contact with electrode 450 and electrode 451 must be taken into consideration.

[0075] In addition, the electrodes 450 and 451 contain a conductor having a function of suppressing oxygen permeation. The electrodes 450 and 451 may be formed as a multilayer film having a function of suppressing oxygen permeation. By using a conductor having the above structure, oxidation of the electrode 450 and the electrode 451 can be prevented. Excess oxygen consumption may be reduced.

[0076] FIG. 3 is a perspective view of the portion where the electrode 450 or the electrode 451 contacts the insulator 415. The electrode 450 is a substantially rectangular parallelepiped, and the length of one side of the bottom and top surfaces of the electrode 450 is W. If the thickness of the insulator 415 is T, the electrode 450 is in contact with the insulator 415. The surface area is W x T x 4. The same applies to the electrode 451 as described above.

[0077] The amount of excess oxygen consumed in the insulator 415 also varies depending on the density of the transistor. The amount of oxygen supplied to the oxide 406b of each transistor and the The side surfaces of the conductor 416a1 and the conductor 416a2 are in contact with the insulator 415. The amount of oxygen that diffuses into the region where the transistors are located increases as the transistor density increases.

[0078] In this embodiment, the transistor density and the electrode 450 or the electrode 451 are insulators 41 Evaluate the relationship between the surface area in contact with 5 and the Vsh of the transistor. axis, square root of drain current Id 1 / 2 Plot the Id-Vg curve with [A] as the vertical axis. In this specification, the gate voltage at the rise of the drain current is called Vsh. h is plotted with the gate voltage Vg [V] on the horizontal axis and the logarithm of the drain current Id [A] on the vertical axis. In the simulated Id-Vg curve, the tangent at the point where the slope of the curve is maximum and the point where Id=1 .0×10 -12 It is defined as the gate voltage at the intersection with the line [A]. Vsh is calculated assuming that the drain voltage Vd is 3.3V.

[0079] Vsh depends on the density of oxygen vacancies in the channel formation region. If the density of oxygen vacancies in the silicon dioxide is high, Vsh will decrease. In other words, Vsh will shift in the negative direction. Therefore, the oxide having the channel formation region By supplying oxygen into 406b, the density of oxygen vacancies in the channel formation region is reduced. By doing so, it is possible to prevent a negative shift in Vsh and obtain normally-off transistor characteristics. This can be done.

[0080] The evaluation was carried out using four samples with insulator 415 thicknesses of 10 nm, 32 nm, 62 nm, and 100 nm. For each sample, the transistor density is 1 / μm 2 , 2 pieces / μm 2 , 2.9 pieces / μm 2 The Vsh of the transistor was measured for each sample and each transistor density. In both cases, the length of one side of the bottom or top surface of electrode 450 or electrode 451 was set to 100 nm.

[0081] The graph shown in FIG. 4(A) shows Vsh on the vertical axis and transistor density on the horizontal axis. The figure shows the transistor density dependence of h. The surface area of ​​the insulating layer 415 is calculated as S=W×T×4 as described above. nm is S=0.004μm 2 , T=32nm, S=0.013μm 2 , T=62nm is S =0.025μm 2 , T=100nm, S=0.04μm 2 This becomes:

[0082] According to Figure 4(A), transistor density dependence is observed for all surface areas. As the resistor density increases, Vsh decreases, i.e., there is a tendency for it to shift negatively. However, it was found that the magnitude of the transistor density dependence differs depending on the surface area. That is, the surface area is 0.004 μm 2 The transistor density is highly dependent on the surface area. , 0.025 μm 2 The density dependency of the transistor is small.

[0083] Figure 4(B) shows the same data as above, with Vsh on the vertical axis and surface area on the horizontal axis. The graph below shows the surface area dependence of Vsh. , the surface area is 0.025 μm at any transistor density. 2In the vicinity, each transistor It can be seen that the difference in Vsh between the different star densities is the smallest.

[0084] Figure 4(C) shows the transistor density of 1 / μm for each surface area. 2 In the case of Vsh and , transistor density is 2.9 / μm 2 The difference between Vsh and ΔVsh is ΔV The graph shows the surface area dependence of ΔVsh, with sh on the vertical axis and surface area on the horizontal axis. It is something.

[0085] According to Figure 4(C), ΔVsh is 2 The smallest in the neighborhood In other words, the surface area is 0.025 μm 2 In the vicinity, the most transistor density dependent It is clear that the sex is small.

[0086] The smaller the surface area of ​​the electrode 450 or 451 in contact with the insulator 415, the The excess oxygen consumption of 5 should be suppressed, and the graph in Figure 4(B) shows a downward sloping curve. However, when the transistor density is 1 / μm 2 In samples other than As mentioned above, the 2 The vicinity is the maximum value of Vsh.

[0087] FIG. 5B shows the graph of FIG. 4B, with the horizontal axis representing the film thickness of the insulator 415, that is, the oxynitride film thickness. According to FIG. 5(B), the thickness of the silicon dioxide film is replaced with that of the silicon dioxide film. This graph shows the tendency of the electrode to be This is because the length was fixed at 100 nm.

[0088] From the above, Vsh is determined by the transistor density, the electrode 450 or the electrode 451 being an insulator 41 5 and the thickness of the insulator 415. 25 μm 2 Vsh transistor near or insulator 415 film thickness near 60 nm Density dependence is small.

[0089] Here, a sample was prepared to estimate the amount of excess oxygen added to the insulator 415. The material was an insulator placed on a substrate, and an oxide was placed on the insulator. Silicon oxide was used as the insulating material, and aluminum oxide was used as the oxide. The film thickness was set to 0 nm, 10 nm, 20 nm, 30 nm, 40 nm, 50 nm, and 100 nm. The results are shown in Table 1. The amount of oxygen released from each film was measured. can be estimated as the amount of excess oxygen added to the insulator. Using thermal desorption spectroscopy, the surface temperature of the insulating film was measured in the range of 50 to 500°C. The amount of released oxygen was measured in terms of oxygen molecules. .

[0090] As shown in Figure 5(A), in the region where the film thickness is 0 nm or more and approximately 40 nm or less, the film thickness increases. The amount of excess oxygen increases rapidly with increasing film thickness. The increase tends to saturate. In the region below 450, the dependence of Vsh is The thickness of the insulator 415 is stronger than the surface area. On the other hand, in the region thicker than about 40 nm, the amount of excess oxygen is Vsh is saturated and the change due to the film thickness becomes small. That is, the electrode 450 or the electrode 451 depends on the surface area in contact with the insulator 415. As the surface area in contact with 15 increases, Vsh tends to decrease (negative shift).

[0091] From the above results, it is possible to determine whether the electrode 450 or the electrode 450 has a small transistor density dependency of Vsh. 451 can achieve an optimum range of surface area in contact with the insulator 415. The thickness of the insulator 415 is preferably 40 nm or more. The surface area of ​​electrode 450 or electrode 451 is 0.035 μm 2 It is preferable to do the following: The density of the transistor is 0.01 pieces / μm 2 More than 2500 pieces / μm 2 Less than or equal to 0. 1 piece / μm 2 More than 2500 pieces / μm 2 Less than or equal to 1 particle / μm 2 Over 2500 pieces / μm 2 or less, and even more preferably 10 particles / μm 2 More than 2500 pieces / μm 2 below, Even more preferably, 100 particles / μm 2 More than 2500 pieces / μm 2 The following applies.

[0092] <Configuration Example 2 of Semiconductor Device> An example of a semiconductor device having a different structure from that of the semiconductor device shown in FIG. 1 will be described with reference to FIG. 2. .

[0093] 2A is a top view of the semiconductor device. FIG. 2B shows the A1- FIG. 2(C) is a cross-sectional view of the portion indicated by the dashed line A2. Also, FIG. 2(C) is a cross-sectional view of the portion indicated by the dashed line A3-A in FIG. 2B is a cross-sectional view of the semiconductor device shown by the dashed line in FIG. 2C is a cross-sectional view of the transistor in the channel length direction, and 4 is a cross-sectional view of a transistor included in a semiconductor device in the channel width direction. In the plan view, some elements are omitted for clarity of illustration.

[0094] In FIGS. 2B and 2C, the oxide 418 on the transistor included in the semiconductor device An oxide 408a and an oxide 408b are disposed in this order on the insulating layer 408. An insulator 408 is disposed on the oxide 408b. The semiconductor device shown in FIG. 1B and FIG. 1C has a different configuration from the semiconductor device shown in FIG. .

[0095] The oxide 408a is preferably a metal oxide film formed by the ALD method. For example, it is preferable to use aluminum oxide. It is possible to form a film with excellent coverage even in areas with few through holes and unevenness. The oxide 408b can be formed by using a metal oxide film formed by sputtering. It is preferable to use aluminum oxide, for example. By using the oxide 408b, the oxide 408b is converted into the oxide 408a and the insulator 412. Oxygen is supplied to the insulator 412 through the surface where the oxide 408a contacts the insulator 412, and the insulator 412 is oxidized. The excess oxygen can be converted into an oxide in contact with the insulator 412 by heat treatment or the like. The region where the channel of the oxide 406b is formed (called the channel forming region) passes through 406c. ) and oxide 406a (path 1). 8b to the insulator 402 via the oxide 408a and the interface between the insulator 402 and the oxide 408a. By supplying oxygen to the insulator 402, the insulator 402 can be made to have an excess of oxygen. The region where the channel of the oxide 406b is formed from the insulator 402 by a process such as a channel This can be effectively supplied to the oxide 406a (referred to as the formation region) and the oxide 406b (path 2). These two routes can reduce the oxygen vacancies in the oxide 406a and the oxide 406b. The insulator 412 and the insulator 402 are made of the oxide 420 or the oxide 422. An insulating material that is easily permeable to oxygen is used. For example, silicon oxide or silicon oxynitride can be used.

[0096] The oxide 408a and the oxide 408b preferably have a function of suppressing oxygen permeation. By having such a function, it is possible to supply oxide 406a and oxide 406b with This can prevent the trapped oxygen from diffusing outward.

[0097] Moreover, the oxide 408a and the oxide 408b are permeable to impurities such as hydrogen and water. It is preferable that the film has a function of suppressing water from the outside. The oxide 406a and the oxide 406b are formed by the insulating layer 406. The insulating layer 406a prevents impurities such as silicon and water from penetrating into the oxide 406a and the oxide 406b. You can do this.

[0098] The thickness of the oxide 408a is 3 nm or less, preferably 0.5 nm or more, and more preferably 1.5 nm or less. The thickness of the oxide 408b is preferably equal to or greater than the thickness of the oxide 408a. .

[0099] For other configurations and effects, the semiconductor device in FIG. 1 can be referred to.

[0100] <Substrate> The substrate 400 may be, for example, an insulating substrate, a semiconductor substrate, or a conductive substrate. Examples of insulating substrates include glass substrates, quartz substrates, sapphire substrates, and stabilized silica substrates. Zirconia substrates (yttria-stabilized zirconia substrates, etc.), resin substrates, etc. The solid substrate may be, for example, a semiconductor substrate such as silicon or germanium, or a silicon carbide substrate. silicon germanium, gallium arsenide, indium phosphide, zinc oxide, gallium oxide Furthermore, there are compound semiconductor substrates that have an insulating region inside the semiconductor substrate. A semiconductor substrate having such a structure, for example, an SOI (Silicon On Insulator) substrate Conductive substrates include graphite substrates, metal substrates, alloy substrates, and conductive resin substrates. Alternatively, there are substrates having metal nitrides, substrates having metal oxides, etc. The substrates include a substrate in which a conductor or a semiconductor is provided on an insulating substrate, a substrate in which a conductor or an insulator is provided on a semiconductor substrate, and There are substrates provided with an edge, and substrates in which a semiconductor or an insulator is provided on a conductive substrate. Alternatively, a substrate having an element provided thereon may be used. Examples of the elements include capacitance elements, resistance elements, switch elements, light-emitting elements, and memory elements.

[0101] A flexible substrate may also be used as the substrate 400. As a method for providing a transistor, a transistor is formed on a non-flexible substrate, and then the transistor is There is also a method of peeling off the transistor and transferring it to the substrate 400, which is a flexible substrate. In this case, a peeling layer may be provided between the non-flexible substrate and the transistor. For example, a sheet, film, or foil having woven fibers may be used. The substrate 400 may have elasticity. When the bending or pulling is stopped, the substrate 400 returns to its original shape. The substrate may have the property of returning to its original shape, or may have the property of not returning to its original shape. 400 is, for example, 5 μm or more and 700 μm or less, preferably 10 μm or more and 500 μm or less. More preferably, the substrate 400 has a region having a thickness of 15 μm or more and 300 μm or less. By thinning the substrate, the weight of the semiconductor device having the transistor can be reduced. By making 400 thinner, it can be stretched and bent even when using glass. When the force is released, the product may return to its original shape. This can reduce the impact on the semiconductor device on the substrate 400. A suitable semiconductor device can be provided.

[0102] The substrate 400, which is a flexible substrate, may be made of, for example, metal, alloy, resin, or glass. Alternatively, fibers thereof can be used. The substrate 400, which is a flexible substrate, has a linear expansion coefficient of 1.5. The lower the elongation, the more preferable it is because deformation due to the environment is suppressed. For example, the linear expansion coefficient is 1×10 -3 / K or less, 5×10 -5 / K or less, or 1× 10 -5 The resin may be, for example, polyester, Polyolefin, polyamide (nylon, aramid, etc.), polyimide, polycarbonate Aramid, in particular, has a low linear expansion coefficient, making it suitable for flexible substrates. It is suitable as the plate 400.

[0103] <Insulator> Insulators include oxides, nitrides, oxynitrides, nitride oxides, and metal oxides that have insulating properties. These include metal oxide nitrides, metal oxynitrides, and metal oxynitrides.

[0104] The transistor is made of an insulator that has the function of suppressing the permeation of impurities such as hydrogen and oxygen. By surrounding the insulator 303, the transistor characteristics can be stabilized. , oxide 401a, oxide 401b, oxide 408a, oxide 408b, oxide 418, The oxide 420 and the oxide 422 suppress the permeation of impurities such as hydrogen and oxygen. Any functional insulator may be used.

[0105] Examples of insulators that have the function of suppressing the permeation of impurities such as hydrogen and oxygen include: Boron, carbon, nitrogen, oxygen, fluorine, magnesium, aluminum, silicon, phosphorus, salt Argon, Gallium, Germanium, Yttrium, Zirconium, Lanthanum, Neo Insulators containing zinc, hafnium or tantalum may be used in single or multilayer configurations.

[0106] Also, for example, the insulator 303, the oxide 401a, the oxide 401b, the oxide 408a, the oxide The oxide 408b, oxide 418, oxide 420, and oxide 422 are aluminum oxide. Smoke, magnesium oxide, gallium oxide, germanium oxide, yttrium oxide, zinc oxide gold, zinc oxide, lanthanum oxide, neodymium oxide, hafnium oxide or tantalum oxide Metal oxide, silicon nitride oxide, silicon nitride, or the like may be used. 3, oxide 401a, oxide 401b, oxide 418, oxide 420 and oxide 422 Preferably, the coating comprises aluminum oxide.

[0107] Also, for example, the oxide 422 can be formed by sputtering using plasma containing oxygen. When the oxide is deposited, oxygen can be added to the insulating layer that serves as the oxide underlayer.

[0108] Insulator 301, insulator 302, insulator 402, insulator 412, insulator 410 and insulator The body 415 may be, for example, boron, carbon, nitrogen, oxygen, fluorine, magnesium, or aluminum. Nitride, silicon, phosphorus, chlorine, argon, gallium, germanium, yttrium, di a single layer of an insulator containing zinc, lanthanum, neodymium, hafnium or tantalum; Alternatively, they may be stacked. For example, an insulator 301, an insulator 302, an insulator 402, an insulator The body 412, the insulator 410, and the insulator 415 may be silicon oxide or silicon oxynitride. Alternatively, it preferably comprises silicon nitride.

[0109] In particular, it is preferable that the insulators 402 and 412 have a high relative dielectric constant. For example, the insulators 402 and 412 may be made of gallium oxide, hafnium oxide, or Oxides containing zirconium, aluminum and hafnium, aluminum and hafnium oxides containing silicon and hafnium, oxides containing silicon and hafnium, Hafnium-containing oxynitride or silicon and hafnium-containing nitride, etc. Alternatively, the insulators 402 and 412 may be made of silicon oxide or It is preferable that the film has a laminated structure of silicon oxynitride and an insulator having a high relative dielectric constant. Silicon nitride and silicon oxynitride are thermally stable and therefore act as insulators with high dielectric constants. By combining these, it is possible to create a thermally stable laminated structure with a high relative dielectric constant. For example, the insulators 402 and 412 may be made of aluminum oxide, gallium oxide, or By having hafnium oxide on the oxide 406c side, silicon oxide or silicon oxynitride This can prevent silicon contained in the silicon from being mixed into the oxide 406b. For example, insulators 402 and 412 may be made of silicon oxide or silicon oxynitride. By having the compound on the oxide 406c side, it is possible to form a compound such as aluminum oxide, gallium oxide, or halogen oxide. A trap center is formed at the interface between fluorine and silicon oxide or silicon oxynitride. The trapping centers may increase the threshold of the transistor by capturing electrons. In some cases, the value voltage can be changed in the positive direction.

[0110] Insulators 410 and 415 preferably comprise insulators with low dielectric constants. For example, the insulator 410 may be silicon oxide, silicon oxynitride, silicon nitride oxide, silicon nitride, or silicon nitride. Silicon, fluorine-doped silicon oxide, carbon-doped silicon oxide, carbon and nitrogen It is preferable to use silicon oxide doped with silicon dioxide, silicon oxide having pores, or resin. Alternatively, the insulator 410 may be silicon oxide, silicon oxynitride, silicon nitride oxide, Silicon nitride, fluorine-doped silicon oxide, carbon-doped silicon oxide, carbon and A laminated structure of silicon oxide with nitrogen added or silicon oxide with pores and resin. Silicon oxide and silicon oxynitride are thermally stable. Therefore, by combining it with resin, it is possible to create a thermally stable laminated structure with a low dielectric constant. Examples of resins include polyester, polyolefin, polyamide (nylon, aramid, polyimide, polycarbonate or acrylic.

[0111] The barrier film 417a1 and the barrier film 417a2 are formed by removing impurities such as hydrogen and oxygen. The barrier film 417a1 and the barrier The film 417a2 allows excess oxygen in the insulator 415 to pass through the conductor 416a1 and the conductor 416 This can prevent the spread to a2.

[0112] The barrier film 417a1 and the barrier film 417a2 may be made of, for example, aluminum oxide, Magnesium oxide, gallium oxide, germanium oxide, yttrium oxide, zirconium oxide Metal oxides such as ammonium, lanthanum oxide, neodymium oxide, hafnium oxide or tantalum oxide Silicon oxide, silicon nitride, silicon nitride, or the like may be used.

[0113] <Conductors> Conductor 404a, Conductor 404b, Conductor 310a, Conductor 310b, Conductor 416a 1. The conductor 416a2, the electrode 450 and the electrode 451 may be made of aluminum, chromium, Copper, silver, gold, platinum, tantalum, nickel, titanium, molybdenum, tungsten, hafnium Aluminum, vanadium, niobium, manganese, magnesium, zirconium, beryllium, indium Materials containing one or more metal elements selected from the group consisting of ammonium, ammonium, and phosphorus can also be used. semiconductors with high electrical conductivity, such as polycrystalline silicon containing impurity elements, Silicides such as kelsilicide may also be used.

[0114] In addition, the metals applicable to oxide 406a, oxide 406b, and oxide 406c described later can be used. Alternatively, a conductive material containing oxygen and a metal element contained in a metal oxide may be used. Conductive materials containing metal elements and nitrogen may also be used. For example, titanium nitride, titanium nitride, Alternatively, a conductive material containing nitrogen, such as indium tin oxide (ITO), may be used. Indium Tin Oxide, indium oxide containing tungsten oxide, oxide Indium zinc oxide containing tungsten, indium oxide containing titanium oxide, titanium oxide Indium tin oxide containing tungsten, indium zinc oxide, silicon-doped indium Tin oxide may be used. Indium gallium zinc oxide containing nitrogen may also be used. By using such a material, oxide 406a, oxide 406b, and oxide 406c are formed. It may be possible to capture hydrogen contained in 6c. Or, it may be possible to capture hydrogen from the outer insulator. In some cases, it may be possible to capture the invading hydrogen.

[0115] Alternatively, a plurality of conductive layers made of the above materials may be stacked. A laminated structure in which a material containing a metal element and a conductive material containing oxygen are combined may be used. In addition, a laminated layer that combines the material containing the metal element and the conductive material containing nitrogen is also available. In addition, a material containing the above-mentioned metal element, a conductive material containing oxygen, and a material containing nitrogen may be used. A laminated structure may be formed by combining a conductive material containing a silicon dioxide.

[0116] When an oxide is used for the channel formation region of a transistor, the The laminated structure is made by combining the material containing the metal element and the conductive material containing oxygen. In this case, it is preferable to provide a conductive material containing oxygen on the channel formation region side. By providing a conductive material containing oxygen on the channel formation region side, The released oxygen is more easily supplied to the channel formation region.

[0117] <Metal oxides applicable to oxide 406a, oxide 406b, and oxide 406c> The oxide 406a, the oxide 406b, and the oxide 406c are made of metal oxides. However, instead of the oxide 406a, the oxide 406b, and the oxide 406c, In addition, silicon (including strained silicon), germanium, silicon germanium, silicon carbide gallium arsenide, aluminum gallium arsenide, indium phosphide, gallium nitride or In some cases, it may be acceptable to use an organic semiconductor.

[0118] Next, the metal oxides applicable to oxide 406a, oxide 406b, and oxide 406c are This article explains:

[0119] The metal oxide preferably contains at least indium or zinc. In addition to these, aluminum, gallium, It is preferable that yttrium or tin is contained. Also, boron, silicon, Titanium, iron, nickel, germanium, zirconium, molybdenum, lanthanum, cerium , neodymium, hafnium, tantalum, tungsten, magnesium, etc. One or more of these may be included.

[0120] Here, the metal oxide is InMZnO, which has indium, element M, and zinc. The element M can be aluminum, gallium, yttrium, tin, etc. Other elements that can be used for element M include boron, silicon, titanium, iron, Nickel, germanium, zirconium, molybdenum, lanthanum, cerium, neodymium, Hafnium, tantalum, tungsten, magnesium, etc. However, as the element M In some cases, a combination of the above elements may be used.

[0121] <Structure> Oxides are divided into single crystal oxides and other non-single crystal oxides. Examples of the crystals include CAAC-OS (c-axis aligned crystals). Line oxide semiconductor), polycrystalline oxide, nc-OS( nanocrystalline oxide semiconductor), pseudo-non amorphous-like oxide (a-like OS) These include amorphous oxides and amorphous semiconductors.

[0122] CAAC-OS has a c-axis orientation and multiple nanocrystals are connected in the ab-plane direction. The crystal structure is distorted by the connection of multiple nanocrystals. In the region, the lattice arrangement is changed between a region with a uniform lattice arrangement and another region with a uniform lattice arrangement. This refers to the point where the direction of the

[0123] Nanocrystals are basically hexagonal, but are not limited to regular hexagonal shapes. They may also have non-regular hexagonal shapes. In addition, the distortion may have lattice arrangements such as pentagons and heptagons. In addition, in CAAC-OS, clear grain boundaries (grain bows) are not observed even near the strain. It is not possible to confirm the presence of grain boundaries (also called grain boundaries). This is because the CAAC-OS has a crystalline structure in the ab-plane direction. The oxygen atoms are not densely packed, and the bond distance between atoms is shortened by the substitution of metal elements. This is thought to be because distortion can be tolerated by changing the thickness of the film.

[0124] In addition, the CAAC-OS has a layer containing indium and oxygen (hereinafter referred to as an In layer) and an elemental A layered crystal consisting of layers containing element M, zinc, and oxygen (hereinafter referred to as the (M,Zn) layer). It is noted that indium and element M tend to have a structure (also called a layered structure). When the element M in the (M,Zn) layer is replaced with indium, the (In,M,Zn) ) layer. Also, when indium in the In layer is replaced with element M, it can be expressed as (In, It can also be expressed as the M layer.

[0125] nc-OS is a material that can be used in microscopic areas (e.g., areas between 1 nm and 10 nm, especially areas between 1 nm and 10 nm). The atomic arrangement is periodic in the region of 3 nm or less. There is no regularity in the crystal orientation between the crystals. Therefore, no orientation is observed throughout the film. Therefore, depending on the analytical method, nc-OS can be distinguished from a-like OS and amorphous oxides. There may be cases where there is no distinction.

[0126] a-like OS is an oxide with a structure between nc-OS and amorphous oxides. The a-like OS has voids or low density regions. It has lower crystallinity than nc-OS and CAAC-OS.

[0127] Oxides have a variety of structures, each with different properties. The materials are amorphous oxides, polycrystalline oxides, a-like OS, nc-OS, and CAAC-OS. The compound may have two or more of the above.

[0128] <Atomic ratio> Next, with reference to FIGS. 23(A), 23(B), and 23(C), the oxidation method according to the present invention will be described. A preferred range of the atomic ratio of indium, element M, and zinc contained in the material will be described below. In addition, in Figures 23(A), 23(B), and 23(C), the atomic ratio of oxygen is The atomic ratio of indium, element M, and zinc contained in the oxide is not described. Let the terms be [In], [M], and [Zn], respectively.

[0129] In Figures 23(A), 23(B), and 23(C), the dashed lines indicate the ratio of [In]:[M ]:[Zn]=(1+α):(1-α):1 atomic ratio (-1≦α≦1), The line where the atomic ratio of [In]:[M]:[Zn]=(1+α):(1-α):2, [ The line where the atomic ratio of In]:[M]:[Zn]=(1+α):(1-α):3 is n]:[M]:[Zn]=(1+α):(1-α):4, and The line where the atomic ratio of [In]:[M]:[Zn]=(1+α):(1-α):5 is shown. vinegar.

[0130] The dashed line indicates the atomic ratio of [In]:[M]:[Zn]=5:1:β (β≧0). The line where the atomic ratio of [In]:[M]:[Zn]=2:1:β is ]:[M]:[Zn]=1:1:β, the atomic ratio line, [In]:[M]:[Zn ]=1:2:β, and the atomic ratio of [In]:[M]:[Zn]=1:3:β. The atomic ratio of [In]:[M]:[Zn]=1:4:β Represents a line.

[0131] In addition, the [In]:[M]: Oxides with an atomic ratio of [Zn]=0:2:1 and values ​​close to it have a spinel-type crystal structure. Easy to take.

[0132] In addition, multiple phases may coexist in an oxide (two-phase coexistence, three-phase coexistence, etc.). For example, When the atomic ratio is close to [In]:[M]:[Zn]=0:2:1, the spinel type The two phases of the crystal structure and the layered crystal structure tend to coexist. When the value of Zn is close to 1:0:0, the bixbyite-type crystal structure and the layered crystal structure are When multiple phases coexist in an oxide, two phases with different crystal structures tend to coexist. Grain boundaries may be formed between the grains.

[0133] The region A shown in FIG. 23(A) is the region containing the elements of indium, element M, and zinc contained in the oxide. An example of a preferred range of the electron number ratio is shown.

[0134] By increasing the indium content of the oxide, the carrier mobility (electron mobility) of the oxide can be improved. Therefore, oxides with a high indium content can increase the The carrier mobility is higher compared to oxides with lower content.

[0135] On the other hand, when the content of indium and zinc in the oxide is low, the carrier mobility is low. Therefore, the atomic ratio [In]:[M]:[Zn]=0:1:0 and its neighboring values In this case (for example, region C shown in FIG. 23(C)), the insulating properties are high.

[0136] Therefore, the oxide according to one embodiment of the present invention has high carrier mobility and few grain boundaries. It is preferable that the atomic ratio shown in region A in FIG. 23(A) be such that a layered structure is easily formed. stomach.

[0137] In particular, in region B shown in FIG. 23(B), CAAC-OS is more likely to occur than in region A. In this way, an excellent oxide having high carrier mobility can be obtained.

[0138] CAAC-OS is a highly crystalline oxide. On the other hand, CAAC-OS has clear crystalline grains. Since the grain boundaries cannot be seen, the decrease in electron mobility caused by the grain boundaries is unlikely to occur. In addition, the crystallinity of oxides can be reduced by the incorporation of impurities or the generation of defects. Therefore, CAAC-OS can be considered an oxide with few impurities and defects (such as oxygen vacancies). Therefore, the physical properties of oxides containing CAAC-OS are stable. Oxides containing C-OS are heat resistant and highly reliable.

[0139] Region B is [In]:[M]:[Zn]=4:2:3 to 4.1 and its vicinity. Near values ​​include, for example, [In]:[M]:[Zn]=5:3:4 In addition, region B is [In]:[M]:[Zn]=5:1:6 and its neighboring values, and and [In]:[M]:[Zn]=5:1:7, and their neighboring values.

[0140] The properties of oxides are not uniquely determined by the atomic ratio. Even if the oxide is formed, the properties of the oxide may differ depending on the formation conditions. When a film is formed using a targeting device, the resulting film has an atomic ratio that differs from the atomic ratio of the target. In addition, depending on the substrate temperature during film formation, the [Zn] in the film may be higher than the [Zn] in the target. Therefore, the regions shown are areas where oxides tend to have particular properties. The regions show a certain atomic ratio, and the boundaries between regions A and C are not strict.

[0141] [Oxide-based transistors] Next, the case where the oxide is used in a transistor will be described.

[0142] By using the oxide in a transistor, carrier scattering at the grain boundary can be prevented. This allows for the realization of transistors with high field-effect mobility. Furthermore, a highly reliable transistor can be realized.

[0143] In addition, it is preferable to use an oxide film with low carrier density for the transistor. When the carrier density of the oxide film is reduced, the impurity concentration in the oxide film is reduced, and the defects are reduced. In this specification and the like, the low impurity concentration and the low defect level density are For example, an oxide film has a high carrier density. Degrees are 8 x 10 11 / cm 3 Less than 1 x 10 11 / cm 3 Less than, preferably is 1 x 10 10 / cm 3 Less than 1 x 10 -9 / cm 3 That's all there is to it.

[0144] Furthermore, a highly pure intrinsic or substantially highly pure intrinsic oxide film has a low defect level density. Therefore, the trap level density may also be low.

[0145] In addition, the charges trapped in the oxide trap levels take a long time to disappear, Therefore, oxides with high trap level density can behave as if they are fixed charges. A transistor in which a channel formation region is formed in a material may have unstable electrical characteristics. .

[0146] Therefore, in order to stabilize the transistor characteristics, it is necessary to reduce the impurity concentration in the oxide. In order to reduce the impurity concentration in the oxide, it is effective to It is also preferable to reduce the concentration of impurities. These include lithium-earth metals, iron, nickel, and silicon.

[0147] <Impurities> Here, the influence of each impurity in the oxide will be explained.

[0148] When oxides contain silicon or carbon, which are elements of Group 14, Therefore, the concentration of silicon and carbon in the oxide and the The concentration of silicon and carbon near the interface with the silicon substrate was measured by secondary ion mass spectrometry (SIMS). The concentration obtained by ion mass spectrometry (Ion Mass Spectrometry) was calculated by 2× 10 18 atoms / cm 3 Less than or equal to 2 x 10 17 atoms / cm 3 The following do.

[0149] In addition, if an oxide contains an alkali metal or alkaline earth metal, a defect level is formed. Therefore, alkali metals or alkaline earth metals are Transistors using oxides containing SiO2 tend to be normally-on. It is preferable to reduce the concentration of alkali metals or alkaline earth metals in the oxide. The concentration of alkali metals or alkaline earth metals in the oxide obtained by SIMS is , 1×10 18 atoms / cm 3 Less than or equal to 2 x 1016 atoms / cm 3 Below Put it down.

[0150] In addition, when nitrogen is contained in an oxide, electrons that act as carriers are generated, and the carrier density As a result, transistors using oxides containing nitrogen as semiconductors Therefore, in the oxide, nitrogen is easily For example, the nitrogen concentration in the oxide is preferably as low as possible by SIMS. , 5×10 19 atoms / cm 3 Less than 5 x 10 18 atoms / cm 3 Below or less, more preferably 1 x 10 18 atoms / cm 3 Less than 5 × 10, more preferably 1 7 atoms / cm 3 The following applies.

[0151] In addition, the hydrogen contained in the oxide reacts with the oxygen that bonds with the metal atom to form water, so the acid When hydrogen enters the oxygen vacancy, electrons, which act as carriers, are generated. In addition, some of the hydrogen atoms may bond with oxygen atoms that bond with metal atoms, forming carriers. Therefore, transistors using oxides containing hydrogen can generate electrons. Therefore, hydrogen in the oxide should be reduced as much as possible. Specifically, it is preferable that the hydrogen concentration in the oxide is measured by SIMS. Degrees, 1 x 10 20 atoms / cm 3 Less than 1 x 10 19 atoms / cm 3 less than 5 × 1018 atoms / cm 3 Less than 1×1 0 18 atoms / cm 3 Less than.

[0152] By using an oxide with sufficiently reduced impurities for the channel formation region of a transistor, Stable electrical properties can be imparted.

[0153] <Band diagram> Next, the case where the oxide has a two-layer structure or a three-layer structure will be described. , oxide S2, and oxide S3, and the band diagram of the insulator adjacent to the stacked structure. The band diagram of the stacked structure of oxide S2 and oxide S3, and the insulator adjacent to the stacked structure. The band diagram of the stacked structure of oxide S1 and oxide S2, and the insulator adjacent to the stacked structure. The above will be explained with reference to FIG.

[0154] FIG. 24(A) shows an insulator I1, an oxide S1, an oxide S2, an oxide S3, and an insulator I 24(B) is an example of a band diagram in the film thickness direction of a laminated structure having an insulator 2. Bands in the thickness direction of a stacked structure consisting of I1, oxide S2, oxide S3, and insulator I2 24(C) shows an example of the insulator I1, the oxide S1, the oxide S2, and 1 is an example of a band diagram in the film thickness direction of a laminated structure having an insulator I2. To simplify the solution, we will use insulator I1, oxide S1, oxide S2, oxide S3, and insulator I. The energy level (Ec) at the bottom of the conduction band of 2 is shown.

[0155] The oxides S1 and S3 have a lower energy level at the bottom of the conduction band closer to the vacuum level than the oxide S2. The energy level of the conduction band minimum of oxide S2 is close to that of oxide S1. The difference in energy level from the bottom of the conduction band of S3 is 0.15 eV or more, or 0.5 eV or more and preferably 2 eV or less, or 1 eV or less. The difference between the electron affinity of the oxide S3 and the electron affinity of the oxide S2 is 0.15 eV or more, or It is preferably 0.5 eV or more and 2 eV or less, or 1 eV or less.

[0156] As shown in Figures 24(A), 24(B), and 24(C), oxide S1, oxide In oxide S2 and oxide S3, the energy level at the bottom of the conduction band changes gradually. If we have such a band diagram, we can say that it changes continuously or that it is a continuous junction. In order to do this, the interface between oxide S1 and oxide S2 or the interface between oxide S2 and oxide S3 must be It is preferable to reduce the defect level density of the mixed layer formed on the surface.

[0157] Specifically, oxides S1 and S2, and oxides S2 and S3 have common elements other than oxygen. By containing the element (as the main component), a mixed layer with a low defect level density can be formed. For example, when oxide S2 is an In-Ga-Zn oxide, oxides S1 and S3 are For this purpose, it is preferable to use In-Ga-Zn oxide, Ga-Zn oxide, gallium oxide, or the like.

[0158] At this time, the main path of the carriers is the oxide S2. The defect level density at the interface between the oxide S2 and the oxide S3 can be reduced. Therefore, the effect of interface scattering on carrier conduction is small, resulting in a high on-state current.

[0159] When electrons are captured in the trap level, the captured electrons behave like fixed charges. Therefore, the threshold voltage of the transistor shifts in the positive direction. By providing the oxide S3, the trap level can be kept away from the oxide S2. This structure prevents the threshold voltage of the transistor from shifting in the positive direction. It is possible.

[0160] Oxide S1 and oxide S3 are materials with sufficiently low electrical conductivity compared to oxide S2. At this time, the oxide S2, the interface between the oxide S2 and the oxide S1, and the oxide S2 and the oxide S1 are The interface with the oxide S3 mainly functions as the channel formation region. The oxide S3 has an atomic ratio shown in region C in FIG. 23(C) where the insulating property is high. In the region C shown in FIG. 23(C), [In]:[M]:[Zn]=0 :1:0 and its neighbors, [In]:[M]:[Zn]=1:3:2 and its neighbors value, and the atomic ratio of [In]:[M]:[Zn]=1:3:4 and its neighboring values This shows:

[0161] In particular, when oxide S2 is an oxide having an atomic ratio shown in region A, oxide S1 and For the oxide S3, an oxide having [M] / [In] of 1 or more, preferably 2 or more is used. In addition, it is preferable that the oxide S3 has a sufficiently high insulating property [M]. It is preferable to use an oxide in which / ([Zn]+[In]) is 1 or more.

[0162] This embodiment may be implemented by appropriately combining with the configurations described in other embodiments or examples. It is possible to do this.

[0163] (Embodiment 2) A method for manufacturing the semiconductor device shown in FIG. 1 will be described below with reference to FIGS.

[0164] <Method for manufacturing semiconductor device> In Fig. 6 to Fig. 15, (A) of each figure is a top view. (B) of each figure is a bottom view. ) is a cross-sectional view of the part indicated by the dashed line A1-A2 in each figure. A) is a cross-sectional view of the portion indicated by the dashed line A3-A4 in each figure. A2 is a cross-sectional view of the transistor in the channel length direction, and in (C) of each figure, A3-A 4 is a cross-sectional view of the transistor in the channel width direction.

[0165] First, a substrate 400 is prepared.

[0166] Next, an oxide film 401a is formed. The oxide film 401a can be formed by a sputtering method, a chemical method, or the like. Chemical Vapor Deposition (CVD), molecular beam Epitaxy (MBE: Molecular Beam Epitaxy) method, pulsed laser Pulsed Laser Deposition (PLD) or atomic layer deposition This is done using deposition (ALD: Atomic Layer Deposition) method, etc. It is possible.

[0167] The CVD method is a plasma CVD (PECVD) method that uses plasma. Enhanced CVD (TCVD) method, and thermal CVD (TCVD) method. These methods can be further classified into the VD method, which uses light, and the Photo CVD method. Depending on the source gas, metal CVD (MCVD) and metal organic CVD are used. (MOCVD: Metal Organic CVD) method.

[0168] The plasma CVD method can produce high-quality films at relatively low temperatures. This film formation method does not use a plasma, so it is possible to reduce plasma damage to the object being treated. For example, wiring, electrodes, elements (transistors, capacitors, etc.) included in a semiconductor device ) may become charged up by receiving an electric charge from the plasma. When accumulated electric charges destroy wiring, electrodes, elements, etc. included in a semiconductor device. On the other hand, in the case of thermal CVD methods that do not use plasma, such plasma damage occurs. In addition, the thermal CVD method can increase the yield of semiconductor devices. Since no plasma damage occurs in the film, a film with few defects can be obtained.

[0169] The ALD method is also a film formation method that can reduce plasma damage to the workpiece. In addition, the ALD method does not cause plasma damage during film formation, so films with few defects can be produced. is obtained.

[0170] The CVD and ALD methods are film formation methods in which particles emitted from a target are deposited. It is a film forming method in which a film is formed by a reaction on the surface of the object to be treated. Therefore, this is a film forming method that is less affected by the shape of the workpiece and has good step coverage. In addition, the ALD method has excellent step coverage and thickness uniformity, making it suitable for forming thin films with high aspect ratios. However, the ALD method is relatively slow in forming films. Because the deposition rate is slow, it should be used in combination with other deposition methods such as CVD, which has a high deposition rate. may be preferable.

[0171] In the CVD and ALD methods, the composition of the resulting film is controlled by the flow rate ratio of the source gases. For example, in the CVD and ALD methods, the flow rate ratio of the source gases can be adjusted to any value. In addition, for example, in the CVD method and the ALD method, it is possible to form a film having the following composition. By changing the flow rate ratio of the source gases while oxidizing, a film with a continuously changing composition can be formed. When forming a film while changing the flow rate ratio of the source gases, multiple film forming chambers can be used. Compared to forming a film using a vacuum chamber, the time required for film formation is shorter due to the time required for transport and pressure adjustment. Therefore, the productivity of the semiconductor device can be increased in some cases.

[0172] Next, oxide 401b is formed on oxide 401a. The deposition can be performed by a deposition method, a CVD method, an MBE method, a PLD method, an ALD method, or the like. Next, the insulator 301 is formed on the oxide 401b. The insulator 301 is formed by sputtering. The deposition can be carried out by using a laser deposition method, a CVD method, an MBE method, a PLD method, an ALD method, or the like.

[0173] Next, a groove is formed in the insulator 301, reaching the oxide 401b. The groove may be, for example, a recess or The grooves may be formed by wet etching, but the grooves may be formed by driving. In addition, the oxide 401b is formed on the insulator 3. An insulator that functions as an etching stopper film when etching O1 to form a groove is selected. For example, when a silicon oxide film is used as the insulator 301 for forming the groove, In this case, the oxide 401b is a silicon nitride film, an aluminum oxide film, or a hafnium oxide film. It would be good to do so.

[0174] In this embodiment, the oxide 401a is formed by sputtering aluminum oxide. Then, an aluminum oxide film is formed as the oxide 401b by the ALD method. Further, as the insulator 301, a silicon oxide film is formed by the CVD method.

[0175] After the grooves are formed, a conductor that will become the conductor 310a is deposited. It is desirable that the insulating layer contains a conductor having a function of suppressing oxygen permeation. Tantalum, tungsten nitride, titanium nitride, etc. can be used. Tungsten, titanium, molybdenum, aluminum, copper, molybdenum-tungsten alloys The conductive material to be the conductive material 310a can be formed by a sputtering method, This can be done using a CVD method, an MBE method, a PLD method, an ALD method, or the like.

[0176] In this embodiment, the conductor 310a is formed by sputtering a nitride film. A tantalum chloride film is formed.

[0177] Next, a conductor that will become the conductor 310b is formed as a film on the conductor that will become the conductor 310a. The conductive film that becomes the conductive body 310b can be formed by a sputtering method, a CVD method, an MBE method, or a PLD method. Alternatively, it can be performed using an ALD method or the like.

[0178] In this embodiment, the conductor 310b is formed by depositing titanium nitride by a CVD method. A film of titanium nitride is formed, and a film of tungsten is formed on the titanium nitride by a CVD method.

[0179] Next, Chemical Mechanical Polishin 3.g: CMP) is performed to form the conductor 310a on the insulator 301 and the conductor As a result, the conductor that will become conductor 310a is removed only in the groove. The conductor that will become the conductor 310a and the conductor 310b remains. A conductor 310 including b can be formed.

[0180] Next, the insulator 302 is formed on the insulator 301 and the conductor 310. The film is formed by sputtering, CVD, MBE, PLD, ALD, etc. This can be done.

[0181] Next, an insulator 303 is formed on the insulator 302. The insulator 303 is formed by sputtering. The deposition can be carried out by using a deposition method, a CVD method, an MBE method, a PLD method, an ALD method, or the like.

[0182] Next, the insulator 402 is deposited on the insulator 303. The insulator 402 is deposited by sputtering. The deposition can be carried out by using a deposition method, a CVD method, an MBE method, a PLD method, an ALD method, or the like.

[0183] In this embodiment, silicon oxynitride is deposited as the insulator 302 by a CVD method. As the insulator 303, hafnium oxide is deposited by the ALD method, and as the insulator 402, A silicon oxynitride film is formed using the CVD method.

[0184] Next, CMP may be performed to planarize the top surface of the insulator 402. The height of the conductor 310 and the height of the upper surface of the insulator 301 are different, and the upper surface of the conductor 310 and the upper surface of the insulator 301 are different. , a step may occur near the boundary. By reducing the step by CMP, This prevents the coverage of the film to be formed later from being deteriorated, and prevents a decrease in the yield of the semiconductor device. The step after CMP is preferably 3 nm or less, more preferably 1 nm or less. do.

[0185] Next, a first heat treatment is preferably performed. The first heat treatment is performed at a temperature of 250° C. or higher and 650° C. or lower. The temperature is preferably 450°C or higher and 600°C or lower, and more preferably 520°C or higher and 570°C or lower. The first heat treatment is carried out in a nitrogen or inert gas atmosphere, or in an atmosphere containing an oxidizing gas at 10 ppm. The first heat treatment is carried out in an atmosphere containing 1% or more, 1% or more, or 10% or more. Alternatively, the first heat treatment may be performed in a nitrogen or inert gas atmosphere, followed by degassing. To compensate for the oxygen that has been released, an atmosphere containing oxidizing gases of 10 ppm or more, 1% or more, or 10% or more is used. The first heat treatment may be performed in an atmosphere. In the first heat treatment, impurities such as fluorine and fluorine can be removed. A plasma treatment containing oxygen may be performed. The plasma treatment containing oxygen may be performed using, for example, microwaves. It is preferable to use an apparatus having a power supply that generates high density plasma using Alternatively, a power source for applying RF (Radio Frequency) may be provided on the substrate side. By using high density plasma, high density oxygen radicals can be generated, and R By applying F, oxygen radicals generated by high-density plasma are efficiently converted into insulator 4 Alternatively, this device can be used to perform plasma treatment containing an inert gas. After the treatment, a plasma treatment containing oxygen may be performed to compensate for the oxygen that has been desorbed. In some cases, the heat treatment may not be necessary.

[0186] The heat treatment is performed after the formation of the insulator 302, the formation of the insulator 303, and the formation of the insulator 402. The heat treatment can be carried out after the film formation. The heat treatment can be carried out under the first heat treatment conditions. However, the heat treatment after the formation of the insulator 302 is preferably performed in an atmosphere containing nitrogen.

[0187] In this embodiment, after the insulator 402 is formed, the insulator is heated at 400° C. for 1 hour in a nitrogen atmosphere. After the treatment, a subsequent treatment is carried out in an oxygen atmosphere at a temperature of 400° C. for 1 hour.

[0188] Next, an oxide 406a1 is deposited over the insulator 402. It can be performed using methods such as sputtering, CVD, MBE, PLD, or ALD. can.

[0189] Next, a process for adding oxygen to the oxide 406a1 may be performed. The oxide 406a is formed by, for example, ion implantation or plasma treatment. The oxygen added to oxide 406a1 becomes excess oxygen. The oxide 406b1 is formed by sputtering, CVD, MBE, PLD, etc. The method can be carried out by using the ALD method or the like.

[0190] Next, a second heat treatment may be performed. The heat treatment may be performed under the same conditions as the first heat treatment. The second heat treatment removes impurities such as hydrogen and water from the oxide 406b1. In this embodiment, the treatment is carried out in a nitrogen atmosphere at a temperature of 400° C. for 1 hour. After that, the substrate is treated in an oxygen atmosphere at 400° C. for 1 hour.

[0191] Next, the conductor 416 is deposited on the oxide 406b1. The deposition can be performed by a deposition method, a CVD method, an MBE method, a PLD method, an ALD method, or the like. The conductor 416 is made of a conductive oxide, for example, indium tin oxide (ITO). : Indium Tin Oxide), indium oxide containing tungsten oxide, acid Indium zinc oxide containing tungsten oxide, indium oxide containing titanium oxide, Titanium-doped indium tin oxide, indium zinc oxide, silicon-doped indium A film of indium tin oxide or nitrogen-containing indium gallium zinc oxide is formed on the oxide, Aluminum, chromium, copper, silver, gold, platinum, tantalum, nickel, titanium, molybdenum, Tungsten, hafnium, vanadium, niobium, manganese, magnesium, zirconium Materials containing one or more metal elements selected from aluminum, beryllium, indium, etc., or Semiconductors with high electrical conductivity, such as polycrystalline silicon containing impurity elements such as silicon, A silicide such as nickel silicide may also be deposited.

[0192] The oxide absorbs hydrogen in the oxide 406a1 and the oxide 406b1 and absorbs it from the outside. It may have the function of capturing diffusing hydrogen, which may affect transistor characteristics and reliability. Alternatively, titanium may be used in place of the oxide to achieve the same function. In this embodiment, a tantalum nitride film is formed as the conductor 416.

[0193] Next, a barrier film 417 is formed on the conductor 416. The barrier film 417 is formed by sputtering. The deposition can be performed by a deposition method, a CVD method, an MBE method, a PLD method, an ALD method, or the like. In this embodiment, the barrier film 417 is formed of aluminum oxide.

[0194] Next, a conductor 411 is formed on the barrier film 417. The conductor 411 is formed by sputtering. This can be done using a laser deposition method, a CVD method, an MBE method, a PLD method, an ALD method, or the like. In this embodiment, a tantalum nitride film is formed as the conductor 411 (FIGS. 6(A) and 6(B)). ) and (C).

[0195] Next, the conductor 411 is processed by lithography to form the conductor 411a. In this processing, it is preferable that the cross section of the conductor 411a has a tapered shape. The taper angle is 30 degrees or more and less than 75 degrees with respect to a plane parallel to the bottom surface of the substrate, preferably The taper angle is between 30 degrees and 70 degrees. The coating property of the film in the film process is improved. In addition, the processing is performed by using a dry etching method. The processing by dry etching is preferably performed in the fine processing and the processing of the above-mentioned tapered shape. (See Figures 7(A), (B) and (C)).

[0196] In the lithography method, first, the resist is exposed to light through a mask. The resist mask is formed by removing or leaving the resist patterned area using a developer. By etching through the resist mask, a conductor, a semiconductor, an insulator, etc. For example, KrF excimer laser light, ArF excimer laser light, Laser light, EUV (Extreme Ultraviolet) light, etc. A resist mask can be formed by exposing the substrate to light. An immersion technique may be used in which the substrate is filled with a liquid (for example, water) and exposed to light. Alternatively, an electron beam or an ion beam may be used. In this case, the mask is not required. Which dry etching process should be performed, which wet etching process should be performed, and which dry etching process should be performed? wet etching after treatment, or wet etching after dry etching A processing can be performed.

[0197] The dry etching equipment is a capacitively coupled plasma (CCP) device with parallel plate electrodes. (Capacitively Coupled Plasma) etching equipment is used. The capacitively coupled plasma etching apparatus having parallel plate electrodes can Alternatively, a high frequency power supply may be applied to one of the parallel plate type electrodes. Alternatively, a parallel plate electrode may be used. Alternatively, a parallel plate electrode may be used. Alternatively, a high-density plasma source may be provided. A dry etching apparatus having a high density plasma source can be used. The plasma processing device is, for example, an inductively coupled plasma (ICP) type. A plasma etching device or the like can be used.

[0198] Next, a resist 421 is formed by lithography.

[0199] Next, the conductor 411a, the barrier film 417, and the resist 421 are etched using the resist 421 as an etching mask. The conductor 411a1, the conductor 411a2, the barrier film 41 7a and the conductor 416a are formed (see FIGS. 8(A), (B) and (C)).

[0200] Next, after removing the resist 421, the conductors 411a1 and 411a2 are etched. The barrier film 417a is etched using the etching mask, and the barrier film 417a1 and the barrier film 417b are removed. A rear film 417a2 is formed.

[0201] Next, the surfaces of the conductors 411a1, 411a2, and 416a are exposed. The oxide 406a1 and the oxide 406b1 are etched using the portions as an etching mask. In this embodiment, the conductor 41 is Tantalum nitride is used for the conductors 1a1, 411a2, and 416a. The etching rate of oxide 406a1 and oxide 406b1 is compared with that of tantalum nitride. It is preferable to process the tantalum nitride under etching conditions that result in a faster etching rate. If the etching rate of the oxide 406a1 and the oxide 406b1 is 1, The speed is set to 3 or more and 50 or less, preferably 5 or more and 30 or less (FIGS. 9(A), (B) and See (C). ).

[0202] Next, the surfaces of the conductors 411a1, 411a2, and 416a are exposed. The remaining portions are etched to form conductors 416a1 and 416a2 (FIG. 10(A)). ), (B) and (C). Here, as shown in FIG. 10(C), oxide 406b The oxide 406b may have a curved surface between the side and top surfaces. is between 3 nm and 10 nm.

[0203] Next, wash with a solution of hydrofluoric acid diluted with carbonated water or pure water (diluted hydrofluoric acid solution). In this embodiment, cleaning is performed using a mixed solution of carbonated water and hydrofluoric acid. The concentration of hydrofluoric acid is approximately 70 ppm.

[0204] Next, a third heat treatment may be performed. The heat treatment conditions may be the same as those for the first heat treatment. In this embodiment, the third heat treatment is not performed.

[0205] By performing conventional dry etching, impurities originating from etching gas are removed. The oxide 406a and the oxide 406b may adhere to or diffuse into the surface or the interior of the oxide 406a and the oxide 406b. The impurities include, for example, fluorine or chlorine.

[0206] By carrying out the above-mentioned treatment, the concentration of these impurities can be reduced. The moisture concentration and hydrogen concentration in the oxide 406a film and the oxide 406b film can be reduced. can.

[0207] Next, an oxide film 406c1 is formed. The oxide film 406c1 is formed by a sputtering method. The deposition can be carried out by using a CVD method, an MBE method, a PLD method, an ALD method, or the like. It is preferable to form the film by sputtering. A mixed gas of oxygen and argon is used, preferably under conditions of high oxygen partial pressure, more preferably under conditions of oxygen The film is formed at room temperature or at a temperature of 100° C. or higher and 200° C. or lower using the conditions of only the SiO 2 film.

[0208] By forming the oxide 406c1 under the above conditions, the oxide 406a and the oxide Preferably, excess oxygen can be added to the material 406b and the insulator 402.

[0209] Next, the insulator 412a is deposited over the oxide 406c1. It can be performed using methods such as sputtering, CVD, MBE, PLD, or ALD. (See Figures 11(A), (B) and (C)).

[0210] Here, a fourth heat treatment may be performed. The heat treatment may be performed under the same conditions as the first heat treatment. The heat treatment can reduce the moisture concentration and hydrogen concentration in the insulator 412a. In this embodiment, the fourth heat treatment is not performed.

[0211] Next, a film of a conductor that will become the conductor 404 is formed. It can be performed using methods such as sputtering, CVD, MBE, PLD, or ALD. can.

[0212] The conductor 404 may be a multilayer film including, for example, a conductor 404a and a conductor 404b. For example, the oxide used as the conductor for the conductor 404a may be the oxide 406c1 described above. Oxygen can be added to the insulator 412a by forming the insulator under similar conditions. The oxygen added to body 412a becomes excess oxygen.

[0213] Next, a conductor is formed on the oxide by sputtering, thereby The electrical resistance value of the oxide can be reduced to make it a conductor that becomes the conductor 404a. A conductor that will become the conductor 404b is formed on the conductor that will become the conductor 404a by sputtering or the like. In this embodiment, the conductor 404a is formed by sputtering. Titanium nitride is formed by the ring method, and a conductor that becomes the conductor 404b is formed by sputtering. A tungsten film is formed by the etching method.

[0214] Here, a fifth heat treatment may be performed. The heat treatment may be performed under the same conditions as the first heat treatment. In this embodiment, the fifth heat treatment is not performed.

[0215] The conductors to be the conductors 404a and 404b are formed by lithography. Thus, the conductor 404a and the conductor 404b are formed (FIGS. 12(A) and 12(B)). and (c).

[0216] Next, an oxide film may be formed to become the oxide 418. It is preferable to use a metal oxide, and the method is a sputtering method, a CVD method, an MBE method, a PL method, etc. For example, aluminum oxide can be produced by the ALD method. By forming a film of aluminum, the top and side surfaces of the conductor 404 are provided with fewer pinholes and are clean. Furthermore, since the film thickness can be uniformly formed, oxidation of the conductor 404 can be prevented. In this embodiment, aluminum oxide is deposited by the ALD method.

[0217] Next, the oxide that will become oxide 418, the insulator 412a, and the oxide 406c1 are lithographically The oxide 418, the insulator 412, and the oxide 406c are formed by the Pfie method. Here, the edge of the oxide 418, the edge of the insulator 412, and the edge of the oxide 406c are in the plane. In the channel length direction, the barrier film 417a1 and the barrier film 417a2 (See Figures 13(A), (B) and (C)).

[0218] Next, the insulator 415 is formed. The insulator 415 is formed by a sputtering method or a CVD method. The insulator 415 can be formed by using a method such as MBE, PLD, or ALD. It is preferable that the oxide 418 has a function of being more permeable to oxygen than the oxide 418. A silicon oxide film is formed by the CVD method.

[0219] Next, oxide 420 and oxide 422 are deposited. The film is preferably formed by using a metal oxide, and is formed by a sputtering method, a CVD method, an MBE method, etc. The deposition can be carried out by using a PLD method, an ALD method, or the like.

[0220] The oxide 420 is aluminum oxide deposited by sputtering using oxygen plasma. By forming an oxygen film, oxygen can be added to the insulator 415. The added oxygen is Excess oxygen is formed in the insulator 415, and by performing heat treatment after the formation of the oxide 420, The excess oxygen flows from the insulator 415 through the insulator 402 to the oxide 40 having the channel forming region. It is effectively added to 6b and can repair defects in the channel formation region.

[0221] The oxide 422 is made of aluminum oxide by ALD method. The film thickness can be uniformly formed with little hole, so impurities such as hydrogen can be prevented from entering from the outside. In addition, it is possible to prevent the oxygen added to the oxide 422 from diffusing outward. In this embodiment, aluminum oxide is deposited by sputtering as the oxide 420. A film of aluminum is formed, and then an aluminum oxide film is formed as oxide 422 by the ALD method.

[0222] Next, the insulator 410 is formed. The insulator 410 can be formed by a sputtering method, a CVD method, or the like. This can be done by using an MBE method, a PLD method, an ALD method, or the like. Next, CMP is performed to flatten the top surface of the insulator 410. (See Figures 14(A), (B) and (C)).

[0223] Next, the insulator 410, the oxide 422, the oxide 420, and the insulator are formed by lithography. An opening is formed through body 415 and barrier film 417a1 to conductor 416a1. A conductor is embedded in the opening to form an electrode 450. In addition, an insulator 410 and an oxide 4 22, the oxide 420, the insulator 415, and the barrier film 417a2, and the conductor 416a2 An opening is formed that reaches the substrate 451. A conductor is embedded in the opening to form an electrode 451 (FIG. 15( See A), (B) and (C).

[0224] When forming the opening, a conductor is formed on the insulator 410, and an insulating film is further formed on the conductor. An insulating film is formed, a resist mask is formed on the insulating film, and the resist mask is etched. The conductor and insulator are processed as a mask, and the conductor and insulator are used as an etching mask. The opening may be formed by the above method.

[0225] The conductive film forming the electrodes 450 and 451 can be formed by sputtering, CVD, or the like. The method can be performed by using a method such as an MBE method, a PLD method, or an ALD method. The conductors that form the electrodes 451 and 452 can have a multi-layer structure. Alternatively, a laminated structure may be used in which a conductor having a suppressing function and a conductor different from the conductor having the suppressing function are laminated. In this embodiment, titanium nitride and tungsten are successively deposited in this order by the CVD method. In this manner, the semiconductor device shown in FIG. 1 can be manufactured.

[0226] This embodiment may be implemented by appropriately combining with the configurations described in other embodiments or examples. It is possible to do this.

[0227] (Embodiment 3) In this embodiment, one mode of a semiconductor device will be described with reference to FIGS. The semiconductor device shown in FIGS. 6 and 17 includes a transistor 300, a transistor 200, and and a capacitance element 100 .

[0228] The transistor 200 is a transistor in which a channel is formed in a semiconductor layer including an oxide semiconductor. The transistor 200 is used in a memory device because its off-state current is small. This allows the memory contents to be retained for a long period of time. Since no refresh operation is required or the frequency of refresh operations is extremely low, Power consumption can be reduced sufficiently.

[0229] 16 and 17, the wiring 3001 is electrically connected to the source of the transistor 300. The wiring 3002 is electrically connected to the drain of the transistor 300. The wiring 3003 is electrically connected to one of the source and drain of the transistor 200. The wiring 3004 is electrically connected to the first gate of the transistor 200. 6 is electrically connected to the second gate of the transistor 200. The gate of the transistor 300 and the other of the source and drain of the transistor 200 are connected to a capacitance element. The wiring 3005 is electrically connected to one of the electrodes of the capacitor 100 . and is electrically connected.

[0230] In the semiconductor device shown in FIGS. 16 and 17, the potential of the gate of the transistor 300 can be maintained. This property allows information to be written, stored, and read, as shown below. It is Noh.

[0231] The writing and holding of information will be explained. First, the potential of the wiring 3004 is applied to the transistor. This sets the potential at which transistor 200 is in a conducting state, thereby making transistor 200 in a conducting state. As a result, the potential of the wiring 3003 is applied to the gate of the transistor 300 and the potential of the capacitor 100. The voltage is applied to a node FG electrically connected to one of the electrodes of the transistor 300. A predetermined charge is applied to the gate (write). Either the low-level charge or the high-level charge is given. After that, the potential of the wiring 3004 is changed so that the transistor 200 is turned off. By setting the potential at the node FG to 0V, the transistor 200 is turned off, and a charge is stored in the node FG. To be held (retained).

[0232] When the off-state current of the transistor 200 is small, the charge of the node FG is retained for a long period of time. It will be held.

[0233] Next, the reading of information will be explained. When a predetermined potential (constant potential) is applied to the wiring 3001, In this state, when an appropriate potential (read potential) is applied to the wiring 3005, the wiring 3002 The potential depends on the amount of charge held in the gate FG. In the case of a transistor of the type, when a high level charge is applied to the gate of the transistor 300, The apparent threshold voltage V th_H applies a low level voltage to the gate of transistor 300. The apparent threshold voltage V under load th_L Because it will be lower. Here, the apparent threshold voltage is the voltage required to make the transistor 300 "conductive." This refers to the required potential of the wiring 3005. Therefore, the potential of the wiring 3005 is V th _H and V th_L By setting the potential V0 between For example, in a write operation, a high-level charge is applied to node FG. In this case, the potential of the wiring 3005 is V0 (>V th_H ), then transistor 300 is On the other hand, if a low-level charge is applied to node FG, The potential of the wiring 3005 is V0( <V th_L ), transistor 300 remains "non-conducting" Therefore, by determining the potential of the wiring 3002, the node FG is maintained in the "state". The information stored in the memory can be read.

[0234] <Configuration Example 3 of Semiconductor Device> The semiconductor device of one embodiment of the present invention includes a transistor 300 and a transistor The transistor 200 is located above the transistor 300. The capacitor element 100 is provided above the transistor 300 and the transistor 200. It is being used.

[0235] The transistor 300 is disposed on a substrate 311, and includes a conductor 316, an insulator 315, and a substrate A semiconductor region 313 consisting of a part of 311 and functioning as a source region or a drain region. The semiconductor device has a low resistance region 314a that functions as a dielectric film, and a low resistance region 314b.

[0236] In this embodiment, the transistor 300 is described as an n-channel transistor. However, transistor 300 may be either a p-channel or an n-channel type.

[0237] The region where the channel of the semiconductor region 313 is formed, the region in the vicinity thereof, the source region, or In the low resistance region 314a which becomes the drain region and the low resistance region 314b, silicon It preferably contains a semiconductor such as a silicon-based semiconductor, and it preferably contains single crystal silicon. Or Ge (germanium), SiGe (silicon germanium), GaAs (gallium It may be made of materials containing gallium aluminum arsenide (GaAlAs) or GaAlAs (Gallium Aluminum Arsenide). Silicon with effective mass controlled by applying stress to the crystal lattice and changing the lattice spacing. Alternatively, GaAs and GaAlAs may be used to form a transistor. The Star 300 is a HEMT (High Electron Mobility Transistor) stor) can also be used.

[0238] The low resistance region 314a and the low resistance region 314b are formed by the semiconductor layer applied to the semiconductor region 313. In addition to the conductive material, elements that impart n-type conductivity, such as arsenic and phosphorus, or p-type conductivity, such as boron, are added. It contains elements that impart electrical conductivity to the material.

[0239] The conductor 316, which functions as a gate electrode, is made of arsenic, phosphorus, or the like, which provides n-type conductivity. Semiconductor materials such as silicon that contain elements or elements that give them p-type conductivity, such as boron Conductive materials such as aluminum, metal, alloy, or metal oxide materials can be used. .

[0240] The threshold voltage can be adjusted by determining the work function depending on the conductor material. Specifically, it is preferable to use materials such as titanium nitride and tantalum nitride for the conductor. Furthermore, in order to achieve both conductivity and embeddability, tungsten or aluminum is used as the conductor. It is preferable to use metal materials such as tungsten as lamination materials, and tungsten is particularly suitable for this purpose. This is preferable in terms of thermal stability.

[0241] The transistor 300 shown in FIG. 16 is an example, and the structure is not limited to this. Appropriate transistors may be used depending on the structure and driving method.

[0242] Over the transistor 300 are insulators 320, 322, 324, and The edge members 326 are stacked in order.

[0243] The insulators 320, 322, 324, and 326 may be, for example, an acid. silicon oxide, silicon oxynitride, silicon nitride oxide, silicon nitride, aluminum oxide, Aluminum oxynitride, aluminum nitride oxide, aluminum nitride, or the like may be used.

[0244] The insulator 322 serves to eliminate a step caused by the transistor 300 and other components disposed below it. For example, the top surface of the insulator 322 may have a function as a planarizing film. To improve flatness, the surface is flattened by a planarization process using chemical mechanical polishing (CMP) or other methods. It may be possible.

[0245] The insulator 324 is also provided with a substrate 311 or a transistor 300 or the like. A film having a barrier property to prevent diffusion of hydrogen and impurities is formed in the area where the sta 200 is provided. It is preferable to use

[0246] An example of a film having a barrier property against hydrogen is silicon nitride formed by CVD. Here, a semiconductor having an oxide semiconductor such as the transistor 200 can be used. The diffusion of hydrogen into the semiconductor element may cause a deterioration in the characteristics of the semiconductor element. A film that suppresses hydrogen diffusion is used between the transistor 200 and the transistor 300. Specifically, the film that suppresses hydrogen diffusion is a film that desorbs a small amount of hydrogen. do.

[0247] The amount of hydrogen desorption can be analyzed using, for example, thermal desorption spectroscopy (TDS). For example, the amount of hydrogen desorption from the insulator 324 can be measured by TDS analysis. In the range of 0°C, the amount of desorption converted into hydrogen atoms is converted into the area of ​​the insulator 324. 10 x 10 15 atoms / cm 2 Less than or equal to 5 x 10 15 atoms / cm 2 The following is fine.

[0248] It is preferable that the insulator 326 has a lower relative dielectric constant than the insulator 324. For example, The dielectric constant of the insulator 326 is preferably less than 4, more preferably less than 3. The dielectric constant of the body 326 is preferably 0.7 times or less, more preferably 0.6 times or less, the relative dielectric constant of the insulator 324. By using a material with a low relative dielectric constant as the interlayer film, the parasitic capacitance generated between wirings can be reduced. can be reduced.

[0249] In addition, the insulators 320, 322, 324, and 326 are provided with capacitive elements. 100, or a conductor 328 electrically connected to the transistor 200, and a conductor 33 0 and so on are embedded. The conductors 328 and 330 are electrodes or wiring. In addition, the conductor that functions as an electrode or wiring can be used to combine multiple structures. In this specification and the like, the wiring and the wiring are electrically connected. The conductor may be integral with the electrode to be connected, i.e., a part of the conductor functions as wiring. In some cases, a part of the conductor functions as an electrode.

[0250] The materials for the electrodes and wiring (the conductors 328 and 330, etc.) are metal materials. Conductive materials such as metals, alloys, metal nitrides, or metal oxides are deposited as single layers or They can be used in layers. Materials such as tungsten and molybdenum, which have both heat resistance and conductivity, are It is preferable to use a high melting point material such as tungsten. It is preferable to form the conductive layer from a low-resistance conductive material such as aluminum or copper. By using this, the wiring resistance can be reduced.

[0251] A wiring layer may be provided on the insulator 326 and the conductor 330. For example, in FIG. In this case, an insulator 350, an insulator 352, and an insulator 354 are stacked in this order. In addition, a conductor 356 is formed on the insulators 350, 352, and 354. The conductor 356 functions as an electrode or a wiring. 328 and the conductor 330 can be formed using the same material.

[0252] For example, the insulator 350 has a barrier property against hydrogen, similar to the insulator 324. It is preferable to use an insulator having a barrier property against hydrogen. It is preferable that the insulating material 350 has a barrier property against hydrogen. A conductor having a barrier property against hydrogen is formed in the opening. The transistor 300 and the transistor 200 can be separated by a barrier layer. This makes it possible to suppress the diffusion of hydrogen from the transistor 300 to the transistor 200.

[0253] As a conductor having a barrier property against hydrogen, for example, tantalum nitride or the like is used. In addition, by laminating tantalum nitride and highly conductive tungsten, The diffusion of hydrogen from the transistor 300 can be suppressed while maintaining the overall conductivity. In this case, the tantalum nitride layer having a barrier property against hydrogen is It is preferable that the insulating body 350 has a structure in which the insulating body 350 is in contact with the insulating body 350.

[0254] A wiring layer may be provided on the insulator 350 and the conductor 356. For example, in FIG. In this case, an insulator 360, an insulator 362, and an insulator 364 are stacked in this order. In addition, a conductor 366 is formed on the insulators 360, 362, and 364. The conductor 366 functions as an electrode or a wiring. 328 and the conductor 330 can be formed using the same material.

[0255] For example, the insulator 360 has a barrier property against hydrogen, similar to the insulator 324. It is preferable to use an insulator having a barrier property against hydrogen. It is preferable that the insulating material 360 has a barrier property against hydrogen. A conductor having a barrier property against hydrogen is formed in the opening. The transistor 300 and the transistor 200 can be separated by a barrier layer. This makes it possible to suppress the diffusion of hydrogen from the transistor 300 to the transistor 200.

[0256] A wiring layer may be provided on the insulator 364 and the conductor 366. For example, in FIG. In this case, an insulator 370, an insulator 372, and an insulator 374 are stacked in this order. In addition, a conductor 376 is formed on the insulators 370, 372, and 374. The conductor 376 functions as an electrode or a wiring. 328 and the conductor 330 can be formed using the same material.

[0257] For example, the insulator 370 has a barrier property against hydrogen, similar to the insulator 324. It is preferable to use an insulator having a barrier property against hydrogen. In particular, an insulator 370 having a barrier property against hydrogen is useful. A conductor having a barrier property against hydrogen is formed in the opening. The transistor 300 and the transistor 200 can be separated by a barrier layer. This makes it possible to suppress the diffusion of hydrogen from the transistor 300 to the transistor 200.

[0258] A wiring layer may be provided on the insulator 374 and the conductor 376. For example, in FIG. In this case, an insulator 380, an insulator 382, ​​and an insulator 384 are stacked in this order. In addition, a conductor 386 is formed on the insulators 380, 382, ​​and 384. The conductor 386 functions as an electrode or a wiring. 328 and the conductor 330 can be formed using the same material.

[0259] For example, the insulator 380 has a barrier property against hydrogen, similar to the insulator 324. It is preferable to use an insulator having a barrier property against hydrogen. It is preferable that the insulator 380 has a barrier property against hydrogen. A conductor having a barrier property against hydrogen is formed in the opening. The transistor 300 and the transistor 200 can be separated by a barrier layer. This makes it possible to suppress the diffusion of hydrogen from the transistor 300 to the transistor 200.

[0260] On the insulator 384, the insulators 210, 212, 214, and 301 are disposed. are stacked in this order. It is preferable that the insulator 301 is made of a material that has a barrier property against oxygen and hydrogen. It's nice.

[0261] For example, the insulator 210 and the insulator 214 may include, for example, a substrate 311 or a transformer. The region where the transistor 300 is provided is filled with hydrogen and impurities. It is preferable to use a film having a barrier property that prevents the diffusion of the insulator 324. The same materials as those mentioned above can be used.

[0262] As an example of a film with barrier properties against hydrogen, silicon nitride formed by CVD is used. Here, a semiconductor element including an oxide semiconductor, such as the transistor 200, However, the diffusion of hydrogen may deteriorate the characteristics of the semiconductor element. It is preferable to use a film that suppresses hydrogen diffusion between the gate electrode 200 and the transistor 300. A film that suppresses hydrogen diffusion is preferably a film that desorbs a small amount of hydrogen.

[0263] In addition, as a film having a barrier property against hydrogen, for example, an insulator 210 and an insulator 214 uses metal oxides such as aluminum oxide, hafnium oxide, and tantalum oxide. It is preferable that

[0264] In particular, aluminum oxide is highly resistant to oxygen, hydrogen, and water, which are factors that cause fluctuations in transistor characteristics. Therefore, the membrane has a high blocking effect against impurities such as oxidized acid and Aluminum is a material that is resistant to impurities such as hydrogen and moisture during and after the transistor manufacturing process. It is possible to prevent the intrusion of foreign substances into the transistor 200. Therefore, the release of oxygen from the oxide constituting the transistor 20 can be suppressed. It is suitable for use as a protective film against 0.

[0265] For example, the insulator 212 and the insulator 301 may be made of the same material as the insulator 320. In addition, by using a material with a relatively low dielectric constant as the interlayer film, For example, the insulator 212 and the insulator 301 can be formed by As the insulating film, a silicon oxide film, a silicon oxynitride film, or the like can be used.

[0266] In addition, the insulators 210, 212, 214, and 301 are made of conductive materials. 218, and the conductor (conductor 310) that constitutes the transistor 200 are embedded. Note that the conductor 218 is electrically connected to the capacitor 100 or the transistor 300. The conductor 218 functions as an electrode or wiring. The conductive body 330 can be formed using the same material as the conductive body 330 .

[0267] In particular, the insulator 210 and the conductor 310 in the area in contact with the insulator 214 are resistant to oxygen, hydrogen, It is preferable that the conductive material has a barrier property against water. The transistor 300 and the transistor 200 have a barrier property against oxygen, hydrogen, and water. The layer having the hydrogen atoms can be separated from the transistor 300 to the transistor 200. The diffusion of the substance can be suppressed.

[0268] The transistor 200 is provided above the insulator 214. The structure of 200 can be realized by using the transistors included in the semiconductor device described in the previous embodiment. The transistor 200 shown in FIG. 16 is merely an example, and the present invention is not limited to this structure. Appropriate transistors may be used depending on the circuit configuration and driving method.

[0269] An insulator 415 is provided above the transistor 200. The insulator 415 contains excess oxygen. In particular, it is preferable that the transistor 200 is formed using an oxide semiconductor. In this case, an insulator having an excess oxygen region is provided in an interlayer film or the like near the transistor 200. As a result, the oxide 406a, the oxide 406b, and the oxide 406c of the transistor 200 are Since the oxygen vacancies in 6c can be reduced, the reliability of the transistor 200 can be improved. This can be done.

[0270] As an insulator having an excess oxygen region, specifically, an oxide in which a part of oxygen is released by heating is used. It is preferable to use oxide materials. Oxides that release oxygen when heated are those that are The amount of oxygen released is 1.0 x 10 14 molecules / cm 2 or more, preferably 1.0 × 10 15 molecules / cm 2 The oxide film is as follows: The surface temperature of the film during the TDS analysis was 100°C or higher and 700°C or lower. Alternatively, the temperature is preferably in the range of 100°C or higher and 500°C or lower.

[0271] For example, such a material may include silicon oxide or silicon oxynitride. Alternatively, a metal oxide can also be used. Silicon oxynitride refers to a material whose composition contains more oxygen than nitrogen. Silicon nitride oxide refers to a material whose composition contains more nitrogen than oxygen.

[0272] An oxide 420 is provided on the insulator 415. The oxide 420 is formed by oxygen and hydrogen. For example, the oxide 420 is preferably made of an oxide material having barrier properties against the metal. It is preferable to use metal oxides such as aluminum oxide, hafnium oxide, and tantalum oxide.

[0273] In particular, aluminum oxide is highly resistant to oxygen, hydrogen, and water, which are factors that cause fluctuations in transistor characteristics. Therefore, the membrane has a high blocking effect against impurities such as oxidized acid and Aluminum is a material that is resistant to impurities such as hydrogen and moisture during and after the transistor manufacturing process. It is possible to prevent the intrusion of foreign substances into the transistor 200. Therefore, the release of oxygen from the oxide constituting the transistor 20 can be suppressed. It is suitable for use as a protective film against 0.

[0274] The oxide 420 is a metal oxide film formed by sputtering. It is preferable to use aluminum oxide, for example. By using the above, the oxide 420 is bonded to the insulator 415 through the interface between the oxide 420 and the insulator 415. Oxygen can be supplied to make the insulator 415 an insulator with excess oxygen.

[0275] Furthermore, an oxide 422 is provided on the oxide 420. The oxide 422 is a metal oxide. For example, aluminum oxide can be deposited using the ALD method. Therefore, it is possible to form a film with few pinholes and a uniform thickness, and it is possible to prevent impurities such as hydrogen from entering from the outside. It can prevent things from getting in.

[0276] An insulator 410 is provided on the oxide 422. By using the material as an interlayer film, the parasitic capacitance that occurs between wirings can be reduced. The edge 410 may be made of a silicon oxide film, a silicon oxynitride film, or the like.

[0277] The insulator 415, the oxide 420, the oxide 422 and the insulator 410 are connected to the electrode 45. 0 and electrode 451 are embedded. Insulator 302, insulator 303, insulator 4 02, insulator 415, oxide 420, oxide 422 and insulator 410 are connected to electrode 452 is embedded.

[0278] The electrode 450, the electrode 451, and the electrode 452 are connected to the capacitor 100, the transistor 200, Alternatively, the electrode 4 functions as an electrode or a wiring electrically connected to the transistor 300. 50, the electrodes 451 and 452 are made of the same material as the conductors 328 and 330. Here, the electrodes 450, 451, and 452 can be provided using The surface areas of these in contact with the insulator 415 are approximately equal.

[0279] Next, the capacitor 100 is provided above the transistor 200. 100 includes a conductor 110, a conductor 120, and an insulator .

[0280] In addition, the conductor 112 may be provided over the electrode 450. The conductor 112 is a transistor 200 or the transistor 300. The conductor 110 functions as one electrode of the capacitor 100. and the conductor 110 can be formed simultaneously.

[0281] The conductor 112 and the conductor 110 may be made of molybdenum, titanium, tantalum, tungsten, or the like. Metal film containing elements selected from the group consisting of silicon, aluminum, copper, chromium, neodymium, and scandium or a metal nitride film containing the above-mentioned elements (tantalum nitride film, titanium nitride film, nitride Molybdenum film, tungsten nitride film, etc. can be used. Indium oxide containing tungsten oxide, indium zinc oxide containing tungsten oxide oxide, indium oxide with titanium oxide, indium tin oxide with titanium oxide, Conductive materials such as indium zinc oxide and indium tin oxide with added silicon oxide are used You can also do this.

[0282] In FIG. 16, the conductor 112 and the conductor 110 are shown as having a single-layer structure. For example, a conductive material having a barrier property and a conductive material having a high conductivity may be used. Conductors with barrier properties between weak conductors and highly conductive conductors with good adhesion may form a highly conductive material.

[0283] In addition, an insulating layer is formed on the conductor 112 and the conductor 110 as a dielectric of the capacitance element 100. The insulator 130 is made of, for example, silicon oxide, silicon oxynitride, or silicon nitride. Silicon nitride, silicon nitride, aluminum oxide, aluminum oxynitride, aluminum nitride oxide Aluminum, aluminum nitride, hafnium oxide, hafnium oxynitride, hafnium oxynitride , hafnium nitride, or the like may be used, and the insulating layer may be provided as a laminated layer or a single layer.

[0284] For example, if a material with high dielectric strength such as silicon oxynitride is used for the insulator 130, With this configuration, the capacitance element 100 has an improved dielectric strength due to the insulator 130. Furthermore, electrostatic breakdown of the capacitance element 100 can be suppressed.

[0285] The conductor 120 is provided over the insulator 130 so as to overlap with the conductor 110. The conductor 20 functions as the other electrode of the capacitor 100. Conductive materials such as metals, alloy materials, or metal oxide materials can be used. It is preferable to use a high melting point material such as tungsten or molybdenum, which has both high melting point and high electrical conductivity. It is particularly preferable to use tungsten. In this case, low-resistance metal materials such as Cu (copper) and Al (aluminum) can be used. .

[0286] An insulator 150 is provided on the conductor 120 and the insulator 130. The insulator 50 can be made of the same material as the insulator 320. , and may function as a planarizing film that covers the underlying unevenness.

[0287] In addition, a conductor 156 is embedded in the insulator 150 and the insulator 130. The body 156 functions as an electrode, electrically connecting to the electrode 450 via the conductor 112. The conductor 156 is also electrically connected to the conductor 120.

[0288] A conductor 166 is provided on the conductor 156. The conductor 166 serves as a wiring. The insulator 160 is provided on the conductor 166. The insulating layer 320 may be made of the same material as the insulating layer 320. Alternatively, an organic resin film may be used. It's fine.

[0289] The above is a description of an example of the structure of the semiconductor device. In a semiconductor device using a transistor having a semiconductor, fluctuations in electrical characteristics are suppressed. In addition, reliability can be improved. Alternatively, a transistor including an oxide semiconductor having a low off-state current can be provided. Alternatively, a semiconductor device with reduced power consumption can be provided. It can be provided.

[0290] <Modification of Semiconductor Device> FIG. 17 shows an example of a modification of this embodiment. FIG. 17 shows a modification of FIG. 16. The configuration of Star 300 is different.

[0291] The transistor 300 shown in FIG. 17 includes a semiconductor region 313 (substrate 31) where a channel is formed. The side and top surfaces of the semiconductor region 313 are covered with the insulator 31. The conductor 316 is provided to cover the insulating film 311 via the insulating film 311. The conductor 316 has a work function Such a transistor 300 can be fabricated by utilizing the protruding portion of the semiconductor substrate. It is also called a FIN type transistor because it uses a The insulating layer may have an insulating material that functions as a mask for forming the semiconductor portion. Although the case where a convex portion is formed by processing a part of a conductor substrate has been shown, it is also possible to process an SOI substrate to form a convex shape. Alternatively, a semiconductor film having the following structure may be formed.

[0292] The above is the description of the modified example. By using this structure, In semiconductor devices using transistors, the fluctuation of electrical characteristics is suppressed and reliability is improved. Alternatively, a transistor including an oxide semiconductor with a large on-state current can be provided. Alternatively, a transistor including an oxide semiconductor and having a low off-state current can be provided. Alternatively, a semiconductor device with reduced power consumption can be provided. do.

[0293] <Configuration example of memory cell array> An example of the memory cell array of this embodiment is shown in FIG. 18. A memory cell array can be configured by arranging semiconductor devices in a matrix. FIG. 18 shows a part of a row when the memory devices shown in FIG. 17 are arranged in a matrix. FIG.

[0294] FIG. 18 shows a circuit diagram of a semiconductor device having a transistor 300, a transistor 200, and a capacitor 100. a semiconductor device having a transistor 340, a transistor 201, and a capacitor 101; The semiconductor devices are arranged in the same row.

[0295] As shown in FIG. 18, the memory cell array is made up of a plurality of transistors (transistors in the figure). 200, and transistor 201).

[0296] When memory cells are arranged in an array, the information of a desired memory cell is read out. For example, if the memory cell array is a NOR type, the information By making the transistor 300 of the memory cell from which information is not to be read non-conductive, the desired memory cell In this case, the charge applied to node FG is Regardless of the voltage, the transistor 300 is in a "non-conducting state", i.e., V th_H twist A low potential may be applied to the wiring 3005 connected to the memory cell from which data is not read. Alternatively, for example, if the memory cell array is a NAND type, the memory from which information is not read may be By turning on the transistor 300 of the desired memory cell, the information of only the desired memory cell can be read. In this case, the charge applied to the node FG is not related to the charge of the transistor 30. 0 is the potential at which the device is in a "conducting state," that is, V th_L A higher potential is applied to read out the information. It is sufficient to provide it to the wiring 3005 connected to the memory cell that is not to be used.

[0297] <Storage device configuration example> FIG. 19 illustrates an example of a memory device using a semiconductor device according to one embodiment of the present invention.

[0298] The memory device shown in FIG. 19 includes the transistor 200, the transistor 300, and the In addition to the semiconductor device having the capacitor 100, the semiconductor device also has a transistor 345.

[0299] Transistor 345 can control the second gate voltage of transistor 200. For example, the first gate and the second gate of the transistor 345 are connected to the source and the diode. and connect the source of transistor 345 to the second gate of transistor 200. In this configuration, when the second gate of the transistor 200 is held at a negative potential, The first gate-source voltage and the second gate-source voltage of the transistor 345 are The second gate voltage and the first gate voltage of the transistor 345 are equal to 0V. The drain current at 0V is very small, so the transistor 200 and the transistor Even if power is not supplied to the transistor 345, the negative potential of the second gate of the transistor 200 can be maintained for a long time. This allows transistor 200 and transistor 345 A storage device having the above structure can retain stored contents for a long period of time.

[0300] Therefore, in FIG. 19, the wiring 3001 is electrically connected to the source of the transistor 300. The wiring 3002 is electrically connected to the drain of the transistor 300. The wiring 3003 is electrically connected to one of the source and drain of the transistor 200. The wiring 3004 is electrically connected to the gate of the transistor 200, and the wiring 3006 is electrically connected to the gate of the transistor 200. The second gate of the transistor 200 is electrically connected to the second gate of the transistor 300. The gate and the other of the source and drain of the transistor 200 are connected to the capacitor 100. The wiring 3005 is electrically connected to one of the electrodes of the capacitor 100. The wiring 3007 is electrically connected to the source of the transistor 345. 3008 is electrically connected to the gate of the transistor 345, and the wiring 3009 is The wiring 3010 is electrically connected to the drain of the transistor 345. Here, the wiring 3006, the wiring 3007, the wiring 3008, and wiring 3009 are electrically connected.

[0301] The memory device shown in FIG. 19 has a characteristic that the potential of the gate of the transistor 300 can be maintained. By having this, it is possible to write, hold, and read information as shown below.

[0302] 19 is arranged in a matrix, similar to the storage device shown in FIG. By doing so, a memory cell array can be configured. 5 can control the second gate voltages of the plurality of transistors 200. , the number of transistors 345 can be less than the number of transistors 200.

[0303] Transistor 345 is formed in the same layer as transistor 200 and is fabricated in parallel. The transistor 345 is a transistor that can be A functional conductor 460 (conductor 460a and conductor 460b) and a second gate electrode The conductor 405 (conductor 405a and conductor 405b) functions as a 0, and the insulators 302 and 303 functioning as gate insulating layers. , insulator 402, and insulator 455, and oxide 43 having a region where a channel is to be formed. 0c, a conductor 440b serving as either a source or a drain, an oxide 431a, and an oxide 431b and a conductor 440a serving as the other of the source and drain. The oxide 432a and the oxide 432b are connected to the barrier layer 445 (the barrier layer 445a and The insulating layer 445 has a barrier layer 445b).

[0304] In the transistor 345, the conductor 405 is the same layer as the conductor 310. The oxide 431a and oxide 432a are the same layer as the oxide 406a. The conductor 440a and the oxide 432b are the same layer as the oxide 406b. The conductor 440b is the same layer as the conductors 416a1 and 416a2. The oxide layer 430c is the same as the oxide layer 406c. The insulator 455 is the same as the insulator 412. The conductor 460 is the same layer as the conductor 404. The barrier layer 470 is an oxide. It is in the same layer as 418.

[0305] The oxide 430c, which serves as the active layer of the transistor 345, is formed by the oxide 406a, the oxide 406b, and the oxide 406c. As with the oxide 406b and the oxide 406c, oxygen vacancies are reduced and impurities such as hydrogen or water are removed. This reduces the threshold voltage of transistor 345 to above 0V. When the second gate voltage and the first gate voltage are 0V, the drain The on-current can be made very small.

[0306] Furthermore, by dividing a large-area substrate into individual semiconductor elements, multiple semiconductor devices can be manufactured into chips. Dicing lines (scribe lines, dividing lines, or (This is sometimes called a cutting line.) As a dividing method, for example, first, After forming grooves (dicing lines) on the substrate to separate the semiconductor elements, In some cases, the semiconductor device is cut at the in-line and divided (divided) into multiple semiconductor devices. For example, as shown in FIG. The structure 500 shown in FIG. 1 shows a cross section near the dicing line.

[0307] For example, as shown in structure 500, transistor 200 or transistor 345 In the vicinity of the region overlapping with the dicing line provided on the outer edge of the memory cell, an insulating The insulator 415, the insulator 402, the insulator 303, the insulator 302, and the insulator 216 are provided with openings. In addition, the insulator 415, the insulator 402, the insulator 303, the insulator 302, and the insulator 21 An oxide 420 is provided to cover the side surfaces of the electrode 6.

[0308] That is, the insulator 210 and the oxide 420 come into contact with each other at the opening. The insulator 210 and the oxide 420 are formed using the same material and method, thereby improving adhesion. For example, aluminum oxide can be used.

[0309] This structure allows the insulator 210 and oxide 420 to separate the insulator 415 and the transistor 2. 00, and transistor 345. Insulator 210 and oxide 4 20 has the function of suppressing the diffusion of oxygen, hydrogen, and water. By dividing the substrate into individual circuit areas where semiconductor elements are formed, multiple chips can be created. Even after processing, impurities such as hydrogen or water can enter from the side of the divided substrate, causing damage to the transistors. This prevents diffusion to the transistor 200 or the transistor 345.

[0310] In addition, this structure prevents excess oxygen in the insulator 415 from diffusing to the outside of the oxide 420. Therefore, the excess oxygen in the insulator 415 can be effectively prevented from being transferred to the transformer. The oxide on which the channel in transistor 200 or transistor 345 is formed is supplied. The oxygen causes the channel in transistor 200 or transistor 345 to This reduces the oxygen vacancies in the oxide where the pores are formed. 00, or the oxide in which the channel of the transistor 345 is formed is The transistor 20 can be an oxide semiconductor having low and stable characteristics. 0, or suppressing fluctuations in the electrical characteristics of the transistor 345 and improving reliability. Alternatively, a transistor including an oxide semiconductor with high on-state current can be provided. Alternatively, a transistor including an oxide semiconductor and having a low off-state current can be provided. Alternatively, a semiconductor device with reduced power consumption can be provided.

[0311] This embodiment may be implemented by appropriately combining with the configurations described in other embodiments or examples. It is possible to do this.

[0312] (Fourth embodiment) In this embodiment, one mode of a semiconductor device will be described with reference to FIGS.

[0313] <Semiconductor wafers and chips> FIG. 20(A) shows a top view of the substrate 711 before the dicing process is performed. The substrate 711 may be, for example, a semiconductor substrate (also called a "semiconductor wafer"). A plurality of circuit regions 712 are provided on the substrate 711. A semiconductor device or the like according to one embodiment of the present invention can be provided in the semiconductor device.

[0314] Each of the multiple circuit regions 712 is surrounded by an isolation region 713. A separation line (also called a "dicing line") 714 is set at a position where the separation line overlaps with the separation line. By cutting the substrate 711 along 714, a chip 715 including a circuit region 712 is formed on the substrate. It can be cut out from 711. An enlarged view of the chip 715 is shown in FIG.

[0315] In addition, a conductive layer, a semiconductor layer, or the like may be provided in the separation region 713. By providing a semiconductor layer, etc., ESD that may occur during the dicing process can be mitigated, and the dicing This prevents the decrease in yield caused by the dicing process. For the purposes of cooling the substrate, removing shavings, and preventing static electricity, carbon dioxide gas is dissolved in the The cutting is performed while supplying pure water with reduced resistivity to the cutting portion. By providing the above, the amount of pure water used can be reduced. This can reduce production costs and increase productivity of semiconductor devices.

[0316] <Electronic components> An example of an electronic component using the chip 715 will be described with reference to FIGS. 21(A) and 21(B). The electronic components are also called semiconductor packages or IC packages. Electronic components have multiple standards and names depending on the terminal direction, terminal shape, etc. There is.

[0317] The electronic component is assembled with the semiconductor device shown in the above embodiment in the assembly process (post-process). The semiconductor device is completed by combining it with other components.

[0318] The post-process will be explained using the flowchart shown in FIG. After forming a semiconductor device according to one aspect of the present invention on the substrate 711, the back surface ( The back surface (the surface on which semiconductor devices are not formed) is ground (step By thinning the substrate 711 by grinding, it is possible to miniaturize the electronic components. Cut.

[0319] Next, a "dicing step" is performed to separate the substrate 711 into a plurality of chips 715 (step Then, the separated chips 715 are bonded onto individual lead frames (called "Da-Pack"). The die bonding process is then performed (step S723). The bonding between the P715 and the lead frame can be done by resin bonding or tape bonding. Select the appropriate method depending on the product. Note that an interposer is used instead of a lead frame. A chip 715 may be bonded onto the substrate.

[0320] Next, the leads of the lead frame and the electrodes on the chip 715 are connected with thin metal wires (wires). ) and perform the "wire bonding process" to electrically connect them (step S724). For the thin wire, silver wire, gold wire, etc. can be used. For example, ball bonding or wedge bonding can be used.

[0321] The wire-bonded chip 715 is sealed with epoxy resin or other materials in a process called "sealing." The electronic component is then sealed (molding process) (step S725). The inside of the chip 715 is filled with resin, and the wire connecting the chip 715 and the lead is protected from external mechanical force. This can protect the device and reduce deterioration of characteristics (reduced reliability) caused by moisture, dust, etc. This can be done.

[0322] Next, a "lead plating process" is carried out to plate the leads of the lead frame (step (Step S726). The plating process prevents the leads from rusting and allows them to be mounted on a printed circuit board later. This allows for more reliable soldering during the process. The leads are then cut and shaped. Then, a "molding step" is carried out (step S727).

[0323] Next, a "marking process" is carried out to print (mark) the surface of the package. Then, an "inspection process" is carried out to check whether the external appearance is good or not, whether there is any malfunction, etc. (Step S728). After passing through the "process" (step S729), the electronic component is completed.

[0324] A perspective view of the completed electronic component is shown in FIG. 21(B). As an example of a component, a perspective schematic diagram of a QFP (Quad Flat Package) is shown below. The electronic component 750 shown in FIG. 21(B) has leads 755 and a chip 715. The electronic component 750 may include multiple chips 715.

[0325] The electronic component 750 shown in FIG. 21(B) is mounted on, for example, a printed circuit board 752. A plurality of such electronic components 750 are combined together, and each is electrically connected to a printed circuit board 752. By connecting the components to the board, a board (mounting board 754) on which electronic components are mounted is completed. The mounting board 754 is used in electronic devices and the like.

[0326] This embodiment may be implemented by appropriately combining with the configurations described in other embodiments or examples. It is possible to do this.

[0327] (Embodiment 5) A semiconductor device according to one embodiment of the present invention can be used in various electronic devices.

[0328] <Electronic equipment> 22A to 22C illustrate specific examples of electronic devices using a semiconductor device according to one embodiment of the present invention.

[0329] 22(A) is an external view showing an example of an automobile. The automobile 2980 has a body 2981 2982, a dashboard 2983, and lights 2984. The vehicle 2980 is equipped with an antenna, a battery, etc.

[0330] The information terminal 2910 shown in FIG. 22B includes a housing 2911, a display unit 2912, a microphone 2913, and a microphone 2914. 917, a speaker unit 2914, a camera 2913, an external connection unit 2916, and an operation switch The display unit 2912 includes a display panel using a flexible substrate and The information terminal 2910 is equipped with a touch screen. The information terminal 2910 also has an antenna inside the housing 2911. The information terminal 2910 is, for example, a smartphone, a mobile phone, a tablet, or the like. Used as a bullet-type information terminal, tablet-type personal computer, e-book reader, etc. It is possible.

[0331] The notebook personal computer 2920 shown in FIG. 22(C) includes a housing 2921, a display 2922, a keyboard 2923, and a pointing device 2924. The notebook personal computer 2920 also has an antenna, a battery, and a It is equipped with batteries, etc.

[0332] The video camera 2940 shown in FIG. 22(D) includes a housing 2941, a housing 2942, a display unit 2 943, an operation switch 2944, a lens 2945, and a connection part 2946. The operation switch 2944 and the lens 2945 are provided in the housing 2941. 43 is provided in a housing 2942. A video camera 2940 is provided in a housing 2941. The housing 2941 and the housing 2942 are connected to each other. The angle between the housing 2941 and the housing 2942 is The structure can be changed by the housing 2946. Depending on the angle of the screen, the orientation of the image displayed on the display unit 2943 can be changed, and the image can be displayed or hidden. You can switch between the following.

[0333] An example of a bangle-type information terminal is shown in FIG. 22(E). The information terminal 2950 has a housing 295 1 and a display unit 2952. The information terminal 2950 is provided with a housing 2951. The display unit 2952 is supported by a curved housing 2951. The display unit 2952 is provided with a display panel using a flexible substrate, It is possible to provide a flexible, lightweight, and easy-to-use information terminal 2950.

[0334] An example of a wristwatch-type information terminal is shown in FIG. 22(F). The information terminal 2960 has a housing 2961 , display unit 2962, band 2963, buckle 2964, operation switch 2965, input / output The information terminal 2960 is provided with a terminal 2966 and the like. The information terminal 2960 also has an antenna inside the housing 2961. The information terminal 2960 is equipped with a mobile phone, e-mail, text browsing and creation functions. Various applications such as music playback, internet communication, and computer games can be executed.

[0335] The display surface of the display unit 2962 is curved, and display can be performed along the curved display surface. The display unit 2962 is also equipped with a touch sensor, allowing you to touch the screen with your finger or a stylus. For example, the icon 2967 displayed on the display unit 2962 can be By touching it, you can start an application. In addition to setting the time, you can also turn the power on and off, turn wireless communication on and off, and activate silent mode. It can have various functions such as turning on and off the power saving mode, turning on and off the power saving mode, etc. For example, the operating system installed in the information terminal 2960 controls the operation switch 2 You can also set the functions of the 965.

[0336] In addition, the information terminal 2960 is capable of performing standardized short-range wireless communication. For example, by communicating with a wireless headset, hands-free communication is possible. The information terminal 2960 also has an input / output terminal 2966, and can be used to communicate with other information terminals. Data can be exchanged directly through the terminal and connector. Charging can also be performed via the input / output terminal 2966. This may be done by wireless power supply.

[0337] For example, a memory device using the semiconductor device of one embodiment of the present invention can be used for the control information of the above-described electronic devices. The semiconductor device according to one aspect of the present invention can store information, control programs, and the like for a long period of time. By using the device, highly reliable electronic equipment can be realized.

[0338] This embodiment may be implemented by appropriately combining with the configurations described in other embodiments or examples. It is possible to do this. [Example]

[0339] In this example, the semiconductor device shown in FIG. 1 was fabricated. Four samples were prepared. The transistor characteristics of each sample were measured, and then additional heat treatment was performed. The influence of the heat treatment time on the transistor characteristics was evaluated.

[0340] The semiconductor device is manufactured by forming a silicon oxide film on a silicon single crystal wafer by thermal oxidation. Next, a first aluminum oxide film was formed by sputtering. A silicon film was formed to a thickness of 40 nm.

[0341] Next, a first silicon oxynitride film is formed on the first aluminum oxide film by a CVD method. A film of 150 nm thick was formed on the first silicon oxynitride film by sputtering. Then, a first tungsten film was formed to a thickness of 35 nm. The first tungsten film is processed to form a hard mask having the first tungsten film. Ta.

[0342] Next, the first silicon oxynitride film is processed using the hard mask. A groove was formed in the aluminum film, and then a first nitride film was deposited in the groove by sputtering. a tantalum nitride film is formed on the first tantalum nitride film by the ALD method and the CVD method; A first titanium nitride film and a second tungsten film were formed. Then, a first CMP process was performed. The second tungsten film, the first nitride film, and the second tungsten film are then deposited until they reach the top surface of the first silicon oxynitride film. The titanium nitride film, the first tantalum nitride film, and the first tungsten film are polished, and a second tantalum nitride film is formed in the groove. a first titanium nitride film and a first tantalum nitride film are buried in the insulating layer, and a wiring layer and a A first gate electrode and a second gate electrode were formed.

[0343] Next, a second silicon oxynitride film was formed to a thickness of 10 nm by CVD. Next, a hafnium oxide film was formed to a thickness of 20 nm by the ALD method. The third silicon oxynitride film was formed to a thickness of 30 nm by the above method. The silicon oxide film, the hafnium oxide film, and the third silicon oxynitride film are used as a second gate insulating film. Next, the first heat treatment was carried out in an atmosphere containing nitrogen. The sample was then treated at 400°C for 1 hour in an oxygen-containing atmosphere at 400°C for 1 hour. Processing was carried out between

[0344] Next, the first oxide (S1) is formed by sputtering In-Ga-Zn oxide. The film was deposited to a thickness of 5 nm. S1 is a target with an atomic ratio of In:Ga:Zn=1:3:4. The conditions were oxygen gas flow rate 45sccm, pressure 0.7Pa, and substrate temperature 200℃. The film was formed.

[0345] Next, a second oxide (S2) is deposited on S1 by sputtering. The n-oxide was deposited to a thickness of 15 nm. S2 was prepared by In:Ga:Zn=4:2:4.1 [primary Using a target with a molecular ratio of 1.0, argon gas flow rate was 40 sccm, oxygen gas flow rate was 5 sccm The film was formed under the conditions of 0.7 m, pressure of 0.7 Pa, and substrate temperature of 130°C.

[0346] Next, a second heat treatment was carried out. The second heat treatment was carried out in a nitrogen-containing atmosphere at a temperature of 400°C for 1 The sample was then treated for 1 hour at 400°C in an oxygen-containing atmosphere.

[0347] Next, a second tantalum nitride film was formed on S2 by sputtering to a thickness of 20 nm. Next, a second aluminum oxide film was deposited on the second tantalum nitride film by ALD. Next, a 5 nm thick aluminum oxide film was formed on the second aluminum oxide film by sputtering. A third tantalum nitride film was formed to a thickness of 15 nm by the method.

[0348] Next, a third tantalum nitride film is formed by lithography in the area where the channel will be formed. The resist film was then etched. The etching was carried out by dry etching. The mask was removed by oxygen plasma.

[0349] Next, a resist mask is formed by lithography, and a third tantalum nitride film and a second The second aluminum oxide film and the second tantalum nitride film are etched, and the resist mask is The second aluminum oxide film is removed by oxygen plasma. Next, the unnecessary portions of S2 and S1 were etched in order. The etching was performed using a dry etching method.

[0350] Next, the second tantalum nitride film was etched in the area where the channel was to be formed. The third tantalum film on the second aluminum oxide film was also etched at the same time by etching. The etching was carried out by dry etching.

[0351] Next, the third oxide (S3) is deposited by sputtering using In-Ga-Zn oxide. The film was deposited to a thickness of 5 nm. S3 was a type with an atomic ratio of In:Ga:Zn=4:2:4.1. The conditions were oxygen gas flow rate 45sccm, pressure 0.7Pa, and substrate temperature 130℃. The film was formed under the conditions.

[0352] Next, a fourth silicon oxynitride film having a function as a first gate oxide film is formed by a CVD method. A film with a thickness of 10 nm was formed by the method.

[0353] Next, a second titanium nitride film was formed to a thickness of 10 nm by sputtering. A third tungsten film was deposited on the second titanium nitride film by sputtering to a thickness of 30 nm. The second titanium nitride film and the third tungsten film were deposited successively.

[0354] Next, a third tungsten film and a second titanium nitride film are formed by lithography. The gate electrode was formed by etching the silicon dioxide film in this order. The etching was performed by dry etching. .

[0355] Next, a third aluminum oxide film was formed to a thickness of 7 nm by ALD. The temperature was set to 250°C.

[0356] Next, a resist mask is formed by lithography, and a third aluminum oxide film is formed. The third aluminum oxide film and the fourth silicon oxynitride film were partially etched. The etching of the first silicon oxynitride film is performed by wet etching, and the etching of the fourth silicon oxynitride film is performed by Dry etching was used. Next, after removing the resist mask, S3 was etched. S3 was etched using diluted phosphoric acid solution.

[0357] Next, a fifth silicon oxynitride film was formed by CVD. The thickness of the sample B was 30 nm, that of the sample C was 60 nm, and that of the sample D was 100 nm. The silicon film corresponds to the insulator 415 in FIG.

[0358] Next, a fourth aluminum oxide film was deposited by sputtering at an argon gas flow rate of 25 s. ccm, oxygen gas flow rate 25sccm, pressure 0.4Pa, substrate temperature 250℃ The film was deposited to a thickness of 100 nm.

[0359] Next, a fifth aluminum oxide film is formed on the fourth aluminum oxide film by the ALD method. The substrate temperature was set to 250°C.

[0360] Next, a third heat treatment was performed in an oxygen-containing atmosphere at a temperature of 350° C. Treatment was carried out for 1 hour.

[0361] Next, a sixth silicon oxynitride film was formed to a thickness of 350 nm by a CVD method. Next, a second CMP process is performed to polish the sixth silicon oxynitride film. The surface of the silicon film was flattened.

[0362] Next, a fourth tungsten film was formed to a thickness of 90 nm by sputtering. Next, a silicon nitride film was formed to a thickness of 130 nm using the CVD method.

[0363] Next, the silicon nitride film and the fourth tungsten film are processed by lithography. A hard mask having a silicon nitride film and a fourth tungsten film was then formed. The hard mask is used as an etching mask to form a second tungsten film (second gate electrode ), and a contact hole reaching the third tungsten film (first gate electrode). The contact holes and the contacts reaching the second tantalum nitride film (source and drain electrodes) Contact holes were formed, and a third titanium nitride film was deposited by ALD at a substrate temperature of 375°C. A fifth tungsten film was formed by CVD at a substrate temperature of 350 The film was formed at 150°C to a thickness of 150 nm.

[0364] Next, a third CMP process is performed to form a fifth tungsten film, a third titanium nitride film, and a silicon nitride film. The silicon film and the fourth tungsten film are polished until the sixth silicon oxynitride film is reached. A fifth tungsten film and a third titanium nitride film are buried in each contact hole. A buried electrode was formed.

[0365] Next, a sixth tungsten film was formed to a thickness of 50 nm by sputtering. Next, a portion of the sixth tungsten film is etched by lithography to form a wiring. A line layer was formed.

[0366] Next, a fourth heat treatment was carried out at a temperature of 250° C. for 1 hour.

[0367] Next, a photoresist film was formed to a thickness of 1.0 μm by coating. The photoresist film on the part that will become the measurement terminal (measurement pad) is removed by the lithography method. Ta.

[0368] In this manner, the semiconductor device shown in FIG. 1 was fabricated.

[0369] Next, the transistor characteristics of each sample were measured. The design value of the channel length (L) is 60 nm, the design value of the channel width (W) is 60 nm, and the Transistor density = 2.9 pieces / μm 2 The length of one side of the bottom or top surface of the electrode was set to 100 nm. .

[0370] The transistor characteristics are measured by the source-drain voltage (hereinafter referred to as the drain voltage Vd). ) is set to 0.1V and 1.2V, and for each Vd, the source-gate voltage (hereinafter The source and gate voltages are called Vg and Vs when the The change in the drain-drain current (hereinafter referred to as drain current Id) was measured. The Vg characteristics were measured. The gate voltage Vg is the voltage of the first gate electrode (top gate electrode). In this measurement, the second gate electrode (back gate The voltage of the electrode was set to 0V.

[0371] In addition, from the measurement data of Id-Vg characteristics at Vd=0.1V, gradual channel Using the linear region equation of the approximation, the field-effect mobility μFE (cm 2 / Vs) was calculated.

[0372] 25 and 26 show the Id-Vg curves for samples A to D at Vd=0.1 and 1.2 V. The graphs of the characteristics and μFE characteristics at Vd=0.1V are summarized in FIG. The initial characteristics of D, the characteristics after 1 hour of additional heat treatment, and the characteristics after a total of 2 hours of additional heat treatment are shown in Figure 26. indicates the properties after a total of 3 hours of additional heating time and the properties after a total of 4 hours of additional heating time. The treatment was carried out in a nitrogen atmosphere at a temperature of 350°C. The vertical axis on the left side of each graph represents The vertical axis on the right represents Id, the horizontal axis represents μFE, and the vertical axis represents Vg.

[0373] As shown in FIGS. 25 and 26, the structure of one embodiment of the present invention can be obtained by performing a long-term additional heat treatment. However, it was confirmed that the transistor characteristics maintained good on / off characteristics. Specifically, the fifth silicon oxynitride film corresponding to the insulator 415 in FIG. 1(B) has a thickness of 6 The negative shift in transistor characteristics with respect to the additional heat treatment time was the largest for sample C with a thickness of 0 nm. The normally-off characteristics were maintained even after a total additional heat treatment time of 4 hours. However, in the case of sample D, the thickness of the fifth silicon oxynitride film is 100 nm, which is thicker than 60 nm. Alternatively, sample B, which is 30 nm thinner than 60 nm, and sample A, which is 10 nm, are the fifth Compared with sample C, which has a silicon oxynitride film thickness of 60 nm, the resistance to additional heat treatment is One of the reasons for this is that the oxide 420 in Fig. 1(B) and (C) The amount of oxygen added to the fifth silicon oxynitride film by the fourth aluminum oxide film is The change in the thickness of the silicon oxynitride film 5 is one example (see FIG. 5(A)).

[0374] Based on the above, the fifth silicon oxynitride film thickness was set to 100 nm, which was thicker than 60 nm. The reason why the resistance to the heat treatment is weak is that the amount of excess oxygen in the fifth silicon oxynitride film is 6000 kJ / cm. The thickness is roughly the same as that of the 500 nm case, but the surface area where the fifth silicon oxynitride film and the electrode come into contact increases. This is thought to be because the effect of oxygen absorption by the electrodes increases as the temperature increases.

[0375] On the other hand, if the thickness of the fifth silicon oxynitride film is thinner than 60 nm, the resistance to the additional heat treatment is low. The reason why the effect was weak was when the thickness of the fifth silicon oxynitride film was thinner than 60 nm. Then, the amount of oxygen added to the fifth silicon oxynitride film by forming the fourth aluminum oxide film is This is thought to be because the transistor characteristics were shifted negatively as a result.

[0376] As described above, in the structure of the semiconductor device according to one embodiment of the present invention, the fifth By reducing the surface area of ​​the electrode in contact with the silicon oxynitride film, It was confirmed that the characteristic fluctuation of the transistor can be suppressed. [Example]

[0377] In this example, a sample corresponding to the semiconductor device shown in FIG. Samples E and F were used. First, the transistor characteristics and transistor density were measured using sample E. The transistor density was 1.0 / μm. 2 , 2.0 pieces / μm 2 and 2.9 pieces / μm 2 In addition, the second gate insulating film was evaluated using Samples E and F. The difference in Vsh dependency on Vbg when the film thickness was changed was evaluated.

[0378] First, the methods for fabricating Samples E and F in this example will be described. Unless otherwise specified, the preparation methods for specimens E and F are the same. A silicon oxide film was formed on the silicon wafer by thermal oxidation to a thickness of 400 nm. A first aluminum oxide film was formed on the substrate by sputtering to a thickness of 40 nm. .

[0379] Next, a first silicon oxynitride film is formed on the first aluminum oxide film by a CVD method. A film of 200 nm thick was formed on the first silicon oxynitride film by sputtering. Then, a first tungsten film was formed to a thickness of 35 nm. The first tungsten film is processed to form a hard mask having the first tungsten film. Ta.

[0380] Next, the first silicon oxynitride film is processed to form a groove that reaches the first aluminum oxide film. Next, a first tantalum nitride film was formed in the groove by sputtering. On the tantalum nitride film, a first titanium nitride film and a second titanium nitride film are formed by ALD and CVD. Then, a first tungsten film was formed on the first silicon oxynitride film by a first CMP process. The second tungsten film, the first titanium nitride film, and the first titanium nitride film are deposited until the top surface of the titanium nitride film is reached. The tungsten film and the first tungsten film are polished, and the second tungsten film and the first titanium nitride film are deposited in the grooves. A tantalum film and a first tantalum nitride film are buried to form a wiring layer and a second gate electrode. Ta.

[0381] Next, Samples E and F were prepared by different methods. Sample E was prepared by the following method: A second silicon oxynitride film is formed to a thickness of 5 nm by CVD, and then a second silicon oxynitride film is formed by ALD. A hafnium oxide film was formed to a thickness of 10 nm by the above method, and then heat treatment was carried out. The treatment was carried out in a nitrogen-containing atmosphere at 400°C for 1 hour, followed by treatment in an oxygen-containing atmosphere. The treatment was carried out at a temperature of 400°C for 1 hour. Next, a third silicon oxynitride film was formed by the CVD method. The silicon film was deposited to a thickness of 15 nm.

[0382] The sample F was fabricated by depositing the second silicon oxynitride film on the substrate for 5 minutes by CVD. Then, a hafnium oxide film was formed to a thickness of 10 nm by the ALD method. The heat treatment was carried out at 400°C for 1 hour in a nitrogen-containing atmosphere. Then, the CV was applied to the sample in an oxygen-containing atmosphere at 400°C for 1 hour. The third silicon oxynitride film was formed to a thickness of 5 nm by the D method. The silicon film, the hafnium oxide film, and the third silicon oxynitride film form a second gate insulating film. Next, a heat treatment was carried out. The heat treatment was carried out in a nitrogen-containing atmosphere at a temperature of 4 00℃ for 1 hour, followed by treatment in an oxygen-containing atmosphere at 400℃ for 1 hour. was carried out.

[0383] The above steps are the different manufacturing methods for Sample E and Sample F. The same conditions were set for Sample E and Sample F. Next, the first oxide (S1) was deposited by sputtering. In-Ga-Zn oxide was deposited to a thickness of 5 nm by the annealing method. A target of Zn=1:3:4 [atomic ratio] was used, and the oxygen gas flow rate was 45 sccm and pressure The film was formed under the conditions of a pressure of 0.7 Pa and a substrate temperature of 200°C.

[0384] Next, a second oxide (S2) is deposited on S1 by sputtering. The n-oxide was deposited to a thickness of 15 nm. S2 was prepared by In:Ga:Zn=4:2:4.1 [primary Using a target with a molecular ratio of 1.0, argon gas flow rate was 40 sccm, oxygen gas flow rate was 5 sccm The film was formed under the conditions of 0.7 m, pressure of 0.7 Pa, and substrate temperature of 130°C.

[0385] Next, a heat treatment was carried out at 400°C for 1 hour in a nitrogen-containing atmosphere. Then, the sample was treated in an oxygen-containing atmosphere at 400°C for 1 hour.

[0386] Next, a second tantalum nitride film was formed on S2 by sputtering to a thickness of 20 nm. Next, a second aluminum oxide film was deposited on the second tantalum nitride film by ALD. Next, a 5 nm thick aluminum oxide film was formed on the second aluminum oxide film by sputtering. A third tantalum nitride film was formed to a thickness of 15 nm by the method.

[0387] Next, a resist mask is formed by lithography, and the resist mask is etched. The third tantalum nitride film was etched as a etching mask in the area where the channel was to be formed. The etching was carried out by dry etching. Next, the resist mask was removed by oxygen plating. Removed by Zuma.

[0388] Next, a resist mask is formed by lithography, and the resist mask is etched. As a mask, a third tantalum nitride film, a second aluminum oxide film, and a second nitride film are formed. The tantalum film is etched, and then the resist mask is removed by oxygen plasma. The second aluminum oxide was etched away from the channel formation area. The unnecessary parts of S1 were sequentially etched away by dry etching.

[0389] Next, the second tantalum nitride film was etched in the area where the channel was to be formed. The third tantalum film on the second aluminum oxide was also etched at the same time by etching. The etching was performed by dry etching.

[0390] Next, the third oxide (S3) is deposited by sputtering using In-Ga-Zn oxide. The film was deposited to a thickness of 5 nm. S3 was a type with an atomic ratio of In:Ga:Zn=4:2:4.1. The conditions were oxygen gas flow rate 45sccm, pressure 0.7Pa, and substrate temperature 130℃. The film was formed under the conditions.

[0391] Next, a fourth silicon oxynitride film having a function as a first gate oxide film is formed by a CVD method. A film with a thickness of 10 nm was formed by the method.

[0392] Next, a second titanium nitride film was formed to a thickness of 10 nm by sputtering. A third tungsten film was deposited on the second titanium nitride film by sputtering to a thickness of 30 nm. The film was formed to a thickness of 1000 μm.

[0393] Next, a third tungsten film and a second titanium nitride film are formed by lithography. The first gate electrode was formed by etching the first and second gate electrodes in this order. Used.

[0394] Next, a third aluminum oxide film was formed to a thickness of 7 nm by ALD. The temperature was set to 250°C.

[0395] Next, a resist mask is formed by lithography, and a third aluminum oxide film is formed. The third aluminum oxide film and the fourth silicon oxynitride film were partially etched. The etching of the first silicon oxynitride film is performed by wet etching, and the etching of the fourth silicon oxynitride film is performed by Dry etching was used. Next, after removing the resist mask, S3 was etched. S3 was etched using wet etching.

[0396] Next, a fifth silicon oxynitride film was formed to a thickness of 60 nm by CVD. The silicon oxynitride film corresponds to the insulator 415 in FIG.

[0397] Next, a fourth aluminum oxide film was deposited by sputtering at an argon gas flow rate of 25 s. ccm, oxygen gas flow rate 25sccm, pressure 0.4Pa, substrate temperature 250℃ The film was deposited to a thickness of 100 nm.

[0398] Next, a fifth aluminum oxide film is formed on the fourth aluminum oxide film by the ALD method. The substrate temperature was set to 250°C.

[0399] Next, a heat treatment was carried out at a temperature of 350°C for 1 hour in an oxygen-containing atmosphere. The theory was carried out.

[0400] Next, a sixth silicon oxynitride film was formed to a thickness of 350 nm by a CVD method. Next, a second CMP process is performed to polish the sixth silicon oxynitride film. The surface of the silicon film was flattened.

[0401] Next, a fourth tungsten film was formed to a thickness of 90 nm by sputtering. Next, a silicon nitride film was formed to a thickness of 130 nm using the CVD method.

[0402] Next, the silicon nitride film and the fourth tungsten film are processed by lithography. A hard mask having a silicon nitride film and a fourth tungsten film was then formed. The hard mask is used as an etching mask to form a second tungsten film (second gate electrode ), and a contact hole reaching the third tungsten film (first gate electrode). The contact holes and the contacts reaching the second tantalum nitride film (source and drain electrodes) A contact hole was formed.

[0403] Next, a sixth aluminum oxide film was formed to a thickness of 13 nm by ALD. Then, the sixth oxide film is planarized by anisotropic etching using a dry etching method. The sixth aluminum oxide film on the top surface of the silicon nitride film and on the bottom of the contact hole is etched. The sixth aluminum oxide film on the side of the contact hole remained. Thus, a sixth aluminum oxide film was formed so as to be in contact with the side surface of the contact hole.

[0404] Next, a third titanium nitride film was formed by ALD at a substrate temperature of 375°C to a thickness of 10 nm. The fifth tungsten film was formed by CVD at a substrate temperature of 350°C for 150n. The film was deposited to a thickness of 1 m.

[0405] Next, a third CMP process is performed to form a fifth tungsten film, a third titanium nitride film, and a silicon nitride film. The silicon film and the fourth tungsten film are polished until the sixth silicon oxynitride film is reached. A fifth tungsten film and a third titanium nitride film are buried in each contact hole. A buried electrode was formed.

[0406] Next, a sixth tungsten film was formed to a thickness of 50 nm by sputtering. Next, a portion of the sixth tungsten film is etched by lithography to form a wiring. A line layer was formed.

[0407] Next, a heat treatment was carried out at a temperature of 250° C. for 1 hour.

[0408] Next, a photoresist film was formed to a thickness of 1.0 μm by coating. The photoresist film on the part that will become the measurement terminal (measurement pad) is removed by the lithography method. Ta.

[0409] As a result of the above, samples (samples E and F) corresponding to the semiconductor devices shown in FIG. 1 were prepared. .

[0410] Next, the transistor density dependency of the transistor characteristics was evaluated using sample E. The transistor density is 1.0 pieces / μm 2 , 2.0 pieces / μm 2 and 2.9 particles / μm 2 It was decided. The measured transistor size was the design value of channel length (L) = 60 nm, channel width ( The design value was set to 60 nm. The number of measurement points for the transistor was set to 9.

[0411] To measure the transistor characteristics, Vd was set to 0.1V and 1.2V. On the other hand, the change in Id when Vg was changed from -4.0V to +4.0V was measured. In other words, the Id-Vg characteristics were measured. The voltage (Vbg) of the output electrode was set to 0V.

[0412] In addition, from the measurement data of Id-Vg characteristics at Vd=0.1V, gradual channel Using the linear region equation of the approximation, the field-effect mobility μFE (cm 2 / Vs) was calculated.

[0413] In addition, Ion was calculated from the measured data of Id-Vg characteristics. Ion was calculated at Vd=1.2V. , Id at Vg=3.3V. Furthermore, Vsh and Vd at Vd=1.2V The S value at = 1.2V was also calculated. lue) is the Vg required for Id to change by one order of magnitude in the subthreshold region. Define.

[0414] Figure 27 shows the Vd of transistors at each transistor density: Vd = 0.1 and 1. The graphs show the Id-Vg characteristics at 2V and the μFE characteristics at Vd=0.1V. According to Figure 27, the Id-Vg characteristics were roughly the same regardless of the transistor density. .

[0415] In addition, Figure 28 shows the graphs showing the transistor density dependence of Ion, μFE, Vsh, and S value. According to Figure 28, Ion, μFE, Vsh and S value are The density also shows roughly the same value, and the variation is also similar, indicating transistor density dependency. From the above results, it was confirmed that the structure of the semiconductor device according to one embodiment of the present invention In this case, the transistor characteristics are generally constant regardless of the transistor density, and there is little variation, making it safe. It was confirmed that this was the case.

[0416] Next, using Samples E and F, we investigated the Vsh when the thickness of the second gate insulating film was changed. The difference in Vbg dependence was evaluated. The second gate insulating film of sample E was made of a second silicon oxynitride. The silicon nitride film was 5 nm thick, the hafnium oxide film was 10 nm thick, and the third silicon oxynitride film was 15 nm thick. The second gate insulating film of sample F is a 5-nm thick second silicon oxynitride film. A three-layer structure consisting of a 10 nm hafnium oxide film and a 5 nm silicon oxynitride film. Here, the second silicon oxynitride film and the third silicon oxynitride film were used as a reference. , Equivalent Oxide Thickness (EOT) of Samples E and F s), the EOT of sample E is 22.5 nm, and the EOT of sample F is 12.5 nm. Here, the relative dielectric constant of the hafnium oxide film is The relative dielectric constant was set to four times that of the silicon oxynitride film.

[0417] In this embodiment, the voltage Vbg applied to the second gate electrode is set to 0 V, −3 V, −6 V, and The amount of Vsh shift when Vbg is set to -9V is ΔVsh. Using sh as a reference, plot the difference in Vsh at Vbg = -3V, -6V and -9V. The two straight lines in Figure 29 are the ΔV of Sample E and Sample F, respectively. A straight line approximation is shown for the value of sh.

[0418] According to FIG. 29, the slope of the approximation line for sample E is about −0.21, and the slope of the approximation line for sample F is about −0.21. The slope of the curve was about -0.34. In other words, the slope of the curve for sample F, which has a thin EOT of the second gate insulating film, was about -0.34. Compared to sample E, ΔVsh due to the change in Vbg is larger in sample E, and Vs is 1.6 times that of sample E. It was found that h can be changed. It was confirmed that the controllability of Vsh by Vbg was improved by forming a film. [Example]

[0419] In this example, a semiconductor device corresponding to the structure shown in FIG. is a second oxide (S2) corresponding to the oxide 406b in FIGS. 1(B) and 1(C), The sample was fabricated using CAAC-OS, an In-Ga-Zn oxide. The transistor characteristics were measured, and then additional heat treatment was performed to examine the effect of heat treatment time on the transistor characteristics. Evaluated.

[0420] The semiconductor device is manufactured by forming a silicon oxide film on a silicon single crystal wafer by thermal oxidation. Next, a first aluminum oxide film was formed by sputtering. A silicon film was formed to a thickness of 40 nm.

[0421] Next, a first silicon oxynitride film is formed on the first aluminum oxide film by a CVD method. A film of 200 nm thick was formed on the first silicon oxynitride film by sputtering. Then, a first tungsten film was formed to a thickness of 35 nm. The first tungsten film is processed to form a hard mask having the first tungsten film. Ta.

[0422] Next, the first silicon oxynitride film is processed to form a groove that reaches the first aluminum oxide film. Next, a first tantalum nitride film was formed in the groove by sputtering. On the tantalum nitride film, a first titanium nitride film and a second titanium nitride film are formed by ALD and CVD. Then, a first tungsten film was formed on the first silicon oxynitride film by a first CMP process. The second tungsten film, the first titanium nitride film, and the first titanium nitride film are deposited until the top surface of the titanium nitride film is reached. The tungsten film and the first tungsten film are polished, and the second tungsten film and the first titanium nitride film are deposited in the grooves. A tantalum film and a first tantalum nitride film are buried to form a wiring layer and a second gate electrode. did.

[0423] Next, a second silicon oxynitride film was formed to a thickness of 5 nm by CVD. Then, a hafnium oxide film was formed to a thickness of 10 nm by the ALD method. Therefore, the third silicon oxynitride film was formed to a thickness of 15 nm. The hafnium oxide film, the hafnium oxide film, and the third silicon oxynitride film are used as a second gate insulating film. It has the following functions.

[0424] Next, the first heat treatment was carried out. The first heat treatment was carried out in a nitrogen-containing atmosphere at a temperature of 400°C for 1 The sample was then treated for 1 hour at 400°C in an oxygen-containing atmosphere.

[0425] Next, the first oxide (S1) is formed by sputtering In-Ga-Zn oxide. The film was deposited to a thickness of 5 nm. S1 is a target with an atomic ratio of In:Ga:Zn=1:3:4. The conditions were oxygen gas flow rate 45sccm, pressure 0.7Pa, and substrate temperature 200℃. The film was formed.

[0426] Next, a second oxide (S2) is deposited on S1 by sputtering. The n-oxide was deposited to a thickness of 15 nm. S2 was prepared by In:Ga:Zn=4:2:4.1 [primary Using a target with a molecular ratio of 1.0, the argon gas flow rate was 30 sccm and the oxygen gas flow rate was 15 sccm. The film was formed under the conditions of a pressure of 0.7 Pa and a substrate temperature of 200°C.

[0427] Here, the In-Ga-Zn oxide film formed under the same conditions as in S2 was analyzed by X-ray diffraction (XRD: The results of the analysis using X-ray diffraction are shown in Figure 30. The Ga-Zn oxide was analyzed using the out-of-plane method. As shown in the figure, the diffraction angle (2θ) of the In-Ga-Zn oxide peaks at around 31°. This peak is attributed to the (009) plane of the InGaZnO4 crystal. The crystal of the In-Ga-Zn oxide has a c-axis orientation, and the c-axis of the In-Ga-Zn The surface on which the oxide is to be formed (also called the surface on which the oxide is to be formed) or the surface on which the oxide is to be formed should be oriented in a direction substantially perpendicular to the surface. Therefore, the In-Ga-Zn oxide and S2 according to this example , it can be seen that it is CAAC-OS.

[0428] Next, a second heat treatment was carried out. The second heat treatment was carried out in a nitrogen-containing atmosphere at a temperature of 400°C for 1 The sample was then treated for 1 hour at 400°C in an oxygen-containing atmosphere.

[0429] Next, a second tantalum nitride film was formed on S2 by sputtering to a thickness of 25 nm. The film was formed as follows.

[0430] Next, a resist mask is formed by lithography, and a second tantalum nitride film is formed. The resist was then etched into islands by dry etching. The mask was removed using oxygen plasma. Next, the second tantalum nitride film was formed into an island shape. Using this as a mask, S2 and S1 were sequentially etched into islands. An etching method was used.

[0431] Next, the second tantalum nitride films S2 and S1 are deposited by sputtering and ALD. The second aluminum oxide film was formed by sputtering. After depositing a 5 nm film by the deposition method, a 3 nm film was deposited by the ALD method.

[0432] Next, a resist mask is formed by lithography, and the area where the channel is to be formed is The second aluminum oxide film was etched by wet etching. Here, the second aluminum oxide film was formed by the second tantalum nitride film, S2, and The third silicon oxynitride film was formed so as to cover the side surface of S1 and to be in contact with the top surface of the third silicon oxynitride film. By providing a second aluminum oxide film on the insulating film 415, a fifth insulating film corresponding to the insulator 415 shown in FIG. The oxygen contained in the silicon oxynitride film is absorbed by the source electrode or the drain electrode. can be reduced.

[0433] Next, using the second aluminum oxide film as a mask, the second aluminum oxide film is formed on the portion where the channel is to be formed. The tantalum nitride film was etched by dry etching.

[0434] The resist mask was then removed by oxygen plasma.

[0435] Next, the third oxide (S3) is deposited by sputtering using In-Ga-Zn oxide. The film was deposited to a thickness of 5 nm. S3 was a type with an atomic ratio of In:Ga:Zn=4:2:4.1. The conditions were oxygen gas flow rate 45sccm, pressure 0.7Pa, and substrate temperature 130℃. The film was formed under the conditions.

[0436] Next, a fourth silicon oxynitride film was formed to a thickness of 8 nm by a CVD method. A third aluminum oxide film was formed on the fourth silicon oxynitride film to a thickness of 3 nm by ALD. The fourth silicon oxynitride film and the third aluminum oxide film were formed to a thickness of 1000 nm. In this way, the first gate insulating film functions as a gate insulating film for the third aluminum oxide. By providing the silicon oxynitride film, oxygen contained in the fourth silicon oxynitride film is absorbed by the gate electrode. This can reduce the risk of damage.

[0437] Next, a second titanium nitride film is formed to a thickness of 10 nm by the ALD method. A third tungsten film was formed on the titanium film by sputtering to a thickness of 30 nm. The second titanium nitride film and the third tungsten film were deposited successively.

[0438] Next, a third tungsten film and a second titanium nitride film are formed by lithography. The gate electrode was formed by etching the silicon dioxide film in this order. The etching was performed by dry etching. .

[0439] Next, a fourth aluminum oxide film was formed to a thickness of 7 nm by ALD. The temperature was set to 250°C.

[0440] Next, a resist mask is formed by lithography, and a fourth aluminum oxide film is formed. The third aluminum oxide film and the fourth silicon oxynitride film were etched. The aluminum oxide and third aluminum oxide films are etched using wet etching. The fourth silicon oxynitride film was etched by dry etching. After removing the resist mask, S3 was etched. A phosphoric acid solution was used.

[0441] Next, a fifth silicon oxynitride film was formed to a thickness of 60 nm by a CVD method.

[0442] Next, a fifth aluminum oxide film was deposited by sputtering at an argon gas flow rate of 25 s. ccm, oxygen gas flow rate 25sccm, pressure 0.4Pa, substrate temperature 250℃ The film was deposited to a thickness of 100 nm.

[0443] Next, a sixth aluminum oxide film is formed on the fifth aluminum oxide film by the ALD method. The substrate temperature was set to 250°C.

[0444] Next, a sixth silicon oxynitride film was formed to a thickness of 350 nm by a CVD method. Next, a second CMP process is performed to polish the sixth silicon oxynitride film. The surface of the silicon film was flattened.

[0445] Next, a fourth tungsten film was formed to a thickness of 90 nm by sputtering. Next, a silicon nitride film was formed to a thickness of 130 nm using the CVD method.

[0446] Next, the silicon nitride film and the fourth tungsten film are processed by lithography. A hard mask having a silicon nitride film and a fourth tungsten film was then formed. The hard mask is used as an etching mask to form a second tungsten film (second gate electrode ), and a contact hole reaching the third tungsten film (first gate electrode). The contact holes and the contacts reaching the second tantalum nitride film (source and drain electrodes) A contact hole was formed.

[0447] Next, a seventh aluminum oxide film was formed to a thickness of 13 nm. The substrate temperature was 250°C. Then, the seventh aluminum oxide film was anisotropically etched to form the contact hole. In this way, by providing the seventh aluminum oxide film, The oxygen contained in the fifth silicon oxynitride film corresponding to the insulator 415 shown in FIG. 1(B) is The electrons are absorbed into the electrodes, source electrodes, or drain electrodes embedded in the contact holes. can be reduced.

[0448] Next, a third titanium nitride film was formed by ALD at a substrate temperature of 375°C to a thickness of 10 nm. The fifth tungsten film was formed by CVD at a substrate temperature of 350°C for 150n. The film was deposited to a thickness of 1 m.

[0449] Next, a third CMP process is performed to form a fifth tungsten film, a third titanium nitride film, and a silicon nitride film. The silicon film and the fourth tungsten film are polished down to the sixth silicon oxynitride film. The fifth tungsten film and the third titanium nitride film are buried in each contact hole. An inlaid electrode was formed.

[0450] Next, a sixth tungsten film was formed to a thickness of 50 nm by sputtering. Next, a portion of the sixth tungsten film is etched by lithography to form a wiring. A line layer was formed.

[0451] Next, a third heat treatment was carried out at a temperature of 250° C. for 1 hour.

[0452] Next, a photoresist film was formed to a thickness of 1.0 μm by coating. The photoresist film on the part that will become the measurement terminal (measurement pad) is removed by the lithography method. Ta.

[0453] In this manner, the semiconductor device shown in FIG. 1 was fabricated.

[0454] Next, the transistor characteristics of the sample were measured. Design value of channel length (L) = 60 nm, design value of channel width (W) = 60 nm, transistor Star density = 2.0 pieces / μm 2 It was decided.

[0455] The transistor characteristics were measured at drain voltages Vd of 0.1V and 1.2V. The drain current when the gate voltage Vg is changed from -4.0V to +4.0V The change in the on-state current Id was measured. In other words, the Id-Vg characteristics were measured. The voltage (Vbg) of the second gate electrode (back gate electrode) was set to 0V.

[0456] In addition, from the measurement data of Id-Vg characteristics at Vd=0.1V, gradual channel Using the linear region equation of the approximation, the field-effect mobility μFE (cm 2 / Vs) was calculated.

[0457] FIG. 31 shows the Id-Vg characteristics of the sample according to this embodiment at Vd=0.1 and 1.2 V. , and the graph of μFE characteristics at Vd=0.1V is summarized. Figure 31(B) shows the characteristics after a total of four hours of additional heat treatment. The test was carried out in a nitrogen atmosphere at a temperature of 400°C. The vertical axis on the left side of each graph indicates Id. The vertical axis on the right represents μFE, and the horizontal axis represents Vg.

[0458] As shown in FIG. 31B, the structure of one embodiment of the present invention remains stable even after a long period of additional heat treatment. It was confirmed that the transistor characteristics maintained good on / off characteristics. Even after a total heat treatment time of 4 hours, the normally-off characteristics were maintained. The transistor according to the embodiment is resistant to high temperatures (so-called thermal budget) during the manufacturing process. It is also stable against

[0459] In the sample according to this example, S2 has a CAAC-OS. It has few impurities and defects (oxygen deficiency, etc.), high crystallinity, and a dense structure. This suppresses the extraction of oxygen from S2 by the source electrode or drain electrode. This makes it possible to reduce the extraction of oxygen from S2 even when heat treatment is performed. Therefore, transistors with CAAC-OS are stable under thermal budgets. do.

[0460] As described above, in the structure of the semiconductor device according to one embodiment of the present invention, the CAAC-OS It was confirmed that the use of this method can suppress the fluctuation of transistor characteristics due to heat treatment. . [Explanation of symbols]

[0461] I1 insulator I2 insulator S1 oxide S2 oxide S3 oxide 100 Capacitive element 101 Capacitor element 110 Conductors 112 Conductors 120 Conductors 130 Insulator 150 Insulator 156 Conductors 160 Insulator 166 Conductors 200 transistors 201 Transistor 210 Insulator 212 Insulator 214 Insulator 216 Insulator 218 Conductors 300 transistors 301 Insulators 302 Insulators 303 Insulators 310 Conductors 310a Conductor 310b conductor 311 Substrate 313 Semiconductors 314a Low resistance area 314b Low resistance region 315 Insulator 316 Conductors 320 Insulator 322 Insulator 324 Insulators 326 Insulator 328 Conductors 330 Conductors 340 transistors 345 transistors 350 Insulator 352 Insulator 354 Insulators 356 Conductors 360 Insulator 362 Insulators 364 Insulators 366 Conductors 370 Insulator 372 Insulators 374 Insulators 376 Conductors 380 Insulator 382 Insulators 384 Insulators 386 Conductors 400 boards 401a Oxide 401b oxide 402 Insulator 404 Conductors 404a Conductor 404b Conductor 405 Conductors 405a Conductor 405b Conductor 406a Oxide 406a1 Oxides 406b Oxide 406b1 Oxides 406c oxide 406c1 Oxides 408a Oxide 408b oxide 410 Insulator 411 Conductors 411a Conductor 411a1 Electric conductor 411a2 Conductor 412 Insulator 412a Insulator 415 Insulator 416 Conductors 416a Conductor 416a1 Conductors 416a2 Conductor 417 Barrier membrane 417a Barrier film 417a1 Barrier film 417a2 Barrier film 418 Oxide 420 Oxides 421 Resist 422 Oxides 430c oxide 431a Oxide 431b Oxide 432a Oxide 432b Oxide 440 Conductors 440a Conductor 440b Conductor 445 Barrier Layer 445a Barrier layer 445b Barrier layer 450 electrodes 451 Electrode 452 Electrode 455 Insulator 460 Conductors 460a Conductor 460b Conductor 470 Barrier Layer 500 Structure 711 Circuit Board 712 Circuit area 713 Separation area 714 Separation line 715 chips 750 Electronic Components 752 Printed Circuit Board 754 Mounting board 755 leads 2910 Information terminal 2911 Case 2912 Display section 2913 Camera 2914 Speaker section 2915 Operation switch 2916 External connection part 2917 Mike 2920 Notebook Personal Computer 2921 Case 2922 Display section 2923 keyboard 2924 Pointing Device 2940 video camera 2941 Case 2942 Case 2943 Display section 2944 Operation switch 2945 Lens 2946 Connection 2950 Information terminal 2951 Case 2952 Display section 2960 Information Terminal 2961 Case 2962 Display section 2963 bands 2964 Buckle 2965 Operation switch 2966 Input / output terminal 2967 icons 2980 Automobiles 2981 Body 2982 wheels 2983 Dashboard 2984 Light 3001 Wiring 3002 Wiring 3003 Wiring 3004 Wiring 3005 Wiring 3006 Wiring 3007 Wiring 3008 Wiring 3009 Wiring 3010 Wiring

Claims

[Claim 1] a semiconductor layer having indium and oxygen; an insulating film containing oxygen on the semiconductor layer; an oxide on the insulating film; an electrode electrically connected to a source region or a drain region of the semiconductor layer through an opening formed in the insulating film and the oxide; In the opening, the area of ​​the electrode facing the insulating film is 0.035 μm per electrode. ２ The semiconductor device is as follows:

Images