Semiconductor device and data storage system including the same

Abstract

To provide a semiconductor device with improved reliability, and a data storage system including the same.SOLUTION: According to example embodiments, a semiconductor device and a data storage system including the same may include a channel structure including a plurality of channel holes and a channel pattern connecting the plurality of channel holes using a stopper. Accordingly, embodiments of the inventive concept provide a semiconductor device and a data storage system including the same having improved reliability by minimizing and / or improving contact failure due to mis-alignment with a conductive pattern functioning as a common source line in contact with a channel structure.SELECTED DRAWING: Figure 3

Description

[Technical Field]

[0001] The present invention relates to a semiconductor device and a data storage system including the same, and more particularly to a semiconductor device with improved reliability and a data storage system including the same. [Background technology]

[0002] 2. Description of the Related Art In data storage systems that require data storage, there is a demand for semiconductor devices that can store a large amount of data. Accordingly, methods for increasing the data storage capacity of semiconductor devices are being researched. For example, as one method for increasing the data storage capacity of a semiconductor device, a semiconductor device including memory cells arranged three-dimensionally instead of two-dimensionally has been proposed, and improving the reliability of such semiconductor devices is a daily challenge. Summary of the Invention [Problem to be solved by the invention]

[0003] The present invention has been made in view of the above-mentioned problems with conventional semiconductor devices, and an object of the present invention is to provide a semiconductor device with improved reliability and a data storage system including the same. [Means for solving the problem]

[0004] In order to achieve the above object, a semiconductor device according to the present invention includes a first semiconductor structure including a substrate, a circuit element on the substrate, a first wiring structure electrically connected to the circuit element, and a first bonding metal layer on the circuit element and the first wiring structure; and a second semiconductor structure connected to the first semiconductor structure on the first semiconductor structure, wherein the second semiconductor structure includes a memory cell substrate including a conductive pattern and an insulating pattern in contact with a side surface of the conductive pattern, a plurality of gate electrodes stacked below the memory cell substrate and spaced apart from each other along a direction perpendicular to a lower surface of the memory cell substrate, a plurality of channel structures extending through the plurality of gate electrodes and along the perpendicular direction into the memory cell substrate and spaced apart from each other in a first direction intersecting the perpendicular direction, and a plurality of gate electrodes and a plurality of channel structures disposed below the plurality of gate electrodes and the plurality of channel structures. and a second bonding metal layer disposed below the second wiring structure and connected to the first bonding metal layer, wherein each of the plurality of channel structures includes a first channel hole penetrating the plurality of gate electrodes in the vertical direction, a second channel hole penetrating the plurality of gate electrodes in the vertical direction and spaced apart from the first channel hole, and a first channel pattern including a first channel portion disposed in the first channel hole, a second channel portion disposed in the second channel hole, and a first channel connection portion extending from the first channel portion and the second channel portion on the plurality of gate electrodes to connect the first channel portion and the second channel portion, wherein the conductive pattern overlaps the first channel hole in the vertical direction but does not overlap the second channel hole.

[0005] In order to achieve the above object, a semiconductor device according to the present invention includes a first semiconductor structure including a substrate, a circuit element on the substrate, and a first wiring structure on the circuit element, and a second semiconductor structure disposed on the first semiconductor structure, the second semiconductor structure including: a memory cell substrate including a plurality of conductive patterns spaced apart from one another; a plurality of gate electrodes stacked below the memory cell substrate along a direction perpendicular to a lower surface of the memory cell substrate and spaced apart from one another, the plurality of gate electrodes including an upper select gate electrode, a memory gate electrode, and a lower select gate electrode disposed in sequence from the lower surface of the memory cell substrate; first and second isolation structures extending through the plurality of gate electrodes in a first direction intersecting the perpendicular direction and spaced apart from one another in a second direction intersecting the first direction; a first channel structure extending through the plurality of gate electrodes between the first isolation structure and the second isolation structure and spaced apart from one another in the first direction; and a second channel structure spaced apart from the first channel structure in the second direction, and a second wiring structure disposed below the plurality of gate electrodes and the first and second channel structures, wherein each of the first channel structure and the second channel structure includes first to fourth channel holes that penetrate the plurality of gate electrodes in the vertical direction and are spaced apart from each other, first to fourth information storage patterns that are disposed in the first to fourth channel holes, and a first channel pattern that extends from within at least two of the first to fourth channel holes and is exposed from the at least two or more channel holes on the upper select gate electrode, wherein the plurality of conductive patterns include a first conductive pattern extending in the first direction and a second conductive pattern spaced apart from the first conductive pattern in the second direction, and the first conductive pattern contacts a portion of the first channel pattern of each of the first channel structures, and the second conductive pattern contacts a portion of the first channel pattern of each of the second channel structures.

[0006] In order to achieve the above object, a data storage system according to the present invention includes a semiconductor storage device including a first semiconductor structure including a circuit element, a second semiconductor structure disposed on one surface of the first semiconductor structure, and an input / output pad electrically connected to the circuit element, and a controller electrically connected to the semiconductor storage device via the input / output pad and controlling the semiconductor storage device, wherein the second semiconductor structure includes a memory cell substrate including a conductive pattern and an insulating pattern surrounding a side surface of the conductive pattern, a plurality of gate electrodes stacked below the memory cell substrate and spaced apart from each other along a direction perpendicular to a bottom surface of the memory cell substrate, and a plurality of channel structures extending through the plurality of gate electrodes and along the perpendicular direction and spaced apart from each other in a first direction intersecting the perpendicular direction. and each of the channel structures includes a first channel hole penetrating the plurality of gate electrodes in the vertical direction, a second channel hole penetrating the plurality of gate electrodes in the vertical direction and spaced apart from the first channel hole, a first data storage pattern disposed in the first channel hole, a second data storage pattern disposed in the second channel hole, and a channel pattern including a first portion surrounded by the first data storage pattern and the second data storage pattern, a second portion extending from the first portion and exposed from the first data storage pattern and the second data storage pattern, and a third portion extending from the second portion and connecting the second portion, wherein the second portion of the channel pattern has a width that narrows from a bottom surface to an top surface. [Effects of the Invention]

[0007] The semiconductor device and data storage system including the same according to the present invention include a channel structure including a plurality of channel holes and a channel pattern connecting the channel holes by utilizing a stopper. This minimizes and / or improves contact failures due to misalignment between the channel structure and the conductive pattern that functions as a common source line, thereby providing a semiconductor device and a data storage system including the same with improved reliability. [Brief explanation of the drawings]

[0008] [Figure 1] 1 is a block diagram showing a schematic configuration of a semiconductor device according to an embodiment of the present invention; [Figure 2] 2 is an equivalent circuit diagram of a memory cell array of the semiconductor device of FIG. 1. [Figure 3] 1 is a plan view showing a schematic configuration of a semiconductor device according to an embodiment of the present invention; [Figure 4] 4 is an enlarged view of a cell array region of the semiconductor device of FIG. 3. [Figure 5a] 5 is a cross-sectional view of the semiconductor device shown in FIG. 4 taken along line II'. [Figure 5b] FIG. 5b is a partial enlarged view of region A in FIG. 5a. [Figure 6a] 5 is a cross-sectional view of the semiconductor device shown in FIG. 4 taken along line II-II'. [Figure 6b] FIG. 6B is a partial enlarged view of region B in FIG. 6A. [Figure 7] 5b is a partial enlarged view of region A of FIG. 5a according to another embodiment. FIG. [Figure 8] 6b is a partial enlarged view of region B of FIG. 6a according to another embodiment. [Figure 9] 4 is an enlarged view of the cell array region of the semiconductor device of FIG. 3 according to another embodiment. [Figure 10] 4 is an enlarged view of the cell array region of the semiconductor device of FIG. 3 according to another embodiment. [Figure 11] 1A and 1B are diagrams for explaining a method for manufacturing a semiconductor device according to an embodiment of the present invention, in which (a) shows an XY plan view of a cell array region, and (b) shows a cross section of the cell array region taken along line III-III'. [Figure 12] 1A and 1B are diagrams for explaining a method for manufacturing a semiconductor device according to an embodiment of the present invention, in which (a) shows an XY plan view of a cell array region, and (b) shows a cross section of the cell array region taken along line III-III'. [Figure 13]1A and 1B are diagrams for explaining a method for manufacturing a semiconductor device according to an embodiment of the present invention, in which (a) shows an XY plan view of a cell array region, and (b) shows a cross section of the cell array region taken along line III-III'. [Figure 14] 1A and 1B are diagrams for explaining a method for manufacturing a semiconductor device according to an embodiment of the present invention, in which (a) shows an XY plan view of a cell array region, and (b) shows a cross section of the cell array region taken along line III-III'. [Figure 15] 1A and 1B are diagrams for explaining a method for manufacturing a semiconductor device according to an embodiment of the present invention, in which (a) shows an XY plan view of a cell array region, and (b) shows a cross section of the cell array region taken along line III-III'. [Figure 16] 1A and 1B are diagrams for explaining a method for manufacturing a semiconductor device according to an embodiment of the present invention, in which (a) shows an XY plan view of a cell array region, and (b) shows a cross section of the cell array region taken along line III-III'. [Figure 17] 1A and 1B are diagrams for explaining a method for manufacturing a semiconductor device according to an embodiment of the present invention, in which (a) shows an XY plan view of a cell array region, and (b) shows a cross section of the cell array region taken along line III-III'. [Figure 18] 1A and 1B are diagrams for explaining a method for manufacturing a semiconductor device according to an embodiment of the present invention, in which (a) shows an XY plan view of a cell array region, and (b) shows a cross section of the cell array region taken along line III-III'. [Figure 19] 1A and 1B are diagrams for explaining a method for manufacturing a semiconductor device according to an embodiment of the present invention, in which (a) shows an XY plan view of a cell array region, and (b) shows a cross section of the cell array region taken along line III-III'. [Figure 20] 1A and 1B are diagrams for explaining a method for manufacturing a semiconductor device according to an embodiment of the present invention, in which (a) shows an XY plan view of a cell array region, and (b) shows a cross section of the cell array region taken along line III-III'. [Figure 21]1A and 1B are diagrams for explaining a method for manufacturing a semiconductor device according to an embodiment of the present invention, in which (a) shows an XY plan view of a cell array region, and (b) shows a cross section of the cell array region taken along line III-III'. [Figure 22] 1 is a diagram showing a schematic configuration of a data storage system including a semiconductor device according to an embodiment of the present invention. [Figure 23] 1 is a perspective view showing a schematic configuration of a data storage system including a semiconductor device according to an embodiment of the present invention; [Figure 24] 1 is a cross-sectional view showing a schematic configuration of a semiconductor package according to an embodiment of the present invention. DETAILED DESCRIPTION OF THE INVENTION

[0009] Next, specific examples of embodiments for carrying out a semiconductor device and a data storage system including the same according to the present invention will be described with reference to the drawings.

[0010] The same reference numerals are used for the same components in the drawings, and duplicated descriptions of the same components will be omitted.

[0011] FIG. 1 is a block diagram showing a schematic configuration of a semiconductor device according to an embodiment of the present invention. Referring to FIG. 1, a semiconductor device 100 has a characteristic that stored data is maintained even when power is not supplied. The semiconductor device 100 may be a vertical NAND flash memory device. The semiconductor device 100 includes a memory cell array 20 and a peripheral circuit 30.

[0012] The memory cell array 20 includes a plurality of memory cell blocks (BLK1 to BLKn). Each of the memory cell blocks (BLK1 to BLKn) includes a plurality of memory cells. The memory cell array 20 is connected to a peripheral circuit 30 via bit lines BL, word lines WL, at least one string select line SSL, and at least one ground select line GSL. Specifically, the memory cell blocks (BLK1 to BLKn) are connected to the row decoder 33 via word lines WL, string selection lines SSL, and ground selection lines GSL. The memory cell blocks (BLK1 to BLKn) are connected to a page buffer 35 via bit lines BL.

[0013] The peripheral circuit 30 receives an address ADDR, a command CMD, and a control signal CTRL from outside the semiconductor device 100, and transmits and receives data DATA to and from devices outside the semiconductor device 100. The peripheral circuit 30 includes a control logic 37 , a row decoder 33 , and a page buffer 35 . Although not shown in the figure, the peripheral circuit 30 may further include various sub-circuits of an input / output circuit, a voltage generation circuit that generates various voltages necessary for the operation of the semiconductor device 100, and an error correction circuit that corrects errors in the data DATA read from the memory cell array 20.

[0014] The control logic 37 is connected to the row decoder 33, the input / output circuitry, and the voltage generation circuitry. The control logic 37 controls the overall operation of the semiconductor device 100 . The control logic 37 generates various internal control signals used within the semiconductor device 100 in response to the control signal CTRL. For example, the control logic 37 adjusts the voltage levels provided to the word lines WL and bit lines BL when performing a memory operation, such as a program operation or an erase operation.

[0015] The row decoder 33 selects at least one of the multiple memory cell blocks (BLK1 to BLKn) in response to the address ADDR, and selects at least one word line WL, at least one string selection line SSL, and at least one ground selection line GSL of the selected memory cell block (BLK1 to BLKn). The row decoder 33 also transmits a voltage for performing a memory operation to the word lines WL of the selected memory cell blocks (BLK1 to BLKn).

[0016] The page buffer 35 is connected to the memory cell array 20 via bit lines BL. The page buffer 35 acts as a write driver or a sense amplifier. Specifically, when a program operation is performed, the page buffer 35 operates as a write driver and applies a voltage corresponding to the data DATA to be stored in the memory cell array 20 to the bit line BL. On the other hand, when a read operation is performed, the page buffer 35 operates as a sense amplifier to sense the data DATA stored in the memory cell array 20 .

[0017] FIG. 2 is an equivalent circuit diagram of the memory cell array of the semiconductor device of FIG. Referring to FIG. 2, the memory cell array 20 of the semiconductor device 100 includes common source lines (CSL1, CSL2), a plurality of bit lines BL, and a plurality of cell strings CSTR.

[0018] The plurality of common source lines (CSL1, CSL2) are arranged two-dimensionally. For example, the common source lines CSL1 and CSL2 are spaced apart from each other in the second direction (Y direction) and extend in the first direction (X direction). The common source lines (CSL1, CSL2) are electrically supplied with the same voltage or with different voltages, and are controlled separately. Each of the common source lines CSL1 and CSL2 extending in the first direction (X direction) is connected to the ground selection transistors GST arranged in the same row. The ground selection transistors GST arranged in the same row are connected to different bit lines BL.

[0019] The plurality of bit lines BL are arranged two-dimensionally. For example, the bit lines BL are spaced apart from one another in a first direction (X direction) and extend in a second direction (Y direction). A plurality of cell strings CSTR are connected in parallel to each of the bit lines BL. Each of the cell strings CSTR is individually connected to a common source line (CSL1, CSL2). That is, a plurality of cell strings CSTR are arranged between the bit lines BL and the common source lines CSL1 and CSL2.

[0020] Each of the plurality of cell strings CSTR includes a ground selection transistor GST connected to a corresponding common source line (CSL1, CSL2), a string selection transistor SST connected to a corresponding bit line BL, and a plurality of memory cell transistors MCT arranged between the ground selection transistor GST and the string selection transistor SST. The plurality of memory cell transistors MCT include memory cells corresponding to the word lines (WL1 to WLn). Each of the memory cell transistors MCT includes a data storage element. The ground select transistor GST, the string select transistor SST, and the memory cell transistor MCT are connected in series in a third direction (Z direction).

[0021] Common source lines (CSL1, CSL2) are connected to the sources of the ground selection transistors GST, respectively. A ground selection line GSL, a plurality of word lines WL1 to WLn, and a string selection line SSL are arranged between the common source lines CSL1 and CSL2 and the bit lines BL. The ground selection line GSL is used as the gate electrode of each of the ground selection transistors GST, the word lines (WL1 to WLn) are used as the gate electrodes of each of the memory cell transistors MCT, and the string selection line SSL is used as the gate electrode of each of the string selection transistors SST.

[0022] The memory cell transistors MCT are connected to a common ground selection line GSL and a common string selection line SSL. One string selection line (SSL) is connected to a memory cell transistor MCT connected to one bit line BL. The memory cell string CSTR is connected to one string selection line SSL.

[0023] From the viewpoint of circuit operation of the semiconductor device 100, a row decoder (e.g., row decoder 33 in FIG. 1) selects one of a plurality of memory blocks (e.g., a plurality of memory cell blocks (BLK1 to BLKn) in FIG. 1) based on a row address, selects one of the word lines (WL1 to WLn) of the selected memory block, and selects one of the common source lines (CSL1, CSL2).

[0024] FIG. 3 is a plan view showing a schematic configuration of a semiconductor device according to an embodiment of the present invention. Referring to FIG. 3, the semiconductor device 100 includes a cell array region R1, an extension region R2, and a pad region R3. In the cell array region R1, a memory cell array including a plurality of memory cells (for example, the memory cell array 20 in FIG. 1) is formed. For example, in the cell array region R1, a channel structure CH, a bit line (e.g., the bit line BL in FIG. 2), a common source line (e.g., the common source line (CSL1, CSL2) in FIG. 2), a gate electrode (e.g., the gate electrode 130 in FIG. 5a), etc. are arranged.

[0025] Isolation structures (MS1, MS2, MS3) are further arranged in the cell array region R1. In one example, each of the isolation structures (MS1, MS2, MS3) extends through the gate electrode along the first direction (X direction). The isolation structures MS1, MS2, and MS3 include a first isolation structure MS1, a second isolation structure MS2, and a third isolation structure MS3 that extend in a first direction (X direction) and are spaced apart from each other in a second direction (Y direction). The first isolation structure MS1, the second isolation structure MS2, and the third isolation structure MS3 are arranged parallel to each other in the first direction (X direction). Memory cell blocks (BLK1, BLK2) are defined by mold structures separated by isolation structures (MS1, MS2, MS3). For example, the first memory cell block BLK1 is defined by a first isolation structure MS1 and a second isolation structure MS2, and the second memory cell block BLK2 is defined by a second isolation structure MS2 and a third isolation structure MS3.

[0026] A plurality of page regions P1, P2 spaced apart in the second direction (Y direction) are arranged in each of the first and second memory cell blocks BLK1, BLK2. In one example, each of the first and second memory cell blocks (BLK1, BLK2) includes a first page region P1 and a second page region P2. Although the figure shows that two page areas, the first and second page areas (P1, P2), are arranged in each of the first and second memory cell blocks (BLK1, BLK2), this is not limited to this, and three or more page areas may be arranged in each of the first and second memory cell blocks (BLK1, BLK2). The first page region P1 and the second page region P2 are defined by word lines (for example, word lines WL1 to WLn in FIG. 2) included in the first and second memory cell blocks BLK1 and BLK2, respectively.

[0027] A plurality of channel structures CH spaced apart in a first direction (X direction) are arranged in each of the first page region P1 and the second page region P2. Each of the plurality of channel structures CH includes a plurality of channel holes extending in a third direction (Z direction) and penetrating the mold structure. Although each of the plurality of channel structures CH is shown in the figure as penetrating four channel holes, this is not limited thereto, and in other embodiments, each of the plurality of channel structures CH may penetrate two channel holes or four or more channel holes.

[0028] In this specification, the mold structure is a structure in which gate electrodes (for example, gate electrode 130 in FIG. 5a) and mold insulating layers (for example, interlayer insulating layer 120 in FIG. 5a) are alternately stacked. The plurality of channel structures CH are arranged in a first page region P1 and a second page region P2.

[0029] The extension region R2 is disposed around the cell array region R1. In the extension region R2, a gate electrode (for example, the gate electrode 130 in FIG. 5a) is stacked in a stepped manner. In the extension region R2, the cell contact 150 and the dummy channel structure DCH are arranged. The cell contact 150 extends in the vertical direction (Z direction) to contact the gate electrode (for example, the gate electrode 130 in FIG. 5a) disposed on the topmost stage of the gate electrodes. The dummy channel structure DCH has a shape similar to that of the channel structure CH, and can reduce stress applied to the mold structure in the extension region R2.

[0030] The pad region R3 is disposed inside the cell array region R1 and the extension region R2, or is disposed inside the cell array region R1 and the extension region R2. Input / output contacts 160 are arranged in pad region R3. An external device and the semiconductor device 100 are electrically connected to each other via the input / output contacts 160 .

[0031] FIG. 4 is an enlarged view of the cell array region of the semiconductor device of FIG. Referring to Figures 3 and 4, Figure 4 shows a plan view of one of the multiple memory cell blocks (BLK1, BLK2) in the cell array region R1 of the semiconductor device 100 and the first and second page regions (P1, P2) within one memory cell block.

[0032] Referring to FIG. 4, a plurality of channel structures CH are disposed in each of the first and second page regions P1 and P2 of the semiconductor device 100. A first channel structure CH1 is arranged in the first page region P1, and a second channel structure CH2 is arranged in the second page region P2. Each of the first channel structure CH1 and the second channel structure CH2 includes a plurality of channel structures CHS spaced apart in a first direction (X direction).

[0033] Each of the plurality of channel structures CHS includes first, second, third, and fourth channel holes (CHa, CHb, CHc, CHd) and a connection pattern CB connecting the first, second, third, and fourth channel holes (CHa, CHb, CHc, CHd). In one example, each of the first, second, third, and fourth channel holes (CHa, CHb, CHc, CHd) extends in a third direction (Z direction) and penetrates the mold structure. The first, second, third, and fourth channel holes (CHa, CHb, CHc, CHd) are arranged alternately in a first direction (X direction) and a second direction (Y direction) in a plan view. For example, the first, second, third, and fourth channel holes (CHa, CHb, CHc, and CHd) are sequentially arranged in a zigzag pattern in the second direction (Y direction). In one example, the connection pattern CB extends from each of the first, second, third, and fourth channel holes (CHa, CHb, CHc, CHd) and has a structure that connects the first, second, third, and fourth channel holes (CHa, CHb, CHc, CHd).

[0034] The semiconductor device 100 further includes first, second, third, and fourth conductive wirings (BLa, BLb, BLc, BLd) arranged in a cell array region (e.g., cell array region R1) and connected to the first, second, third, and fourth channel holes (CHa, CHb, CHc, CHd), respectively. The first, second, third, and fourth conductive lines (BLa, BLb, BLc, BLd) extend in the second direction (Y direction) and are spaced apart from each other in the first direction (X direction). The first conductive wiring BLa overlaps the first channel hole CHa in the vertical direction (Z direction) and is connected to the first channel hole CHa via the first contact pad BTa. The second conductive wiring BLb overlaps the third channel hole CHc in the vertical direction (Z direction) and is connected to the third channel hole CHc via the third contact pad BTc. The third conductive wiring BLc overlaps the second channel hole CHb in the vertical direction (Z direction) and is connected to the second channel hole CHb via the second contact pad BTb. The fourth conductive wiring BLd overlaps the fourth channel hole CHd in the vertical direction (Z direction) and is connected to the fourth channel hole CHd via a fourth contact pad BTd.

[0035] The first, second, third, and fourth conductive lines (BLa, BLb, BLc, BLd) correspond to the bit lines BL in FIG. In one example, each first channel hole CHa of the first channel structure CH1 and each first channel hole CHa of the second channel structure CH2 are contacted to a common first conductive wiring BLa. The second channel holes CHb of the first channel structure CH1 and the second channel holes CHb of the second channel structure CH2 are contacted to a common third conductive wiring BLc. The third channel holes CHc of the first channel structure CH1 and the third channel holes CHc of the second channel structure CH2 are contacted to a common second conductive wiring BLb. The respective fourth channel holes CHd of the first channel structure CH1 and the respective fourth channel holes CHd of the second channel structure CH2 are contacted to a common fourth conductive wiring BLd.

[0036] The semiconductor device 100 further includes a first conductive pattern 101 arranged on the first page region P1 and a second conductive pattern 102 arranged on the second page region P2. In one example, the first conductive pattern 101 and the second conductive pattern 102 extend in a first direction (X direction) and are spaced apart in a second direction (Y direction). The first conductive pattern 101 is on the first channel structure CH1 and overlaps at least a portion of the first channel structure CH1. The second conductive pattern 102 is on the second channel structure CH2 and overlaps at least a portion of the second channel structure CH2. Each of the first and second conductive patterns (101, 102) overlaps with at least two adjacent channel holes among the first to fourth channel holes (CHa to CHd), but does not overlap with the remaining channel holes.

[0037] In one example, the first conductive pattern 101 overlaps the second and third channel holes (CHb, CHc) of the channel structure CHS of the first channel structure CH1 and contacts the channel connection portion overlapping with the second and third channel holes (CHb, CHc). The second conductive pattern 102 overlaps the second and third channel holes (CHb, CHc) of the channel structure CHS of the second channel structure CH2, and contacts the channel connection portion overlapping with the second and third channel holes (CHb, CHc). The first and second conductive patterns (101, 102) do not overlap the first channel hole CHa and the fourth channel hole CHd. However, this is not limited to this, and in other embodiments, the first and second conductive patterns (101, 102) may be such that the first conductive pattern 101 overlaps with the first to third channel holes (CHa to CHc) but does not overlap with the fourth channel hole CHd, and the second conductive pattern 102 overlaps with the second and third channel holes (CHb, CHc) but does not overlap with the first and fourth channel holes (CHa, CHd). The first and second conductive patterns (101, 102) correspond to the common source lines (CSL1, CSL2) in FIG. The first conductive pattern 101 functions as a first common source line CSL1 in FIG. 2, and the second conductive pattern 102 functions as a second common source line CSL2 in FIG.

[0038] A semiconductor device according to an embodiment of the present invention includes first and second isolation structures (MS1, MS2) extending in a first direction (X direction) and penetrating a gate electrode, first and second channel structures (CH1, CH2) disposed between the first and second isolation structures (MS1, MS2), and first and second conductive patterns (101, 102) respectively disposed on the first and second channel structures (CH1, CH2) and extending in the first direction (X direction), wherein each of the channel structures (CH1, CH2) includes channel structures CHS spaced apart in the first direction (X direction), and each of the channel structures CHS includes a channel pattern extending from and connecting a plurality of channel holes. As a result, the first and second conductive patterns (101, 102) that contact the first and second channel structures (CH1, CH2), respectively, are arranged on a page-by-page basis, minimizing and / or improving contact failures between the first and second channel structures (CH1, CH2) and the first and second conductive patterns (101, 102), thereby providing a semiconductor device with improved electrical characteristics.

[0039] 5a is a cross-sectional view of the semiconductor device shown in FIG. 4 taken along line II', FIG. 5b is a partially enlarged view of region A in FIG. 5a, FIG. 6a is a cross-sectional view of the semiconductor device shown in FIG. 4 taken along line II-II', and FIG. 6b is a partially enlarged view of region B in FIG. 6a. Referring to Figures 5a, 5b, 6a, and 6b, the semiconductor device 100 includes a peripheral circuit structure PERI, which is a first semiconductor structure, and a memory cell structure CELL, which is a second semiconductor structure, which are bonded by a wafer bonding method.

[0040] That is, the semiconductor device 100 has a C2C (chip to chip) structure. The C2C structure means that after fabricating a memory cell structure CELL and a peripheral circuit structure PERI, the memory cell structure CELL and the peripheral circuit structure PERI are connected to each other by a bonding method. In one example, this refers to a method of electrically connecting a second bonding metal layer 198 formed on a second bonding insulating layer 199 at the bottom of a memory cell structure CELL and a bonding metal formed on a first bonding metal layer 298 formed on a first bonding insulating layer 299 at the top of a peripheral circuit structure PERI. The memory cell structure CELL is disposed on the peripheral circuit structure PERI. In another example, the memory cell structure CELL may be disposed below the peripheral circuit structure PERI.

[0041] The peripheral circuit structure PERI includes a substrate 201, an impurity region 205 in the substrate 201, an isolation region 210, a circuit element 220 on the substrate 201, a circuit contact plug 270, a circuit wiring line 280, a peripheral region insulating layer 290, and a peripheral bonding structure. The peripheral bonding structure includes a first bonding metal layer 298 and a first bonding insulating layer 299 . The substrate 201 has a top surface that extends in a first direction (X direction) and a second direction (Y direction). In the substrate 201, active regions are defined by element isolation regions 210. In a part of the active region, impurity regions 205 serving as source / drain regions are arranged. The substrate 201 may include a semiconductor material, such as a Group IV semiconductor, a Group III-V compound semiconductor, or a Group II-VI compound semiconductor. The substrate 201 may be provided as a bulk wafer or an epitaxial layer.

[0042] The circuit element 220 includes a planar transistor. Each circuit element 220 includes a circuit gate dielectric layer 222 , a spacer layer 224 , and a circuit gate electrode 225 . On either side of the circuit gate electrode 225 , impurity regions 205 are disposed in the substrate 201 . The peripheral region insulating layer 290 is disposed on the substrate 201 and above the circuit elements 220 . The peripheral region insulating layer 290 includes a plurality of insulating layers formed in different process steps. The peripheral region insulating layer 290 may be made of an insulating material.

[0043] The circuit contact plugs 270 and the circuit wiring lines 280 form a circuit wiring structure electrically connected to the circuit elements 220 and the impurity regions 205 . The circuit contact plug 270 has a cylindrical shape, and the circuit wiring line 280 has a line shape. Electrical signals are applied to the circuit elements 220 through the circuit contact plugs 270 and the circuit wiring lines 280 . In a region not shown in the figure, a circuit contact plug 270 is also connected to the circuit gate electrode 225 . The circuit contact plugs 270 and the circuit wiring lines 280 may include a conductive material, such as tungsten (W), copper (Cu), aluminum (Al), etc., and each of the structures may further include a diffusion barrier layer. The circuit wiring lines 280 are connected to the circuit contact plugs 270 and are arranged in multiple layers. In this specification, the circuit contact plug 270 and the circuit wiring line 280 are referred to as a first wiring structure.

[0044] The first bonding metal layer 298 is connected to the second bonding metal layer 198 of the memory cell structure CELL. The first bonding metal layer 298, together with the second bonding metal layer 198, provides an electrical connection path by joining the memory cell structure CELL and the peripheral circuit structure PERI. Although not shown, at least a portion of the first bonding metal layer 298 is connected to the circuit contact plug 270 and / or the circuit wiring line 280 . In other embodiments, portions of the first bonding metal layer 298 may not be connected to the circuit contact plugs 270 and / or the circuit wiring lines 280, but may be provided solely for bonding purposes.

[0045] The first bonding metal layer 298 includes a conductive material, for example, copper (Cu). A first bonding insulating layer 299 is disposed around the first bonding metal layer 298 . The first bonding insulating layer 299 may also function as a diffusion barrier for the first bonding metal layer 298 and may include, for example, at least one of SiN, SiON, SiCN, SiOC, SiOCN, and SiO.

[0046] The memory cell structure CELL includes first and second conductive patterns (101, 102), an insulating pattern 105 surrounding the sides of the first and second conductive patterns (101, 102), a passivation layer 106 on the first and second conductive patterns (101, 102) and the insulating pattern 105, a gate electrode 130 stacked on the underside of the first and second conductive patterns (101, 102) and the insulating pattern 105, an interlayer insulating layer 120 stacked alternately with the gate electrode 130 to form a gate structure, first and second channel structures (CH1, CH2) arranged to penetrate the gate electrode 130 and the interlayer insulating layer 120, and a cell bonding structure. The cell bonding structure includes a second bonding metal layer 198 and a second bonding insulating layer 199 . In this specification, the substrate structure including the first and second conductive patterns (101, 102) and the insulating pattern 105 surrounding the sides of the first and second conductive patterns (101, 102) is referred to as a "memory cell substrate."

[0047] The first and second conductive patterns 101 and 102 each have a plate shape extending in a first direction (X direction) and spaced apart from each other in a second direction (Y direction). The first and second conductive patterns (101, 102) are disposed between the first isolation structure MS1 and the second isolation structure MS2. The first and second conductive patterns (101, 102) include a conductive material. For example, the first and second conductive patterns (101, 102) may include a semiconductor material, such as a group IV semiconductor, a group III-V compound semiconductor, or a group II-VI compound semiconductor. For example, the Group IV semiconductor may include silicon, germanium, or silicon-germanium. The first and second conductive patterns (101, 102) may further include impurities. The first and second conductive patterns (101, 102) may be provided as polycrystalline semiconductor layers, such as polycrystalline silicon layers, or epitaxial layers. The first conductive pattern 101 is directly connected to each channel pattern 140 of the first channel structure CH1. The second conductive pattern 102 is directly connected to each channel pattern 140 of the second channel structure CH2.

[0048] The gate electrodes 130 are stacked on the lower surface of the memory cell substrate at intervals in the vertical direction (Z direction), and together with the interlayer insulating layer 120 form a mold structure (or a stack structure). The gate electrodes 130 include upper gate electrodes 130L constituting a ground selection transistor, memory gate electrodes 130M constituting a plurality of memory cells, and lower gate electrodes 130U constituting a string selection transistor. The capacity of the semiconductor device 100 determines the number of memory gate electrodes 130M that constitute a memory cell. There may be one or more upper gate electrodes 130L and lower gate electrodes 130U. In another example, a gate electrode including an erase transistor is disposed between the memory gate electrode 130M and the upper gate electrode 130L, and between the memory gate electrode 130M and the lower gate electrode 130U. In one embodiment, a portion of the memory gate electrode 130M may be a dummy gate electrode. The gate electrode 130 may include a conductive material, for example, at least one metal material selected from the group consisting of tungsten (W), molybdenum (Mo), tantalum (Ta), ruthenium (Ru), niobium (Nb), osmium (Os), zirconium (Zr), iridium (Ir), rhenium (Re), and titanium (Ti), or a semiconductor material such as polycrystalline silicon.

[0049] The interlayer insulating layer 120 is disposed between the gate electrodes 130 . Similar to the gate electrodes 130, the interlayer insulating layers 120 are also arranged to be spaced apart from each other in the third direction (Z direction) which is a direction perpendicular to the lower surface of the memory cell substrate. The interlayer insulating layer 120 includes an insulating material such as silicon oxide or silicon nitride. In embodiments, the thickness of each of the interlayer insulating layers 120 may vary.

[0050] The first and second isolation structures MS1 and MS2 are disposed to extend through the gate electrode 130 in a first direction (X direction). As shown in FIG. 3, the first and second isolation structures MS1 and MS2 are arranged parallel to each other in a first direction (X direction). The gate electrodes 130 separated by the first and second isolation structures (MS1, MS2) form one memory cell block (for example, a first memory cell block BLK1). The range of the memory cell block is not limited to this. The first and second isolation structures MS1 and MS2 contact the insulating pattern 105 by passing through the gate electrode 130 stacked on the lower surface of the memory cell substrate. The first and second isolation structures (MS1, MS2) may include an insulating material, such as silicon oxide, silicon nitride, or silicon oxynitride.

[0051] The first channel structure CH1 is disposed between the first isolation structure MS1 and the second isolation structure MS2, extends through the gate electrode 130 in the third direction (Z direction), and is connected to the first conductive pattern 101. The first channel structure CH1 is a channel structure disposed in a first page region (for example, the first page region P1 in FIG. 3) of a first memory cell block (for example, the first memory cell block BLK1 in FIG. 3). The second channel structure CH2 is disposed between the first isolation structure MS1 and the second isolation structure MS2 and is spaced apart from the first channel structure CH1 in the second direction (Y direction). The second gate structure CH2 extends in the third direction (Z direction) through the gate electrode 130 and is connected to the second conductive pattern 102. The second channel structure CH2 is a channel structure disposed in a second page region (for example, the second page region P2 in FIG. 3) of a second memory cell block (for example, the second memory cell block BLK2 in FIG. 3).

[0052] Each of the first channel structure CH1 and the second channel structure CH2 includes a channel structure CHS. In one example, each of the channel structures CHS includes first to fourth channel holes (CHa to CHd) that penetrate the gate electrode 130 and the interlayer insulating layer 120 in the third direction (Z direction) and a connection pattern CB that connects the first to fourth channel holes (CHa to CHd). The first to fourth channel holes (CHa to CHd) are arranged in a zigzag pattern in the second direction (Y direction) on the XY plane. The first to fourth channel holes (CHa to CHd) each have a pillar shape, and have inclined side surfaces that become narrower as they approach the first conductive pattern 101 (or the second conductive pattern 102). Each of the channel structures CH includes information storage patterns (141, 142, 143) disposed in the first to fourth channel holes (CHa to CHd) of the channel structures CHS constituting the channel structure CH, a channel pattern 140 extending from within each of the first to fourth channel holes (CHa to CHd), and a channel-buried insulating layer 147. In one example, the information storage patterns (141, 142, 143) are disposed between the gate electrode 130 and the channel pattern 140 in the first to fourth channel holes (CHa to CHd). The channel pattern 140 and the channel-buried insulating layer 147 constitute the respective connection patterns CB of the channel structure CHS.

[0053] The channel pattern 140 includes channel portions 140a disposed in the first to fourth channel holes CHa to CHd, respectively, and channel connection portions 140b and 140c extending from the channel portions 140a and connecting the channel portions 140a. The channel portion 140a is surrounded by the information storage patterns (141, 142, 143) in each of the first to fourth channel holes (CHa to CHd) and is formed in an annular shape surrounding the channel-buried insulating layer 147. In some embodiments, the channel portion 140 a has a columnar shape, such as a cylindrical or rectangular column, without the channel buried insulating layer 147 . The channel portion 140a includes a first channel portion (or a first channel layer) disposed in the first channel hole CHa, a second channel portion (or a second channel layer) disposed in the second channel hole CHb, a third channel portion (or a third channel layer) disposed in the third channel hole CHc, and a fourth channel portion (or a fourth channel layer) disposed in the fourth channel hole CHd.

[0054] The channel connection portions (140b, 140c) extend from the channel portion 140a and are exposed from the first to fourth channel holes (CHa to CHd), and contact the first and second conductive patterns (101, 102) or the insulating pattern 105. In one example, the channel connection portions (140b, 140c) of the first channel structure CH1 contact the first conductive pattern 101 or the insulating pattern 105, and the channel connection portions (140b, 140c) of the second channel structure CH2 contact the second conductive pattern 102 or the insulating pattern 105. In one example, for the first and second channel structures (CH1, CH2), a portion of the channel connection portion (140b, 140c) contacts the first and second conductive patterns (101, 102), and the remaining portion of the channel connection portion (140b, 140c) contacts the insulating pattern 105. The channel connection portions (140b, 140c) include a first channel connection portion that connects the first channel portion arranged in the first channel hole CHa and the second channel portion arranged in the second channel hole CHb, and a second channel connection portion that connects the third channel portion arranged in the third channel hole CHc and the fourth channel portion arranged in the fourth channel hole CHd. The first channel connecting portion and the second channel connecting portion may be integral.

[0055] The channel connecting portion (140b, 140c) includes an extension portion 140b extending from the channel portion 140a and a main body portion 140c connecting the extension portion 140b. The extension portions 140b extend from the (first to fourth) channel portions 140a in the first to fourth channel holes (CHa to CHd), respectively, and have a columnar shape. The body portion 140c extends from the extension portion 140b and has a lower surface disposed at a level higher than the upper surface of the gate electrode . The extension 140b has a shape that narrows from the bottom surface to the top surface. The extensions 140b branch off from the main body 140c and are connected to the (first to fourth) channel portions 140a in the first to fourth channel holes (CHa to CHd), respectively. The channel pattern 140 includes a semiconductor material such as polycrystalline silicon or single crystal silicon.

[0056] Channel connection portions (140b, 140c) extended from at least two of the first to fourth channel holes (CHa to CHd) contact the first and second conductive patterns (101, 102) or the insulating pattern 105. In one example, the channel connection portions (140b, 140c) extended from the second and third channel holes (CHb, CHc) contact the first and second conductive patterns (101, 102), and the channel connection portions (140b, 140c) extended from the first and fourth channel holes (CHa, CHd) contact the insulating pattern 105. The channel connection portions (140b, 140c) extended from the second and third channel portions of the second and third channel holes (CHb, CHc) of the channel structure CHS constituting the first channel structure CH1 contact the first conductive pattern 101, and the channel connection portions (140b, 140c) extended from the first and fourth channel portions of the first and fourth channel holes (CHa, CHd) contact the insulating pattern 105. The channel connection portions (140b, 140c) extended from the second and third channel portions of the second and third channel holes (CHb, CHc) of the channel structure CHS constituting the second channel structure CH2 contact the second conductive pattern 102, and the channel connection portions (140b, 140c) extended from the first and fourth channel portions of the first and fourth channel holes (CHa, CHd) contact the insulating pattern 105.

[0057] The channel buried insulating layer 147 is surrounded by the channel pattern 140 . The channel-buried insulating layer 147 includes a first insulating connection portion 147a surrounded by the channel portion 140a of the channel pattern 140 within the first to fourth channel holes (CHa to CHd), and a second insulating connection portion 147b extended from the insulating portion, exposed from the first to fourth channel holes (CHa to CHd), and surrounded by the channel connection portions (140b, 140c). The channel buried insulating layer 147 includes an insulating material, and may include, for example, silicon oxide, silicon nitride, or silicon oxynitride.

[0058] Each of the first and second channel structures (CH1, CH2) further includes a channel pad 149 disposed at the lower end of each of the first to fourth channel holes (CHa to CHd). The channel pad 149 comprises, for example, doped polycrystalline silicon. The channel pads 149 arranged at the bottom ends of the first to fourth channel holes (CHa to CHd) of the channel structures CHS constituting the first channel structure CH1 are connected to the first to fourth studs (171a to 171d). In one example, the channel pad 149 arranged at the lower end of the first channel hole CHa of the first channel structure CH1 is connected to the first stud 171a, the channel pad 149 arranged at the lower end of the second channel hole CHb of the first channel structure CH1 is connected to the second stud 171b, the channel pad 149 arranged at the lower end of the third channel hole CHc of the first channel structure CH1 is connected to the third stud 171c, and the channel pad 149 arranged at the lower end of the fourth channel hole CHd of the first channel structure CH1 is connected to the fourth stud 171d. The first channel hole CHa of the first channel structure CH1 is connected to the first conductive wiring BLa via the first stud 171a, the second channel hole CHb of the first channel structure CH1 is connected to the third conductive wiring BLc via the second stud 171b, the third channel hole CHc of the first channel structure CH1 is connected to the second conductive wiring BLb via the third stud 171c, and the fourth channel hole CHd of the first channel structure CH1 is connected to the fourth conductive wiring BLd via the fourth stud 171d.

[0059] In one embodiment, the second channel hole CHb of the first channel structure CH1 and the second channel hole CHb of the second channel structure CH2 are connected to the same bit line (eg, bit line BL in FIG. 1). For example, the second stud 171b arranged below the channel pad 149 of the second channel hole CHb of the first channel structure CH1 and the second stud 172b arranged below the channel pad 149 of the second channel hole CHb of the second channel structure CH2 are commonly connected to the third conductive wiring BLc. In one example, the fourth channel hole CHd of the first channel structure CH1 and the fourth channel hole CHd of the second channel structure CH2 are connected to the same bit line (eg, the bit line BL in FIG. 1). For example, the fourth stud 171d arranged below the channel pad 149 of the fourth channel hole CHd of the first channel structure CH1 and the fourth stud 172d arranged below the channel pad 149 of the fourth channel hole CHd of the second channel structure CH2 are commonly connected to the fourth conductive wiring BLd.

[0060] The information storage patterns (141, 142, 143) are disposed between the channel portion 140a of the channel pattern 140 and the gate electrode . The information storage pattern (141, 142, 143) includes a blocking layer 141, a data storage layer 142, and a tunneling layer 143. A blocking layer 141, a data storage layer 142, and a tunneling layer 143 are sequentially disposed on the gate electrode 130. The information storage patterns (141, 142, 143) include a first information storage pattern arranged in the first channel hole CHa, a second information storage pattern arranged in the second channel hole CHb, a third information storage pattern arranged in the third channel hole CHc, and a fourth information storage pattern arranged in the fourth channel hole CHd. The information storage patterns (141, 142, 143) are disposed only in the first to fourth channel holes (CHa to CHd) and are not exposed by the first to fourth channel holes (CHa to CHd).

[0061] The tunneling layer 143 is disposed between the data storage layer 142 and the channel portion 140a of the channel pattern 140, allows charges to tunnel into the data storage layer 142, and may include, for example, silicon oxide (SiO2), silicon nitride (Si3N4), silicon oxynitride (SiON), or a combination thereof. The data storage layer 142 is disposed between the blocking layer 141 and the tunneling layer 143 and is a charge trapping layer or a floating gate conductive layer. The blocking layer 141 is disposed between the gate electrode 130 and the data storage layer 142 and may include silicon oxide (SiO2), silicon nitride (Si3N4), silicon oxynitride (SiON), a high-k dielectric material, or a combination thereof.

[0062] The cell region insulating layer 190 is disposed on the lower surface of the gate electrode 130 and contacts the cell bonding structures (198, 199). The contact plug 174 and the wiring line 172 are included in the cell region insulating layer 190 . The contact plug 174 has a cylindrical shape, and the wiring line 172 has a line shape. The contact plug 174 and the wiring line 172 may include a conductive material such as tungsten (W), copper (Cu), or aluminum (Al), and each of the components may further include a diffusion barrier. The contact plug 174 and the wiring line 172 are referred to as a second wiring structure.

[0063] The second bonding metal layer 198 is connected to the first bonding metal layer 298 of the peripheral circuit structure PERI. In another example, a portion of the second bonding metal layer 198 may not be connected to the cell wiring structure and may be disposed only for bonding. The second bonding metal layer 198 includes a conductive material, for example, copper (Cu). A second bonding insulating layer 199 is disposed around the second bonding metal layer 198 . The second bonding insulating layer 199 may also function as a diffusion barrier for the second bonding metal layer 198 and may include, for example, at least one of SiN, SiON, SiCN, SiOC, SiOCN, and SiO.

[0064] FIG. 7 is a partial enlarged view of region A in FIG. 5a according to another embodiment, and FIG. 8 is a partial enlarged view of region B in FIG. 6a according to another embodiment. 7 and 8, the remaining configuration of the semiconductor device 100', except for the channel structure CH', is the same as or corresponds to the configuration shown in FIGS. 5a to 6b.

[0065] Each of the channel structures CH' includes information storage patterns (141, 142, 143) disposed in the first to fourth channel holes (CHa to CHd) of the channel structures CHS constituting the channel structure CH', a channel pattern 140 extending from within each of the first to fourth channel holes (CHa to CHd), a channel-filled insulating layer 147, and a conductive liner 148. In one example, the information storage patterns (141, 142, 143) are disposed between the gate electrode 130 and the channel pattern 140 in the first to fourth channel holes (CHa to CHd). The channel pattern 140, the channel-filled insulating layer 147, and the conductive liner 148 constitute each connection pattern CB of the channel structure CHS.

[0066] The conductive liner 148 covers the channel pattern 140 exposed from the first to fourth channel holes (CHa to CHd). In one example, the conductive liner 148 covers only the channel connecting portions (140b, 140c) of the channel pattern 140. The conductive liner 148 is arranged according to the surface profile of the channel connecting portions (140b, 140c) of the channel pattern 140. In one example, the conductive liner 148 comprises a semiconductor material such as polycrystalline silicon or single crystal silicon. The conductive liner 148 includes an impurity region containing a first impurity, which may include at least one of phosphorus (P), arsenic (As), and antimony (Sb) as an n-type impurity. The conductive liner 148 may be formed by an atomic layer deposition (ALD) process or an area selective deposition (ASD) process.

[0067] 9 and 10 are enlarged views of the cell array region of the semiconductor device of FIG. 3 according to other embodiments. 9 and 10 show plan views of the first and second page regions (P1, P2) in one memory cell block among a plurality of memory cell blocks (BLK1, BLK2) in the cell array region R1 of the semiconductor device (100a, 100b).

[0068] Referring to FIG. 9, a plurality of channel structures CH″ are arranged in each of the first and second page regions P1 and P2 of the semiconductor device 100a. A first channel structure CH1'' is arranged in the first page region P1, and a second channel structure CH2'' is arranged in the second page region P2. Each of the first channel structure CH1'' and the second channel structure CH2'' includes a plurality of channel structures CHS' spaced apart in a first direction (X direction). Each of the plurality of channel structures CHS' includes a first channel structure CHS1 and a second channel structure CHS2 spaced apart from the first channel structure CHS1 in the second direction (Y direction).

[0069] Each of the first channel structures CHS1 includes a first channel hole CHa, a second channel hole CHb, and a first connection pattern CB1 connecting the first channel hole CHa and the second channel hole CHb. The first channel structures CHS1 are spaced apart from each other in the first direction (X direction). Each of the first and second channel holes CHa and CHb extends in the third direction (Z direction) and penetrates the mold structure. The first channel holes CHa and the second channel holes CHb are arranged alternately in a direction between a first direction (X direction) and a second direction (Y direction) on the XY plane. The first connection pattern CB1 is extended from each of the first channel hole CHa and the second channel hole CHb, and has a structure for connecting the first and second channel holes CHa and CHb.

[0070] Each of the second channel structures CHS2 includes a third channel hole CHc, a fourth channel hole CHd, and a second connection pattern CB2 connecting the third channel hole CHc and the fourth channel hole CHd. The second channel structures CHS2 are spaced apart from each other in the first direction (X direction). The third and fourth channel holes CHc and CHd extend in the third direction (Z direction) and penetrate the mold structure. The third channel holes CHc and the fourth channel holes CHd are arranged alternately in a direction between the first direction (X direction) and the second direction (Y direction) on the XY plane. The second connection pattern CB2 is extended from each of the third channel hole CHc and the fourth channel hole CHd, and has a structure for connecting the third and fourth channel holes CHc and CHd.

[0071] The first and second channel holes CHa and CHb of the first channel structure CHS1 and the third and fourth channel holes CHc and CHd of the second channel structure CHS2 are sequentially arranged in a zigzag pattern in the second direction (Y direction). The first connection patterns CB1 of the first channel structures CHS1 and the second connection patterns CB2 of the second channel structures CHS2 are spaced apart in the second direction (Y direction).

[0072] The semiconductor device 100a further includes first, second, third, and fourth conductive wirings (BLa, BLb, BLc, BLd) arranged in a cell array region (e.g., cell array region R1) and connected to the first, second, third, and fourth channel holes (CHa, CHb, CHc, CHd), respectively. The first, second, third, and fourth conductive lines (BLa, BLb, BLc, BLd) extend in the second direction (Y direction) and are spaced apart from each other in the first direction (X direction). The first conductive wiring BLa overlaps the first channel hole CHa of the first channel structure CHS1 in the vertical direction (Z direction) and is connected to the first channel hole CHa via the first contact pad BTa. The second conductive wiring BLb overlaps the third channel hole CHc of the second channel structure CHS2 in the vertical direction (Z direction) and is connected to the third channel hole CHc via the third contact pad BTc. The third conductive wiring BLc overlaps the second channel hole CHb of the first channel structure CHS1 in the vertical direction (Z direction) and is connected to the second channel hole CHb via the second contact pad BTb. The fourth conductive wiring BLd overlaps the fourth channel hole CHd of the second channel structure CHS2 in the vertical direction (Z direction) and is connected to the fourth channel hole CHd via a fourth contact pad BTd. The first, second, third, and fourth conductive lines (BLa, BLb, BLc, BLd) correspond to the bit lines BL in FIG.

[0073] The semiconductor device 100a further includes a first conductive pattern 101 arranged on the first page region P1 and a second conductive pattern 102 arranged on the second page region P2. In one example, the first conductive pattern 101 and the second conductive pattern 102 extend in a first direction (X direction) and are spaced apart in a second direction (Y direction). The first conductive pattern 101 is on the first channel structure CH1 and overlaps at least a portion of the first channel structure CH1''. The second conductive pattern 102 is on the second channel structure CH2″ and overlaps at least a portion of the second channel structure CH2. In one example, the first conductive pattern 101 overlaps with the second channel hole CHb of the first channel structure CHS1 and the third channel hole CHc of the second channel structure CHS2 of the first channel structure CH1''. The first conductive pattern 101 does not overlap with the first channel hole CHa of the first channel structure CHS1 of the first channel structure CH1'' and the fourth channel hole CHd of the second channel structure CHS2.

[0074] The first conductive pattern 101 contacts a part of the first connection pattern CB1 of the first channel structure CHS1 of the first channel structure CH1'' and a part of the second connection pattern CB2 of the second channel structure CHS2. The second conductive pattern 102 overlaps with the second channel hole CHb of the first channel structure CHS1 of the second channel structure CH2'' and the third channel hole CHc of the second channel structure CHS2. The second conductive pattern 102 does not overlap with the first channel hole CHa of the first channel structure CHS1 of the first channel structure CH1'' and the fourth channel hole CHd of the second channel structure CHS2. The second conductive pattern 102 contacts a part of the first connection pattern CB1 of the first channel structure CHS1 of the second channel structure CH2'' and a part of the second connection pattern CB2 of the second channel structure CHS2. The first and second conductive patterns (101, 102) do not overlap the first channel hole CHa and the fourth channel hole CHd.

[0075] Referring to FIG. 10, a third channel structure CH3 is disposed in a first page region P1 of the semiconductor device 100b, and a fourth channel structure CH4 is disposed in a second page region P2. Each of the third channel structure CH3 and the fourth channel structure CH4 includes a channel structure CHS''. The channel structure CHS'' includes a plurality of channel structures (CHSa, CHSb) and a plurality of connection patterns (CBa, CBb, CBc) that connect the plurality of channel structures (CHSa, CHSb). The channel structure CHS" has a mesh pattern.

[0076] Each of the plurality of channel structures (CHSa, CHSb) corresponds to each of the channel structures CHS in FIG. That is, each of the plurality of channel structures (CHSa, CHSb) includes first to fourth channel holes (CHa to CHd) and a connection pattern CB that connects the first to fourth channel holes (CHa to CHd). The multiple connection patterns (CBa, CBb, CBc) to be connected include a (1-1) connection pattern CBa that connects the first channel hole CHa of the channel structure CHSa and the second channel hole CHb of the channel structure CHSb, a (1-2) connection pattern CBb that connects the third channel hole CHc of the channel structure CHSa and the second channel hole CHb of the channel structure CHSb, and a (1-3) connection pattern CBc that connects the third channel hole CHc of the channel structure CHSa and the fourth channel hole CHd of the channel structure CHSb.

[0077] The semiconductor device 100b further includes a first conductive pattern 101 arranged on the first page region P1 and a second conductive pattern 102 arranged on the second page region P2. In one example, the first conductive pattern 101 and the second conductive pattern 102 extend in a first direction (X direction) and are spaced apart in a second direction (Y direction). The first conductive pattern 101 is on the third channel structure CH3 and overlaps at least a portion of the third channel structure CH3. The second conductive pattern 102 is on the fourth channel structure CH4 and overlaps at least a portion of the fourth channel structure CH4. In one example, the first conductive pattern 101 overlaps with the second and third channel holes (CHb, CHc) of the channel structure CHS" of the third channel structure CH3, but does not overlap with the first and fourth channel holes (CHa, CHd) of the channel structure CHS" of the third channel structure CH3. The second conductive pattern 102 overlaps with the second and third channel holes (CHb, CHc) of the channel structure CHS" of the fourth channel structure CH4, but does not overlap with the first and fourth channel holes (CHa, CHd) of the channel structure CHS" of the fourth channel structure CH4.

[0078] 11 to 21 are diagrams illustrating a method for manufacturing a semiconductor device according to an embodiment of the present invention. 11 to 21, (a) of FIG. 11, (a) of FIG. 12, (a) of FIG. 13, (a) of FIG. 14, (a) of FIG. 15, (a) of FIG. 16, (a) of FIG. 17, (a) of FIG. 18, (a) of FIG. 19, (a) of FIG. 20, and (a) of FIG. 21 show XY plan views of a cell array region (e.g., cell array region R1 of FIG. 3), and (b) of FIG. 11, (b) of FIG. 12, (b) of FIG. 13, (b) of FIG. 14, (b) of FIG. 15, (b) of FIG. 16, (b) of FIG. 17, (b) of FIG. 18, (b) of FIG. 19, (b) of FIG. 20, and (b) of FIG. 21 show cross sections taken along line III-III' of the cell array region.

[0079] 11(a) and 11(b), first to fourth auxiliary channel holes (CHa_P to CHd_P) are formed alternately in a second direction (Y direction) on the XY plane of the auxiliary semiconductor substrate 10, and an auxiliary connection pattern (CB_P) connecting the first to fourth auxiliary channel holes (CHa_P to CHd_P) is formed. The first to fourth auxiliary channel holes (CHa_P to CHd_P) and the auxiliary connection pattern (CB_P) are formed in regions corresponding to the positions of the channel structures (CHS11, CHS12) of the first channel structure CH1 and the channel structures (CHS21, CHS22) of the second channel structure CH2, which will be formed in a subsequent process.

[0080] The channel structures (CHS11, CHS12) of the first channel structure CH1 and the channel structures (CHS21, CHS22) of the second channel structure CH2 formed in a subsequent process are spaced apart in the second direction (Y direction), and accordingly, the positions where the first to fourth auxiliary channel holes (CHa_P to CHd_P) and the auxiliary connection pattern (CB_P) are formed are determined. The channel structures (CHS11, CHS12) of the first channel structure CH1 and the channel structures (CHS21, CHS22) of the second channel structure CH2 each correspond to the channel structure CHS in FIG.

[0081] The first to fourth preliminary channel holes (CHa_P to CHd_P) and the preliminary connection pattern (CB_P) are formed by etching a part of the upper surface of the preliminary semiconductor substrate 10 through an etch-back process. The first to fourth preliminary channel holes (CHa_P to CHd_P) and the preliminary connection pattern (CB_P) are formed by a wet or dry etching process.

[0082] A first opening OPN1 is formed on the XY plane of the spare semiconductor substrate 10 in correspondence with the first to fourth spare channel holes (CHa_P to CHd_P), and a second opening OPN2 that connects the first opening OPN1 is formed on the XY plane of the spare semiconductor substrate 10 in correspondence with the spare connection pattern (CB_P). The second opening portion OPN2 extends toward the first opening portion OPN1 in which the first to fourth auxiliary channel holes (CHa_P to CHd_P) are formed between the first to fourth auxiliary channel holes (CHa_P to CHd_P).

[0083] Referring to (a) and (b) of FIG. 12, the first to fourth preliminary channel holes (CHa_P to CHd_P) and the preliminary connection pattern (CB_P) are filled with a sacrificial material SCF. The sacrificial material SCF may include polycrystalline silicon.

[0084] Referring to (a) and (b) of Figures 13, a plurality of mold sacrificial films 13 and a plurality of interlayer insulating layers 120 are alternately formed on a preliminary semiconductor substrate 10, and first to fourth channel holes (CHa to CHd) are formed through the plurality of mold sacrificial films 13 and the plurality of interlayer insulating layers 120, and connected to the first to fourth preliminary channel holes (CHa_P to CHd_P). The plurality of mold sacrificial layers 13 include a material having an etching selectivity with respect to the plurality of interlayer insulating layers 120 .

[0085] In one example, the plurality of mold sacrificial films 13 include silicon nitride, and the plurality of interlayer insulating layers 120 include silicon oxide. By forming the first to fourth channel holes (CHa to CHd) that penetrate the plurality of mold sacrificial films 13 and the plurality of interlayer insulating layers 120, the first to fourth preliminary channel holes (CHa_P to CHd_P) on the preliminary semiconductor substrate 10 are exposed. The first to fourth channel holes (CHa to CHd) are formed by forming a hard mask pattern on the plurality of mold sacrificial films 13 and the plurality of interlayer insulating layers 120, and anisotropically etching the plurality of mold sacrificial films 13 and the plurality of interlayer insulating layers 120 using the hard mask pattern as an etching mask, thereby forming the first to fourth channel holes (CHa to CHd) extending in the third direction (Z direction).

[0086] Referring to (a) and (b) of Figures 14, preliminary information storage patterns (141P, 142P, 143P), a channel pattern 140, and a channel-buried insulating layer 147 are sequentially formed within the first to fourth channel holes (CHa to CHd), the first to fourth spare channel holes (CHa_P to CHd_P), and the spare connection pattern (CB_P). The preliminary information storage patterns (141P, 142P, 143P), channel pattern 140, and channel-buried insulating layer 147 are formed with a uniform thickness on the bottom surfaces of the first to fourth preliminary channel holes (CHa_P to CHd_P) and preliminary connection patterns (CB_P) and on the sidewalls of the first to fourth channel holes (CHa to CHd).

[0087] The data storage layer 142P may include silicon nitride or metal oxide, which is a material capable of trapping charges, and the blocking layer 141P and the tunneling layer 143P may be made of silicon oxide or metal oxide. Here, metal oxide is a material having a higher dielectric constant than silicon nitride. The preliminary information storage patterns (141P, 142P, 143P), the channel pattern 140, and the channel-buried insulating layer 147 can be formed by a chemical vapor deposition (CVD) or atomic layer deposition (ALD) process. The enlarged view shown in FIG. 14(a) shows a cross section of a region where the auxiliary connection pattern (CB_P) that connects the first to fourth auxiliary channel holes (CHa_P to CHd_P) in FIG. 11(a) is arranged.

[0088] Referring to (a) and (b) of Figure 15, the method includes the steps of forming a channel pad 149 on each of the first to fourth channel holes (CHa to CHd), removing a plurality of mold sacrificial films 13 to form a gate electrode 130, and forming a contact plug 174, wiring lines 172, 180, a cell region insulating layer 190, a second bonding metal layer 198, and a second bonding insulating layer 199.

[0089] After the preliminary information storage patterns (141P, 142P, 143P), the channel pattern 140, and the channel-buried insulating layer 147 are formed in sequence, a channel pad 149 is formed on the first to fourth channel holes (CHa to CHd). The channel pads 149 are formed by forming a mask pattern on the first to fourth channel holes (CHa to CHd) and using the mask pattern. The channel pad 149 includes a conductive material and may include, for example, polycrystalline silicon. After forming the channel pad 149, the method further includes forming studs (171b, 171d, 172a, 172b) on the channel pad 149 and forming conductive lines (BLa, BLc, BLd) connected to the studs (171b, 171d, 172a, 172b).

[0090] In one example, a second stud 171b is formed on the channel pad 149 of the second channel hole CHb of the first channel structure CH1, and a fourth stud 171d is formed on the channel pad 149 of the fourth channel hole CHd of the first channel structure CH1. A second stud 172a is formed on the channel pad 149 of the first channel hole CHa of the second channel structure CH2, and a second stud 172b is formed on the channel pad 149 of the second channel hole CHb of the second channel structure CH2. A third conductive wiring BLc is formed on the second stud 171b of the first channel structure CH1 and the second stud 172b of the second channel structure CH2, a fourth conductive wiring BLd is formed on the fourth stud 171d of the first channel structure CH1, and a first conductive wiring BLa is formed on the first stud 172a of the second channel structure CH2.

[0091] The plurality of mold sacrificial films 13 are removed, and a conductive material is deposited in the removed areas to form the gate electrode 130 . The conductive material may include a metal, polycrystalline silicon, or metal silicide material. Contact plugs 174 and wiring lines 172 are formed in the cell region insulating layer 190 . A second bonding metal layer 198, which is a cell bonding structure, is formed on the cell region insulating layer 190, and a second bonding insulating layer 199 is formed to surround the second bonding metal layer 198. Cell bonding structures 198 and 199 are formed on the cell region insulating layer 190 to form a spare memory cell structure CELL_P.

[0092] Referring to FIGS. 16(a) and 16(b), the spare memory cell structure CELL_P is turned upside down and brought into contact with the peripheral circuit structure PERI. The peripheral circuit structure PERI can be formed in advance prior to the formation of the spare memory cell structure (CELL_P). The peripheral circuit structure PERI can be formed prior to the manufacturing process of the memory cell structure CELL, or can be formed after the manufacturing process of the spare memory cell structure CELL_P.

[0093] A peripheral circuit structure PERI is fabricated by forming a substrate 201, circuit elements 220 on the substrate 201, circuit contact plugs 270, circuit wiring lines 280, a peripheral region insulating layer 290, and peripheral bonding structures. The spare memory cell structure CELL_P and the peripheral circuit structure PERI are connected by bonding using pressure applied to the first bonding insulating layer 299, the second bonding insulating layer 199, the first bonding metal layer 298, and the second bonding metal layer 198.

[0094] Referring to (a) and (b) of FIG. 17, the spare semiconductor substrate 10 is removed. By removing the spare semiconductor substrate 10, the spare information storage patterns (141P, 142P, 143P) exposed from the first to fourth channel holes (CHa to CHd) are exposed to the outside. In one example, the insides of the first to fourth spare channel holes (e.g., the first to fourth spare channel holes (CHa_P to CHd_P) in Figure 13) and the spare connection pattern (CB_P) (e.g., the spare connection pattern (CB_P) in Figure 13) on one surface of the spare semiconductor substrate 10 are filled, and the spare information storage patterns (141P, 142P, 143P) surrounding the channel pattern 140 are exposed to the outside. Due to the difference in etching rate between the material constituting the preliminary semiconductor substrate 10 and the material of the preliminary information storage patterns (141P, 142P, 143P), the preliminary semiconductor substrate 10 in contact with the blocking layer 141P is removed by a wet etching process.

[0095] Referring to (a) and (b) of FIG. 18, the preliminary information storage patterns (141P, 142P, 143P) exposed from the first to fourth channel holes (CHa to CHd) are removed. Information storage patterns (141, 142, 143) are formed to be disposed only in the first to fourth channel holes (CHa to CHd). By removing the preliminary information storage patterns (141P, 142P, 143P) exposed from the first to fourth channel holes (CHa to CHd), the channel patterns 140 extended from the first to fourth channel holes (CHa to CHd) are exposed.

[0096] Referring to (a) and (b) of FIG. 19, a conductive liner 148 is formed to cover the channel pattern 140 exposed from the first to fourth channel holes (CHa to CHd). The conductive liner 148 is formed uniformly along the surface profile of the channel pattern 140 exposed from the first to fourth channel holes (CHa to CHd). The conductive liner 148 covers the extension portion (for example, the extension portion 140b in FIG. 5B) and the main portion (for example, the main portion 140c in FIG. 5B) of the channel pattern 140. The conductive liner 148 comprises a semiconductor material such as polycrystalline silicon or single crystal silicon. The conductive liner 148 includes an impurity region containing a first impurity, which may include at least one of phosphorus (P), arsenic (As), and antimony (Sb) as an n-type impurity. The conductive liner 148 is formed by an area selective deposition (ASD) process. In other embodiments, the process step of forming the conductive liner 148 may be omitted.

[0097] Referring to (a) and (b) of Figure 20, for each of the first and second channel structures (CH1, CH2), a mask pattern M is formed on the first to fourth channel holes (CHa to CHd) having an open portion OP that exposes the second and third channel holes (CHb, CHc) and a non-open portion UOP that covers the first and fourth channel holes (CHa, CHd). The mask pattern M defines an area where the first and second conductive patterns (for example, the first and second conductive patterns (101, 102) in FIG. 21) are to be disposed. The mask pattern M includes amorphous carbon or polysilicon. A mask pattern M extending in a first direction (X direction) is formed on the first channel structure CH1 formed in the first page region P1 and the second channel structure CH2 formed in the second page region P2. Forming the mask pattern M involves forming a photoresist film (not shown) and performing a photo process and an etching process.

[0098] Referring to (a) and (b) of Figure 21, for each of the first and second channel structures (CH1, CH2), first and second conductive patterns (101, 102) are formed on the open portion OP of the mask pattern M that exposes the second and third channel holes (CHb, CHc). By forming the first and second conductive patterns (101, 102) through the mask pattern M, the first conductive pattern 101 contacts the conductive liner 148 exposed from the second and third channel holes (CHb, CHc) of the first channel structure CH1, and the second conductive pattern 102 contacts the conductive liner 148 exposed from the second and third channel holes (CHb, CHc) of the second channel structure CH2. This causes the first conductive pattern 101 to be self-aligned with respect to the first channel structure CH1, and the second conductive pattern 102 to be self-aligned with respect to the second channel structure CH2. The first conductive pattern 101 overlaps in a third direction (Z direction) that is perpendicular to at least two or more adjacent channel holes among the first to fourth channel holes (CHa to CHd) of the first channel structure CH1, and similarly, the second conductive pattern 102 overlaps in the third direction (Z direction) that is perpendicular to at least two or more adjacent channel holes among the first to fourth channel holes (CHa to CHd) of the second channel structure CH2.

[0099] After removing the mask pattern M, an insulating pattern 105 is formed between the first and second conductive patterns (101, 102). The insulating pattern 105 overlaps the first and fourth channel holes CHa and CHd. Thereafter, a passivation layer 106 is formed on the first and second conductive patterns (101, 102) and the insulating pattern 105, thereby forming the semiconductor device 100'. In another example, if the process step of forming the conductive liner 148 is omitted, the first conductive pattern 101 contacts the channel pattern 140 exposed from the second and third channel holes (CHb, CHc) of the first channel structure CH1, and the second conductive pattern 102 contacts the channel pattern 140 exposed from the second and third channel holes (CHb, CHc) of the second channel structure CH2. In this case, after the process of forming the first and second conductive patterns (101, 102) and the insulating pattern 105, the semiconductor device 100 is formed by forming a passivation layer 106 on the first and second conductive patterns (101, 102) and the insulating pattern 105.

[0100] FIG. 22 is a diagram showing a schematic configuration of a data storage system including a semiconductor device according to an embodiment of the present invention. Referring to FIG. 22, an electronic system 1000 according to an embodiment of the present invention includes a semiconductor device 1100 and a controller 1200 electrically connected to the semiconductor device 1100. The electronic system 1000 may be a storage device including one or more semiconductor devices 1100 or an electronic device including a storage device. For example, the electronic system 1000 may be a solid state drive device (SSD device), a Universal Serial Bus (USB), a computing system, a medical device, or a communications device that includes one or more semiconductor devices 1100.

[0101] The semiconductor device 1100 may be a non-volatile memory device, such as the NAND flash memory device described above with reference to FIGS. The semiconductor device 1100 includes a first structure 1100F and a second structure 1100S on the first structure 1100F. In the exemplary embodiment, a first structure 1100F is positioned next to a second structure 1100S. The first structure 1100F is a peripheral circuit structure including a decoder circuit 1110, a page buffer 1120, and a logic circuit 1130. The second structure 1100S is a memory cell structure including a bit line BL, a common source line CSL, a word line WL, first and second gate upper lines (UL1, UL2), first and second gate lower lines (LL1, LL2), and a memory cell string CSTR between the bit line BL and the common source line CSL.

[0102] In the second structure 1100S, each memory cell string CSTR includes a lower transistor (LT1, LT2) adjacent to a common source line CSL, an upper transistor (UT1, UT2) adjacent to a bit line BL, and multiple memory cell transistors MCT arranged between the lower transistor (LT1, LT2) and the upper transistor (UT1, UT2). The number of lower transistors (LT1, LT2) and the number of upper transistors (UT1, UT2) may be variously changed according to the embodiment. In an exemplary embodiment, the upper transistors (UT1, UT2) comprise string select transistors and the lower transistors (LT1, LT2) comprise ground select transistors. The lower gate lines (LL1, LL2) are the gate electrodes of the lower transistors (LT1, LT2), respectively. The word line WL may be a gate electrode of the memory cell transistor MCT, and the gate upper lines (UL1, UL2) may be gate electrodes of the upper transistors (UT1, UT2), respectively.

[0103] In an exemplary embodiment, the bottom transistors (LT1, LT2) include a series-connected bottom erase control transistor LT1 and a ground select transistor LT2. The upper transistors (UT1, UT2) include a series-connected string select transistor UT1 and an upper erase control transistor UT2. At least one of the lower erase control transistor LT1 and the upper erase control transistor UT2 is used for an erase operation that erases data stored in the memory cell transistor MCT by utilizing a gate-induced drain leakage (GIDL) phenomenon.

[0104] The common source line CSL, the first and second gate lower lines (LL1, LL2), the word line WL, and the first and second gate upper lines (UL1, UL2) are electrically connected to the decoder circuit 1110 via a first connection wiring 1115 extending from within the first structure 1100F to the second structure 1100S. The bit line BL is electrically connected to the page buffer 1120 via a second connection wiring 1125 extending from within the first structure 1100F to the second structure 1100S.

[0105] In the first structure 1100F, a decoder circuit 1110 and a page buffer 1120 perform a control operation on at least one selected memory cell transistor among the plurality of memory cell transistors MCT. The decoder circuit 1110 and the page buffer 1120 are controlled by a logic circuit 1130 . The semiconductor device 1100 communicates with the controller 1200 via an input / output pad 1101 electrically connected to the logic circuit 1130 . The input / output pads 1101 are electrically connected to the logic circuit 1130 via input / output connection wiring 1135 that extends from within the first structure 1100F to the second structure 1100S.

[0106] The controller 1200 includes a processor 1210, a NAND controller 1220, and a host interface 1230. Depending on the embodiment, the electronic system 1000 may include multiple semiconductor devices 1100, in which case the controller 1200 controls the multiple semiconductor devices 1100. The processor 1210 controls the overall operation of the electronic system 1000 , including the controller 1200 . The processor 1210 operates according to predetermined firmware and controls the NAND controller 1220 to access the semiconductor device 1100 .

[0107] The NAND controller 1220 includes a controller interface 1221 that handles communication with the semiconductor device 1100 . Control commands for controlling the semiconductor device 1100, data to be recorded in the memory cell transistor MCT of the semiconductor device 1100, data to be read from the memory cell transistor MCT of the semiconductor device 1100, etc. are transferred via the controller interface 1221. The host interface 1230 provides communication between the electronic system 1000 and an external host. When a control command is received from an external host via the host interface 1230, the processor 1210 controls the semiconductor device 1100 in response to the control command.

[0108] FIG. 23 is a perspective view showing a schematic configuration of a data storage system including a semiconductor device according to an embodiment of the present invention. Referring to FIG. 23, an electronic system 2000 according to an embodiment of the present invention includes a main board 2001, a controller 2002 mounted on the main board 2001, one or more semiconductor packages 2003, and a DRAM 2004. The semiconductor package 2003 and the DRAM 2004 are connected to the controller 2002 by a wiring pattern 2005 formed on the main board 2001 .

[0109] The main board 2001 includes a connector 2006 including a plurality of pins that are coupled to an external host. In the connector 2006, the number and arrangement of the multiple pins can be changed depending on the communication interface between the electronic system 2000 and an external host. In an exemplary embodiment, electronic system 2000 communicates with an external host according to any of the following interfaces: Universal Serial Bus (USB), Peripheral Component Interconnect Express (PCI-Express), Serial Advanced Technology Attachment (SATA), M-Phy for Universal Flash Storage (UFS), etc. In the exemplary embodiment, electronic system 2000 operates from power supplied by an external host via connector 2006 . The electronic system 2000 may further include a PMIC (Power Management Integrated Circuit) that distributes power supplied from an external host to the controller 2002 and the semiconductor package 2003.

[0110] The controller 2002 can write data to or read data from the semiconductor package 2003 to improve the operating speed of the electronic system 2000 . The DRAM 2004 may be a buffer memory for reducing the speed difference between the semiconductor package 2003, which is a data storage space, and the external host. The DRAM 2004 included in the electronic system 2000 can also function as a kind of cache memory, and can provide space for temporarily storing data during control operations for the semiconductor package 2003. If the electronic system 2000 includes a DRAM 2004 , the controller 2002 may further include a DRAM controller for controlling the DRAM 2004 in addition to the NAND controller for controlling the semiconductor package 2003 .

[0111] The semiconductor package 2003 includes first and second semiconductor packages (2003a, 2003b) spaced apart from each other. The first and second semiconductor packages (2003a, 2003b) are semiconductor packages each including a plurality of semiconductor chips 2200. Each of the first and second semiconductor packages (2003a, 2003b) includes a package substrate 2100, a semiconductor chip 2200 on the package substrate 2100, an adhesive layer 2300 disposed on the lower surface of each of the semiconductor chips 2200, a connection structure 2400 that electrically connects the semiconductor chip 2200 and the package substrate 2100, and a molding layer 2500 that covers the semiconductor chip 2200 and the connection structure 2400 on the package substrate 2100.

[0112] The package substrate 2100 may be a printed circuit board that includes package top pads 2130 . Each semiconductor chip 2200 includes input / output pads 2210 . The input / output pad 2210 corresponds to the input / output pad 1101 in FIG. Each of the semiconductor chips 2200 includes a gate electrode 3210 and a memory channel structure 3220 . Each of the semiconductor chips 2200 may include the semiconductor device described above with reference to FIGS.

[0113] In an exemplary embodiment, the connection structure 2400 may be a bond wire that electrically connects the input / output pad 2210 and the package top pad 2130 . Therefore, in each of the first and second semiconductor packages (2003a, 2003b), the semiconductor chips 2200 are electrically connected to each other by bonding wires and to the upper package pads 2130 of the package substrate 2100. According to an embodiment, in each of the first and second semiconductor packages (2003a, 2003b), the semiconductor chips 2200 may be electrically connected to each other by a connection structure including a through silicon via (TSV) instead of a bonding wire type connection structure 2400.

[0114] In an exemplary embodiment, the controller 2002 and the semiconductor chip 2200 may be included in a single package. In an exemplary embodiment, the controller 2002 and the semiconductor chip 2200 may be mounted on a separate interposer substrate different from the main substrate 2001, and the controller 2002 and the semiconductor chip 2200 may be connected to each other by wiring formed on the interposer substrate.

[0115] FIG. 24 is a cross-sectional view showing a schematic configuration of a semiconductor package according to an embodiment of the present invention. 24A and 24B illustrate exemplary embodiments of the semiconductor package 2003 of FIG. 23 and conceptually show a cross-sectional area of ​​the first semiconductor package 2003a of FIG. 23 taken along line IV-IV'. Referring to FIG. 24, in a first semiconductor package 2003a, a package substrate 2100 is a printed circuit board.

[0116] The package substrate 2100 includes a package substrate body 2120, package upper pads 2130 arranged on the upper surface of the package substrate body 2120, lower pads 2125 arranged on the lower surface of the package substrate body 2120 or exposed through the lower surface, and internal wiring 2135 electrically connecting the package upper pads 2130 and the lower pads 2125 inside the package substrate body 2120. The package top pad 2130 is electrically connected to the connection structure 2400 . The lower pad 2125 is connected to a wiring pattern 2005 on a main board 2001 of the electronic system 2000 as shown in FIG. 23 via a conductive connection 2800.

[0117] In the first semiconductor package 2003a, each of the semiconductor chips 2200a includes a semiconductor substrate 4010, a first structure 4100 on the semiconductor substrate 4010, and a second structure 4200 on the first structure 4100 and bonded to the first structure 4100 using a wafer bonding method. The first structure 4100 includes a peripheral circuit region including peripheral wiring 4110 and a first junction structure 4150 . The second structure 4200 includes a common source line 4205, a gate electrode 4210 between the common source line 4205 and the first structure 4100, a memory channel structure 4220 and an isolation structure 4230 penetrating the gate electrode 4210, and a second junction structure 4250 electrically connected to the word line (WL in FIG. 1) of the memory channel structure 4220 and the gate electrode 4210, respectively.

[0118] For example, the second junction structure 4250 is electrically connected to the memory channel structure 4220 and the word line (WL in FIG. 1) via a gate connection wiring (e.g., a channel contact plug 170 and / or a channel wiring line 180 in FIG. 5a) electrically connected to the bit line 4240 and the word line (WL in FIG. 1), respectively. The first joining structure 4150 of the first structure 4100 and the second joining structure 4250 of the second structure 4200 are joined together while being in contact with each other. The joined portions of the first joint structure 4150 and the second joint structure 4250 may be made of, for example, copper (Cu).

[0119] As shown in the enlarged view, the second structure 4200 further includes information storage patterns (141, 142, 143) in the channel holes (e.g., the first to fourth channel holes (CHa to CHd) in FIG. 6b), a channel pattern 140 that is surrounded and extended from the information storage patterns (141, 142, 143) in the channel holes and extends from the channel holes, and a channel-buried insulating layer 147 that is surrounded by the channel pattern 140. Each of the semiconductor chips 2200a further includes an input / output pad 2210 and an input / output connection wiring 4265 below the input / output pad 2210. The input / output connection wiring 4265 is electrically connected to a part of the second junction structure 4250 . The first semiconductor chips 2200a in FIG. 24 are electrically connected to each other by connection structures 2400 in the form of bonding wires. However, in an exemplary embodiment, semiconductor chips in one semiconductor package, such as the first semiconductor chip 2200a in FIG. 24, may also be electrically connected to each other by a connection structure including through-silicon vias TSVs.

[0120] The present invention is not limited to the above-described embodiment, and various modifications can be made without departing from the technical scope of the present invention. [Explanation of symbols]

[0121] 20 Memory Cell Array 30 Peripheral circuits 33 Low Decoder 35 page buffer 37 Control Logic 100 Semiconductor device 101, 102 First and second conductive patterns 105 Insulation Pattern 106 Passivation Layer 130 gate electrode 130L Upper gate electrode 130M memory gate electrode 130U Bottom gate electrode 140 Channel pattern 140a (1st to 4th) channel part 140b, 140c Channel connection part 141 Blocking Layer 142 Data Storage Layer 143 Tunneling Layer 149 Channel Pad 150 cell contacts 160 input / output contacts 170, 180 2nd wiring structure 171a~171d (1st~4th) Studs 172 Wiring Line 174 Contact plug 190 Cell area insulating layer 198 Second bonding metal layer 199 Second bonding insulating layer 201 Substrate 205 Impurity region 210 Element isolation region 220 Circuit Elements 222 Circuit gate dielectric layer 224 spacer layer 225 Circuit gate electrode 270 Circuit contact plug (first wiring structure) 280 Circuit wiring line (first wiring structure) 298 First bonding metal layer 299 First bonding insulating layer BLa, BLb, BLc, BLd (1st to 4th) conductive wiring BTa, BTb, BTc, BTd (1st to 4th) contact pads CB connection pattern CH Channel Structure CH1, CH2 (1st and 2nd) channel structures CHa, CHb, CHc, CHd (1st to 4th) channel holes CHS Channel structure DCH Dummy Channel Structure MS1, MS2, MS3 (1st to 3rd) separation structure

Claims

1. a first semiconductor structure including a substrate, a circuit element on the substrate, a first wiring structure electrically connected to the circuit element, and a first bonding metal layer on the circuit element and the first wiring structure; a second semiconductor structure on the first semiconductor structure and connected to the first semiconductor structure; The second semiconductor structure is a memory cell substrate including a conductive pattern and an insulating pattern in contact with a side surface of the conductive pattern; a plurality of gate electrodes stacked below the memory cell substrate and spaced apart from each other along a direction perpendicular to a lower surface of the memory cell substrate; a plurality of channel structures extending through the plurality of gate electrodes and extending along the vertical direction into the memory cell substrate, the channel structures being spaced apart from each other in a first direction intersecting the vertical direction; a second wiring structure disposed below the plurality of gate electrodes and the plurality of channel structures; a second bonding metal layer disposed under the second wiring structure and connected to the first bonding metal layer; Each of the plurality of channel structures comprises: a first channel hole passing through the plurality of gate electrodes in the perpendicular direction; a second channel hole that penetrates the plurality of gate electrodes in the perpendicular direction and is separated from the first channel hole; a first channel pattern including a first channel portion disposed in the first channel hole, a second channel portion disposed in the second channel hole, and a first channel connecting portion extending from the first channel portion and the second channel portion on the plurality of gate electrodes to connect the first channel portion and the second channel portion; The conductive pattern overlaps the second channel hole in the perpendicular direction, but does not overlap the first channel hole.

2. Each of the plurality of channel structures comprises: a first information storage pattern disposed within the first channel hole; a second information storage pattern disposed in the second channel hole; a channel-buried insulating layer surrounded by the first channel pattern, 2. The semiconductor device according to claim 1, wherein the first channel connection portion is exposed from the first and second information storage patterns.

3. 2. The semiconductor device of claim 1, further comprising: a first wiring extending in the perpendicular direction and a second direction intersecting the first direction and connected to the first channel hole; and a second wiring spaced apart from the first wiring in the first direction and connected to the second channel hole.

4. The conductive pattern extends in the first direction, 2. The semiconductor device according to claim 1, wherein a portion of the first channel connection portion of the first channel pattern is in contact with the conductive pattern, and the remaining other portion of the first channel connection portion of the first channel pattern is exposed from the conductive pattern.

5. Each of the plurality of channel structures comprises: a third channel hole passing through the plurality of gate electrodes in the perpendicular direction; a fourth channel hole that penetrates the plurality of gate electrodes in the perpendicular direction and is separated from the third channel hole; a second channel pattern including a third channel portion disposed in the third channel hole, a fourth channel portion disposed in the fourth channel hole, and a second channel connecting portion extending from the third channel portion and the fourth channel portion on the gate electrode to connect the first channel portion and the second channel portion, the third channel hole is spaced apart from the first channel hole in a direction perpendicular to the first direction and a second direction intersecting the first direction; the fourth channel hole is spaced apart from the second channel hole in the second direction; 2. The semiconductor device according to claim 1, wherein the conductive pattern overlaps the third channel hole in the perpendicular direction, but does not overlap the fourth channel hole.

6. The semiconductor device of claim 5 , wherein the first channel pattern and the second channel pattern are spaced apart in the second direction.

7. a first semiconductor structure including a substrate, a circuit element on the substrate, and a first wiring structure on the circuit element; a second semiconductor structure disposed on the first semiconductor structure; The second semiconductor structure is a memory cell substrate including a plurality of spaced apart conductive patterns; a plurality of gate electrodes stacked below the memory cell substrate and spaced apart from each other along a direction perpendicular to the lower surface of the memory cell substrate, the gate electrodes including an upper select gate electrode, a memory gate electrode, and a lower select gate electrode sequentially arranged from the lower surface of the memory cell substrate; first and second isolation structures extending through the plurality of gate electrodes in a first direction intersecting the perpendicular direction and spaced apart from each other in a second direction intersecting the first direction; first channel structures extending along the vertical direction between the first isolation structure and the second isolation structure, passing through the gate electrodes and spaced apart from each other in the first direction; a second channel structure extending along the vertical direction between the first isolation structure and the second isolation structure, penetrating the plurality of gate electrodes, and spaced apart from the first channel structure in the second direction; a second wiring structure disposed below the plurality of gate electrodes and the first and second channel structures, Each of the first channel structure and the second channel structure comprises: first to fourth channel holes that penetrate the plurality of gate electrodes in the perpendicular direction and are spaced apart from one another; first to fourth information storage patterns disposed in the first to fourth channel holes; a first channel pattern extending from within at least two of the first to fourth channel holes and exposed from the at least two channel holes on the upper select gate electrode; the plurality of conductive patterns include a first conductive pattern extending in the first direction and a second conductive pattern spaced apart from the first conductive pattern in the second direction; the first conductive pattern contacts a portion of the first channel pattern of each of the first channel structures; The semiconductor device, wherein the second conductive pattern contacts a portion of the first channel pattern of each of the second channel structures.

8. the first conductive pattern overlaps the second channel hole and the third channel hole of each of the first channel structures, but does not overlap the first channel hole and the fourth channel hole of each of the first channel structures; 8. The semiconductor device of claim 7, wherein the second conductive pattern overlaps the second channel hole and the third channel hole of each of the second channel structures, but does not overlap the first channel hole and the fourth channel hole of each of the second channel structures.

9. an insulating pattern disposed between the first conductive pattern and the second conductive pattern and extending in the first direction; The semiconductor device of claim 8 , wherein the insulating pattern contacts a portion of the first channel pattern of each of the first channel structures and a portion of the first channel pattern of each of the second channel structures.

10. a semiconductor storage device including a first semiconductor structure including a circuit element, a second semiconductor structure disposed on one surface of the first semiconductor structure, and an input / output pad electrically connected to the circuit element; a controller electrically connected to the semiconductor storage device via the input / output pad and controlling the semiconductor storage device; The second semiconductor structure is a memory cell substrate including a conductive pattern and an insulating pattern surrounding a side surface of the conductive pattern; a plurality of gate electrodes stacked below the memory cell substrate and spaced apart from each other along a direction perpendicular to a lower surface of the memory cell substrate; a plurality of channel structures extending along the vertical direction through the plurality of gate electrodes and spaced apart in a first direction intersecting the vertical direction; Each of the channel structures comprises: a first channel hole passing through the plurality of gate electrodes in the perpendicular direction; a second channel hole that penetrates the plurality of gate electrodes in the perpendicular direction and is separated from the first channel hole; a first information storage pattern disposed within the first channel hole; a second information storage pattern disposed in the second channel hole; a channel pattern including a first portion surrounded by the first information storage pattern and the second information storage pattern, a second portion extending from the first portion and exposed from the first information storage pattern and the second information storage pattern, and a third portion extending from the second portion and connecting the second portion, The data storage system, wherein the second portion of the channel pattern has a width that narrows from the bottom surface to the top surface.

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