Display device

Abstract

To provide a display device capable of suppressing deterioration in reliability.SOLUTION: According to an embodiment, a display device includes a substrate, an organic insulating layer disposed above the substrate, a lower electrode disposed above the organic insulating layer, a rib layer covering an end portion of the lower electrode and having a pixel opening overlapping the lower electrode, and an organic insulating layer covering the lower electrode through the pixel opening. A partition wall including an organic layer that emits light in response to application of a voltage, an upper electrode that covers the organic layer, and a lower portion disposed on the rib layer and an upper portion having an end portion protruding from a side surface of the lower portion, wherein the rib layer includes an upper layer in contact with the lower portion of the partition wall, a lower layer that covers an end portion of the lower electrode and is in contact with the lower electrode, an intermediate layer disposed between the upper layer and the lower layer, and an inclined surface that forms the pixel opening, A recess is formed in the inclined surface.SELECTED DRAWING: Figure 1

Description

[Technical Field]

[0001] FIELD An embodiment of the present invention relates to a display device. [Background technology]

[0002] In recent years, display devices that use organic light-emitting diodes (OLEDs) as display elements have come into practical use. Technology that can prevent a decrease in reliability is needed for such display devices. [Prior art documents] [Patent documents]

[0003] [Patent Document 1] U.S. Patent No. 1,161,0954 [Patent Document 2] US Patent Application Publication No. 2023 / 0263014 Summary of the Invention [Problem to be solved by the invention]

[0004] An object of the present invention is to provide a display device capable of suppressing a decrease in reliability. [Means for solving the problem]

[0005] Generally, according to an embodiment, a display device comprises a substrate, an organic insulating layer arranged above the substrate, a lower electrode arranged above the organic insulating layer, a rib layer covering an end of the lower electrode and having a pixel opening overlapping the lower electrode, an organic layer covering the lower electrode through the pixel opening and emitting light in response to application of a voltage, an upper electrode covering the organic layer, and a partition including a lower portion arranged on the rib layer and an upper portion having an end protruding from a side surface of the lower portion, wherein the rib layer comprises an upper layer in contact with the lower portion of the partition, a lower layer covering the end of the lower electrode and in contact with the lower electrode, an intermediate layer arranged between the upper layer and the lower layer, and an inclined surface forming the pixel opening, and the ends of the upper layer and the lower layer protrude beyond the end of the intermediate layer, thereby forming a recess in the inclined surface.

[0006] According to an embodiment, a display device includes a substrate, an organic insulating layer disposed above the substrate, a lower electrode disposed above the organic insulating layer, a rib layer covering an end of the lower electrode and having a pixel opening overlapping the lower electrode, an organic layer covering the lower electrode through the pixel opening and emitting light in response to application of a voltage, an upper electrode covering the organic layer, and a partition wall including a lower portion disposed on the rib layer and an upper portion having an end protruding from a side surface of the lower portion, and the rib layer is an upper layer in contact with the lower portion of the partition wall, and covers the end of the lower electrode and is disposed on a front surface of the partition wall. The pixel electrode includes a lower layer in contact with the lower electrode, an intermediate layer arranged between the upper layer and the lower layer, and an inclined surface that forms the pixel opening, and the intermediate layer includes a first intermediate layer in contact with the lower layer, a second intermediate layer in contact with the upper layer, and a third intermediate layer arranged between the first intermediate layer and the second intermediate layer, and a first recess is formed in the inclined surface by the ends of the lower layer and the third intermediate layer protruding beyond the end of the first intermediate layer, and a second recess is formed in the inclined surface by the ends of the upper layer and the third intermediate layer protruding beyond the end of the second intermediate layer. [Brief explanation of the drawings]

[0007] [Figure 1] FIG. 1 is a diagram showing an example of the configuration of a display device according to an embodiment. [Figure 2]FIG. 2 is a schematic plan view showing an example of a layout of sub-pixels. [Figure 3] FIG. 3 is a schematic cross-sectional view of the display device taken along line III-III in FIG. [Figure 4] FIG. 4 is a schematic cross-sectional view of the display device taken along line IV-IV in FIG. [Figure 5] FIG. 5 is a diagram showing an example of a layer structure that can be applied to the organic layer shown in FIG. [Figure 6] FIG. 6 is a schematic cross-sectional view of the display device taken along line VV in FIG. [Figure 7A] FIG. 7A is a schematic cross-sectional view showing a manufacturing process of a display device. [Figure 7B] FIG. 7B is a schematic cross-sectional view showing a manufacturing process of the display device. [Figure 7C] FIG. 7C is a schematic cross-sectional view showing a manufacturing process of the display device. [Figure 7D] FIG. 7D is a schematic cross-sectional view showing a manufacturing process of the display device. [Figure 7E] FIG. 7E is a schematic cross-sectional view showing a manufacturing process of the display device. [Figure 7F] FIG. 7F is a schematic cross-sectional view showing a manufacturing process of the display device. [Figure 8A] FIG. 8A is a schematic cross-sectional view showing a method for manufacturing a display device. [Figure 8B] FIG. 8B is a schematic cross-sectional view showing a method for manufacturing the display device. [Figure 8C] FIG. 8C is a schematic cross-sectional view showing a method for manufacturing the display device. [Figure 8D] FIG. 8D is a schematic cross-sectional view showing a method for manufacturing the display device. [Figure 8E] FIG. 8E is a schematic cross-sectional view showing a method for manufacturing the display device. [Figure 8F] FIG. 8F is a schematic cross-sectional view showing a method for manufacturing the display device. [Figure 9] FIG. 9 is a schematic cross-sectional view showing a manufacturing process of a display device. [Figure 10]FIG. 10 is a cross-sectional view showing a display device of a comparative example. [Figure 11] FIG. 11 is a cross-sectional view showing a display device of a comparative example. [Figure 12] FIG. 12 is a schematic cross-sectional view showing another example of the configuration of the display device shown in FIG. DETAILED DESCRIPTION OF THE INVENTION

[0008] An embodiment will be described with reference to the drawings. The disclosure is merely an example, and appropriate modifications that a person skilled in the art can easily make while maintaining the gist of the invention are naturally included within the scope of the present invention. Furthermore, the drawings may be schematic in terms of the width, thickness, shape, etc. of each part compared to the actual embodiment for the sake of clarity, but these are merely examples and are not intended to limit the interpretation of the present invention. Furthermore, in this specification and each drawing, components that perform the same or similar functions as those described above with reference to the previous drawings are designated by the same reference numerals, and redundant detailed descriptions may be omitted as appropriate.

[0009] In the drawings, mutually orthogonal X, Y, and Z axes are shown as necessary to facilitate understanding. The direction along the X axis is referred to as the X direction, the direction along the Y axis is referred to as the Y direction, and the direction along the Z axis is referred to as the Z direction. The Z direction is the normal direction of a plane including the X and Y directions. Viewing various elements parallel to the Z direction is referred to as planar view.

[0010] The display device according to this embodiment is an organic electroluminescence display device that includes an organic light-emitting diode (OLED) as a display element, and can be installed in various electronic devices such as televisions, personal computers, in-vehicle devices, tablet devices, smartphones, mobile phone devices, and wearable devices.

[0011] FIG. 1 is a diagram showing an example of the configuration of a display device DSP according to an embodiment.

[0012] The display device DSP includes an insulating substrate 10. The substrate 10 has a display area DA for displaying an image and a peripheral area SA around the display area DA. The substrate 10 may be made of glass or a flexible resin film.

[0013] In this embodiment, the shape of the substrate 10 in plan view is rectangular. However, the shape of the substrate 10 in plan view is not limited to rectangular, and may be other shapes such as square, circular, or elliptical.

[0014] The display area DA includes a plurality of pixels PX arranged in a matrix in the first direction X and the second direction Y. Each pixel PX includes a plurality of subpixels SP that display different colors. In this embodiment, it is assumed that the pixel PX includes a blue subpixel SP1 (first subpixel), a green subpixel SP2 (second subpixel), and a red subpixel SP3 (third subpixel). However, the pixel PX may include subpixels SP of other colors, such as white, in addition to or instead of the subpixels SP1, SP2, and SP3.

[0015] The subpixel SP includes a pixel circuit 1 and a display element DE driven by the pixel circuit 1. The pixel circuit 1 includes a pixel switch 2, a drive transistor 3, and a capacitor 4. The pixel switch 2 and the drive transistor 3 are switching elements formed of, for example, thin film transistors.

[0016] In the display area DA, there are arranged a plurality of scanning lines GL that supply scanning signals to the pixel circuits 1 of each subpixel SP, a plurality of signal lines SL that supply video signals to the pixel circuits 1 of each subpixel SP, and a plurality of power supply lines PL. In the example of Fig. 1, the scanning lines GL and the power supply lines PL extend in the X direction, and the signal lines SL extend in the Y direction.

[0017] The gate electrode of the pixel switch 2 is connected to the scanning line GL. The source electrode of the pixel switch 2 is connected to the signal line SL. The drain electrode of the pixel switch 2 is connected to the gate electrode of the drive transistor 3 and the capacitor 4. The source electrode of the drive transistor 3 is connected to the power line PL and the capacitor 4. The drain electrode of the drive transistor 3 is connected to the display element DE.

[0018] The configuration of the pixel circuit 1 is not limited to the example shown in the drawing. For example, the pixel circuit 1 may include more thin film transistors and capacitors.

[0019] The display element DE is an organic light-emitting diode (OLED) as a light-emitting element, and may be called an organic EL element.

[0020] FIG. 2 is a schematic plan view showing an example of the layout of the subpixels SP1, SP2, and SP3.

[0021] 2, the subpixels SP2 and SP3 are aligned with the subpixel SP1 in the X direction, and the subpixels SP2 and SP3 are aligned with each other in the Y direction.

[0022] When the subpixels SP1, SP2, and SP3 are laid out in this manner, the display area DA is formed with columns in which the subpixels SP2 and SP3 are alternately arranged in the Y direction, and columns in which multiple subpixels SP1 are repeatedly arranged in the Y direction. These columns are arranged alternately in the X direction. Note that the layout of the subpixels SP1, SP2, and SP3 is not limited to the example in FIG. 2.

[0023] A rib layer 5 is disposed in the display area DA. The rib layer 5 has pixel openings AP1, AP2, and AP3 in the subpixels SP1, SP2, and SP3, respectively. In the example of FIG. 2, the pixel opening AP1 is larger than the pixel opening AP2, and the pixel opening AP2 is larger than the pixel opening AP3. That is, among the subpixels SP1, SP2, and SP3, the subpixel SP1 has the largest aperture ratio and the subpixel SP3 has the smallest aperture ratio. Note that the sizes of the pixel openings AP1, AP2, and AP3 are not limited to this example. For example, at least two of the pixel openings AP1, AP2, and AP3 may have the same size.

[0024] Subpixel SP1 includes a lower electrode LE1, an upper electrode UE1, and an organic layer OR1 that overlap with pixel aperture AP1. Subpixel SP2 includes a lower electrode LE2, an upper electrode UE2, and an organic layer OR2 that overlap with pixel aperture AP2. Subpixel SP3 includes a lower electrode LE3, an upper electrode UE3, and an organic layer OR3 that overlap with pixel aperture AP3.

[0025] The portions of the lower electrode LE1, upper electrode UE1, and organic layer OR1 that overlap with the pixel aperture AP1 constitute the display element DE1 of the subpixel SP1. The portions of the lower electrode LE2, upper electrode UE2, and organic layer OR2 that overlap with the pixel aperture AP2 constitute the display element DE2 of the subpixel SP2. The portions of the lower electrode LE3, upper electrode UE3, and organic layer OR3 that overlap with the pixel aperture AP3 constitute the display element DE3 of the subpixel SP3. The display elements DE1, DE2, and DE3 may further include a cap layer, which will be described later. The rib layer 5 surrounds each of these display elements DE1, DE2, and DE3.

[0026] Partition walls 6 are arranged in the display area DA. The partition walls 6 are located above the rib layer 5 and entirely overlap the rib layer 5. In the example of FIG. 2, the partition walls 6 have the same planar shape as the rib layer 5. That is, the partition walls 6 have openings in each of the subpixels SP1, SP2, and SP3. From another perspective, the rib layer 5 and the partition walls 6 have a lattice shape in a planar view and surround each of the display elements DE1, DE2, and DE3. The partition walls 6 serve as wiring that supplies a common voltage to the upper electrodes UE1, UE2, and UE3.

[0027] The lower electrodes LE1, LE2, and LE3 are connected to the pixel circuits 1 (more specifically, the drain electrodes of the driving transistors 3 shown in FIG. 1 ) of the subpixels SP1, SP2, and SP3, respectively, through contact holes (not shown) provided in the organic insulating layer 12, which will be described later. All of the contact holes overlap with the rib layer 5 and the partition wall 6.

[0028] 3 is a schematic cross-sectional view of the display device DSP taken along line III-III in FIG. 2. A circuit layer 11 is disposed on the above-described substrate 10. The circuit layer 11 includes various circuits and wirings such as the pixel circuits 1, scanning lines GL, signal lines SL, and power supply lines PL shown in FIG. 1. The circuit layer 11 is covered with an organic insulating layer 12. The organic insulating layer 12 functions as a planarizing film that flattens unevenness caused by the circuit layer 11.

[0029] The lower electrodes LE1, LE2, and LE3 are disposed on the organic insulating layer 12. The rib layer 5 is disposed on the organic insulating layer 12 and the lower electrodes LE1, LE2, and LE3. The ends of the lower electrodes LE1, LE2, and LE3 are all covered with the rib layer 5.

[0030] The partition wall 6 includes a conductive lower portion 61 disposed on the rib layer 5 and an upper portion 62 disposed on the lower portion 61. The upper portion 62 has a width greater than that of the lower portion 61. As a result, both ends of the upper portion 62 protrude beyond the side surfaces of the lower portion 61. In other words, the partition wall 6 has an overhanging shape in which both ends of the upper portion 62 protrude beyond the side surfaces of the lower portion 61.

[0031] In the example of Figure 3, the lower part 61 has a bottom layer 63 and an axial layer 64. The bottom layer 63 is located between the axial layer 64 and the rib layer 5. Furthermore, in the example of Figure 3, the upper part 62 has a first top layer 65 and a second top layer 66. The first top layer 65 is disposed on the axial layer 64. The second top layer 66 is disposed on the first top layer 65.

[0032] The organic layer OR1 covers the lower electrode LE1 through the pixel opening AP1. The upper electrode UE1 covers the organic layer OR1 and faces the lower electrode LE1. The organic layer OR2 covers the lower electrode LE2 through the pixel opening AP2. The upper electrode UE2 covers the organic layer OR2 and faces the lower electrode LE2. The organic layer OR3 covers the lower electrode LE3 through the pixel opening AP3. The upper electrode UE3 covers the organic layer OR3 and faces the lower electrode LE3. The upper electrodes UE1, UE2, and UE3 are in contact with the lower part 61 of the partition wall 6.

[0033] Display element DE1 includes a cap layer CP1 that covers the upper electrode UE1. Display element DE2 includes a cap layer CP2 that covers the upper electrode UE2. Display element DE3 includes a cap layer CP3 that covers the upper electrode UE3. The cap layers CP1, CP2, and CP3 serve as optical adjustment layers that improve the extraction efficiency of light emitted from the organic layers OR1, OR2, and OR3, respectively.

[0034] In the following description, a multilayer body including an organic layer OR1, an upper electrode UE1, and a cap layer CP1 will be referred to as a laminate film FL1, a multilayer body including an organic layer OR2, an upper electrode UE2, and a cap layer CP2 will be referred to as a laminate film FL2, and a multilayer body including an organic layer OR3, an upper electrode UE3, and a cap layer CP3 will be referred to as a laminate film FL3.

[0035] Sealing layers SE11, SE12, and SE13 are disposed in the subpixels SP1, SP2, and SP3, respectively, to cover the stacked films FL1, FL2, and FL3. Specifically, the sealing layer SE11 continuously covers the cap layer CP1 and the partition wall 6 around the subpixel SP1. The sealing layer SE12 continuously covers the cap layer CP2 and the partition wall 6 around the subpixel SP2. The sealing layer SE13 continuously covers the cap layer CP3 and the partition wall 6 around the subpixel SP3.

[0036] 3, the sealing layer SE11 on the partition wall 6 between the subpixels SP1 and SP2 is spaced apart from the sealing layer SE12 on the partition wall 6. In addition, the sealing layer SE11 on the partition wall 6 between the subpixels SP1 and SP3 is spaced apart from the sealing layer SE13 on the partition wall 6. However, any two of the sealing layers SE11, SE12, and SE13 may be in contact with each other above the partition wall 6.

[0037] For example, gaps are formed between the sealing layers SE11, SE12, and SE13 and the upper portion 62 of the partition wall 6. The stacked films FL1, FL2, and FL3 may be disposed in at least a part of these gaps.

[0038] The sealing layers SE11, SE12, and SE13 are covered with a resin layer RS1. The resin layer RS1 is covered with a sealing layer SE2. The sealing layer SE2 is covered with a resin layer RS2. The resin layers RS1 and RS2 and the sealing layer SE2 are provided continuously at least over the entire display area DA, with a portion of them extending into the peripheral area SA.

[0039] A cover member such as a polarizing plate, a protective film, or a cover glass may be further disposed above the resin layer RS2. Such a cover member may be adhered to the resin layer RS2 via an adhesive layer such as OCA (Optical Clear Adhesive).

[0040] The electrodes constituting the touch panel may be disposed on the sealing layer SE2. Also, color filters corresponding to the colors of the subpixels SP1, SP2, SP3 may be disposed above the display elements DE1, DE2, DE3, respectively.

[0041] The organic insulating layer 12 is made of an organic insulating material such as polyimide. The rib layer 5 and the sealing layers SE11, SE12, SE13, and SE2 are made of an inorganic insulating material such as silicon nitride (SiNx), silicon oxide (SiOx), or silicon oxynitride (SiON). The resin layers RS1 and RS2 are made of a resin material (organic insulating material) such as epoxy resin or acrylic resin.

[0042] The upper electrodes UE1, UE2, UE3 are formed of a metal material such as an alloy of magnesium and silver (MgAg). For example, the lower electrodes LE1, LE2, LE3 correspond to anodes, and the upper electrodes UE1, UE2, UE3 correspond to cathodes.

[0043] The organic layers OR1, OR2, and OR3 are each composed of a plurality of thin films including an emitting layer. In one example, the organic layers OR1, OR2, and OR3 have a structure in which a hole injection layer, a hole transport layer, an electron blocking layer, an emitting layer, a hole blocking layer, an electron transport layer, and an electron injection layer are stacked in this order in the Z direction. However, the organic layers OR1, OR2, and OR3 may have other structures, such as a so-called tandem structure including a plurality of emitting layers.

[0044] The cap layers CP1, CP2, and CP3 have a laminated structure in which, for example, multiple transparent layers are stacked. These transparent layers may include layers formed from inorganic materials and layers formed from organic materials. These transparent layers have different refractive indices. For example, the refractive indices of these transparent layers are different from the refractive indices of the upper electrodes UE1, UE2, and UE3 and the sealing layers SE11, SE12, and SE13. At least one of the cap layers CP1, CP2, and CP3 may be omitted.

[0045] A common voltage is supplied to the partition wall 6. This common voltage is supplied to each of the upper electrodes UE1, UE2, and UE3 in contact with the lower portion 61. A pixel voltage corresponding to the video signal on the signal line SL is supplied to each of the lower electrodes LE1, LE2, and LE3 through the pixel circuits 1 of the subpixels SP1, SP2, and SP3, respectively.

[0046] The organic layers OR1, OR2, and OR3 emit light in response to the application of voltage. Specifically, when a potential difference is created between the lower electrode LE1 and the upper electrode UE1, the light-emitting layer of the organic layer OR1 emits light in the blue wavelength range. When a potential difference is created between the lower electrode LE2 and the upper electrode UE2, the light-emitting layer of the organic layer OR2 emits light in the green wavelength range. When a potential difference is created between the lower electrode LE3 and the upper electrode UE3, the light-emitting layer of the organic layer OR3 emits light in the red wavelength range.

[0047] As another example, the light-emitting layers of the organic layers OR1, OR2, and OR3 may emit light of the same color (e.g., white). In this case, the display device DSP may include color filters that convert the light emitted by the light-emitting layers into light of the colors corresponding to the subpixels SP1, SP2, and SP3. The display device DSP may also include a layer containing quantum dots that are excited by the light emitted by the light-emitting layers to generate light of the colors corresponding to the subpixels SP1, SP2, and SP3.

[0048] The bottom layer 63 and the shaft layer 64 are formed of, for example, a metal material. Examples of the metal material for the bottom layer 63 include molybdenum (Mo), titanium (Ti), titanium nitride (TiN), molybdenum-tungsten alloy (MoW), and molybdenum-niobium alloy (MoNb). Examples of the metal material for the shaft layer 64 include aluminum (Al), aluminum-neodymium alloy (AlNd), aluminum-yttrium alloy (AlY), and aluminum-silicon alloy (AlSi). At least one of the bottom layer 63 and the shaft layer 64 may have a multi-layer structure. The shaft layer 64 may include a layer made of an insulating material. Furthermore, the lower portion 61 may have a single-layer structure made of a conductive material.

[0049] For example, the first top layer 65 is formed of a metal material, and the second top layer 66 is formed of a transparent conductive oxide. Examples of the metal material for the first top layer 65 include titanium, titanium nitride, molybdenum, tungsten, a molybdenum-tungsten alloy, and a molybdenum-niobium alloy. Examples of the conductive oxide for the second top layer 66 include indium tin oxide (ITO), indium zinc oxide (IZO), and indium gallium zinc oxide (IGZO). The upper portion 62 may have a single-layer structure made of a specific material. Furthermore, the upper portion 62 may include a layer made of an insulating material.

[0050] Fig. 4 is a schematic cross-sectional view of the display device DSP taken along line IV-IV in Fig. 2. In this figure, the organic insulating layer 12, the rib layer 5, the partition wall 6, and the lower electrodes LE1 and LE2 are shown, and other elements are omitted.

[0051] As shown in FIG. 4, the rib layer 5 includes a lower layer 51 arranged on the organic insulating layer 12 and the lower electrodes LE1, LE2, and LE3, an upper layer 52 arranged above the lower layer 51, and an intermediate layer 53 arranged between the lower layer 51 and the upper layer 52.

[0052] As shown in FIG. 4, ends E1 and E2 of lower electrodes LE1 and LE2 are both covered with lower layer 51. Although not shown in the cross section of FIG. 4, end E3 of lower electrode LE3 is also covered with lower layer 51. Lower layer 51 is in contact with lower electrodes LE1 and LE2. Although not shown in the cross section of FIG. 4, lower layer 51 is also in contact with lower electrode LE3. Intermediate layer 53 is disposed on lower layer 51, and upper layer 52 is disposed on intermediate layer 53.

[0053] The partition wall 6 is disposed on the upper layer 52. The upper layer 52 is in contact with the lower portion 61 of the partition wall 6. In the example of FIG. 4 , an end portion of the bottom layer 63 of the partition wall 6 protrudes from the side surface of the stem layer 64. The stem layer 64 is formed thicker than the bottom layer 63, the first top layer 65, and the second top layer 66.

[0054] 4, step portions ST due to the ends E1 and E2 of the lower electrodes LE1 and LE2 are formed on the upper surface of the lower layer 51, the lower surface of the upper layer 52, and the upper and lower surfaces of the intermediate layer 53. Although not shown in the cross section of FIG. 4, step portions ST due to the end E3 of the lower electrode LE3 are also formed on the upper surface of the lower layer 51, the lower surface of the upper layer 52, and the upper and lower surfaces of the intermediate layer 53.

[0055] As shown enlarged in FIG. 4, near the pixel opening AP1, the lower layer 51 has an end E51, the upper layer 52 has an end E52, and the intermediate layer 53 has an end E53. The ends E51 and E52 are tapered so that their thickness gradually decreases. The end E52 is recessed from the end E51. These ends E51 and E52 form inclined surfaces 5a at the ends of the rib layer 5. The inclined surfaces 5a form the pixel opening AP1. The end E51 of the lower layer 51 and the end E52 of the upper layer 52 protrude further than the end E53 of the intermediate layer. As a result, a recess 5b is formed in the middle of the inclined surface 5a. The recess 5b is surrounded by the upper surface of the lower layer 51, the lower surface of the upper layer 52, and the side surface of the intermediate layer 53.

[0056] As shown in FIG. 4, the recess 5b has a depth D1. The depth D1 corresponds to the protrusion length of the upper layer 52 from the intermediate layer 53. The depth D1 of the recess 5b is greater than the thickness T3 of the intermediate layer 53. This allows the hole injection layer HIL included in the organic layers OR1, OR2, and OR3, which will be described later, to be more reliably separated. As an example, the thickness T3 of the intermediate layer 53 is 30 nm, and the depth D1 of the recess 5b is greater than 30 nm, for example, 50 to 300 nm. However, the depth D1 and the thickness T3 are not limited to those exemplified here.

[0057] The structure of the rib layer 5 near the pixel opening AP2 and the structure of the rib layer 5 near the pixel opening AP3 are similar to the structure of the rib layer 5 near the pixel opening AP1.

[0058] 2, the recess 5b surrounds the pixel apertures AP1, AP2, and AP3 in plan view. The recess 5b does not overlap with the end E62 of the upper portion 62 of the partition wall 6 in plan view.

[0059] The lower layer 51 and the upper layer 52 can be formed of an inorganic insulating material. The intermediate layer 53 can be formed of an inorganic insulating material having a higher etching rate than the lower layer 51 and the upper layer 52. For example, the lower layer 51 and the upper layer 52 can be formed of silicon oxynitride, and the intermediate layer 53 can be formed of silicon nitride or aluminum oxide.

[0060] 4, the thickness T1 of the lower layer 51 and the thickness T2 of the upper layer 52 are both greater than the thickness T3 of the intermediate layer 53. In addition, in the example shown in FIG. 4, the thickness T1 is equal to the thickness T2, but the thickness T1 does not have to be equal to the thickness T2.

[0061] For example, the thickness T1 of the lower layer 51 is 250 nm, the thickness T2 of the upper layer 52 is 250 nm, and the thickness T3 of the intermediate layer 53 is 20 to 30 nm. However, the thicknesses T1, T2, and T3 are not limited to those exemplified here.

[0062] FIG. 5 is a diagram showing an example of a layer structure that can be applied to the organic layers OR1, OR2, and OR3 shown in FIG. The organic layers OR1, OR2, and OR3 each include a hole injection layer HIL and a hole transport layer HTL. The organic layer OR1 further includes an organic layer OR11, the organic layer OR2 further includes an organic layer OR21, and the organic layer OR3 further includes an organic layer OR31. The organic layer OR1 has, for example, a structure in which a hole injection layer HIL, a hole transport layer HTL, and an organic layer OR11 are stacked in this order in the third direction Z. The organic layer OR2 has, for example, a structure in which a hole injection layer HIL, a hole transport layer HTL, and an organic layer OR21 are stacked in this order in the third direction Z. The organic layer OR3 has, for example, a structure in which a hole injection layer HIL, a hole transport layer HTL, and an organic layer OR31 are stacked in this order in the third direction Z.

[0063] Each of the organic layers OR11, OR21, and OR31 has a structure in which, for example, an electron blocking layer EBL, an emitting layer EML, a hole blocking layer HBL, an electron transport layer ETL, and an electron injection layer EIL are stacked in this order in the third direction Z.

[0064] Fig. 6 is a schematic cross-sectional view of the display device DSP taken along line VV in Fig. 2. In this figure, the organic insulating layer 12, the rib layer 5, the partition wall 6, the lower electrode LE1, the organic layer OR1, and the upper electrode UE1 are shown, and other elements are omitted.

[0065] The organic layer OR1 includes a hole injection layer HIL, a hole transport layer HTL, and an organic layer OR11, which are stacked in this order in the third direction Z. The organic layer OR11 includes an electron blocking layer EBL, an emitting layer EML, a hole blocking layer HBL, an electron transport layer ETL, and an electron injection layer EIL, which are stacked in this order in the third direction Z. Of these layers, the hole transport layer HTL is the thickest. The thickness of the hole transport layer HTL accounts for, for example, more than half of the total thickness of the organic layer OR1.

[0066] 6, the hole injection layer HIL covers the inclined surfaces 5a at the ends of the rib layer 5 and also covers the upper surface of the upper layer 52 of the rib layer 5. In the example shown in FIG. 6, the hole injection layer HIL is not in contact with the partition wall 6, and specifically, the hole injection layer HIL is spaced apart from the end of the bottom layer 63 of the lower part 61. The hole injection layer HIL may also be in contact with the partition wall 6.

[0067] As shown in Figure 6, the hole transport layer HTL covers the hole injection layer HIL and also covers the edge of the bottom layer 63 of the lower part 61. The organic layer OR11 covers the hole transport layer HTL. The upper electrode UE1 covers the organic layer OR11 and is in contact with at least one of the bottom layer 63 of the lower part 61 and the axial layer 64. In the example shown in Figure 6, the upper electrode UE1 is in contact with the axial layer 64. The thicknesses of the hole injection layer HIL, the hole transport layer HTL, and the organic layer OR11 decrease as they approach the side of the axial layer 64 of the lower part 61.

[0068] 6, a portion of the hole injection layer HIL enters a recess 5b formed in the middle of the inclined surface 5a, and the hole injection layer HIL is divided at the recess 5b. Also, a portion of the hole transport layer HTL enters the recess 5b and blocks the entrance of the recess 5b. The hole transport layer HTL is not divided at the recess 5b.

[0069] The thickness T3 of the intermediate layer 53 is greater than the thickness T4 of the hole injection layer HIL on the inclined surface 5a. This allows the hole injection layer HIL to be divided by the recessed portion 5b more reliably. Furthermore, the thickness T3 of the intermediate layer 53 is smaller than the total thickness T5 of the hole injection layer HIL and the hole transport layer HTL on the inclined surface 5a. This prevents the upper electrode UE1 formed above the hole transport layer HTL from being divided by the recessed portion 5b.

[0070] The organic layers OR2 and OR3 and the upper electrodes UE2 and UE3 have the same structure as the organic layer OR1 and the upper electrode UE1 shown in Fig. 5. However, the thickness of each layer included in the organic layers OR1, OR2, and OR3 may be different.

[0071] Next, an example of a manufacturing method of the display device DSP will be described. Figures 7A to 7F, 8A to 8F, and 9 are schematic cross-sectional views showing the manufacturing process of the display device DSP. Figures 7A to 7F correspond to a cross section taken along line IV-IV in Figure 2, and Figures 8A to 8F correspond to a cross section taken along line III-III in Figure 2. In these figures, the substrate 10 and the circuit layer 11 are omitted from illustration.

[0072] In manufacturing the display device DSP, first, a circuit layer 11 is formed on a substrate 10. Furthermore, an organic insulating layer 12 having contact holes is formed on the circuit layer 11.

[0073] After the organic insulating layer 12 is formed, the lower electrodes LE1, LE2, and LE3 are formed on the organic insulating layer 12 as shown in FIG. 7A.

[0074] After the lower electrodes LE1, LE2, and LE3 are formed, as shown in FIG. 7B, a lower layer 51 is formed to cover the lower electrodes LE1, LE2, and LE3, an intermediate layer 53 is formed to cover the lower layer 51, and an upper layer 52 is formed to cover the intermediate layer 53, thereby forming a rib layer 5.

[0075] After the rib layer 5 is formed, a partition wall 6 having a lower portion 61 and an upper portion 62 is formed on the rib layer 5, as shown in Fig. 7C. The lower portion 61 includes a bottom layer 63 and an axial layer 64 as shown in Fig. 3. The upper portion 62 includes a first top layer 65 and a second top layer 66 as shown in Fig. 3.

[0076] After the partition walls 6 are formed, a resist R0 having a shape corresponding to the rib layer 5 is placed on the upper layer 52, as shown in Fig. 7D. The resist R0 covers the partition walls 6. Furthermore, the rib layer 5 is etched.

[0077] Etching of the rib layer 5 will be described. First, a case will be described in which the lower layer 51 and the upper layer 52 are formed of silicon oxynitride and the intermediate layer 53 is formed of silicon nitride. First, anisotropic dry etching is performed as the first etching to remove the portions of the rib layer 5 exposed from the resist R0 as shown in FIG. 7E. Next, isotropic dry etching is performed as the second etching to form the recesses 5b as shown in FIG. 7F. The material forming the intermediate layer 53 has a higher etching rate in the second dry etching than the materials forming the lower layer 51 and the upper layer 52. Therefore, the intermediate layer 53 is eroded by the lower layer 51 and the upper layer 52, forming the recesses 5b on the inclined surface 5a. Alternatively, the recesses 5b may be formed by performing anisotropic dry etching as the first etching and then wet etching with dilute hydrofluoric acid as the second etching. The material forming the intermediate layer 53 has a higher etching rate in the second dry etching than the materials forming the lower layer 51 and the upper layer 52. 7F, the middle layer 53 is eroded by the lower layer 51 and the upper layer 52, and a recess 5b is formed on the inclined surface 5a. However, by performing the first etching and the second etching by dry etching, the first etching and the second etching can be performed as a single continuous process, and therefore the etching process for the rib layer 5 can be simplified.

[0078] Next, a case where the lower layer 51 and the upper layer 52 are formed of silicon oxynitride and the intermediate layer 53 is formed of aluminum oxide will be described. First, anisotropic dry etching is performed as the first etching to remove the portion of the upper layer 52 exposed from the resist R0. Next, wet etching using dilute hydrofluoric acid is performed as the second etching to remove the portion of the intermediate layer 53 exposed from the resist R0. Here, the material forming the intermediate layer 53 has a higher etching rate in the second etching than the materials forming the lower layer 51 and the upper layer 52. Therefore, the edge of the intermediate layer 53 is eroded more than the edge of the upper layer 52. Next, anisotropic dry etching is performed as the third etching to remove the portion of the lower layer 51 exposed from the resist R0. As a result, a recess 5b is formed on the inclined surface 5a as shown in FIG. 7F. After this etching of the rib layer 5, the resist R0 is removed as shown in FIG. 7F.

[0079] Next, a process for forming display elements DE1, DE2, and DE3 is performed. In this embodiment, it is assumed that display element DE1 is formed first, display element DE2 is formed next, and display element DE3 is formed last. However, the order in which display elements DE1, DE2, and DE3 are formed is not limited to this example.

[0080] To form the display element DE1, first, as shown in Fig. 8A, a laminated film FL1 is formed over the entire display area DA and peripheral area SA. As shown in Fig. 3, the laminated film FL1 includes an organic layer OR1 in contact with the lower electrode LE1 through the pixel opening AP1, an upper electrode UE1 covering the organic layer OR1, and a cap layer CP1 covering the upper electrode UE1. The laminated film FL1 is divided into multiple parts by overhanging partition walls 6. The organic layer OR1, the upper electrode UE1, and the cap layer CP1 are formed by vapor deposition.

[0081] After the stacked film FL1 is formed, a sealing layer SE11 is formed over the entire display area DA and the peripheral area SA, as shown in FIG. 8B. The sealing layer SE11 is formed by CVD. The sealing layer SE11 continuously covers each divided portion of the stacked film FL1 and the partition walls 6.

[0082] After the sealing layer SE11 is formed, a resist R1 is disposed on the sealing layer SE11 as shown in Fig. 8C. The resist R1 covers the subpixel SP1 and part of the partition wall 6 around it.

[0083] Then, as shown in FIG. 8D, etching is performed using the resist R1 as a mask to remove the stacked film FL1 and the portions of the sealing layer SE11 that are not covered by the resist R1. This results in the formation of a display element DE1 in the subpixel SP1. For example, this etching may include wet etching or dry etching, which is performed sequentially on the sealing layer SE11, the cap layer CP1, the upper electrode UE1, and the organic layer OR1. After these etching steps, the resist R1 is removed.

[0084] Display elements DE2 and DE3 are formed in the same manner as display element DE1. That is, when display element DE2 is formed, a stacked film FL2 and a sealing layer SE12 are formed over the entire display area DA and peripheral area SA. As shown in FIG. 3, stacked film FL2 includes an organic layer OR2 in contact with the lower electrode LE2 through the pixel opening AP2, an upper electrode UE2 covering the organic layer OR2, and a cap layer CP2 covering the upper electrode UE2. By patterning such stacked film FL2 and sealing layer SE12, display element DE2 is formed in subpixel SP2, as shown in FIG. 8E.

[0085] Furthermore, when forming the display element DE3, a laminated film FL3 and a sealing layer SE13 are formed over the entire display area DA and peripheral area SA. As shown in Fig. 3, the laminated film FL3 includes an organic layer OR3 in contact with the lower electrode LE3 through the pixel opening AP3, an upper electrode UE3 covering the organic layer OR3, and a cap layer CP3 covering the upper electrode UE3. By patterning the laminated film FL3 and the sealing layer SE13, the display element DE3 is formed in the subpixel SP3, as shown in Fig. 8F.

[0086] After the display elements DE1, DE2, and DE3 are formed, the resin layer RS1, the sealing layer SE2, and the resin layer RS2 are formed in this order as shown in Fig. 3. Through these steps, the display device DSP is completed.

[0087] 8A, the upper electrode UE1 can be formed by, for example, applying an oblique deposition method in which deposition is performed from an oblique direction relative to the normal (third direction Z) of the substrate 10. For example, as shown in FIG. 9, when a deposition source 100 is placed at the upper right and an upper electrode material is deposited, the upper electrode material adheres thickly to the inclined surface 5a1 facing the deposition source 100. This makes it possible to prevent the upper electrode UE1 from being divided at the inclined surface 5a1.

[0088] 9, the upper electrode material is thinly deposited on the inclined surface 5a2, which forms the same pixel aperture AP1 as the inclined surface 5a1 and faces the inclined surface 5a1. In other words, the thickness T61 of the upper electrode UE1 formed on the inclined surface 5a1 is greater than the thickness T62 of the upper electrode UE1 formed on the inclined surface 5a2.

[0089] FIG. 10 is a cross-sectional view showing a display device DSP' of a comparative example. The comparative display device DSP' shown in Figure 10 differs from the display device DSP shown in Figures 3 to 6 in that no recesses 5b are formed on the inclined surfaces 5a that form the pixel openings AP1, AP2, and AP3 of the rib layer 5.

[0090] In the display device DSP' shown in Figure 10, if the hole injection layer HIL of the organic layers OR1, OR2, and OR3 comes into contact with the conductive lower part 61, leakage current will flow from the lower electrodes LE1, LE2, and LE3 to the lower part 61 via the hole injection layer HIL without passing through layers such as the emitting layer EML, which may result in display defects.

[0091] In contrast, in the display device DSP of this embodiment, recesses 5b are formed on the inclined surfaces 5a that form the pixel openings AP1, AP2, and AP3 of the rib layer 5. This allows the hole injection layer HIL to be divided at the recesses 5b, so that even if the hole injection layer HIL comes into contact with the conductive lower portion 61, undesired leakage current is prevented from flowing from the lower electrodes LE1, LE2, and LE3 to the lower portion 61, thereby preventing display defects caused by leakage current. In this way, the display device DSP of this embodiment can prevent a decrease in reliability.

[0092] As described above, when the depth D1 of the recess 5b is greater than the thickness T1 of the lower layer 51, the hole injection layer HIL can be divided more reliably.

[0093] FIG. 11 is a cross-sectional view showing a display device DSP' of another comparative example.

[0094] The comparative display device DSP' shown in Figure 11 differs from the display device DSP shown in Figures 3 to 6 in that the rib layer 5 does not have a lower layer 51, and the ends E51, E52 of the lower layer 51 and upper layer 52 protrude beyond the end E53 of the intermediate layer 53, so that no recess 5b is formed in the middle of the inclined surface 5a.

[0095] 11, the recess 5b is surrounded by the lower surface of the upper layer 52, the side surface of the intermediate layer 53, and the upper surface of the lower electrode LE1. In manufacturing such a display device DSP', if excessive etching is performed when forming the recess 5b, the depth D1 of the recess 5b may become excessive, and the ends (E1, E2, E3) of the lower electrodes LE1, LE2, LE3 may become exposed. The exposed ends (E1, E2, E3) of the lower electrodes LE1, LE2, LE3 may be damaged in subsequent manufacturing processes, or moisture may penetrate, resulting in display defects.

[0096] In the display device DSP of this embodiment, the ends E1, E2, and E3 of the lower electrodes LE1, LE2, and LE3 are covered by the lower layer 51. Therefore, even if etching is excessive when forming the recesses 5b, the ends (E1, E2, and E3) of the lower electrodes LE1, LE2, and LE3 are not exposed, and as a result, display defects caused by excessive etching can be suppressed. In this way, the display device DSP of this embodiment can suppress a decrease in reliability.

[0097] Fig. 12 is a schematic cross-sectional view showing another example of the configuration of the display device DSP shown in Fig. 4. Fig. 12 is a schematic cross-sectional view of the display device DSP taken along line IV-IV in Fig. 2. In this figure, the organic insulating layer 12, the rib layer 5, the partition wall 6, and the lower electrodes LE1 and LE2 are shown, and other elements are omitted. Explanation of the same configuration as the display device DSP shown in Fig. 4 will be omitted, as the above explanation is used.

[0098] 12, the rib layer 5 includes a lower layer 51 disposed on the organic insulating layer 12 and the lower electrodes LE1, LE2, and LE3, an upper layer 52 disposed above the lower layer 51, and an intermediate layer 53 disposed between the lower layer 51 and the upper layer 52. The intermediate layer 53 includes a first intermediate layer 531 disposed on the lower layer 51, a second intermediate layer 532 disposed between the first intermediate layer 531 and the upper layer 52, and a third intermediate layer 533 disposed between the first intermediate layer 531 and the second intermediate layer 532.

[0099] As shown in FIG. 12, the first intermediate layer 531 is disposed on the lower layer 51, the third intermediate layer 533 is disposed on the first intermediate layer 531, the second intermediate layer 532 is disposed on the third intermediate layer 533, and the upper layer 52 is disposed on the second intermediate layer 532.

[0100] 12, step portions ST due to the ends E1 and E2 of the lower electrodes LE1 and LE2 are formed on the upper surface of the lower layer 51, the lower surface of the upper layer 52, and the upper and lower surfaces of the first intermediate layer 531, the second intermediate layer 532, and the third intermediate layer 533. Although not shown in the cross section of FIG. 4, step portions ST due to the end E3 of the lower electrode LE3 are also formed on the upper surface of the lower layer 51, the lower surface of the upper layer 52, and the upper and lower surfaces of the first intermediate layer 531, the second intermediate layer 532, and the third intermediate layer 533.

[0101] As shown enlarged in FIG. 12, the lower layer 51 has an end E51, the upper layer 52 has an end E52, the first intermediate layer 531 has an end E531, the second intermediate layer 532 has an end E532, and the third intermediate layer 533 has an end E533. The ends E51, E52, and E533 have tapered shapes with gradually decreasing thickness. The end E533 is set back from the end E51, and the end E52 is set back from the end E533. Such ends E51, E52, and E533 form inclined surfaces 5a at the ends of the rib layer 5. The inclined surfaces 5a form pixel apertures AP1.

[0102] The end E51 of the lower layer 51 and the end E533 of the third intermediate layer 533 protrude further than the end E531 of the first intermediate layer 531. As a result, a recess 5b1 is formed in the middle of the inclined surface 5a. Furthermore, the end E533 of the third intermediate layer 533 and the end E52 of the upper layer 52 protrude further than the end E532 of the second intermediate layer 532. As a result, a recess 5b2 is formed in the middle of the inclined surface 5a. That is, two recesses 5b1 and 5b2 are formed in the middle of the inclined surface 5a. The recesses 5b1 and 5b2 surround the pixel openings AP1, AP2, and AP3 in a plan view. The recesses 5b1 and 5b2 do not overlap with the ends of the upper portion 62 of the partition wall 6 in a plan view.

[0103] The two recesses 5b1 and 5b2 are formed in the middle of the inclined surface 5a, so that the hole injection layers HIL included in the organic layers OR1, OR2, and OR3 can be divided more reliably.

[0104] In the example shown in FIG. 12, two recesses 5b are formed in the middle of the inclined surface 5a, but two or more recesses 5b may be formed in the inclined surface 5a.

[0105] As shown in FIG. 12, the recesses 5b1 and 5b2 have depths D11 and D12. The depth D11 corresponds to the protrusion length of the third intermediate layer 533 from the first intermediate layer 531, and the depth D12 corresponds to the protrusion length of the upper layer 52 from the second intermediate layer 532. In the example shown in FIG. 12, the depths D11 and D12 are equal to each other, but they do not have to be equal to each other. The depth D11 is greater than the thickness T31 of the first intermediate layer 531, and the depth D12 is greater than the thickness T32 of the second intermediate layer 532. This makes it possible to more reliably separate the hole injection layer HIL included in the organic layers OR1, OR2, and OR3 described below.

[0106] For example, the thicknesses T31 and T32 of the first intermediate layer 531 and the second intermediate layer 532 are 30 nm, and the depths D11 and D12 of the recesses 5b1 and 5b2 are greater than 30 nm, for example, 50 to 300 nm. However, the depths D12 and D11 and the thicknesses T31 and T32 are not limited to those exemplified here.

[0107] The lower layer 51, the upper layer 52, and the third intermediate layer 533 can be formed of an inorganic insulating material. The first intermediate layer 531 and the second intermediate layer 532 can be formed of an inorganic insulating material having a higher etching rate than the lower layer 51, the upper layer 52, and the third intermediate layer 533. For example, the lower layer 51, the upper layer 52, and the third intermediate layer 533 can be formed of silicon oxynitride, and the first intermediate layer 531 and the second intermediate layer 532 can be formed of silicon nitride or aluminum oxide.

[0108] 12, the thickness T1 of the lower layer 51, the thickness T2 of the upper layer 52, and the thickness T33 of the third intermediate layer 533 are all greater than the thickness T31 of the first intermediate layer 531 and the thickness T32 of the second intermediate layer 532. In the example shown in FIG. 12, the thicknesses T1 and T2 are greater than the thickness T33, but the thicknesses T1, T2, and T33 may be equal to each other.

[0109] The structure of the rib layer 5 near the pixel opening AP2 and the structure of the rib layer 5 near the pixel opening AP3 are similar to the structure of the rib layer 5 near the pixel opening AP1.

[0110] In this configuration example, the same effects as those of the display device DSP shown in FIG. 4 can be obtained.

[0111] As described above, according to this embodiment, it is possible to provide a display device capable of suppressing a decrease in reliability.

[0112] All display device manufacturing methods that can be implemented by a person skilled in the art by making appropriate design modifications based on the display device manufacturing method described above as an embodiment of the present invention also fall within the scope of the present invention as long as they include the gist of the present invention.

[0113] Within the scope of the concept of the present invention, a person skilled in the art may conceive of various modifications, and these modifications are also understood to fall within the scope of the present invention. For example, even if a person skilled in the art appropriately adds or deletes components or modifies the design of the above-described embodiment, or adds or omits steps or modifies conditions, these modifications are also included within the scope of the present invention as long as they maintain the gist of the present invention.

[0114] Furthermore, with regard to other effects brought about by the aspects described in the above embodiments, those that are clear from the description in this specification or that can be appropriately thought of by a person skilled in the art are naturally understood to be brought about by the present invention. [Explanation of symbols]

[0115] DSP…display device 10…board 5...Rib layer 51...Lower layer 52...Upper layer 53...Intermediate layer 6...Bulkhead 61...Lower 62...Upper 63...Bottom layer 64...Axis layer 65...First top layer 66...Second top layer 10... Substrate 11... Circuit layer 12... Organic insulating layer AP1, AP2, AP3...pixel aperture SP1, SP2, SP3...subpixels DE1, DE2, DE3...Display element (organic EL element) LE1, LE2, LE3…lower electrode UE1, UE2, UE3...upper electrode OR1, OR2, OR3…Organic layer CP1, CP2, CP3...cap layer SE11, SE12, SE13...Sealing layer DA: Display area SA: Surrounding area

Claims

1. A substrate; an organic insulating layer disposed above the substrate; a lower electrode disposed above the organic insulating layer; a rib layer covering an end portion of the lower electrode and having a pixel opening overlapping the lower electrode; an organic layer that covers the lower electrode through the pixel opening and emits light in response to application of a voltage; an upper electrode covering the organic layer; a partition wall including a lower portion disposed on the rib layer and an upper portion having an end portion protruding from a side surface of the lower portion; The rib layer is an upper layer in contact with the lower portion of the partition wall; a lower layer covering an end portion of the lower electrode and in contact with the lower electrode; an intermediate layer disposed between the upper layer and the lower layer; an inclined surface that forms the pixel opening; A display device, wherein ends of the upper layer and the lower layer protrude beyond an end of the intermediate layer, thereby forming a recess on the inclined surface.

2. The display device according to claim 1 , wherein the depth of the recess is greater than the thickness of the intermediate layer.

3. The display device according to claim 1 , wherein the recess does not overlap the end of the upper portion of the partition wall in a plan view.

4. The display device according to claim 1 , wherein the recess surrounds the pixel opening in a plan view.

5. the upper layer and the lower layer are formed of an inorganic insulating material, The display device according to claim 1 , wherein the intermediate layer is formed of an inorganic insulating material having a higher etching rate than the upper and lower layers.

6. the upper layer and the lower layer are formed of silicon oxynitride; The display device according to claim 5 , wherein the intermediate layer is made of silicon nitride or aluminum oxide.

7. 2. The display device according to claim 1, wherein the organic layer is made up of a plurality of layers including a hole injection layer covering the lower electrode and a hole transport layer covering the hole injection layer.

8. the organic layer covers the inclined surface of the rib layer; The display device according to claim 7 , wherein the hole injection layer is divided at the recessed portion of the inclined surface.

9. The display device according to claim 8 , wherein the hole transport layer is not divided at the recessed portion of the inclined surface.

10. the inclined surface has a first inclined surface and a second inclined surface that form the same pixel opening and are opposed to each other; the organic layer covers the first inclined surface and the second inclined surface, the upper electrode covers the organic layer; The display device according to claim 1 , wherein the thickness of the upper electrode formed on the first inclined surface is greater than the thickness of the upper electrode formed on the second inclined surface.

11. 8. The display device according to claim 7, wherein the thickness of the intermediate layer is greater than the thickness of the hole injection layer and less than the total thickness of the hole injection layer and the hole transport layer.

12. The display device according to claim 1 , wherein the lower portion of the partition wall comprises a conductive bottom layer disposed above the rib layer and a conductive axis layer disposed above the bottom layer.

13. The display device according to claim 12 , wherein an end portion of the bottom layer protrudes from a side surface of the axis layer.

14. The display device according to claim 12 , wherein the upper electrode is in contact with at least one of the bottom layer and the axis layer.

15. A substrate; an organic insulating layer disposed above the substrate; a lower electrode disposed above the organic insulating layer; a rib layer covering an end portion of the lower electrode and having a pixel opening overlapping the lower electrode; an organic layer that covers the lower electrode through the pixel opening and emits light in response to application of a voltage; an upper electrode covering the organic layer; a partition wall including a lower portion disposed on the rib layer and an upper portion having an end portion protruding from a side surface of the lower portion; The rib layer is an upper layer in contact with the lower portion of the partition wall; a lower layer covering an end portion of the lower electrode and in contact with the lower electrode; an intermediate layer disposed between the upper layer and the lower layer; an inclined surface that forms the pixel opening; the intermediate layer comprises a first intermediate layer in contact with the lower layer, a second intermediate layer in contact with the upper layer, and a third intermediate layer disposed between the first intermediate layer and the second intermediate layer; an end portion of the lower layer and the third intermediate layer protrudes beyond an end portion of the first intermediate layer, thereby forming a first recessed portion on the inclined surface; A display device in which ends of the upper layer and the third intermediate layer protrude beyond an end of the second intermediate layer, thereby forming a second recess in the inclined surface.

16. the upper layer, the lower layer, and the third intermediate layer are formed of an inorganic insulating material; 16. The display device according to claim 15, wherein the first intermediate layer and the second intermediate layer are formed of an inorganic insulating material having a higher etching rate than the upper layer, the lower layer, and the third intermediate layer.

17. The display device according to claim 16 , wherein the third intermediate layer is formed of the same inorganic insulating material as the upper layer and the lower layer.

18. the upper layer, the lower layer, and the third intermediate layer are formed of silicon oxynitride; 18. The display device according to claim 17, wherein the first intermediate layer and the second intermediate layer are formed of silicon nitride or aluminum oxide.

19. The display device according to claim 15 , wherein the thickness of the third intermediate layer is smaller than the thicknesses of the upper layer and the lower layer.

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