Method for evaluating silicon single crystal wafer and method for manufacturing semiconductor device

Abstract

To provide a method for evaluating a silicon single crystal wafer, which is useful for suppressing the occurrence of dislocation at a place where a Line & Space pattern is formed.SOLUTION: Forming a plurality of L & S patterns on a surface of the Si single crystal wafer by a SiN film while changing a formation direction of the L & S patterns, forming a thermal oxide film on a surface of the Si single crystal wafer on a side where the L & S patterns are formed, performing a first process of removing the thermal oxide film, and performing a second process of visualizing dislocations existing at a formation position of the L & S patterns as dislocation pits by selective etching; The evaluation method of the Si single crystal wafer includes a process of measuring the density of dislocation pits for each L & S pattern, and a process of determining and evaluating the formation direction of the L & S pattern having the lowest density of dislocation pits as the optimum formation direction from the measurement result.SELECTED DRAWING: Figure 1

Description

[Technical Field]

[0001] The present invention relates to a method for evaluating a silicon single crystal wafer and a method for manufacturing a semiconductor device. [Background technology]

[0002] Silicon wafers produced by the Czochralski (CZ) method are primarily used as substrates for manufacturing semiconductor integrated circuits. In particular, cutting-edge logic devices use the FinFET structure, in which the channel is surrounded by insulating films and metal electrodes on three sides, or the Gate All Around (GAA) structure, in which the channel is surrounded by insulating films and metal electrodes on four sides, in order to suppress the short channel effect.

[0003] In these structures, an insulating film and metal electrodes are present around the silicon that forms the channel, and because the insulating film and metal electrodes have different thermal expansion coefficients from the silicon, strong stress can be applied to the silicon, causing dislocations. The generated dislocations cause leakage current and thus deteriorate device characteristics. Therefore, to prevent dislocations from occurring, it is necessary to use insulating film and metal electrode materials with a linear expansion coefficient similar to that of silicon. However, finding such materials is extremely difficult, and it is difficult to address this issue by simply selecting these materials.

[0004] On the other hand, one way to address this issue within the silicon wafer itself is to dope it with elements that have the effect of suppressing dislocation propagation. Specific examples include oxygen and nitrogen. However, there are concerns that these elements themselves may also affect device characteristics. Oxygen forms oxygen precipitates during heat treatment, which become the source of leakage. Heat treatment also forms oxygen donors, which change the resistivity. Nitrogen also forms nitrogen donors, which change the resistivity and affect device characteristics. Furthermore, outward diffusion during heat treatment in the device process reduces the nitrogen concentration in the surface region that becomes the device active layer, thereby reducing the effect of suppressing dislocation propagation.

[0005] On the other hand, patterns fabricated in device processes are based on a linear line-and-space structure (line-and-space pattern). Channels and electrodes are generally formed using this structure through repeated etching and film formation. For this reason, it is important to suppress the generation or propagation of dislocations when forming the L&S structure.

[0006] Patent Document 1 is an example of a defect evaluation technique after device pattern formation. This technique requires the device film to be removed, but some types of film are difficult to remove by wet etching, necessitating mechanical polishing. Furthermore, Patent Document 1 describes a process for depositing only a SiN film, and dislocations may not occur in the high-stress region below the SiN film. Furthermore, implanting ions such as As can cause interactions between dislocations and defects due to ion implantation or the As element itself, making accurate evaluation difficult. [Prior art documents] [Patent documents]

[0007] [Patent Document 1] Japanese Patent Application Laid-Open No. 2007-300144 Summary of the Invention [Problem to be solved by the invention]

[0008] Dislocations, which are the source of leakage and degrade device characteristics, are generated by stress caused by the difference in the linear expansion coefficient between the insulating film or metal electrode and silicon, and a method to suppress this stress is needed. However, it is extremely difficult to make the linear expansion coefficient of the silicon that forms the channel approximately the same as that of the metal electrode or insulating film. There is also a method of doping with elements that have the effect of suppressing dislocation propagation, but these elements themselves can also act as donors or form defects, thereby deteriorating device characteristics.

[0009] Therefore, the present invention has been made to solve the above problems, and has an object to provide a silicon single crystal wafer evaluation method that can be used to suppress the occurrence of dislocations in areas where line and space patterns are formed, and a semiconductor device manufacturing method that can suppress the occurrence of the above dislocations by using the evaluation method. [Means for solving the problem]

[0010] In order to achieve the above object, the present invention provides a method for evaluating a silicon single crystal wafer used when manufacturing a semiconductor device using a line and space pattern, comprising: a line & space forming step of forming a plurality of line & space patterns on the surface of the silicon single crystal wafer using a SiN film by changing the direction of forming the line & space patterns; a thermal oxide film forming step of forming a thermal oxide film on the surface of the silicon single crystal wafer on which the line & space pattern is formed; a dislocation pit revealing step including a first step of removing the thermal oxide film and a second step of revealing dislocations present in the area where the line and space pattern is to be formed as dislocation pits by selective etching; a dislocation pit density measuring step of measuring the density of the revealed dislocation pits for each of the line and space patterns; a formation direction determining step of determining and evaluating the formation direction of the line and space pattern having the lowest density of dislocation pits based on the measurement results of the density of dislocation pits as the optimal formation direction among the formation directions of the plurality of line and space patterns formed; The present invention provides a method for evaluating a silicon single crystal wafer, comprising:

[0011] The silicon single crystal wafer evaluation method of the present invention makes it possible to evaluate the optimal formation direction that can suppress the occurrence of dislocations at the formation location of a line and space pattern (hereinafter also referred to as an L&S pattern).Furthermore, by forming an L&S pattern in the evaluated optimal formation direction and manufacturing a device, it is possible to suppress the occurrence and propagation of dislocations and prevent deterioration of device characteristics. Furthermore, by forming a thermal oxide film as described above, it is possible to apply a higher stress to the silicon single crystal wafer than the film stress caused by the SiN film. This allows for a higher stress to be generated than with only the SiN film, and if dislocations are present, this makes it easier to reveal dislocation pits. This makes it possible to reveal dislocations that would not be visible with just the formation of the SiN film, enabling more accurate evaluation.

[0012] In the above Line & Space forming process, it is sufficient that the number of silicon single crystal wafers on which the L&S pattern is formed is one or more. That is, it is possible to prepare one wafer and form multiple L&S patterns with different formation directions on the surface of the single wafer, or to prepare multiple wafers and form multiple L&S patterns with one formation direction per wafer but with different formation directions for each wafer. In this way, it is sufficient to prepare multiple L&S patterns with different formation directions.

[0013] At this time, in the thermal oxide film forming step, the thermal oxide film can be formed to a thickness of 400 to 600 nm.

[0014] By forming the thermal oxide film to a thickness of 400 nm or more, it is possible to impart a more appropriate film stress of the thermal oxide film to the silicon single crystal wafer, and more effectively prevent the dislocation density from being too low, which makes it difficult to produce differences between the formation directions. Furthermore, by setting the thickness to 600 nm or less, it is possible to more reliably prevent the dislocation density from becoming higher than necessary, and the individual dislocation pits from overlapping each other after selective etching. By setting the film thickness within this range, the density of dislocation pits can be measured more accurately.

[0015] Furthermore, in the dislocation pit revealing step, the removal of the thermal oxide film in the first treatment and the revealing of the dislocation pits in the second treatment can be carried out simultaneously by the selective etching.

[0016] For example, if the selective etching is performed using a selective etching solution containing hydrofluoric acid, depending on the thickness of the thermal oxide film, the selective etching can conveniently remove the thermal oxide film and expose the dislocation pits at the same time.

[0017] The present invention also provides a method for manufacturing a semiconductor device using a line and space pattern formed on a surface of a silicon single crystal wafer, comprising: When the line and space pattern is formed in the manufacturing of the semiconductor device, There is provided a method for manufacturing a semiconductor device, characterized in that the line and space pattern is formed in the optimum direction determined by the silicon single crystal wafer evaluation method of the present invention.

[0018] According to the method for manufacturing a semiconductor device of the present invention, it is possible to suppress the generation and propagation of dislocations, and to manufacture a device in which deterioration of device characteristics is prevented. [Effects of the Invention]

[0019] The silicon single crystal wafer evaluation method of the present invention makes it possible to evaluate the optimal formation direction that can suppress the occurrence of dislocations at the L&S pattern formation location in the silicon single crystal wafer. Furthermore, the semiconductor device manufacturing method of the present invention forms an L&S pattern based on the above evaluation and then manufactures the semiconductor device, thereby preventing the occurrence of dislocations due to stress caused by L&S pattern formation. As a result, it is possible to prevent the device characteristics from deteriorating. [Brief explanation of the drawings]

[0020] [Figure 1] FIG. 1 is a flow chart showing an example of steps of a method for evaluating a silicon single crystal wafer according to the present invention. [Figure 2] FIG. 1 is a schematic diagram showing an L&S pattern and its formation direction on a (110) wafer. [Figure 3] FIG. 1 is a schematic diagram showing the positional relationship between the notch position on a (110) wafer and the longitudinal direction of the L&S pattern. [Figure 4] FIG. 2 is an observation view showing an example of a cross-sectional SEM image after the formation of a thermal oxide film. [Figure 5] These are images observed with a stereomicroscope after selective etching in each formation direction on a (110) wafer. [Figure 6] 1 is a graph showing the relationship between line width and dislocation pit density in a (110) wafer. [Figure 7] FIG. 1 is a schematic diagram showing an L&S pattern and its formation direction on a (001) wafer. [Figure 8] FIG. 1 is a schematic diagram showing the positional relationship between the notch position on a (001) wafer and the longitudinal direction of the L&S pattern. [Figure 9] 1 is a graph showing the relationship between line width and dislocation pit density in a (001) wafer. [Figure 10] FIG. 1 is a simulation diagram showing resolved shear stress distribution by finite element method analysis when the pattern formation direction is [-11-1] on a (110) wafer. [Figure 11] This is a simulation diagram showing resolved shear stress distribution by finite element method analysis when the pattern formation direction is

[0001] on a (110) wafer. [Figure 12] 10 is a graph showing the relationship between line width and dislocation pit density in a (110) wafer in Comparative Example 3 (no thermal oxide film formed). DETAILED DESCRIPTION OF THE INVENTION

[0021] The present invention will be described in detail below as an example of an embodiment with reference to the drawings, but the present invention is not limited to this. As described above, in devices in which a strong stress is applied to the channel region, it is necessary to determine the direction in which the L&S pattern is formed in order to suppress the occurrence of dislocations that are the source of leakage. Therefore, the present inventors have conducted extensive research into this problem. As a result, the inventors have found that a method for evaluating silicon single crystal wafers used in manufacturing semiconductor devices using L&S patterns, the method including: an L&S formation step of changing the formation direction of the L&S pattern and forming a plurality of the L&S patterns from a SiN film on the surface of the silicon single crystal wafer; a thermal oxide film formation step of forming a thermal oxide film on the surface of the silicon single crystal wafer on the side on which the L&S pattern is formed; a dislocation pit manifestation step including a first process of removing the thermal oxide film and a second process of manifesting dislocations present in the locations where the L&S patterns are formed as dislocation pits by selective etching; a dislocation pit density measurement step of measuring the density of the manifested dislocation pits for each of the L&S patterns; and a formation direction determination step of determining and evaluating the formation direction of the L&S pattern having the lowest dislocation pit density as the optimal formation direction among the formation directions of the plurality of L&S patterns formed, based on the measurement results of the dislocation pit density. Furthermore, the inventors discovered that if an L&S pattern is formed based on the formation direction and a device is manufactured, the occurrence of dislocations can be suppressed and the deterioration of device characteristics can be prevented, thereby completing the present invention.

[0022] An example of the steps of the method for evaluating silicon single crystal wafers of the present invention is shown in Figure 1. As shown in Figure 1, the evaluation method of the present invention is broadly divided into a line and space formation step (L&S formation step), a thermal oxide film formation step, a dislocation pit manifestation step, a dislocation pit density measurement step, and a formation direction determination step. Each step will be described in detail below, giving specific examples.

[0023] (Line&Space formation process) The L&S formation process consists of the steps of preparing a silicon single crystal wafer (simply called a silicon wafer or wafer), depositing a SiN film, and forming an L&S pattern with a tilted formation direction. [Silicon single crystal wafer preparation] In preparing the silicon single crystal wafer, a wafer similar to the wafer used when actually manufacturing a semiconductor device using an L&S pattern is prepared. As an example of a sample, a silicon single crystal wafer with a diameter of 300 mm, a resistivity of 10 Ω·cm, and a surface orientation of (110) was prepared.

[0024] At this time, there is no particular limit to the number of wafers to be prepared, and as described above, if L&S patterns with different formation directions are to be formed later on the surface of one wafer, only one wafer may be prepared. Alternatively, if an L&S pattern is to be formed with a different formation direction on each wafer, multiple wafers can be prepared, equal to the number of different formation directions. When preparing multiple wafers, it is preferable to prepare wafers with the same conditions, such as oxygen concentration and resistivity. For example, when preparing wafers by slicing them from a CZ ingot and performing various processes, it is recommended to use wafers sliced ​​from adjacent (or nearby) locations. Note that the latter method of preparing multiple wafers is preferable because it simplifies the formation of L&S patterns, etc. Here, the explanation will be given assuming that multiple sheets (four sheets) are prepared as in the latter case.

[0025] [SiN film deposition] Next, a SiN film is formed on the surface of each of the prepared wafers. This can be done by a conventional method, such as LP-CVD (low-pressure chemical vapor deposition). The film formation conditions are not particularly limited, but can be the same as those used when actually manufacturing semiconductor devices using an L&S pattern. Here, a SiN film having a thickness of 200 nm and a true stress of about 2 GPa was formed under the following conditions. Film forming temperature: 760℃ Other conditions: LP-CVD method

[0026] [Formation of L&S pattern with shifted formation direction] Next, by changing the formation direction, multiple L&S patterns are formed. For example, the SiN film formed as described above is subjected to photolithography to form a predetermined stripe shape (L&S pattern), and the SiN film is then removed by dry etching to form the L&S pattern. The dimensions of this L&S pattern are not particularly limited, but may be the same as those when actually manufacturing a semiconductor device using an L&S pattern, for example. There are no particular limitations on the type of forming direction of the L&S pattern; the more types there are, the more detailed the evaluation can be performed. For example, the L&S pattern can be formed by appropriately selecting from the forming directions that are often used in actual device manufacturing.

[0027] Here, L&S patterns with four different formation directions, specifically, L&S patterns with longitudinal directions of [00-1], [-11-2], [-11-1], and [-110], were formed on the surfaces of four wafers, one each. At this time, assuming various line widths, an L&S pattern with line widths from 1 to 10 μm at a pitch of 0.2 μm and a space width of 10 μm was formed.

[0028] The L&S pattern thus formed and a schematic diagram of its formation direction (orientation) are shown in Figure 2. The units of values ​​in Figure 2 are μm, and the symbol y is the space width of 10 μm. Additionally, a schematic diagram of the relationship between the notch position on the wafer and the longitudinal position of the L&S pattern is shown in Figure 3. Here, L&S patterns in four formation directions are shown together on the surface of a single wafer to make it easier to understand the relationship between the formation directions.

[0029] (Thermal oxide film formation process) After that, a thermal oxide film (SiO2 film) is formed. This thermal oxide film is formed on at least the wafer surface on which the L&S pattern is formed. It can be formed using a conventional heat treatment device. The purpose of forming a thermal oxide film is to apply a higher stress to the wafer than the film stress of the SiN film, which can generate a higher stress than would be generated by the SiN film alone, making dislocations, if any, more likely to become apparent. The conditions for forming the thermal oxide film at this time are not particularly limited, but for example, the thickness of the thermal oxide film to be formed can be in the range of 400 to 600 nm, the oxidation treatment atmosphere can be wet O2, the temperature can be 1000°C, and the time can be in the range of 150 to 250 minutes.

[0030] Although the thickness of the thermal oxide film is not particularly limited, it is preferable to set the thickness to 400 nm or more in order to prevent the film stress of the thermal oxide film from being small, which would reduce the local stress of the wafer and result in a low dislocation density, making it difficult to evaluate differences between formation directions. On the other hand, to prevent the occurrence of overlapping of individual dislocation pits after selective etching in a later process due to an excessively high dislocation density, it is preferable to set the thermal oxide film thickness to 600 nm or less. By setting the film thickness to such a value, the dislocation pit density can be measured more accurately in a later process.

[0031] In this case, a thermal oxide film with a thickness of 550 nm was formed. Furthermore, SEM observation of the cross section of the L&S pattern confirmed that the pattern was formed as designed, as shown in Figure 4.

[0032] (Dislocation pit revealing process) Next, a process including a first process for removing the thermal oxide film and a second process for making dislocations present in the areas where the L&S pattern is to be formed visible as dislocation pits by selective etching is carried out. [First process] Any method can be used as long as it can remove the formed thermal oxide film (SiO2 film), but it can be easily removed using, for example, hydrofluoric acid. [Second process] The selective etching solution is not particularly limited as long as it can reveal dislocations. For example, a solution with a 61% concentration of nitric acid, a ratio of hydrofluoric acid: 1: nitric acid: 15: acetic acid: 1: water: 4, and an etching time of 1 minute can be used (solution C in JIS H 0609).

[0033] Here, the selective etching solution was used to remove the thermal oxide film having a thickness of 550 nm and to expose the dislocations occurring in the space portions. If the thermal oxide film has a thickness of about 600 nm or less, it can be removed using a selective etching solution containing HF. In this way, depending on the thickness of the thermal oxide film, selective etching in the second process can conveniently perform both the removal of the thermal oxide film in the first process and the exposure of dislocation pits in the second process. Of course, the first and second processes can also be performed separately.

[0034] (Dislocation pit density measurement process) The density of the revealed dislocation pits is measured for each L&S pattern. For example, the dislocation pits can be observed and measured using a stereo microscope. Here, the results of observing dislocation pits made apparent by selective etching in the L&S patterns formed in the four different directions mentioned above using a stereomicroscope are shown in Figure 5. As can be seen from the observation in Figure 5, the density of dislocation pits differs depending on the direction in which the L&S pattern is formed. The results of actual measurements of dislocation pit density are shown in Figure 6. It can be seen that differences in the formation direction result in large numerical differences in dislocation pit density. The conditions for measuring the density of dislocation pits can be, for example, as follows. Pit size: 0.6 μm or more Other conditions: Measurement in air

[0035] (Formation direction determination process) From the measurement results of the dislocation pit density, the L&S pattern formation direction that results in the lowest dislocation pit density is determined to be the optimal formation direction among the formation directions of the multiple L&S patterns formed, and is evaluated. Comparing the dislocation pit density at the same line width, as shown in Figure 6, first, among the three formation directions, [-11-2], [-11-1], and [-110], the density value basically increases as the line width increases, with the relationship being [-11-2] ≒ [-11-1] < [-110]. On the other hand, it was found that no dislocation pits were observed in the remaining formation direction, [00-1], even when the line width was wide. Therefore, among these four formation directions, [00-1] had the lowest dislocation pit density and was determined to be the optimal formation direction.

[0036] By using the evaluation method of the present invention as described above, it is possible to evaluate the formation direction of the L&S pattern that can best suppress the occurrence of dislocations in the silicon single crystal wafer used for evaluation. Then, by actually forming the L&S pattern in the optimal formation direction based on this evaluation and manufacturing a semiconductor device, it is possible to obtain an excellent semiconductor device that can prevent deterioration of device characteristics due to the occurrence of dislocations.

[0037] In the above example, the case of a wafer with a (110) orientation was specifically explained, but the following will explain the case where a (001) orientation wafer is prepared and subjected to the same process. (Line&Space formation process) [Preparation of silicon single crystal wafer] ~ [Formation of L&S pattern with alternating formation direction] Five silicon single crystal wafers with a diameter of 300 mm, a resistivity of 10 Ω·cm, and a surface orientation of (001) were prepared as samples. After forming a 200 nm thick SiN film with a true stress of about 2 GPa on these samples, an L&S pattern with line widths from 1 to 10 μm at a 0.2 μm pitch and a space width of 10 μm was formed. Here, L&S patterns with five different formation directions, specifically L&S patterns with longitudinal directions of [1-10], [3-20], [2-10], [3-10], and

[0100] , were formed one on each of the five wafer surfaces.

[0038] The L&S pattern thus formed and a schematic diagram of its formation direction (orientation) are shown in Fig. 7. The units of values ​​in Fig. 7 are μm, and the symbol y is the space width of 10 μm. Additionally, a schematic diagram of the relationship between the notch position on the wafer and the longitudinal position of the L&S pattern is shown in Figure 8. Here, L&S patterns in five formation directions are shown together on the surface of a single wafer to make it easier to understand the relationship between the formation directions.

[0039] (Thermal oxide film formation process) After that, a thermal oxide film (SiO2 film) with a thickness of 550 nm was formed.

[0040] (Dislocation pit revealing process) [1st process]~[2nd process] After forming the thermal oxide film, selective etching was performed to reveal dislocations that occurred in the space area. Thermal oxide films with a thickness of approximately 600 nm or less can be removed using a selective etching solution containing HF.

[0041] (Dislocation pit density measurement process) Observation of dislocation pits revealed by selective etching using a stereomicroscope revealed that the density of dislocation pits differed depending on the direction of the L&S pattern formation. FIG. 9 shows the results of actual measurements of the dislocation pit density.

[0042] (Formation direction determination process) As shown in Figure 9, when comparing the dislocation pit densities for the same line width, it was found that [1-10] < [3-20] ≒ [2-10] ≒

[0100] ≒ [3-10]. Therefore, among these five formation directions, [1-10] had the lowest density of dislocation pits and was determined to be the optimal formation direction.

[0043] <Consideration> Here, we considered why the dislocation density (dislocation pit density) differs when the L&S pattern formation direction is changed in (110) wafers and (001) wafers. This is because, although the film stress due to the SiN film or thermal oxide film itself does not change depending on the pattern formation direction, the resolved shear stress related to the generation and propagation of dislocations differs depending on the pattern formation direction.

[0044] To confirm this, a finite element method model was created and a stress simulation was performed based on the cross-sectional SEM observation results in Figure 4. This simulation was performed using the commercially available software Femtet. The physical properties used in the calculation are: Silicon Young's modulus: 170 GPa, Poisson's ratio: 0.20, linear expansion coefficient: 3.0E-6K -1 , SiN Young's modulus: 300 GPa, Poisson's ratio: 0.25, linear expansion coefficient: 0.9E-6K -1 , True stress: 2.3GPa, SiO2 Young's modulus: 70GPa, Poisson's ratio: 0.17, linear expansion coefficient: 0.9E-6K -1 , True stress: 80GPa It was decided.

[0045] The six types of stresses (σxx, σyy, σzz, σzy, σzx, σxy) obtained by calculation were converted into resolved shear stresses (12 types of slip systems) that serve as the driving force for dislocation propagation in the cases where the pattern formation direction is [-11-1] on a (110) wafer and the pattern formation direction is

[0001] on a (110) wafer. Here, σxx, σyy, and σzz are normal stresses in each direction, and σzy, σzx, and σxy are shear stresses. The resolved shear stress is the shear stress acting in the direction of the slip on the slip plane. For example, in the case of (1-11) /

[0110] , it is the shear stress acting on the (1-11) plane in the

[0110] direction.

[0046] The simulation results are shown in Figures 10 and 11. Figure 10 shows the resolved shear stress distribution by finite element method analysis when the pattern formation direction on a (110) wafer is [-11-1]. Figure 11 shows the resolved shear stress distribution by finite element method analysis when the pattern formation direction on a (110) wafer is

[0001] . As shown in Figures 10 and 11, we found that even with the same slip system, the stress distribution differs depending on the pattern formation direction of the two. This is the reason why dislocation behavior differs even when the film stress is the same.

[0047] 10 and 11, the stress is distributed in the range of 500 to -500 MPa, and the difference between the positive and negative sides is the difference in the direction of the shear stress. For example, in the case of (1-11) /

[0110] , the shear stress acting on the (1-11) plane in the

[0110] direction is expressed as a positive value, and the shear stress acting in the opposite direction, the [-1-10] direction, is expressed as a negative value. 10 and 11, plus (+) signs are added to areas on the plus side, and minus (-) signs are added to areas on the minus side.

[0048] The evaluation method for silicon single crystal wafers of the present invention has been described above using (110) wafers and (001) wafers as examples, but the present invention is not limited to these and can also be applied to wafers with other surface orientations.

[0049] Next, a method for manufacturing a semiconductor device according to the present invention will be described. More specifically, this is a method for manufacturing a semiconductor device using an L&S pattern formed on the surface of a silicon single crystal wafer. In manufacturing this semiconductor device, the aforementioned evaluation method of the present invention is used when forming the L&S pattern. That is, the L&S pattern is formed in the optimal formation direction of the L&S pattern determined by the evaluation method. The formed L&S pattern is then subjected to, for example, an etching process to create a fin structure, tungsten metal electrodes are disposed, and the device is subjected to heat treatment to manufacture a semiconductor device. Note that the process is not limited to the above steps, and further processes as needed can be performed.

[0050] The semiconductor device manufactured in this manner can be one in which the generation and propagation of dislocations are suppressed, and therefore, the deterioration of device characteristics due to the generation of dislocations is suppressed, resulting in a device of excellent quality. [Example]

[0051] The present invention will be explained in more detail below by showing examples of the present invention, but the present invention is not limited to these examples. Example 1 Four silicon single crystal wafers with a diameter of 300 mm, a resistivity of 10 Ω·cm, and a surface orientation of (110) were prepared as samples. On these samples, a SiN film having a thickness of 200 nm and a true stress of about 2 GPa was formed (film formation conditions: LP-CVD method at a film formation temperature of 760°C). After that, an L&S pattern with a line width of 1 to 10 μm at a 0.2 μm pitch and a space width of 10 μm was formed. At that time, photolithography was performed so that the longitudinal directions of the L&S pattern were [00-1], [-11-2], [-11-1], and [-110]. In this way, L&S patterns with different formation directions were formed for each sample.

[0052] Thereafter, a thermal oxide film having a thickness of 500 nm was formed (film formation conditions: wet oxidation treatment at a temperature of 1000° C.). After forming this thermal oxide film, the thermal oxide film was removed by selective etching (selective etching solution: 61% nitric acid, with a ratio of hydrofluoric acid: 1, nitric acid: 15, acetic acid: 1, water: 4), and the dislocations that had occurred in the space areas were made apparent. Dislocation pits revealed by selective etching were observed using a stereo microscope (DSX510 manufactured by Olympus Corporation), and it was found that the density of dislocation pits differed depending on the pattern formation direction. When the dislocation density was actually measured under the following conditions, the same tendency as in Figure 6 was observed. In other words, it was found that setting the pattern formation direction to [00-1] was the most effective way to suppress dislocations among the four formation directions mentioned above. <Dislocation pit density measurement conditions> Stereomicroscope observation in air

[0053] Therefore, using the same (110) wafer as above, an L&S pattern was formed so that the formation direction was [00-1]. More specifically, after forming a SiN film on the wafer surface in the same manner as above, an L&S pattern with a line width of 10 μm and a space width of 10 μm was formed (no thermal oxide film was formed). After that, the fin was etched into a shape, tungsten metal electrodes were placed around it, and heat treatment was performed at 1000°C. After that, the fin portion was observed with a transmission electron microscope (SU-8000 manufactured by Hitachi High-Technologies Corporation), and it was found that no dislocations had occurred.

[0054] Example 2 Five silicon wafers with a diameter of 300 mm, a resistivity of 10 Ω·cm, and a surface orientation of (001) were prepared as samples. In the same manner as in Example 1, a SiN film having a thickness of 200 nm and a true stress of about 2 GPa was formed on each of these samples. After that, an L&S pattern with a line width of 1 to 10 μm at a 0.2 μm pitch and a space width of 10 μm was formed. Photolithography was performed so that the longitudinal directions of the L&S pattern were [1-10], [3-20], [2-10], [3-10], and

[0100] . In this way, L&S patterns with different formation directions were formed for each sample.

[0055] Thereafter, in the same manner as in Example 1, a thermal oxide film was formed to a thickness of 500 nm. After forming this thermal oxide film, the thermal oxide film was removed by selective etching in the same manner as in Example 1, and dislocations occurring in the space portions were made apparent. As in Example 1, dislocation pits that had become apparent through selective etching were observed under a stereomicroscope, and it was found that the density of dislocation pits differed depending on the pattern formation direction. When the dislocation density was actually measured, the same tendency as in Figure 9 was observed. In other words, it was found that the pattern formation direction [1-10] was the most effective in suppressing dislocations among the five formation directions mentioned above.

[0056] Therefore, using the same (001) wafer as above, we formed an L&S pattern with a pattern orientation of [1-10]. More specifically, after forming a SiN film on the wafer surface in the same manner as above, we formed an L&S pattern with a line width of 10 μm and a space width of 10 μm (no thermal oxide film was formed). After that, the fin was etched into a shape, tungsten metal electrodes were placed around it, and heat treatment was performed at 1000°C. After that, the fin was observed with a transmission electron microscope, and the dislocation pit density was found to be approximately 1.0 × 10 7 / cm 2 It was found that this was a lower result than that of Comparative Example 2 (in which the surface orientation of the sample wafer was the same as that of Example 2) described later.

[0057] (Comparative Example 1) As a sample, a silicon single crystal wafer with a diameter of 300 mm, a resistivity of 10 Ω·cm, and a surface orientation of (110) was prepared. Using this (110) wafer, the L&S pattern was formed so that its formation direction was [-11-2], without any particular investigation into the relationship between the formation direction of the L&S pattern and dislocations. After that, the fin was etched into a shape, tungsten metal electrodes were placed around it, and heat treatment was performed at 1000°C. After that, the fin was observed with a transmission electron microscope, and the dislocation pit density was found to be approximately 1.0 × 10 7 / cm 2 This resulted in a deterioration in device characteristics.

[0058] (Comparative Example 2) A silicon single crystal wafer with a diameter of 300 mm, a resistivity of 10 Ω·cm, and a surface orientation of (001) was prepared as a sample. Using this (001) wafer, the L&S pattern was formed so that its formation direction was

[0100] , without any particular investigation into the relationship between the formation direction of the L&S pattern and dislocations. After that, the fin was etched into a shape, tungsten metal electrodes were placed around it, and heat treatment was performed at 1000°C. After that, the fin was observed with a transmission electron microscope, and the dislocation pit density was found to be approximately 1.7 × 10 7 / cm 2 This resulted in a deterioration in device characteristics.

[0059] (Comparative Example 3) Four silicon single crystal wafers with a diameter of 300 mm, a resistivity of 10 Ω·cm, and a surface orientation of (110) were prepared as samples. In the same manner as in Example 1, a SiN film having a thickness of 200 nm and a true stress of about 2 GPa was formed on each of these samples. After that, an L&S pattern with a line width of 1 to 10 μm at a 0.2 μm pitch and a space width of 10 μm was formed. Photolithography was performed so that the longitudinal directions of the L&S pattern were [00-1], [-11-2], [-11-1], and [-110]. In this way, L&S patterns with different formation directions were formed for each sample.

[0060] Thereafter, a heat treatment was carried out in a nitrogen atmosphere at 1000°C for 5 minutes to generate dislocations. Thereafter, in the same manner as in Example 1, dislocations occurring in the space portions were made apparent by selective etching. In the same manner as in Example 1, dislocation pits that had become apparent by selective etching were observed under a stereomicroscope, and their density was measured. The results are shown in Figure 12. As shown in Figure 12, when the pattern formation direction was [-110], it was found that dislocations occurred at a high density, but in all of the other pattern formation directions ([00-1], [-11-2], and [-11-1]), the dislocation density was low, and it was not possible to determine which pattern formation direction could actually suppress the occurrence of dislocations. In fact, as already mentioned in Example 1, unlike [-11-2] or [-11-1], [00-1] is the formation direction that can best suppress the occurrence of dislocations.

[0061] Thus, in Comparative Examples 1 and 2, in which the evaluation method of the present invention was not implemented, dislocations were generated. In Comparative Example 3, no difference in the density of dislocation pits was found in the formation directions other than [-110], and it was not possible to determine the optimal formation direction. This indicates that the stress generated by the SiN film alone is insufficient, and that stress from a thermal oxide film, as in Examples 1 and 2, is necessary.

[0062] The present specification includes the following aspects. [1]: A method for evaluating silicon single crystal wafers used when manufacturing semiconductor devices using line and space patterns, a line & space forming step of forming a plurality of line & space patterns on the surface of the silicon single crystal wafer using a SiN film by changing the direction of forming the line & space patterns; a thermal oxide film forming step of forming a thermal oxide film on the surface of the silicon single crystal wafer on which the line & space pattern is formed; a dislocation pit revealing step including a first step of removing the thermal oxide film and a second step of revealing dislocations present in the area where the line and space pattern is to be formed as dislocation pits by selective etching; a dislocation pit density measuring step of measuring the density of the revealed dislocation pits for each of the line and space patterns; a formation direction determining step of determining and evaluating the formation direction of the line and space pattern having the lowest density of dislocation pits based on the measurement results of the density of dislocation pits as the optimal formation direction among the formation directions of the plurality of line and space patterns formed; A method for evaluating a silicon single crystal wafer, comprising: [2]: The method for evaluating a silicon single crystal wafer according to the above [1], wherein in the thermal oxide film forming step, the thermal oxide film is formed to a thickness of 400 to 600 nm. [3]: The method for evaluating a silicon single crystal wafer according to [1] or [2] above, wherein in the dislocation pit revealing step, the removal of the thermal oxide film in the first treatment and the revealing of the dislocation pits in the second treatment are both carried out by the selective etching. [4]: A method for manufacturing a semiconductor device using a line and space pattern formed on the surface of a silicon single crystal wafer, When the line and space pattern is formed in the manufacturing of the semiconductor device, A method for manufacturing a semiconductor device, in which the line and space pattern is formed in the optimal formation direction determined by the silicon single crystal wafer evaluation method according to any one of [1] to [3] above.

[0063] The present invention is not limited to the above-described embodiments. The above-described embodiments are merely examples, and any configuration that is substantially identical to the technical idea described in the claims of the present invention and that provides similar effects is included within the technical scope of the present invention.

Claims

1. A method for evaluating a silicon single crystal wafer used when manufacturing a semiconductor device using a Line & Space pattern, comprising: a line & space forming step of forming a plurality of line & space patterns on the surface of the silicon single crystal wafer using a SiN film by changing the direction in which the line & space patterns are formed; a thermal oxide film forming step of forming a thermal oxide film on the surface of the silicon single crystal wafer on which the line & space pattern is formed; a dislocation pit revealing step including a first process of removing the thermal oxide film and a second process of revealing dislocations present in the formation portion of the line and space pattern as dislocation pits by selective etching; a dislocation pit density measuring step of measuring the density of the revealed dislocation pits for each of the line and space patterns; a formation direction determining step of determining and evaluating the formation direction of the Line & Space pattern having the lowest density of dislocation pits from the measurement result of the density of dislocation pits as the optimal formation direction among the formation directions of the plurality of Line & Space patterns formed; A method for evaluating a silicon single crystal wafer, comprising:

2. 2. The silicon single crystal wafer evaluation method according to claim 1, wherein in the thermal oxide film forming step, the thermal oxide film is formed to a thickness of 400 to 600 nm.

3. 2. The silicon single crystal wafer evaluation method according to claim 1, wherein in the dislocation pit revealing step, the removal of the thermal oxide film in the first treatment and the revealing of the dislocation pits in the second treatment are both performed by the selective etching.

4. 3. The silicon single crystal wafer evaluation method according to claim 2, wherein in the dislocation pit revealing step, the removal of the thermal oxide film in the first treatment and the revealing of the dislocation pits in the second treatment are both performed by the selective etching.

5. A method for manufacturing a semiconductor device using a Line & Space pattern formed on a surface of a silicon single crystal wafer, comprising: When forming the Line & Space pattern in the manufacturing of the semiconductor device, 5. A method for manufacturing a semiconductor device, comprising forming the Line & Space pattern in an optimal formation direction determined by the silicon single crystal wafer evaluation method according to claim 1.

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