Power supply system

Abstract

To achieve a detection function of power supply abnormality of a plurality of power supply devices and a safe stop function of a power supply device in which abnormality occurs while suppressing an increase in circuit scale.SOLUTION: A power supply system includes a plurality of power supply devices each configured to generate an output voltage when a corresponding control signal among a plurality of control signals is in an enabled state, a control device configured to output the plurality of control signals to the plurality of power supply devices, and a plurality of abnormal voltage detection circuits provided corresponding to the plurality of power supply devices, respectively, and configured to detect whether or not the output voltages generated by the plurality of power supply devices are abnormal, and an abnormality transmission circuit that transmits a plurality of detection results by the plurality of abnormal voltage detection circuits to the control device by a serial signal, wherein the control device outputs the control signal in a disabled state to a power supply device in which an abnormality is detected among the plurality of power supply devices based on the plurality of detection results to stop the operation, and then outputs the control signal in an enabled state.SELECTED DRAWING: Figure 1

Description

[Technical Field]

[0001] The present invention relates to a power supply system. [Background technology]

[0002] In a power supply device that generates multiple types of power supply voltages or multiple power supply devices that each generate multiple types of power supply voltages, a method is known in which a voltage abnormality detection circuit that detects abnormalities in the power supply voltage and a current abnormality detection circuit that detects abnormalities in the power supply current are provided for each of the multiple types of power supply voltages. [Prior art documents] [Patent documents]

[0003] [Patent Document 1] Japanese Patent Application Laid-Open No. 2001-312318 Summary of the Invention [Problem to be solved by the invention]

[0004] For example, if a control device that controls multiple power supply devices detects an abnormality in the power supply voltage or power supply current for each power supply device and shuts down the power supply device in which the abnormality occurred, the control device must receive a notification of the power supply voltage abnormality and a notification of the power supply current abnormality from each of the multiple power supply devices. In this case, multiple signal lines for notifying the abnormality must be wired between the multiple power supply devices and the control device. This increases the circuit size of a power supply system that has multiple power supply devices and control devices, and increases system costs.

[0005] The disclosed technology aims to realize a function for detecting power supply abnormalities in a plurality of power supply devices and a function for safely shutting down a power supply device in which an abnormality has occurred, while suppressing an increase in circuit size. [Means for solving the problem]

[0006] In order to solve the above technical problems, a power supply system of one embodiment of the present invention comprises a plurality of power supply devices that each generate an output voltage when a corresponding one of a plurality of control signals is in an enabled state; a control device that outputs the plurality of control signals to the plurality of power supply devices; and an abnormality transmission circuit that includes a plurality of abnormal voltage detection circuits that are provided corresponding to each of the plurality of power supply devices and detect whether the output voltages generated by the plurality of power supply devices are abnormal, and transmits a plurality of detection results by the plurality of abnormal voltage detection circuits to the control device as a serial signal, wherein the control device outputs an invalid control signal to a power supply device among the plurality of power supply devices that has been detected to be abnormal based on the plurality of detection results, thereby stopping its operation, and then outputs a valid control signal. [Effects of the Invention]

[0007] It is possible to realize a function for detecting power supply abnormalities in a plurality of power supply devices and a function for safely shutting down a power supply device in which an abnormality has occurred, while suppressing an increase in circuit size. [Brief explanation of the drawings]

[0008] [Figure 1] 1 is an example of a block diagram showing a first embodiment of a power supply system according to the present invention. [Figure 2] FIG. 2 is an example of a block diagram illustrating an overview of the power supply device of FIG. 1. [Figure 3] 3 is a circuit diagram showing a specific example of the power supply device of FIG. 2. [Figure 4] 4 is a timing diagram showing an example of operation of the power supply device of FIG. 3. [Figure 5] 2 is a timing chart showing an example of serial data transmitted from the parallel-to-serial conversion circuit of FIG. 1 to a microcomputer. [Figure 6] FIG. 10 is a block diagram illustrating an example of a circuit for detecting a voltage abnormality in another power supply system. [Figure 7] FIG. 4 is an example of a block diagram showing a second embodiment of a power supply system according to the present invention. DETAILED DESCRIPTION OF THE INVENTION

[0009] Hereinafter, the embodiments will be described with reference to the drawings. In the following, the same symbols as the signal names may be used for signal lines, signal terminals, signal nodes, and signal values ​​through which signals are transmitted. The same symbols as the voltage names may be used for voltage lines, voltage terminals, and voltage nodes through which voltages are supplied. In each drawing, the same components are given the same symbols, and duplicated explanations may be omitted.

[0010] (Example of power supply system of first embodiment) Fig. 1 is an example of a block diagram showing a first embodiment of a power supply system according to the present invention. The power supply system SYS shown in Fig. 1 generates power supply voltages used by, for example, a servo motor encoder, a servo amplifier, a PLC (Programmable Logic Controller), a data collection device, and the like included in a servo system. Note that the power supply system SYS may also generate multiple types of power supply voltages used by multiple devices included in a system other than the servo system.

[0011] The power supply system SYS shown in FIG. 1 includes multiple power supply devices 100(1), 100(2), 100(3), and 100(4), a power supply monitoring circuit 200, and a microcomputer 300. Hereinafter, when the power supply devices 100(1)-100(4) are not to be distinguished from one another, they will also be referred to as power supply devices 100. The power supply system SYS has the function of detecting abnormalities such as overvoltage, undervoltage, and overcurrent in each power supply device 100, and safely shutting down and restarting only the power supply device in which an abnormality has occurred. While the power supply system SYS in FIG. 1 includes four power supply devices 100, the number of power supply devices 100 is not limited to four, as long as it is two or more. The microcomputer 300 is an example of a control device that controls each of the multiple power supply devices 100.

[0012] The power supply devices 100(1)-100(4) operate while the control signals EN1, EN2, EN3, and EN4 received from the microcomputer 300 are at assert levels (e.g., high levels) and generate output voltages VOUT1, VOUT2, VOUT3, and VOUT4 using the input voltage VIN. The power supply devices 100(1)-100(4) stop operating while the control signals EN1, EN2, EN3, and EN4 received from the microcomputer 300 are at negate levels (e.g., low levels), and stop generating the output voltages VOUT1, VOUT2, VOUT3, and VOUT4.

[0013] The output voltages VOUT1-VOUT4 are supplied to the power supply monitoring circuit 200 and to loads connected to the power supply devices 100(1)-100(4), respectively. For example, the loads may be servo motor encoders, servo amplifiers, PLCs, data collection devices, etc. The values ​​of the output voltages VOUT1-VOUT4 may be different from one another, may be the same as one another, or may be different from one another and the rest may be the same.

[0014] Furthermore, when the power supply devices 100(1)-100(4) detect an overcurrent in the current flowing through the input voltage line VIN in each power supply device 100, they transmit overcurrent detection signals OCFLG1, OCFLG2, OCFLG3, and OCFLG4 to the microcomputer 300, respectively (OC stands for Over Current). Hereinafter, when the output voltages VOUT1, VOUT2, VOUT3, and VOUT4 are not distinguished from one another, they are also referred to as output voltage VOUT. When the control signals EN1, EN2, EN3, and EN4 are not distinguished from one another, they are also referred to as control signals EN. When the overcurrent detection signals OCFLG1, OCFLG2, OCFLG3, and OCLFG4 are not distinguished from one another, they are also referred to as overcurrent detection signals OCFLG.

[0015] By transmitting the overcurrent detection signal OCFLG to the microcomputer 300 for each power supply device 100, the microcomputer 300 can use the control signal EN to stop and restart only the power supply device 100 in which an overcurrent has occurred. This allows the power supply device 100 in which an abnormality has occurred to be restored from the abnormal state without shutting down the entire power supply system SYS.

[0016] The power supply monitoring circuit 200 has a plurality of abnormal voltage detection circuits 210(1), 210(2), 210(3), and 210(4) corresponding to each power supply device 100, and a parallel-serial conversion circuit 220. Hereinafter, when the abnormal voltage detection circuits 210(1), 210(2), 210(3), and 210(4) are not to be distinguished from one another, they will also be referred to as abnormal voltage detection circuits 210. The power supply monitoring circuit 200 is an example of an abnormality transmission circuit that transmits the detection results of each of the plurality of abnormal voltage detection circuits 210, indicating whether the output voltage is abnormal, to the microcomputer 300 via serial output.

[0017] The parallel-serial conversion circuit 220 has a data latch 211 and a shift register 212, and is connected to the microcomputer 300 using an SPI (Serial Peripheral Interface) interface (I / F). The SPI interface shown in FIG. 1 includes a chip select signal, a clock signal CLK, and a data signal SDO, and transmits data from the parallel-serial conversion circuit 220 to the microcomputer 300.

[0018] The microcomputer 300 operates as a master of the SPI interface and outputs a chip select signal CS and a clock signal CLK to the parallel-serial conversion circuit 220. The parallel-serial conversion circuit 220 operates as a slave of the SPI interface and outputs a data signal SDO. Note that data from the parallel-serial conversion circuit 220 to the microcomputer 300 is transmitted via the I 2 It may also be transmitted using other serial interfaces such as an Inter-Integrated Circuit (C) interface.

[0019] The abnormal voltage detection circuits 210(1)-210(4) are identical except for the resistance values ​​of the built-in resistors. Therefore, the circuit configuration and operation of the abnormal voltage detection circuit 210(1) will be described below. Note that when multiple abnormal voltage detection circuits 210 receive the same output voltage VOUT, the resistance values ​​of the three built-in resistors may be the same for each resistor.

[0020] The abnormal voltage detection circuit 210(1) has resistors R11, R12, and R13 connected in series between the output voltage line VOUT1 and the ground line, and comparators CMPO and CMPU. The negative and positive inputs of the comparator CMPO are connected to the connection node of the resistors R11 and R12 and the reference voltage line VREF1, respectively. The positive and negative inputs of the comparator CMPU are connected to the connection node of the resistors R12 and R13 and the reference voltage line VREF1, respectively.

[0021] When the voltage at the connection node of the resistors R11 and R12 is equal to or higher than the reference voltage VREF1, the comparator CMPO detects that the output voltage VOUT1 is an overvoltage higher than the first determination voltage (first abnormality), and outputs a low-level overvoltage detection signal OV (Over Voltage) 1. When the voltage at the connection node of the resistors R11 and R12 is lower than the reference voltage VREF1, the comparator CMPO detects that the output voltage VOUT1 is not an overvoltage, and outputs a high-level overvoltage detection signal OV1.

[0022] When the voltage at the connection node between resistors R12 and R13 is lower than the reference voltage VREF1, the comparator CMPU detects that the output voltage VOUT1 is an undervoltage (second abnormality) lower than the second determination voltage, and outputs a low-level undervoltage detection signal UV (Under Voltage)1. Here, the second determination voltage is lower than the first determination voltage. When the voltage at the connection node between resistors R12 and R13 is equal to or higher than the reference voltage VREF1, the comparator CMPU detects that the output voltage VOUT1 is not an undervoltage, and outputs a high-level undervoltage detection signal UV1.

[0023] As described above, when the output voltage VOUT1 is an overvoltage, the overvoltage detection signal OV1 and the undervoltage detection signal UV1 go low and high, respectively. When the output voltage VOUT1 is neither an overvoltage nor an undervoltage and is within the normal range, both the overvoltage detection signal OV1 and the undervoltage detection signal UV1 go high. When the output voltage VOUT1 is an undervoltage, the overvoltage detection signal OV1 and the undervoltage detection signal UV1 go high and low, respectively.

[0024] Like the abnormal voltage detection circuit 210(1), the abnormal voltage detection circuit 210(2) outputs a low-level overvoltage detection signal OV2 when it detects an overvoltage of the output voltage VOUT2, and outputs a low-level undervoltage detection signal UV2 when it detects an undervoltage of the output voltage VOUT2. The abnormal voltage detection circuit 210(3) outputs a low-level overvoltage detection signal OV3 when it detects an overvoltage of the output voltage VOUT3, and outputs a low-level undervoltage detection signal UV3 when it detects an undervoltage of the output voltage VOUT3. The abnormal voltage detection circuit 210(4) outputs a low-level overvoltage detection signal OV4 when it detects an overvoltage of the output voltage VOUT4, and outputs a low-level undervoltage detection signal UV4 when it detects an undervoltage of the output voltage VOUT4.

[0025] As described above, each abnormal voltage detection circuit 210 can individually detect an overvoltage or undervoltage in the output voltage VOUT of the corresponding power supply device 100, and can notify the microcomputer 300 of the detection result.

[0026] The data latch 211 of the parallel-serial conversion circuit 220 latches the logical values ​​of the overvoltage detection signals OV1-OV4 and the undervoltage detection signals UV1-UV4 received in parallel from the plurality of abnormal voltage detection circuits 210, and stores the latched logical values ​​in parallel in the shift register 212. Hereinafter, data indicating the logical values ​​of the overvoltage detection signals OV1-OV4 latched in the data latch 211 will also be referred to as data OV1-OV4. Data indicating the logical values ​​of the undervoltage detection signals UV1-UV4 latched in the data latch 211 will also be referred to as data UV1-UV4. Each of the data OV1-OV4 is an example of first data indicating whether or not there is an overvoltage, and each of the data UV1-UV4 is an example of second data indicating whether or not there is an undervoltage.

[0027] Shift register 212 sequentially outputs the held data OV1-OV4, UV1-UV4 serially to microcomputer 300 in synchronization with clock signal CLK while chip select signal CS is at assert level. This makes it possible to transmit a plurality of data OV indicating whether each output voltage VOUT is an overvoltage or not and a plurality of data UV indicating whether each output voltage VOUT is an undervoltage or not to microcomputer 300 using a minimum number of signal lines, even when a large number of power supply devices 100 are mounted in power supply system SYS. Shift register 212 is an example of a data converter that converts data OV1-OV4, UV1-UV4 latched by data latch 211 into serial data.

[0028] Since an increase in the number of signal lines can be suppressed, it is possible to suppress an increase in the size of a system board on which the power supply device 100, the power supply monitoring circuit 200, and the microcomputer 300 are mounted, for example. Therefore, an increase in the circuit scale of the power supply system SYS can be suppressed, and an increase in system costs can be suppressed.

[0029] The microcomputer 300 controls the operation of the multiple power supply devices 100 and also controls the transfer of data OV1-OV4 and UV1-UV4 from the power supply monitoring circuit 200. The microcomputer 300 also receives an overcurrent detection signal OCFLG from each power supply device 100. The microcomputer 300 has an abnormal voltage determination circuit 310 and an overcurrent determination circuit 320.

[0030] The abnormal voltage determination circuit 310 determines whether the output voltages VOUT1-VOUT4 are an overvoltage or an undervoltage based on the logical values ​​of the data OV1-OV4 and UV1-UV4 sequentially received from the parallel-serial conversion circuit 220 via the data line SDO. In other words, the abnormal voltage determination circuit 310 detects the occurrence of an overvoltage or an undervoltage for each power supply device 100.

[0031] The overcurrent determination circuit 320 determines whether an overcurrent has occurred for each power supply device 100 based on the logical values ​​of the overcurrent detection signals OCFLG1-OCFLG4 received from each power supply device 100. In other words, the overcurrent determination circuit 320 detects the occurrence of an overcurrent for each power supply device 100.

[0032] When the abnormal voltage determination circuit 310 detects the occurrence of an abnormal voltage (overvoltage or undervoltage), or when the overcurrent determination circuit 320 detects the occurrence of an abnormal current (overcurrent), the microcomputer 300 changes the control signal EN corresponding to the power supply device 100 in which the abnormality has occurred to low level, thereby stopping the operation of the power supply device 100 in which the abnormality has occurred. Thereafter, the microcomputer 300 changes the control signal EN corresponding to the power supply device 100 in which the abnormality has occurred to high level, thereby restarting the operation of the power supply device 100 in which the abnormality has occurred. The high level of the control signal EN is an example of an active state, and the low level of the control signal EN is an example of an inactive state.

[0033] Since the microcomputer 300 can independently shut down and then independently restart only the power supply device 100 in which an abnormality has occurred, it is possible to safely shut down only the power supply device 100 in which an abnormality has occurred and restore the system from the abnormal state without shutting down the entire power supply system SYS. By providing an abnormal voltage determination circuit 310 for each power supply device 100, it is possible to achieve power supply redundancy, for example, by operating two power supply devices 100 exclusively. In this case, the exclusive operation of the power supply devices 100 can be easily achieved by the control signal EN output by the microcomputer 300.

[0034] (Power supply overview) FIG. 2 is an example of a block diagram showing an overview of the power supply device 100 of FIG. 1. FIG. 1 shows one of the four power supply devices 100 of FIG. 1. For example, the power supply device 100 is an LDO (Low Drop Out). Note that the power supply device 100 may be a DC (Direct Current) / DC converter or an AC (Alternating Current) / DC converter that converts AC voltage to DC voltage. The power supply device 100 includes a start-up circuit 110, a voltage generation circuit 120, an overcurrent detection circuit 130, a latch mask circuit 140, a latch circuit 150, a buffer BUF1, and an AND circuit AND.

[0035] While the control signal EN is at a high level, the start-up circuit 110 generates a reference voltage VREF and outputs it to the voltage generation circuit 120. While the control signal EN is at a low level, the start-up circuit 110 stops generating the reference voltage VREF and sets the reference voltage line VREF to, for example, 0 V. The control signal EN is output to the latch circuit 150 as a control signal VRISE via a buffer BUF1.

[0036] The voltage generating circuit 120 generates the output voltage VOUT from the input voltage VIN using the reference voltage VREF while receiving a positive reference voltage VREF and a low-level (enabled) enable signal / VEN. The voltage generating circuit 120 stops generating the output voltage VOUT while receiving a 0V reference voltage VREF or a high-level (disabled) enable signal / VEN.

[0037] The overcurrent detection circuit 130 monitors, as a voltage, the current flowing from the input voltage line VIN connected to the voltage generation circuit 120 to the ground line via an external resistor RLIM, and detects whether the current flowing from the input voltage line VIN to the output voltage line VOUT is an overcurrent.

[0038] The overcurrent detection circuit 130 outputs a high-level overcurrent detection signal OC to the AND circuit AND when an overcurrent is detected, and outputs a low-level overcurrent detection signal OC to the AND circuit AND when an overcurrent is not detected. Note that the overcurrent detected by the overcurrent detection circuit 130 also includes a rush current that occurs when the power supply device 100 is started up.

[0039] The latch mask circuit 140 outputs a low-level latch mask signal LMSK while the overcurrent detection signal OC is at a high level. The latch mask circuit 140 outputs a high-level latch mask signal LMSK while an overcurrent flows through the input voltage line VIN, charging the capacitor CD, and the voltage VCD of the capacitor CD is equal to or higher than a predetermined voltage.

[0040] The AND circuit AND stops outputting the high-level overcurrent detection signal OC indicating an overcurrent to the latch circuit 150 while the latch mask signal LMSK is at a low level. In this case, the AND circuit AND fixes the overcurrent detection signal OC1 to a low level. While the latch mask signal LMSK is at a high level, the AND circuit AND outputs the high-level overcurrent detection signal OC indicating an overcurrent as the overcurrent detection signal OC1 to the latch circuit 150. This makes it possible to output only the high-level overcurrent detection signal OC indicating the occurrence of an overcurrent, out of the high-level overcurrent detection signals OC output by the overcurrent detection circuit 130 when it detects an overcurrent or a rush current, to the latch circuit 150 as the overcurrent detection signal OC1.

[0041] The latch circuit 150 latches the high level of the overcurrent detection signal OC1 caused by the occurrence of an overcurrent while the control signal VRISE synchronized with the control signal EN is at high level, and outputs a high level enable signal / VEN and a low level overcurrent detection signal OCFLG. While the control signal VRISE is at high level, the latch circuit 150 outputs a low level enable signal / VEN and a high level overcurrent detection signal OCFLG until it receives a high level overcurrent detection signal OC1 from the AND circuit AND.

[0042] While the control signal VRISE is at low level, the latch circuit 150 continues to output the already latched high-level enable signal / VEN and low-level overcurrent detection signal OCFLG. When the control signal VRISE becomes high level again, the latch circuit 150 releases the latch, sets the enable signal / VEN to low level, and sets the overcurrent detection signal OCFLG to high level.

[0043] This makes it possible to stop generation of the output voltage VOUT from the time an overcurrent is detected until the power supply device 100 is restarted. As a result, it is possible to prevent the voltage generating circuit 120 from generating an abnormal output voltage VOUT during the period from the time an overcurrent is detected until the microcomputer 300 negates the control signal EN, thereby preventing malfunction of the power supply device 100 and the power supply system SYS. The overcurrent detection signal OCFLG may be output from a circuit (not shown) that receives the enable signal / VEN.

[0044] The overcurrent detection signal OCFLG is transmitted to the microcomputer 300 of Fig. 1. When the microcomputer 300 receives the low-level overcurrent detection signal OCFLG, it detects that an overcurrent has occurred in the power supply device 100 that transmitted the overcurrent detection signal OCFLG. The microcomputer 300 then sets the high-level control signal EN that it is outputting to the power supply device 100 that transmitted the overcurrent detection signal OCFLG to a low level, and then returns the control signal EN to a high level, thereby restarting the power supply device 100 in which an overcurrent has occurred.

[0045] (Example of power supply unit) FIG. 3 is a circuit diagram showing a specific example of the power supply device 100 of FIG. 2. In FIG. 3, circles attached to a rectangular frame showing the power supply device 100 indicate terminals. The terminal receiving the input voltage VIN is an example of a first terminal, and the terminal outputting the output voltage VOUT is an example of a second terminal. In addition to the circuit shown in FIG. 2, the power supply device 100 has a buffer BUF2 and a transistor Tr4. A pull-up resistor RPUP is connected between the overcurrent detection signal line OCFLG and the power supply line VCC of the power supply device 100. The output voltage line VOUT of the power supply device 100 has a load capacitance Cout.

[0046] The start-up circuit 110 includes a bias circuit 201 and a reference voltage generation circuit 202. The bias circuit 201 is connected to an input voltage line VIN, and starts the reference voltage generation circuit 202 in synchronization with the rising edge of a control signal EN received via a buffer BUF1, causing the reference voltage generation circuit 202 to generate a reference voltage VREF. The bias circuit 201 causes the reference voltage generation circuit 202 to stop generating the reference voltage VREF while the control signal EN is low, and sets the reference voltage line VREF to a low level (0 V or a negative voltage). Furthermore, the bias circuit 201 connects the input voltage line VIN to a capacitor CD while the control signal EN is high, charging the capacitor CD.

[0047] The voltage generating circuit 120 includes a comparator CMP1, a transistor Tr1, and resistors R4 and R5 connected in series. The comparator CMP1 has a negative input connected to a reference voltage line VREF, a positive input connected to the connection node between the resistors R4 and R5, and an output connected to the base of the transistor Tr1. The transistor Tr1 is a PNP transistor with an emitter connected to the input voltage line VIN, a collector connected to the output voltage line VOUT, and a base connected to the output of the comparator CMP1. The transistor Tr1 and resistors R4 and R5 are arranged in series between the input voltage line VIN and the ground line.

[0048] The + input of comparator CMP1 is supplied with a voltage obtained by dividing the output voltage VOUT by resistors R4 and R5, and the reference voltage VREF supplied to the - input of comparator CMP1 is set to the voltage that appears between resistors R4 and R5 when the output voltage VOUT is at the target voltage.

[0049] While receiving a high-level (disabled) enable signal / VEN, comparator CMP1 outputs a high-level output voltage VOUT to the base of transistor Tr1, turning off transistor Tr1. While receiving a low-level (enabled) enable signal / VEN, comparator CMP1 controls the base voltage of transistor Tr1 according to the difference between the output voltage VOUT and the target voltage, causing transistor Tr1 to generate the output voltage VOUT.

[0050] When the enable signal VEN is at a low level and the voltage at the connection node between the resistors R4 and R5 is lower than the reference voltage VREF, the voltage generation circuit 120 lowers the base voltage of the transistor Tr1 to lower the on-resistance of the transistor Tr1. In other words, when the output voltage VOUT is lower than the target voltage, the voltage generation circuit 120 supplies a control voltage to the base of the transistor Tr1 that lowers the on-resistance of the transistor Tr1 the lower the output voltage VOUT is below the target voltage, thereby controlling the output voltage VOUT to approach the target voltage.

[0051] The voltage generating circuit 120 turns off the transistor Tr1 by increasing the base voltage of the transistor Tr1 while the enable signal VEN is at a high level or when the voltage at the connection node of the resistors R4 and R5 is equal to or higher than the reference voltage VREF. That is, the voltage generating circuit 120 turns off the transistor Tr1 when an overcurrent occurs and the enable signal VEN becomes high level, or when the output voltage VOUT is equal to or higher than the target voltage.

[0052] The overcurrent detection circuit 130 includes a transistor Tr2 and a comparator CMP2. The transistor Tr2 is a PNP transistor with an emitter connected to the input voltage line VIN, a collector connected to the positive input of the comparator CMP2 and one end of a resistor RLIM, and a base connected to the output of the comparator CMP1. The other end of the resistor RLIM is connected to the ground line. The transistor Tr2 operates as a current mirror circuit together with the transistor Tr1.

[0053] The comparator CMP2 has a positive input connected to the emitter of the transistor Tr2, a negative input connected to a threshold voltage line Vth2, and an output connected to an overcurrent detection signal line OC. When the voltage generated at one end of the resistor RLIM by the current flowing through the transistor Tr2 is lower than the threshold voltage Vth2, the comparator CMP2 outputs a low-level overcurrent detection signal OC indicating that no overcurrent is occurring.

[0054] When the voltage generated at one end of resistor RLIM by the current flowing through transistor Tr2 exceeds threshold voltage Vth2, comparator CMP2 outputs a high-level overcurrent detection signal OC indicating the occurrence of an overcurrent. For example, threshold voltage Vth2 is set to a value slightly lower than the voltage generated at one end of resistor RLIM when an overcurrent flows through transistors Tr1 and Tr2.

[0055] By using the external resistor RLIM, the current flowing through transistors Tr1 and Tr2 when an overcurrent is detected can be kept below the rated current of transistors Tr1 and Tr2, preventing damage to transistors Tr1 and Tr2.

[0056] When a rush current flows due to charging of the capacitor CD at the start of the power supply device 100, the load capacitance Cout is also charged, and a rush current also flows in the output voltage line VOUT. Therefore, the overcurrent detection circuit 130 can detect both an overcurrent and a rush current. That is, the overcurrent detection signal OC changes to a high level when an overcurrent or a rush current occurs.

[0057] The latch mask circuit 140 includes a transistor Tr3 and a comparator CMP3. The comparator CMP3 has a positive input connected between the bias circuit 201 and the capacitor CD, a negative input connected to the threshold voltage line Vth1, and an output connected to the latch mask signal line LMSK. When the voltage VCD of the capacitor CD is lower than the threshold voltage Vth1, the comparator CMP3 outputs a low-level latch mask signal LMSK. When the voltage VCD of the capacitor CD is equal to or higher than the threshold voltage Vth1, the comparator CMP3 outputs a high-level latch mask signal LMSK.

[0058] The transistor Tr3 is an NPN transistor with its collector connected between the bias circuit 201 and the capacitor CD, its emitter connected to the ground line, and its base connected to the overcurrent detection signal line OC. The transistor Tr3 is turned on while the overcurrent detection signal OC is at a high level, and connects the connection node between the bias circuit 201 and the capacitor CD to the ground line. While the transistor Tr3 is on, the latch mask signal LMSK is set to a low level.

[0059] 2, the AND circuit AND outputs only the high-level overcurrent detection signal OC1 corresponding to the high-level overcurrent detection signal OC indicating the occurrence of an overcurrent, out of the high-level overcurrent detection signals OC output by the overcurrent detection circuit 130 when it detects an overcurrent or a rush current, to the latch circuit 150. In other words, the AND circuit AND prevents the high-level overcurrent detection signal OC1 corresponding to the overcurrent detection signal OC that changes to a high level due to the occurrence of a rush current from being output to the latch circuit 150.

[0060] 2, the latch circuit 150 is enabled for latching operation while the control signal VRISE is at a high level, latches the high level of the overcurrent detection signal OC1 received when an overcurrent occurs, and outputs a high-level enable signal / VEN. Note that the overcurrent detection signal OCFLG, which changes to a low level when an overcurrent occurs, is generated by a buffer BUF2 and a transistor Tr4.

[0061] The latch circuit 150 holds the latched high level until the control signal EN (i.e., VRISE) next becomes high level. This allows the enable signal / VEN to be maintained at a high level (negate level) until the microcomputer 300, which has received the low-level overcurrent detection signal OCFLG, restarts the power supply device 100 in which an overcurrent has occurred, and allows the voltage generating circuit 120 to stop generating the output voltage VOUT.

[0062] The buffer BUF2 is connected between the output of the latch circuit 150 and the base of the transistor Tr4, and outputs to the base of the transistor Tr4 a signal having the same logical value as the enable signal / VEN output from the latch circuit 150. The transistor Tr4 is an NPN transistor having a collector connected to the overcurrent detection signal line OCFLG, an emitter connected to the ground line, and a base connected to the output of the buffer BUF2.

[0063] When an overcurrent (excluding rush current) occurs and the enable signal / VEN is at high level, transistor Tr4 turns on and sets the overcurrent detection signal OCFLG to low level. Transistor Tr4 turns off when no overcurrent occurs and the enable signal / VEN is at low level. When transistor Tr4 is off, the collector of transistor Tr4 is in a floating state and the overcurrent detection signal OCFLG is set to high level by pull-up resistor RPUP.

[0064] 3, the power supply device 100 can suspend generation of the output voltage VOUT from the time an overcurrent is detected until the power supply device 100 is restarted. In addition, by suspending the comparison operation of the comparator CMP1 with a high-level enable signal / VEN and setting the base voltages of the transistors Tr1 and Tr2 to a high level, the transistors Tr1 and Tr2 can be turned off.

[0065] As a result, after detecting an overcurrent, the microcomputer 300 negates the control signal EN, and the voltage generating circuit 120 is prevented from generating an abnormal output voltage VOUT during the time until the control signal EN is set to high level again, thereby preventing malfunction of the power supply device 100 and the power supply system SYS. Furthermore, by turning off the transistors Tr1 and Tr2 when an overcurrent occurs, the overcurrent can be prevented from continuing to flow through the transistors Tr1 and Tr2, and the transistors Tr1 and Tr2 can be prevented from being damaged by the overcurrent.

[0066] (Example of power supply operation) Figure 4 is a timing diagram showing an example of the operation of the power supply device 100 of Figure 3. Figure 4 shows the operation of any of the four power supply devices 100 of Figure 1. First, in the initial state before the input voltage VIN for operating the power supply device 100 is supplied to the power supply device 100, the control signals EN and VRISE are set to a low level, the reference voltage VREF and output voltage VOUT are set to 0 V, the output current IOUT is set to 0 A, the voltage VCD of the capacitor CD is set to 0 V, the overcurrent detection signals OC and OC1 are set to a low level, the latch mask signal LMSK is set to a low level, the enable signal / VEN is set to a low level, and the overcurrent detection signal OCFLG is set to a high level.

[0067] After the input voltage VIN is supplied to the power supply device 100, the microcomputer 300 sets the control signal EN to a high level to start up the power supply device 100. When the control signal EN is set to a high level, the control signal VRISE also changes to a high level (FIG. 4(a)).

[0068] When the control signal VRISE goes high, the start-up circuit 110 generates a reference voltage VREF (not shown), which causes the voltage generation circuit 120 to start operating and the output voltage VOUT rises to a predetermined voltage (FIG. 4(b)). When the power supply device 100 starts up, a rush current flows to charge the capacitor CD and the load capacitance Cout, increasing the output current IOUT and the voltage VCD of the capacitor CD (FIGS. 4(c) and 4(d)).

[0069] The overcurrent detection circuit 130 detects the rush current as an overcurrent and sets the overcurrent detection signal OC to a high level while the rush current is flowing (FIG. 4(e)). The latch mask circuit 140 maintains the latch mask signal LMSK at a low level due to the high level of the overcurrent detection signal OC (FIG. 4(f)).

[0070] The AND circuit AND maintains the output of the overcurrent detection signal OC1 at a low level to the latch circuit 150 due to the low-level latch mask signal LMSK, and inhibits the transmission of the overcurrent detection signal OC at a high level to the latch circuit 150 (FIG. 4(g)). Therefore, while the latch mask signal LMSK is at a low level, the latch circuit 150 maintains the enable signal / VEN at a low level regardless of the logic level of the overcurrent detection signal OC (FIG. 4(h)). Because the transistor Tr4 remains off, the overcurrent detection signal OCFLG is maintained at a high level indicating that no overcurrent is detected when a rush current occurs (FIG. 4(i)).

[0071] When the capacitor CD and the load capacitance Cout are charged, the rush current stops flowing, and the output current IOUT decreases, the overcurrent detection circuit 130 no longer detects the overcurrent, and the overcurrent detection signal OC changes to low level (FIG. 4(j)). The power supply device 100 then enters a steady state in which it generates the output voltage VOUT. In the steady state, when the overcurrent detection circuit 130 detects an overcurrent in the output current IOUT, it changes the overcurrent detection signal OC to high level (FIGS. 4(k) and 4(l)).

[0072] While the latch mask signal LMSK is at a low level, the AND circuit AND masks the transmission of the high-level overcurrent detection signal OC to the latch circuit 150 (FIG. 4(m)). When the voltage VCD rises due to an overcurrent and exceeds the threshold voltage Vth1, the latch mask signal LMSK changes to a high level (FIG. 4(n)). The latch circuit 150 latches the high level of the overcurrent detection signal OC1, enters a latched state, and outputs a high-level enable signal / VEN (FIG. 4(o)). As a result, the AND circuit AND transmits the high level of the overcurrent detection signal OC to the latch circuit 150 as a high level overcurrent detection signal OC1 (FIG. 4(p)).

[0073] When the enable signal / VEN is set to a high level, the comparator CMP1 of the voltage generating circuit 120 stops comparing voltages and outputs a high level. This causes the voltage generating circuit 120 to stop generating the output voltage VOUT, and the output voltage VOUT gradually decreases (FIG. 4(q)). Therefore, the microcomputer 300 receives the low-level data UV from the power supply monitoring circuit 200 of FIG. 1 and can detect the occurrence of an overcurrent as a low-voltage abnormality in the output voltage VOUT.

[0074] Transistor Tr4 receives a high-level enable signal / VEN via buffer BUF2, turns on, and sets the overcurrent detection signal OCFLG to a low level indicating the occurrence of an overcurrent (FIG. 4(r)). The low level of the overcurrent detection signal OCFLG is supplied to overcurrent determination circuit 320 of microcomputer 300.

[0075] The overcurrent determination circuit 320 detects the power supply device 100 in which an overcurrent has occurred based on the low level of the overcurrent detection signal OCFLG. Then, the microcomputer 300 sets the control signal EN, which is output to the power supply device 100 that has output the low-level overcurrent detection signal OCFLG, to low level, and stops the operation of the power supply device 100 in which an overcurrent has occurred (FIG. 4(s)).

[0076] After a predetermined time has elapsed since the microcomputer 300 set the control signal EN to low level, the microcomputer 300 sets the control signal EN to high level, thereby restarting the power supply device 100 in which an overcurrent has occurred (FIG. 4(t)). In response to the high level of the control signal EN, the power supply device 100 sets the control signal VRISE to high level. The high level of the control signal VRISE initializes the latch circuit 150, which sets the enable signal / VEN to low level (FIG. 4(u)). In response to the high level of the enable signal / VEN, the transistor Tr4 sets the overcurrent detection signal OCFLG to high level (FIG. 4(v)).

[0077] The voltage generating circuit 120 starts generating the output voltage VOUT, and the output voltage VOUT rises (FIG. 4(w)). Then, a rush current flows due to the rise in the output voltage VOUT, and the power supply device 100 operates in the same manner as in the first half of FIG.

[0078] (Serial data transmission timing diagram) Fig. 5 is a timing diagram showing an example of serial data transmitted from the parallel-serial conversion circuit 220 of Fig. 1 to the microcomputer 300. Fig. 5 shows an example in which the parallel-serial conversion circuit 220 transmits data in synchronization with the falling edge of the chip select signal CS and the falling edge of the clock signal CLK during the valid period of the low-active chip select signal CS, and the microcomputer 300 receives the data in synchronization with the rising edge of the clock signal CLK.

[0079] When the microcomputer 300 causes the parallel-serial conversion circuit 220 to transmit serial data, it changes the chip select signal CS to low level while the clock signal CLK is low level, and then outputs the clock signal CLK to the parallel-serial conversion circuit 220.

[0080] The parallel-serial conversion circuit 220 outputs the first serial data to the data line SDO in synchronization with the falling edge of the chip select signal CS. Thereafter, while the chip select signal CS is at a low level, the parallel-serial conversion circuit 220 sequentially outputs the serial data to the data line SDO in synchronization with the falling edge of the clock signal CLK. In the example shown in FIG. 5, data OV1, UV1, OV2, UV2, OV3, UV3, OV4, and UV4 are sequentially transmitted to the microcomputer 300, but the order in which the data is output is not limited to the example shown in FIG. 5.

[0081] By determining in advance the order in which data OV1-OV4 and UV1-UV4 are transmitted between power supply monitoring circuit 200 and microcomputer 300, microcomputer 300 can determine in which power supply device 100 an overvoltage or undervoltage has occurred, based on the received serial signal. In FIG. 5, microcomputer 300 can receive 8-bit data OV1-OV4 and UV1-UV4 by using three signal lines CS, CLK, and SDO. If eight power supply devices 100 are installed in power supply system SYS, 16-bit data OV1-OV8 and UV1-UV8 are transmitted using three signal lines CS, CLK, and SDO.

[0082] (Examples of other power supply systems) Fig. 6 is a block diagram showing an example of a circuit for detecting voltage abnormalities in another power supply system. Elements similar to those in Fig. 1 are given the same reference numerals, and detailed descriptions will be omitted. For example, each power supply device 102 is an LDO. The power supply system illustrated in Fig. 6 corresponds to a comparative example of the present invention.

[0083] If the abnormal voltage detection circuit 410 is configured with a single abnormal voltage detection IC (Integrated Circuit) 400, an abnormal voltage detection IC 400 is required for each power supply device 100, increasing the number of ICs used. Furthermore, since each abnormal voltage detection IC 400 outputs data OV and UV indicating whether the voltage is abnormal, if four power supply devices 100 are installed, eight signal lines are required to transmit the data OV and UV to the microcomputer 300. This poses a problem in that the increased number of ICs and signal lines increases the size of the board mounted on the power supply system.

[0084] Even when multiple abnormal voltage detection circuits 510 are configured with a dedicated abnormal voltage detection IC 500, data OV and UV indicating whether the voltage is abnormal must be output from each abnormal voltage detection circuit 510, and eight signal lines are required to transmit the data OV and UV. This increases the number of pins on the abnormal voltage detection IC 500, posing a problem in that the board on which the abnormal voltage detection IC 400 is mounted must be large. Therefore, it is difficult to miniaturize the power supply system with the single IC configuration shown in Figure 6 and the dedicated IC configuration.

[0085] For example, methods for protecting a power supply device from overcurrent include protection using a foldback characteristic, a drooping characteristic, or a thermal protection circuit. With a foldback characteristic, when an overcurrent occurs in the output current, the transistor is turned off by utilizing the characteristic that the output voltage and output current decrease. With a drooping characteristic, when an overcurrent occurs in the output current, the transistor is turned off by utilizing the characteristic that the output voltage decreases while the output current is maintained. A thermal protection circuit detects the heat generated by the overcurrent and turns off the transistor.

[0086] The protection methods using the foldback and drooping characteristics have the problem that the transistor may be repeatedly turned on by the protection function and then turned on by the release of the protection function, making it impossible to shut down the power supply system properly. Furthermore, because the protection methods using the foldback and drooping characteristics are open control, there is a risk that the transistor may be destroyed if the output current exceeds the rated current of the transistor. For this reason, when using the foldback or drooping characteristics to protect against overcurrent, it is necessary to install a thermal protection circuit in the power supply device.

[0087] As described above, in the first embodiment, even when a large number of power supply devices 100 are installed in the power supply system SYS, it is possible to transmit to the microcomputer 300, using a minimum number of signal lines, a plurality of data OV indicating whether each of the output voltages VOUT is an overvoltage or not and a plurality of data UV indicating whether each of the output voltages VOUT is an undervoltage or not.

[0088] Since an increase in the number of signal lines can be suppressed, it is possible to suppress an increase in the size of a system board on which the power supply device 100, the power supply monitoring circuit 200, and the microcomputer 300 are mounted, for example. Therefore, an increase in the circuit scale of the power supply system SYS can be suppressed, and an increase in system costs can be suppressed.

[0089] By transmitting the overcurrent detection signal OCFLG to the microcomputer 300 for each power supply device 100, the microcomputer 300 can independently stop and restart only the power supply device 100 in which an overcurrent has occurred using the control signal EN. This allows only the power supply device 100 in which an abnormality has occurred to be safely stopped and restored from the abnormal state without having to shut down the entire power supply system SYS. As a result, it is possible to achieve a function for detecting power supply abnormalities in multiple power supply devices 100 and a function for safely stopping the power supply device 100 in which an abnormality has occurred, while suppressing an increase in circuit size.

[0090] Incidentally, by providing an abnormal voltage determination circuit 310 for each power supply device 100, it is possible to realize power supply redundancy, for example, by operating two power supply devices 100 exclusively. In this case, the exclusive operation of the power supply devices 100 can be easily achieved by the control signal EN output by the microcomputer 300.

[0091] The power supply device 100 has a latch circuit 150 that negates the enable signal / VEN to a high level when the microcomputer 300 asserts the control signal EN to a high level, and maintains the negated state of the enable signal / VEN until the control signal EN is asserted again when an overcurrent is detected. This makes it possible to stop the generation of the output voltage VOUT from the time an overcurrent is detected until the power supply device 100 is restarted. Furthermore, the enable signal / VEN controls the comparator CMP1 to set the base voltage of the transistor Tr1 to a high level, thereby turning off the transistor Tr1.

[0092] As a result, after an overcurrent is detected, the voltage generating circuit 120 can be prevented from generating an abnormal output voltage VOUT until the microcomputer 300 negates the control signal EN, thereby preventing malfunction of the power supply device 100 and the power supply system SYS. In addition, the overcurrent can be prevented from continuing to flow through the transistors Tr1 and Tr2, preventing the transistors Tr1 and Tr2 from being damaged by the overcurrent.

[0093] By providing the power supply monitoring circuit 200 with an abnormal voltage detection circuit 210 corresponding to each power supply device 100, it is possible to individually detect overvoltage and undervoltage in the output voltage VOUT of the corresponding power supply device 100 and notify the microcomputer 300. Then, data OV indicating whether an overvoltage abnormality has occurred for each power supply device 100 and data UV indicating whether an undervoltage abnormality has occurred can be transmitted to the microcomputer 300 as serial data using the parallel-serial conversion circuit 220.

[0094] (Example of power supply system according to the second embodiment) Fig. 7 is an example of a block diagram showing a second embodiment of a power supply system according to the present invention. Elements similar to those in Fig. 1 are assigned the same reference numerals, and detailed description thereof will be omitted. The power supply system SYS shown in Fig. 7 has a configuration similar to that of the power supply system SYS shown in Fig. 1, except that it has a power supply monitoring circuit 200A instead of the power supply monitoring circuit 200. The power supply monitoring circuit 200A has a parallel-serial conversion circuit 220A instead of the parallel-serial conversion circuit 220 of Fig. 1. The parallel-serial conversion circuit 220A has a data latch 211A and a shift register 212A.

[0095] In this embodiment, the overcurrent detection signal OCFLG output from each power supply device 100 is transmitted as a serial signal to the microcomputer 300 via a parallel-serial conversion circuit 220A. For this reason, the data latch 211A has a latch for the logical values ​​of the overcurrent detection signals OCFLG1-OCFLG4 in addition to latches for the data OV1-OV4 and UV1-UV4. The shift register 212A has a register size that can simultaneously hold the logical values ​​of the data OV1-OV4 and UV1-UV4 and the logical values ​​of the overcurrent detection signals OCFLG1-OCFLG4.

[0096] In the second embodiment, for example, the overcurrent detection signals OCFLG1-OCFLG4 do not need to be transmitted to the microcomputer 300 via wiring formed on a system board on which the power supply device 100, the power supply monitoring circuit 200A, and the microcomputer 300 are mounted. This makes it possible to further prevent the size of the system board from increasing, compared to the first embodiment. As a result, it is possible to further prevent an increase in the circuit scale of the power supply system SYS, and thus to further prevent an increase in system costs.

[0097] The microcomputer 300 can receive the overcurrent detection signals OCFLG1-OCFLG4 via the data line SDO without using a general-purpose input / output port, for example. This allows the use of a microcomputer with fewer general-purpose input / output ports than the microcomputer 300. In this case, increases in system costs can be further suppressed.

[0098] As described above, in the second embodiment, as in the first embodiment, even when a large number of power supply devices 100 are installed in the power supply system SYS, it is possible to transmit to the microcomputer 300, using a minimum number of signal lines, a plurality of data OV indicating whether each of the output voltages VOUT is an overvoltage or not and a plurality of data UV indicating whether each of the output voltages VOUT is an undervoltage or not.

[0099] Furthermore, in the second embodiment, the logical values ​​of the data OV1-OV4, UV1-UV4 and the logical values ​​of the overcurrent detection signals OCFLG1-4 can be transmitted to the microcomputer 300 as serial data using the parallel-serial conversion circuit 220. Since the overcurrent detection signals OCFLG1-OCFLG4 do not need to be transmitted to the microcomputer 300 via wiring formed on the system board, an increase in the size of the system board can be further suppressed. Therefore, an increase in the circuit scale of the power supply system SYS can be further suppressed, and an increase in system costs can be further suppressed.

[0100] Although the present invention has been described above based on the embodiments, the present invention is not limited to the requirements shown in the above embodiments. These requirements can be changed without departing from the spirit of the present invention, and can be appropriately determined depending on the application form. [Explanation of symbols]

[0101] 100, 102 Power supply 110 Starter circuit 120 Voltage generation circuit 130 Overcurrent detection circuit 140 Latch mask circuit 150 Latch Circuit 200, 200A power supply monitoring circuit 201 Bias circuit 210, 410, 510 Abnormal voltage detection circuit 211, 211A Data Latch 212, 212A shift registers 220, 220A parallel-serial conversion circuit 300 Microcomputer 310 Abnormal voltage detection circuit 320 Overcurrent discrimination circuit 400, 500 Abnormal voltage detection IC AND circuit BUF1, BUF2 buffers CD capacitor CLK Clock signal CMP1, CMP2, CMP3 comparators CMPO, CMPU Comparator Cout Load capacity CS Chip select signal EN(EN1-EN4) control signal IOUT Output current Ith1, Ith2 threshold current LMSK Latch Mask Signal OC, OC1 Overcurrent detection signal OCFLG (OCFLG1-OCFLG4) Overcurrent detection signal OV (OV1-OV4) Overvoltage detection signal R4, R5, R11, R12, R13 resistors RLIM Resistor RPUP pull-up resistor SDO data line SYS Power System Tr1-Tr4 transistors UV (UV1-UV4) Low voltage detection signal VCC power line VCD voltage / VEN Enable signal VIN Input voltage VOUT(VOUT1-VOUT4) Output voltage VREF, VREF1 reference voltage VRISE control signal Vth1, Vth2 threshold voltage

Claims

1. a plurality of power supply devices each generating an output voltage when a corresponding one of a plurality of control signals is in an active state; a control device that outputs the plurality of control signals to the plurality of power supply devices, respectively; an abnormality transmission circuit that includes a plurality of abnormal voltage detection circuits provided corresponding to the plurality of power supply devices, each detecting whether the output voltage generated by the plurality of power supply devices is abnormal, and transmits a plurality of detection results by the plurality of abnormal voltage detection circuits to the control device as a serial signal; The control device outputs the control signal in an invalid state to a power supply device in which an abnormality has been detected among the plurality of power supply devices based on the plurality of detection results, thereby stopping the operation, and then outputs the control signal in an valid state. A power supply system characterized by:

2. Each of the plurality of power supply devices a voltage generating circuit that generates the output voltage based on an input voltage received at a first terminal and outputs the generated output voltage to a second terminal; an overcurrent detection circuit that detects whether a current flowing from the first terminal to the second terminal is an overcurrent and transmits the detection result to the control device; The control device outputs the control signal in an invalid state to a power supply device in which an abnormality has been detected among the plurality of power supply devices based on a detection result by the overcurrent detection circuit, thereby stopping the operation, and then outputs the control signal in an valid state.

2. The power supply system according to claim 1.

3. The abnormality transmission circuit transmits a plurality of detection results by the abnormal voltage detection circuit and a detection result by the overcurrent detection circuit of each of the plurality of power supply devices to the control device as a serial signal.

3. The power supply system according to claim 2.

4. Each of the plurality of power supply devices has a latch circuit that outputs an enable signal in an enabled state when the corresponding control signal changes to an enabled state, and sets the enable signal to an disabled state when the overcurrent detection circuit detects an overcurrent until the corresponding control signal changes to an enabled state again, The voltage generating circuit generates the output voltage when the enable signal is in an enabled state, and stops generating the output voltage when the enable signal is in an disabled state.

3. The power supply system according to claim 2.

5. The voltage generating circuit a transistor disposed between the first terminal and the second terminal; a comparator that controls a base voltage of the transistor in accordance with a difference between the input voltage and the output voltage, The comparator When the enable signal is in an enabled state, a control voltage is supplied to the base of the transistor to turn off the transistor when the output voltage is equal to or higher than a target voltage; When the enable signal is in an enabled state, a control voltage is supplied to the base of the transistor, the on-resistance of the transistor being reduced as the output voltage is lower than the target voltage; When the enable signal is in an inactive state, a control voltage is applied to the base of the transistor to turn the transistor off.

5. The power supply system according to claim 4.

6. Each of the plurality of abnormal voltage detection circuits detects a first abnormality when the output voltage generated by the corresponding power supply device is higher than a first determination voltage, and detects a second abnormality when the output voltage generated by the corresponding power supply device is lower than a second determination voltage that is lower than the first determination voltage.

6. The power supply system according to claim 1, wherein the power supply system is a power supply system for supplying power to a power source.

7. the abnormality transmission circuit has a parallel-serial conversion circuit, The parallel-to-serial conversion circuit a data latch that latches data indicating the plurality of detection results in parallel; a data converter that converts the data indicating the detection results latched by the data latch into serial data; 6. The power supply system according to claim 1, wherein the power supply system is a power supply system for supplying power to a power source.

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