Display device

Abstract

To provide a display device capable of improving yield.SOLUTION: In general, according to one embodiment, a display device includes a first sub-pixel, a second sub-pixel, a partition wall including a first segment surrounding the first sub-pixel and a second segment surrounding the second sub-pixel, a first multilayer film disposed in the first sub-pixel and including an electrode electrically connected to the first segment, a second multilayer film disposed in the second sub-pixel and including an electrode electrically connected to the second segment, a first sealing layer formed of an inorganic insulating material and covering the first multilayer film, and a second sealing layer formed of an inorganic insulating material and covering the second multilayer film. The first segment and the second segment are separated by a slit. Furthermore, the first sealing layer overlaps at least a part of the slit in a planar view.SELECTED DRAWING: Figure 2

Description

[Technical Field]

[0001] FIELD An embodiment of the present invention relates to a display device. [Background technology]

[0002] In recent years, display devices using organic light-emitting diodes (OLEDs) as display elements have come into practical use. Technology that enables improvement of yields in this type of display device is required. [Prior art documents] [Patent documents]

[0003] [Patent Document 1] Japanese Patent Application Laid-Open No. 2000-195677 [Patent Document 2] Japanese Patent Application Laid-Open No. 2004-207217 [Patent Document 3] Japanese Patent Application Laid-Open No. 2008-135325 [Patent Document 4] Japanese Patent Application Laid-Open No. 2009-32673 [Patent Document 5] Japanese Patent Application Laid-Open No. 2010-118191 [Patent Document 6] International Publication No. 2018 / 179308 [Patent Document 7] US Patent Application Publication No. 2022 / 0077251 Summary of the Invention [Problem to be solved by the invention]

[0004] An object of the present invention is to provide a display device that can improve yield. [Means for solving the problem]

[0005] Generally, according to an embodiment, a display device includes first and second subpixels, a partition wall including a first segment surrounding the first subpixel and a second segment surrounding the second subpixel, a first stacked film disposed in the first subpixel and including an electrode electrically connected to the first segment, a second stacked film disposed in the second subpixel and including an electrode electrically connected to the second segment, a first sealing layer formed of an inorganic insulating material and covering the first stacked film, and a second sealing layer formed of an inorganic insulating material and covering the second stacked film. The first and second segments are separated by a slit. Furthermore, the first sealing layer overlaps at least a portion of the slit in a plan view.

[0006] According to another aspect of the embodiment, the first sealing layer has a first end portion located inside the slit, and further has a first gap formed below the first end portion. [Brief explanation of the drawings]

[0007] [Figure 1] FIG. 1 is a diagram showing an example of the configuration of a display device according to the first embodiment. [Figure 2] FIG. 2 is a schematic plan view showing an example of a layout of sub-pixels according to the first embodiment. [Figure 3] FIG. 3 is a schematic cross-sectional view of the display device taken along line III-III in FIG. [Figure 4] FIG. 4 is a schematic cross-sectional view showing an enlarged view of the vicinity of the boundary between the sub-pixels in FIG. [Figure 5] FIG. 5 is a schematic cross-sectional view showing an enlarged view of the vicinity of the boundary between the sub-pixels in FIG. [Figure 6] FIG. 6 is a flowchart showing an example of a method for manufacturing a display device. [Figure 7A] FIG. 7A is a schematic cross-sectional view showing a first example of a method for forming a partition wall. [Figure 7B] FIG. 7B is a schematic cross-sectional view showing a step subsequent to FIG. 7A. [Figure 7C]FIG. 7C is a schematic cross-sectional view showing a step subsequent to FIG. 7B. [Figure 7D] FIG. 7D is a schematic cross-sectional view showing a step subsequent to FIG. 7C. [Figure 7E] FIG. 7E is a schematic cross-sectional view showing a step subsequent to FIG. 7D. [Figure 7F] FIG. 7F is a schematic cross-sectional view showing a step subsequent to FIG. 7E. [Figure 7G] FIG. 7G is a schematic cross-sectional view showing a step subsequent to FIG. 7F. [Figure 7H] FIG. 7H is a schematic cross-sectional view showing a step subsequent to FIG. 7G. [Figure 7I] FIG. 7I is a schematic cross-sectional view showing a step subsequent to FIG. 7H. [Figure 8A] FIG. 8A is a schematic cross-sectional view showing a second example of a method for forming a partition wall. [Figure 8B] FIG. 8B is a schematic cross-sectional view showing a step subsequent to FIG. 8A. [Figure 8C] FIG. 8C is a schematic cross-sectional view showing a step subsequent to FIG. 8B. [Figure 8D] FIG. 8D is a schematic cross-sectional view showing a step subsequent to FIG. 8C. [Figure 8E] FIG. 8E is a schematic cross-sectional view showing a step subsequent to FIG. 8D. [Figure 8F] FIG. 8F is a schematic cross-sectional view showing a step subsequent to FIG. 8E. [Figure 8G] FIG. 8G is a schematic cross-sectional view showing a step subsequent to FIG. 8F. [Figure 8H] FIG. 8H is a schematic cross-sectional view showing a step subsequent to FIG. 8G. [Figure 8I] FIG. 8I is a schematic cross-sectional view showing a step subsequent to FIG. 8H. [Figure 8J] FIG. 8J is a schematic cross-sectional view showing a step subsequent to FIG. 8I. [Figure 8K] FIG. 8K is a schematic cross-sectional view showing a step subsequent to FIG. 8J. [Figure 8L] FIG. 8L is a schematic cross-sectional view showing a step subsequent to FIG. 8K. [Figure 9A] FIG. 9A is a schematic cross-sectional view showing a step of forming a pixel opening. [Figure 9B] FIG. 9B is a schematic cross-sectional view showing a step subsequent to FIG. 9A. [Figure 9C] FIG. 9C is a schematic cross-sectional view showing a step of forming a display element. [Figure 9D] FIG. 9D is a schematic cross-sectional view showing a step subsequent to FIG. 9C. [Figure 9E] FIG. 9E is a schematic cross-sectional view showing a step subsequent to FIG. 9D. [Figure 9F] FIG. 9F is a schematic cross-sectional view showing a step subsequent to FIG. 9E. [Figure 10] FIG. 10 is a schematic cross-sectional view showing a configuration according to a comparative example. [Figure 11] FIG. 11 is a schematic plan view of a display area of ​​a display device according to the second embodiment. [Figure 12] FIG. 12 is a schematic plan view of a display region of a display device according to the third embodiment. [Figure 13] FIG. 13 is a schematic cross-sectional view of the display device taken along line XIII-XIII in FIG. [Figure 14] FIG. 14 is a schematic plan view of a display region of a display device according to the fourth embodiment. [Figure 15] FIG. 15 is a schematic plan view of a display region of a display device according to the fifth embodiment. [Figure 16] FIG. 16 is a schematic cross-sectional view of the display device taken along line XVI-XVI in FIG. [Figure 17] FIG. 17 is a schematic cross-sectional view of the display device taken along line XVII-XVII in FIG. [Figure 18] FIG. 18 is a schematic plan view of a display region of a display device according to the sixth embodiment. DETAILED DESCRIPTION OF THE INVENTION

[0008] Some embodiments will be described with reference to the drawings. The disclosure is merely an example, and appropriate modifications that a person skilled in the art can easily make while maintaining the gist of the invention are naturally included within the scope of the present invention. Furthermore, the drawings may be schematic in terms of the width, thickness, shape, etc. of each part compared to the actual embodiment for the sake of clarity, but these are merely examples and are not intended to limit the interpretation of the present invention. Furthermore, in this specification and each drawing, components that perform the same or similar functions as those described above with reference to the previous drawings are designated by the same reference numerals, and redundant detailed descriptions may be omitted as appropriate.

[0009] In the drawings, mutually orthogonal X, Y, and Z axes are shown as necessary to facilitate understanding. The direction along the X axis is referred to as the X direction, the direction along the Y axis is referred to as the Y direction, and the direction along the Z axis is referred to as the Z direction. The Z direction is the normal direction of a plane including the X and Y directions. Viewing various elements parallel to the Z direction is referred to as planar view.

[0010] The display device according to each embodiment is an organic electroluminescence display device having an organic light-emitting diode (OLED) as a display element, and can be installed in various electronic devices such as televisions, personal computers, in-vehicle equipment, tablet terminals, smartphones, mobile phone terminals, and wearable terminals.

[0011] [First embodiment] 1 is a diagram showing an example of the configuration of a display device DSP according to the first embodiment. The display device DSP includes an insulating substrate 10. The substrate 10 has a display area DA for displaying an image and a peripheral area SA around the display area DA. The substrate 10 may be made of glass or a flexible resin film.

[0012] In this embodiment, the shape of the substrate 10 in plan view is rectangular. However, the shape of the substrate 10 in plan view is not limited to rectangular, and may be other shapes such as square, circular, or elliptical.

[0013] The display area DA includes a plurality of pixels PX arranged in a matrix in the X and Y directions. Each pixel PX includes a plurality of subpixels SP that display different colors. In this embodiment, it is assumed that the pixel PX includes a blue subpixel SP1 (first subpixel), a green subpixel SP2 (second subpixel), and a red subpixel SP3 (third subpixel). However, the pixel PX may include subpixels SP of other colors, such as white, in addition to or instead of the subpixels SP1, SP2, and SP3.

[0014] The subpixel SP includes a pixel circuit 1 and a display element DE driven by the pixel circuit 1. The pixel circuit 1 includes a pixel switch 2, a drive transistor 3, and a capacitor 4. The pixel switch 2 and the drive transistor 3 are switching elements formed of, for example, thin film transistors.

[0015] In the display area DA, a plurality of scanning lines G that supply scanning signals to the pixel circuits 1 of each subpixel SP, a plurality of signal lines S that supply video signals to the pixel circuits 1 of each subpixel SP, and a plurality of power supply lines PL are arranged. In the example of Fig. 1, the scanning lines G and the power supply lines PL extend in the X direction, and the signal lines S extend in the Y direction.

[0016] The gate electrode of the pixel switch 2 is connected to the scanning line G. The source electrode of the pixel switch 2 is connected to the signal line S. The drain electrode of the pixel switch 2 is connected to the gate electrode of the drive transistor 3 and the capacitor 4. The source electrode of the drive transistor 3 is connected to the power line PL and the capacitor 4. The drain electrode of the drive transistor 3 is connected to the display element DE.

[0017] The configuration of the pixel circuit 1 is not limited to the example shown in the drawing. For example, the pixel circuit 1 may include more thin film transistors and capacitors.

[0018] Fig. 2 is a schematic plan view showing an example of the layout of subpixels SP1, SP2, and SP3. The example in Fig. 2 shows an area corresponding to four pixels PX. In each pixel PX, subpixels SP1 and SP3 are aligned with subpixel SP2 in the X direction. Furthermore, subpixels SP1 and SP3 are aligned with subpixel SP2 in the Y direction.

[0019] When the subpixels SP1, SP2, and SP3 are laid out in this manner, the display area DA is formed with columns in which the subpixels SP1 and SP3 are alternately arranged in the Y direction, and columns in which multiple subpixels SP2 are repeatedly arranged in the Y direction. These columns are arranged alternately in the X direction. Note that the layout of the subpixels SP1, SP2, and SP3 is not limited to the example in FIG. 2.

[0020] Pixel apertures AP1, AP2, and AP3 are formed in the subpixels SP1, SP2, and SP3, respectively. These pixel apertures AP1, AP2, and AP3 are provided in a rib layer 5 (see, for example, FIG. 3), which will be described later. In the example of FIG. 2, pixel aperture AP1 is larger than pixel aperture AP3, and pixel aperture AP2 is larger than pixel aperture AP1. That is, among the subpixels SP1, SP2, and SP3, subpixel SP2 has the largest aperture ratio and subpixel SP3 has the smallest aperture ratio. Note that the sizes of pixel apertures AP1, AP2, and AP3 are not limited to this example. For example, at least two of the pixel apertures AP1, AP2, and AP3 may have the same size.

[0021] In the display area DA, partition walls 6 are arranged. In FIG. 2, a dotted pattern is applied to the partition walls 6. The area with this dotted pattern is also an area where a bottom layer 63 (described later) is arranged. The partition walls 6 are in a lattice shape surrounding the subpixels SP1, SP2, and SP3.

[0022] The partition wall 6 has a plurality of segments SG1, SG2, and SG3 (first to third segments). In FIG. 2, the segments SG1, SG2, and SG3 are indicated by hatched lines. The segment SG1 surrounds one subpixel SP1. Similarly, the segment SG3 surrounds one subpixel SP3. Meanwhile, the segment SG2 surrounds each of the plurality of subpixels SP2 arranged in the Y direction.

[0023] Slits SL are formed between the segments SG1, SG2, and SG3. As shown in more detail in FIGS. 3 and 4, the slits SL separate the shaft layer 64 and the upper portion 62 that form each of the segments SG1, SG2, and SG3. In this embodiment, the bottom layer 63 overlaps the segments SG1, SG2, and SG3 and the slits SL in a plan view. The slits SL extend in the Y direction between the segments SG1 and SG2 and between the segments SG2 and SG3. The slits SL also extend in the X direction between the segments SG1 and SG3. In this embodiment, each of the segments SG1 and SG3 is surrounded by the slits SL.

[0024] Sealing layers SE11, SE12, and SE13 (first to third sealing layers) are disposed on the subpixels SP1, SP2, and SP3, respectively. The sealing layer SE11 overlaps the subpixel SP1 and the segment SG1. The sealing layer SE12 overlaps the subpixels SP2 and the segments SG2 aligned in the Y direction. The sealing layer SE13 overlaps the subpixel SP3 and the segment SG3.

[0025] The sealing layers SE11, SE12, and SE13 overlap at least a portion of the slit SL. In the example of Fig. 2, the end E1 of the sealing layer SE11 is located in the slit SL over its entire periphery. The end E3 of the sealing layer SE13 is located in the slit SL over its entire periphery. Furthermore, the end E2 of the sealing layer SE12 extending in the Y direction is located entirely in the slit SL.

[0026] 3 is a schematic cross-sectional view of the display device DSP taken along line III-III in FIG. 2. A circuit layer 11 is disposed on the above-described substrate 10. The circuit layer 11 includes various circuits and wirings such as the pixel circuits 1, scanning lines G, signal lines S, and power supply lines PL shown in FIG. 1. The circuit layer 11 is covered with an organic insulating layer 12. The organic insulating layer 12 functions as a planarizing film that flattens unevenness caused by the circuit layer 11.

[0027] The subpixels SP1, SP2, and SP3 each have a lower electrode LE1, LE2, and LE3 disposed on the organic insulating layer 12. The lower electrodes LE1, LE2, and LE3 are connected to the pixel circuit 1 included in the circuit layer 11 through contact holes CH1, CH2, and CH3 (see FIG. 2) provided in the organic insulating layer 12. The contact holes CH1, CH2, and CH3 are provided at positions that overlap with the segments SG1, SG2, and SG3 in a plan view, for example.

[0028] The ends of the lower electrodes LE1, LE2, and LE3 are covered with a rib layer 5. The rib layer 5 has the above-mentioned pixel openings AP1, AP2, and AP3. The lower electrodes LE1, LE2, and LE3 are exposed from the rib layer 5 through the pixel openings AP1, AP2, and AP3, respectively.

[0029] The partition wall 6 includes a conductive bottom layer 63 disposed on the rib layer 5. Segments SG1, SG2, and SG3 of the partition wall 6 are provided on the bottom layer 63. The segments SG1, SG2, and SG3 each include a conductive axial layer 64 located on the bottom layer 63 and an upper portion 62 disposed on the axial layer 64. The bottom layer 63 and the axial layer 64 form a lower portion 61 of the partition wall 6.

[0030] In the example of Figure 3, the upper portion 62 has a first top layer 65 and a second top layer 66. The first top layer 65 is disposed on the axial layer 64. The second top layer 66 is disposed on the first top layer 65.

[0031] In each of the segments SG1, SG2, and SG3, the upper portion 62 has a width greater than that of the shaft layer 64. As a result, both ends of the upper portion 62 protrude beyond the side surfaces of the shaft layer 64. In other words, the segments SG1, SG2, and SG3 have an overhanging shape in which both ends of the upper portion 62 protrude beyond the side surfaces of the shaft layer 64.

[0032] The subpixels SP1, SP2, and SP3 each include a stacked film FL1, FL2, and FL3 (first to third stacked films). The stacked film FL1 includes an organic layer OR1 in contact with the lower electrode LE1 through the pixel opening AP1, an upper electrode UE1 covering the organic layer OR1, and a cap layer CP1 covering the upper electrode UE1. The stacked film FL2 includes an organic layer OR2 in contact with the lower electrode LE2 through the pixel opening AP2, an upper electrode UE2 covering the organic layer OR2, and a cap layer CP2 covering the upper electrode UE2. The stacked film FL3 includes an organic layer OR3 in contact with the lower electrode LE3 through the pixel opening AP3, an upper electrode UE3 covering the organic layer OR3, and a cap layer CP3 covering the upper electrode UE3. The upper electrodes UE1, UE2, and UE3 are electrically connected to the segments SG1, SG2, and SG3, respectively. For example, the upper electrodes UE1, UE2, and UE3 are in contact with the bottom layer 63 below the segments SG1, SG2, and SG3. The upper electrodes UE1, UE2, UE3 may further contact the axial layers 64 of the segments SG1, SG2, SG3, respectively.

[0033] The lower electrode LE1, upper electrode UE1, and organic layer OR1 form the display element DE1 of subpixel SP1. The lower electrode LE2, upper electrode UE2, and organic layer OR2 form the display element DE2 of subpixel SP2. The lower electrode LE3, upper electrode UE3, and organic layer OR3 form the display element DE3 of subpixel SP3.

[0034] The subpixels SP1, SP2, and SP3 include sealing layers SE11, SE12, and SE13, respectively. The sealing layer SE11 continuously covers the stacked film FL1 and the segment SG1. The sealing layer SE12 continuously covers the stacked film FL2 and the segment SG2. The sealing layer SE13 continuously covers the stacked film FL3 and the segment SG3.

[0035] 3, stacked films FL1, FL2, and FL3 are also disposed on the segments SG1, SG2, and SG3, respectively. These stacked films FL1, FL2, and FL3 are covered with sealing layers SE11, SE12, and SE13.

[0036] The sealing layers SE11, SE12, and SE13 are covered with a resin layer RS1. The resin layer RS1 is covered with a sealing layer SE2. The sealing layer SE2 is covered with a resin layer RS2. The resin layers RS1 and RS2 and the sealing layer SE2 are provided continuously over at least the entire display area DA, with a portion of them extending into the peripheral area SA.

[0037] A cover member such as a polarizing plate, a touch panel, a protective film, or a cover glass may be further disposed above the resin layer RS2. Such a cover member may be adhered to the resin layer RS2 via an adhesive layer such as OCA (Optical Clear Adhesive). Electrodes constituting the touch panel may be disposed on the sealing layer SE2.

[0038] The electrodes constituting the touch panel may be disposed on the sealing layer SE2. Also, color filters corresponding to the colors of the subpixels SP1, SP2, SP3 may be disposed above the display elements DE1, DE2, DE3, respectively.

[0039] The organic insulating layer 12 is formed of an organic insulating material such as polyimide. The rib layer 5 and the sealing layers SE11, SE12, SE13, and SE2 are formed of an inorganic insulating material such as silicon nitride (SiNx), silicon oxide (SiOx), or silicon oxynitride (SiON). In one example, the rib layer 5 is formed of silicon oxynitride, and the sealing layers SE11, SE12, SE13, and SE2 are formed of silicon nitride. The resin layers RS1 and RS2 are formed of a resin material (organic insulating material) such as epoxy resin or acrylic resin.

[0040] The upper electrodes UE1, UE2, UE3 are formed of a metal material such as an alloy of magnesium and silver (MgAg). For example, the lower electrodes LE1, LE2, LE3 correspond to anodes, and the upper electrodes UE1, UE2, UE3 correspond to cathodes.

[0041] The organic layers OR1, OR2, and OR3 are each composed of a plurality of thin films including an emissive layer. In one example, the organic layers OR1, OR2, and OR3 have a structure in which a hole injection layer, a hole transport layer, an electron blocking layer, an emissive layer, a hole blocking layer, an electron transport layer, and an electron injection layer are stacked in this order in the Z direction. However, the organic layers OR1, OR2, and OR3 may have other structures, such as a so-called tandem structure including a plurality of emissive layers.

[0042] The capping layers CP1, CP2, and CP3 function as optical adjustment layers that improve the extraction efficiency of light emitted from the organic layers OR1, OR2, and OR3, respectively. These capping layers CP1, CP2, and CP3 may have a laminated structure in which multiple transparent layers with different refractive indices are stacked. At least one of the capping layers CP1, CP2, and CP3 may be omitted.

[0043] A common voltage is supplied to the segments SG1, SG2, and SG3 of the partition wall 6 and the bottom layer 63. This common voltage is supplied to the upper electrodes UE1, UE2, and UE3 that are in contact with at least one of the bottom layer 63 and the axis layer 64. A pixel voltage corresponding to the video signal on the signal line S is supplied to the lower electrodes LE1, LE2, and LE3 through the pixel circuits 1 of the subpixels SP1, SP2, and SP3, respectively.

[0044] The organic layers OR1, OR2, and OR3 emit light in response to the application of voltage. Specifically, when a potential difference is created between the lower electrode LE1 and the upper electrode UE1, the light-emitting layer of the organic layer OR1 emits light in the blue wavelength range. When a potential difference is created between the lower electrode LE2 and the upper electrode UE2, the light-emitting layer of the organic layer OR2 emits light in the green wavelength range. When a potential difference is created between the lower electrode LE3 and the upper electrode UE3, the light-emitting layer of the organic layer OR3 emits light in the red wavelength range.

[0045] As another example, the light-emitting layers of the organic layers OR1, OR2, and OR3 may emit light of the same color (e.g., white). In this case, the display device DSP may include color filters that convert the light emitted by the light-emitting layers into light of the colors corresponding to the subpixels SP1, SP2, and SP3. The display device DSP may also include a layer containing quantum dots that are excited by the light emitted by the light-emitting layers to generate light of the colors corresponding to the subpixels SP1, SP2, and SP3.

[0046] The bottom layer 63 and the shaft layer 64 are formed of, for example, a metal material. Examples of the metal material for the bottom layer 63 include molybdenum (Mo), titanium (Ti), titanium nitride (TiN), a molybdenum-tungsten alloy (MoW), and a molybdenum-niobium alloy (MoNb). Examples of the metal material for the shaft layer 64 include aluminum (Al), an aluminum-neodymium alloy (AlNd), an aluminum-yttrium alloy (AlY), and an aluminum-silicon alloy (AlSi). At least one of the bottom layer 63 and the shaft layer 64 may have a multi-layer structure. The shaft layer 64 may also include a layer formed of an insulating material. As an alternative to the present embodiment in which the lower portion 61 includes the bottom layer 63 and the shaft layer 64, the lower portion 61 may have a single-layer structure formed of a conductive material.

[0047] For example, the first top layer 65 is formed of a metal material, and the second top layer 66 is formed of a transparent conductive oxide. Examples of the metal material for the first top layer 65 include titanium, titanium nitride, molybdenum, tungsten, a molybdenum-tungsten alloy, and a molybdenum-niobium alloy. Examples of the conductive oxide for the second top layer 66 include indium tin oxide (ITO), indium zinc oxide (IZO), and indium gallium zinc oxide (IGZO). The upper portion 62 may have a single-layer structure made of a specific material. Furthermore, the upper portion 62 may include a layer made of an insulating material.

[0048] Fig. 4 is a schematic cross-sectional view showing an enlarged view of the vicinity of the boundary between the subpixels SP1 and SP2 in Fig. 2. Fig. 5 is a schematic cross-sectional view showing an enlarged view of the vicinity of the boundary between the subpixels SP1 and SP3 in Fig. 2.

[0049] 4, the bottom layer 63 extends from below the segment SG1 to below the segment SG2 and is not separated by the slit SL between the segments SG1 and SG2. In the slit SL between the segments SG1 and SG2, the shaft layer 64 and the upper portion 62 of the segment SG1 are separated from the shaft layer 64 and the upper portion 62 of the segment SG2.

[0050] 5, the bottom layer 63 is provided from below the segment SG1 to below the segment SG3 and is not divided by the slit SL between the segments SG1 and SG3. In the slit SL between the segments SG1 and SG3, the shaft layer 64 and the upper portion 62 of the segment SG1 are separated from the shaft layer 64 and the upper portion 62 of the segment SG3.

[0051] As shown in Fig. 4, an end of the bottom layer 63 protrudes from the side surface of the shaft layer 64 of the segment SG1 toward the subpixel SP1. Similarly, an end of the bottom layer 63 protrudes from the side surface of the shaft layer 64 of the segment SG2 toward the subpixel SP2. Furthermore, as shown in Fig. 5, an end of the bottom layer 63 protrudes from the side surface of the shaft layer 64 of the segment SG3 toward the subpixel SP3.

[0052] In each of the segments SG1, SG2, and SG3, both ends of the upper portion 62 protrude from both side surfaces of the axis layer 64. In the segment SG1 of FIG. 4, the protruding length of the end of the upper portion 62 on the subpixel SP1 side is greater than the protruding length of the end of the upper portion 62 on the slit SL side. Similarly, in the segment SG2 of FIG. 4, the protruding length of the end of the upper portion 62 on the subpixel SP2 side is greater than the protruding length of the end of the upper portion 62 on the slit SL side. Also, in the segment SG3 of FIG. 5, the protruding length of the end of the upper portion 62 on the subpixel SP3 side is greater than the protruding length of the end of the upper portion 62 on the slit SL side. The present invention is not limited to these examples, and the protruding lengths of both ends of the upper portion 62 may be equal in each of the segments SG1, SG2, and SG3.

[0053] As shown in Fig. 4, the ends E1 and E2 of the sealing layers SE11 and SE12 are located within the slits SL. In the example of Fig. 4, the ends E1 and E2 are spaced apart in the X direction. As another example, the ends E1 and E2 may be in contact with each other.

[0054] 5, the ends E1 and E3 of the sealing layers SE11 and SE13 are located within the slits SL. In the example of FIG. 5, the ends E1 and E3 are spaced apart in the X direction. As another example, the ends E1 and E3 may be in contact with each other.

[0055] Gaps GP1, GP2, GP3 (first to third gaps) are formed below the ends E1, E2, E3, respectively. In this embodiment, the gaps GP1, GP2, GP3 correspond to the spaces between the sealing layers SE11, SE12, SE13 and the bottom layer 63, respectively.

[0056] 4 and 5, the gaps GP1, GP2, and GP3 are entirely filled with the resin layer RS1. As another example, the resin layer RS1 may fill a portion of the gaps GP1, GP2, and GP3, with the remaining portions being hollow. As yet another example, the stacked films FL1, FL2, and FL3 may be present in at least a portion of the gaps GP1, GP2, and GP3, respectively.

[0057] Next, an example of a method for manufacturing the display device DSP will be described. 6 is a flowchart showing an example of a method for manufacturing the display device DSP. In manufacturing the display device DSP, first, a circuit layer 11 is formed above a substrate 10 (step PR1 in FIG. 6). Then, an organic insulating layer 12 is formed to cover the circuit layer 11 (step PR2 in FIG. 6).

[0058] After step PR2, lower electrodes LE1, LE2, and LE3 are formed on the organic insulating layer 12 (step PR3 in FIG. 6). Furthermore, a rib layer 5 is formed to cover the lower electrodes LE1, LE2, and LE3 (step PR4 in FIG. 6). At this point, pixel openings AP1, AP2, and AP3 are not provided in the rib layer 5. The rib layer 5 can be formed by CVD (Chemical Vapor Deposition).

[0059] After the rib layer 5 is formed, the partition wall 6 including the segments SG1, SG2, and SG3 is formed (step PR5 in FIG. 6). FIGS. 7A to 7I are schematic cross-sectional views showing a first example of a method for forming the partition wall 6. These figures show how adjacent segments SG1 and SG2 are formed with a slit SL interposed between them, as in FIG. 4. Note that elements below the organic insulating layer 12 are omitted in FIGS. 7A to 7I.

[0060] 7A, in forming the partition wall 6, a first layer L1 to be processed into the bottom layer 63, a second layer L2 to be processed into the shaft layer 64, a third layer L3 to be processed into the first top layer 65, and a fourth layer L4 to be processed into the second top layer 66 are formed in this order on the rib layer 5. Furthermore, resists having planar shapes corresponding to the segments SG1, SG2, and SG3 are disposed on the fourth layer L4. In FIG. 7A, a resist Ra1 corresponding to the segment SG1 and a resist Ra2 corresponding to the segment SG2 are shown.

[0061] For example, the first layer L1 is made of a molybdenum-tungsten alloy, the second layer L2 is made of aluminum, the third layer L3 is made of titanium, and the fourth layer L4 is made of ITO. These layers can be formed by sputtering.

[0062] 7A, the second layer L2 is thicker than the first layer L1, the third layer L3, and the fourth layer L4. In one example, the first layer L1 is 50 nm thick, the second layer L2 is 730 nm thick, the third layer L3 is 150 nm thick, and the fourth layer L4 is 50 nm thick.

[0063] Next, as shown in FIG. 7B, the fourth layer L4 is etched (e.g., wet-etched). This removes the fourth layer L4 exposed from the resists Ra1 and Ra2. The fourth layer L4 remaining under the resists Ra1 and Ra2 corresponds to the second top layer 66 of the segments SG1 and SG2.

[0064] After the second top layer 66 is formed, the third layer L3 is etched (e.g., dry etched) as shown in FIG. 7C. This removes the portions of the third layer L3 exposed from the second top layer 66. The third layer L3 remaining under the second top layer 66 corresponds to the first top layer 65 of the segments SG1 and SG2. Furthermore, this etching reduces the thickness of the portions of the second layer L2 exposed from the first top layer 65. In the example of FIG. 7C, this etching slightly reduces the widths of the resists Ra1 and Ra2.

[0065] Next, as shown in FIG. 7D, the second layer L2 is etched (e.g., wet-etched). This removes the portions of the second layer L2 where the thickness has been reduced. Furthermore, the width of the second layer L2 below the first top layer 65 is reduced. The second layer L2 remaining below the first top layer 65 corresponds to the axial layer 64 of the segments SG1 and SG2.

[0066] 7D, the prototype of the overhanging segments SG1 and SG2 is completed, and a slit SL is formed between these segments SG1 and SG2.

[0067] Next, as shown in FIG. 7E, the resists Ra1 and Ra2 are removed (peeled off). Furthermore, as shown in FIG. 7F, a resist Rb is formed to cover the segments SG1 and SG2. The resist Rb fills the slit SL. That is, the resist Rb covers the side surfaces of the shaft layer 64 of the segments SG1 and SG2 on the slit SL side. The other side surface of the shaft layer 64 is not covered by the resist Rb.

[0068] After the resist Rb is formed, the first layer L1 is etched (e.g., dry-etched) as shown in FIG. 7G. This removes the portions of the first layer L1 exposed from the resist Rb and the axis layer 64. The first layer L1 remaining below the axis layer 64 and the resist Rb corresponds to the bottom layer 63 of the partition wall 6. This process determines the protrusion length La of the first top layer 65 from the end of the bottom layer 63 in each of the segments SG1 and SG2. In the example of FIG. 7G, the end of the bottom layer 63 is slightly recessed from the side surface of the axis layer 64.

[0069] Next, as shown in FIG. 7H, the shaft layer 64 exposed from the resist Rb is etched (e.g., wet etching). In this etching, the side surfaces of the shaft layer 64 exposed from the resist Rb are recessed. This process determines the protrusion length Lb of the first top layer 65 from the side surfaces of the shaft layer 64 in each of the segments SG1 and SG2.

[0070] Note that the side surface of the shaft layer 64 on the slit SL side is not exposed to the etching. Therefore, the protrusion length Lc of the first top layer 65 from the side surface of the shaft layer 64 on the slit SL side may be smaller than the protrusion length Lb. After the etching shown in FIG. 7H, the resist Rb is removed (peeled off) as shown in FIG. 7I.

[0071] 8A to 8L are schematic cross-sectional views showing a second example of a method for forming the partition wall 6. As with FIGS. 7A to 7I, these figures show how adjacent segments SG1 and SG2 are formed with a slit SL interposed between them.

[0072] 8A, in the second example, a first layer L1, a second layer L2, a third layer L3, and a fourth layer L4 are formed in this order on the rib layer 5. Furthermore, a resist Rd is formed on the fourth layer L4. The resist Rd has a planar shape corresponding to the entire partition wall 6 including the segments SG1, SG2, SG3, and the slits SL.

[0073] 8B, the fourth layer L4 is etched (for example, wet etching), thereby removing the fourth layer L4 exposed from the resist Rd.

[0074] 8C, the third layer L3 is etched (e.g., dry etched). This removes the portion of the third layer L3 exposed from the fourth layer L4. This etching reduces the thickness of the portion of the second layer L2 exposed from the third layer L3. Also, the width of the resist Rd is slightly reduced.

[0075] Next, as shown in FIG. 8D, the second layer L2 is etched (e.g., wet etched). This removes the portion of the second layer L2 where the thickness has been reduced. Furthermore, the width of the second layer L2 below the third layer L3 is reduced.

[0076] Thereafter, as shown in FIG. 8E, the first layer L1 is etched (e.g., dry etching). This removes the portion of the first layer L1 exposed from the second layer L2. The first layer L1 remaining below the second layer L2 corresponds to the bottom layer 63 of the partition wall 6. This process determines the protrusion length La similar to that shown in FIG. 7G. In the example of FIG. 8E, the end of the bottom layer 63 is slightly recessed from the side surface of the second layer L2.

[0077] Next, as shown in FIG. 8F, etching (e.g., wet etching) is performed on the second layer L2. During this etching, the side surfaces of the second layer L2 are recessed. This process determines the protrusion length Lb similar to that shown in FIG. 7H.

[0078] After the etching, the resist Rd is removed (peeled off) as shown in FIG. 8G. Furthermore, resists Re1 and Re2 are formed as shown in FIG. 8H. The resist Re1 has a shape corresponding to the outer shape of the segment SG1. The resist Re2 has a shape corresponding to the outer shape of the segment SG2.

[0079] After the resists Re1 and Re2 are formed, the fourth layer L4 is etched (e.g., wet-etched) as shown in FIG. 8I. This removes the portions of the fourth layer L4 exposed by the resists Re1 and Re2. The first layer L1 remaining below the resists Re1 and Re2 corresponds to the second top layers 66 of the segments SG1 and SG2, respectively.

[0080] Furthermore, as shown in FIG. 8J, etching (e.g., dry etching) is performed on the third layer L3. This removes the portions of the third layer L3 exposed from the second top layer 66. The third layer L3 remaining under the second top layer 66 corresponds to the first top layer 65 of the segments SG1 and SG2. Furthermore, this etching reduces the thickness of the portions of the second layer L2 exposed from the resists Re1 and Re2 and the first top layer 65. In the example of FIG. 8J, this etching slightly recedes the ends of the resists Re1 and Re2.

[0081] Next, as shown in FIG. 8K, the second layer L2 is etched (e.g., wet-etched). This removes the portions of the second layer L2 where the thickness was reduced. Furthermore, the width of the second layer L2 below the first top layer 65 is reduced. The second layer L2 remaining below the first top layer 65 corresponds to the axial layer 64 of the segments SG1 and SG2. This process determines the protrusion length Lc similar to that shown in FIG. 7H.

[0082] After the etching shown in Fig. 8K, the resists Re1 and Re2 are removed (peeled off) as shown in Fig. 8L, thereby completing the segments SG1 and SG2.

[0083] 7A to 7I and the second example of FIG. 8A to 8L show how the segments SG1 and SG2 are formed, but the segment SG3 is also formed in these steps. The partition wall 6 is not limited to the first and second examples, and may be formed by other methods.

[0084] After the partition walls 6 are formed, pixel openings AP1, AP2, and AP3 are formed in the rib layer 5 (step PR6 in FIG. 6). Furthermore, display elements DE1, DE2, and DE3 are formed (steps PR7, PR8, and PR9 in FIG. 6).

[0085] 9A to 9F are schematic cross-sectional views showing steps for forming pixel openings AP1, AP2, and AP3 and display elements DE1, DE2, and DE3. To form the pixel openings AP1, AP2, and AP3, a resist Rf is formed to cover the segments SG1 and SG2 and the slits SL, as shown in FIG. 9A. Furthermore, the rib layer 5 is etched using this resist Rf as a mask, thereby forming the pixel openings AP1, AP2, and AP3, as shown in FIG. 9B. After the etching, the resist Rf is removed (peeled off).

[0086] To form the display element DE1, first, as shown in FIG. 9C, a laminated film FL1 and a sealing layer SE11 are formed. As shown in FIG. 3, the laminated film FL1 includes an organic layer OR1 in contact with the lower electrode LE1 through the pixel opening AP1, an upper electrode UE1 covering the organic layer OR1, and a cap layer CP1 covering the upper electrode UE1. The organic layer OR1, the upper electrode UE1, and the cap layer CP1 can be formed by, for example, vapor deposition. The sealing layer SE11 can be formed by, for example, CVD.

[0087] The stacked film FL1 and the sealing layer SE11 are formed over the entire display area DA and the peripheral area SA. The stacked film FL1 is divided by overhanging segments SG1, SG2, and SG3. The sealing layer SE11 continuously covers each divided portion of the stacked film FL1 and the segments SG1, SG2, and SG3.

[0088] Next, the stacked film FL1 and the sealing layer SE11 are patterned. In this patterning, a resist Rg is disposed on the sealing layer SE11, as shown in Fig. 9C. The resist Rg covers the subpixel SP1, the segment SG1, and part of the slit SL.

[0089] Then, an etching process is performed using the resist Rg as a mask. In this etching process, as shown in FIG. 9D, the stacked film FL1 and the sealing layer SE11 are removed in portions that are exposed by the resist Rg. This forms a display element DE1 in the subpixel SP1. This etching process may include wet etching or dry etching that is performed sequentially on the sealing layer SE11, the cap layer CP1, the upper electrode UE1, and the organic layer OR1. After these etching processes, the resist Rg is removed (peeled off).

[0090] 9D, the end E1 of the sealing layer SE11 is located in the slit SL. The stacked film FL1 below the end E1 may disappear during etching, thereby forming a gap GP1.

[0091] The display element DE2 is formed by the same process as the display element DE1. That is, first, a stacked film FL2 and a sealing layer SE12 are formed over the entire display area DA and peripheral area SA. As shown in FIG. 3, the stacked film FL2 includes an organic layer OR2 in contact with the lower electrode LE2 through the pixel opening AP2, an upper electrode UE2 covering the organic layer OR2, and a cap layer CP2 covering the upper electrode UE2. The organic layer OR2, the upper electrode UE2, and the cap layer CP2 can be formed by, for example, vapor deposition. The sealing layer SE12 can be formed by, for example, CVD.

[0092] Next, the stacked film FL2 and the sealing layer SE12 are patterned. As a result, a display element DE2 is formed in the subpixel SP2, as shown in FIG. 9E. In FIG. 9E, the end E2 of the sealing layer SE12 is located in the slit SL. The stacked film FL2 below the end E2 may be lost during etching. This forms a gap GP2.

[0093] The display element DE3 is formed by the same process as the display elements DE1 and DE2. That is, first, a stacked film FL3 and a sealing layer SE13 are formed over the entire display area DA and peripheral area SA. As shown in FIG. 3, the stacked film FL3 includes an organic layer OR3 in contact with the lower electrode LE3 through the pixel opening AP3, an upper electrode UE3 covering the organic layer OR3, and a cap layer CP3 covering the upper electrode UE3. The organic layer OR3, the upper electrode UE3, and the cap layer CP3 can be formed by, for example, vapor deposition. The sealing layer SE13 can be formed by, for example, CVD.

[0094] Next, the stacked film FL3 and the sealing layer SE13 are patterned. As a result, a display element DE3 is formed in the subpixel SP3, as shown in FIG. 9F. In FIG. 9F, the end E3 of the sealing layer SE13 is located in the slit SL. The stacked film FL3 below the end E3 may be lost during etching. This forms a gap GP3.

[0095] Although it is assumed here that the display elements DE1, DE2, and DE3 are formed in this order, the display elements DE1, DE2, and DE3 may be formed in a different order.

[0096] After step PR9, a resin layer RS1 is formed (step PR10 in FIG. 6). After step PR10, a sealing layer SE2 covering the resin layer RS1 is formed, for example, by CVD (step PR11 in FIG. 6). Furthermore, a resin layer RS2 covering the sealing layer SE2 is formed (step PR12 in FIG. 6). The resin layers RS1 and RS2 can be formed, for example, by an inkjet method.

[0097] Through the steps described above, it is possible to obtain a display device DSP having the structure shown in Figures 1 to 5. The manufacturing method of the display device DSP is not limited to the example given here, and can be modified as appropriate.

[0098] According to the present embodiment, the yield of the display device DSP can be improved. The following describes this effect in detail.

[0099] 10 is a schematic cross-sectional view showing a configuration according to a comparative example of the present embodiment. Similar to FIG. 5, this figure focuses on the vicinity of the boundary between the subpixels SP1 and SP3. In this comparative example, the axial layer 64 and the upper portion 62 of the partition wall 6 are not divided into segments SG1, SG2, and SG3. Therefore, a single overhanging partition wall 6 is disposed between the subpixels SP1 and SP3. The ends E1 and E3 of the sealing layers SE11 and SE13 are located above the partition wall 6.

[0100] In this comparative example, a gap GP1 is also formed below the end E1. This gap GP1 is generated when the laminated film FL1 below the end E1 disappears during the etching process shown in FIG. 9D. The gap GP1 may widen due to the etching gas used in the dry etching or the etching solution used in the wet etching process used in forming the display elements DE2 and DE3.

[0101] 10, the gap GP1 reaches the vicinity of the laminated film FL1 that constitutes the display element DE1. If the gap GP1 widens further, a path leading to the laminated film FL1 may be formed. If this path is formed, the laminated film FL1 may be damaged in the subsequent etching and cleaning processes.

[0102] In contrast, in this embodiment, the partition wall 6 has segments SG1, SG2, and SG3 separated by slits SL. Furthermore, as shown in FIG. 5, the end E1 of the sealing layer SE11 is located at the slit SL1. That is, the overhanging segment SG1 is interposed between the gap GP1 and the laminated film FL1 that constitutes the display element DE1. In this structure, even if the gap GP1 widens during the etching process used to form the display elements DE2 and DE3, it is unlikely to reach the laminated film FL1 that constitutes the display element DE1.

[0103] In this way, in this embodiment, the situation described using the comparative example is suppressed, and therefore it is possible to select highly isotropic conditions for etching the display elements DE1, DE2, and DE3 and to extend the etching time, thereby suppressing the generation of residues due to insufficient etching and enabling the manufacture of a display device DSP with excellent reliability.

[0104] In this embodiment, a conductive bottom layer 63 is disposed below the segments SG1, SG2, and SG3. This bottom layer 63 is not divided by slits SL. With this configuration, a common voltage can be supplied to the segments SG1, SG2, and SG3 through the bottom layer 63. Therefore, there is no need to provide a structure in the display area DA for supplying power from the circuit layer 11 to the segments SG1, SG2, and SG3.

[0105] [Second embodiment] The second embodiment will be described. The same configuration as the first embodiment can be applied to configurations that are not specifically mentioned.

[0106] 11 is a schematic plan view of a display area DA of a display device DSP according to a second embodiment. This figure shows an area corresponding to four pixels PX, as in FIG. 2. In this embodiment, one segment SG2 is provided for each subpixel SP2. Each segment SG2 surrounds the subpixel SP2. Adjacent segments SG2 in the Y direction are separated by a slit SL. That is, the segments SG2 are surrounded by the slit SL.

[0107] For example, segment SG2, like the example in Fig. 4, includes a shaft layer 64, a first top layer 65, and a second top layer 66. A bottom layer 63 is disposed below the shaft layer 64 of segment SG2. The bottom layer 63 is not separated by the slits SL between segments SG2 adjacent to each other in the Y direction, and overlaps with the slits SL in plan view.

[0108] In this embodiment, the sealing layers SE12 of the subpixels SP2 are independent of each other. For example, the end E2 of each sealing layer SE12 is located in the slit SL along the entire periphery.

[0109] The configuration of this embodiment can also achieve the same effects as those of Embodiment 1. Furthermore, by providing an independent segment SG2 and sealing layer SE12 for each of the multiple subpixels SP2, the display element DE2 in each subpixel SP2 can be individually and effectively sealed.

[0110] [Third embodiment] The third embodiment will be described. The same configuration as the first embodiment can be applied to configurations that are not specifically mentioned.

[0111] 12 is a schematic plan view of a display area DA of a display device DSP according to a third embodiment. This figure shows an area corresponding to four pixels PX, as in FIG. 2. In this embodiment, the partition wall 6 includes a connection portion CP that connects the segments SG1 and SG3 aligned in the Y direction.

[0112] In the example of Fig. 12, segments SG1 and SG3 are connected by two connection parts CP. These connection parts CP connect, for example, both ends of segments SG1 and SG3 in the X direction. However, the number and arrangement positions of connection parts CP connecting segments SG1 and SG3 are not limited to the example of Fig. 12.

[0113] Fig. 13 is a schematic cross-sectional view of the display device DSP taken along line XIII-XIII in Fig. 12. In this embodiment, the bottom layer 63 is divided at a slit SL between the segments SG1 and SG2. In the slit SL, a resin layer RS1 covers the rib layer 5.

[0114] 13, the bottom layer 63 is divided at the slit SL between the segments SG1 and SG3, and also at the slit SL between the segments SG2 and SG3.

[0115] A common voltage is supplied to the conductor formed by the segments SG1 and SG2 connected by the connection part CP, for example, through a power supply part provided in the peripheral area SA. The same applies to the segment SG3.

[0116] In this embodiment, the same effects as in the first embodiment can be obtained. Furthermore, since the bottom layer 63 is not disposed in the slit SL, the transmittance in the slit SL can be improved. This configuration is advantageous, for example, when an optical sensor is disposed on the back side of the display device DSP.

[0117] 12, segments SG2 divided for each subpixel SP2 may be arranged as in the second embodiment. In this case, adjacent segments SG2 in the Y direction may be connected by a connection portion CP.

[0118] [Fourth embodiment] A fourth embodiment will be described. The same configurations as those of the above-described embodiments can be applied to configurations that are not specifically mentioned.

[0119] 14 is a schematic plan view of a display area DA of a display device DSP according to a fourth embodiment. In this embodiment, a plurality of subpixels SP1 are arranged in the Y direction, a plurality of subpixels SP2 are arranged in the Y direction, and a plurality of subpixels SP3 are arranged in the Y direction. For example, one pixel PX is composed of subpixels SP1, SP2, and SP3 arranged in the X direction.

[0120] As in the above-described embodiments, the partition wall 6 includes segments SG1, SG2, and SG3. Furthermore, slits SL are formed between the segments SG1, SG2, and SG3.

[0121] The sealing layer SE11 is formed across multiple subpixels SP1 aligned in the Y direction. The sealing layer SE12 is formed across multiple subpixels SP2 aligned in the Y direction. The sealing layer SE13 is formed across multiple subpixels SP3 aligned in the Y direction. Ends E1, E2, and E3 of the sealing layers SE11, SE12, and SE13 are all located in the slits SL.

[0122] The segments SG1, SG2, and SG3 can have the same configuration as in the above-described embodiments. For example, the bottom layer 63 may not be divided by the slits SL as in the first embodiment, or may be divided by the slits SL as in the third embodiment.

[0123] The configuration of this embodiment can also achieve the same effects as those of the above-described embodiments. Various layouts other than those disclosed in this embodiment and the above-described embodiments can be applied to the subpixels SP1, SP2, and SP3.

[0124] [Fifth embodiment] A fifth embodiment will be described. The same configurations as those of the above-described embodiments can be applied to configurations that are not specifically mentioned.

[0125] 15 is a schematic plan view of a display area DA of a display device DSP according to a fifth embodiment. The layout of subpixels SP1, SP2, and SP3 shown in FIG. 15 is the same as that shown in FIG. 2 in the first embodiment. However, in this embodiment, the partition wall 6 has segments SGa and SGb (first and second segments) separated by slits SL extending in the Y direction. Segment SGa surrounds a plurality of subpixels SP1 and SP3 aligned in the Y direction and a plurality of subpixels SP2 aligned in the Y direction. Similarly, segment SGb surrounds a plurality of subpixels SP1 and SP3 aligned in the Y direction and a plurality of subpixels SP2 aligned in the Y direction.

[0126] 15, the sealing layer SE12 extends across multiple subpixels SP2 aligned in the Y direction. In addition, the ends of the sealing layers SE11 and SE12 adjacent to each other without a slit SL, the ends of the sealing layers SE12 and SE13 adjacent to each other without a slit SL, and the ends of the sealing layers SE11 and SE13 adjacent to each other in the Y direction overlap with each other.

[0127] Fig. 16 is a schematic cross-sectional view of the display device DSP taken along line XVI-XVI in Fig. 15. Like the segments SG1, SG2, and SG3 in the above-described embodiments, the segments SGa and SGb include an axis layer 64, a first top layer 65, and a second top layer 66. A bottom layer 63 is disposed below the segments SGa and SGb. In the example of Fig. 16, the bottom layer 63 is divided by a slit SL.

[0128] The ends E1 and E2 of the sealing layers SE11 and SE12 are located within the slits SL. In the example of Fig. 16, the ends E1 and E2 are spaced apart in the X direction. As another example, the ends E1 and E2 may be in contact with each other. Gaps GP1 and GP2 are formed below the ends E1 and E2, respectively.

[0129] Fig. 17 is a schematic cross-sectional view of the display device DSP taken along line XVII-XVII in Fig. 15. At the position shown in this cross-sectional view, ends E1 and E2 of sealing layers SE11 and SE12 are located above the partition wall 6. Furthermore, end E2 is located above end E1.

[0130] 17, a stacked film FL1 is disposed between the upper portion 62 and the sealing layer SE11. Also, a stacked film FL2 is disposed between the upper portion 62 and the sealing layer SE12. However, this example is not limiting, and the stacked films FL1 and FL2 do not necessarily have to be disposed between the upper portion 62 and the sealing layers SE11 and SE12.

[0131] The structure near the boundary between the subpixels SP2 and SP3 aligned in the X direction with the slit SL between them is the same as that shown in Fig. 16. The structure near the boundary between the subpixels SP2 and SP3 aligned in the X direction without the slit SL between them and the structure near the boundary between the subpixels SP1 and SP2 aligned in the Y direction are the same as those shown in Fig. 17.

[0132] 16 is similar to the structure in the first embodiment shown in Fig. 4 and Fig. 5. Therefore, in the vicinity of the slit SL, damage to the sealing layer SE11 that would reach the display element DE1 is suppressed in the etching process for forming the display elements DE2 and DE3, as in the first embodiment.

[0133] Furthermore, in this embodiment, the end E1 of the sealing layer SE11 overlaps the ends E2 and E3 of the sealing layers SE12 and SE13 in the areas where the slits SL are not provided. As a result, the sealing layers SE12 and SE13 protect the vicinity of the end E1 of the sealing layer SE11 during the etching process for forming the display elements DE2 and DE3, and damage to the sealing layer SE11 as shown in the above-mentioned comparative example is suppressed. As a result, as in the above-mentioned embodiments, a display device DSP can be obtained in which the display element DE1 is well sealed by the sealing layer SE11.

[0134] [Sixth embodiment] A sixth embodiment will be described. The same configurations as those of the above-described embodiments can be applied to configurations that are not specifically mentioned.

[0135] Fig. 18 is a schematic plan view of a display area DA of a display device DSP according to a sixth embodiment. The configuration shown in Fig. 18 is generally similar to that shown in Fig. 15. However, in Fig. 18, the sealing layer SE13 does not overlap with the slits SL. The end E3 of the sealing layer SE13 is located above the partition walls 6 (above the segments SGa and SGb).

[0136] The configuration of this embodiment can also achieve the same effects as those of the fifth embodiment. Furthermore, with the configuration of this embodiment, the transmittance of the slit SL can be improved to the extent that the sealing layer SE13 does not overlap with the slit SL. Note that the sealing layer SE13 is formed after the sealing layers SE11 and SE12. Therefore, the sealing layer SE13 is less likely to suffer the damage described above with respect to the sealing layer SE11.

[0137] In each of the above embodiments, the term "partition wall" includes various overhanging structures. Even if the overhanging structure has a shape different from the partition wall disclosed in each embodiment, the part that protrudes to the side corresponds to the "upper part," and the part that recedes below the part that protrudes to the side corresponds to the "lower part."

[0138] The display device DSP may further include a plurality of dummy pixels arranged around the display area DA. The configuration of the display area DA disclosed in each embodiment can also be applied to a dummy pixel area including these dummy pixels.

[0139] All display devices that can be implemented by a person skilled in the art by appropriately modifying the design based on the display devices disclosed in each embodiment also fall within the scope of the present invention as long as they include the gist of the present invention.

[0140] Within the scope of the concept of the present invention, a person skilled in the art may conceive of various modifications, and these modifications are also understood to fall within the scope of the present invention. For example, even if a person skilled in the art appropriately adds or deletes components or modifies the design of the above-described embodiment, or adds or omits steps or modifies conditions, these modifications are also included within the scope of the present invention as long as they maintain the gist of the present invention.

[0141] Furthermore, with regard to other effects brought about by the aspects described in the above embodiments, those that are clear from the description in this specification or that can be appropriately thought of by a person skilled in the art are naturally understood to be brought about by the present invention. [Explanation of symbols]

[0142] DSP...display device, DA...display area, SA...peripheral area, PX...pixel, SP1, SP2, SP3...subpixel, LE1, LE2, LE3...lower electrode, OR1, OR2, OR3...organic layer, UE1, UE2, UE3...upper electrode, SE11, SE12, SE13, SE2...sealing layer, RS1, RS2...resin layer, 5...rib layer, 6...partition wall, 61...lower part, 62...upper part, 63...bottom layer, 64...axis layer, 65...first top layer, 66...second top layer.

Claims

1. a first subpixel and a second subpixel; a partition wall including a first segment surrounding the first subpixel and a second segment surrounding the second subpixel; a first stacked film including an electrode disposed in the first subpixel and electrically connected to the first segment; a second stacked film including an electrode disposed in the second subpixel and electrically connected to the second segment; a first sealing layer formed of an inorganic insulating material and covering the first laminated film; a second sealing layer formed of an inorganic insulating material and covering the second laminated film; Equipped with the first segment and the second segment are separated by a slit, the first sealing layer overlaps with at least a portion of the slit in a plan view; Display device.

2. the second sealing layer overlaps with at least a portion of the slit in a plan view; The display device according to claim 1 .

3. the partition wall further includes a bottom layer overlapping the first segment, the second segment, and the slit in a plan view; Each of the first segment and the second segment comprises: a shaft layer disposed on the bottom layer; An upper portion disposed on the axial layer and having an end portion protruding beyond a side surface of the axial layer; Equipped with In the slit, the shaft layer and the upper portion of the first segment are spaced apart from the shaft layer and the upper portion of the second segment. The display device according to claim 1 .

4. The first segment is surrounded by the slit. The display device according to claim 1 .

5. The end of the first sealing layer is located in the slit over the entire periphery. The display device according to claim 4 .

6. a plurality of the second sub-pixels; the second segment surrounds each of the second sub-pixels, the second sealing layer continuously covers the second sub-pixels; The display device according to claim 4 .

7. The second segment is surrounded by the slit. The display device according to claim 4 .

8. The end of the second sealing layer is located in the slit over the entire periphery. The display device according to claim 7 .

9. A third subpixel; and a third stacked film disposed in the third subpixel and including an electrode electrically connected to the partition wall; a third sealing layer formed of an inorganic insulating material and covering the third stacked film; Furthermore, the partition wall further includes a third segment surrounding the third subpixel; The display device according to claim 1 .

10. the third segment is surrounded by the slit, an end portion of the third sealing layer being located in the slit over the entire periphery; The display device according to claim 9 .

11. the partition wall further includes a bottom layer overlapping the first segment, the second segment, and the third segment in a plan view; Each of the first to third segments includes: a shaft layer disposed on the bottom layer; An upper portion disposed on the axial layer and having an end portion protruding beyond a side surface of the axial layer; Equipped with At the slit, the bottom layer is divided, the shaft layers of the first to third segments are spaced apart, and the upper portions of the first to third segments are spaced apart. The display device according to claim 9 .

12. the partition wall has a connection portion that connects the first segment and the third segment. The display device according to claim 11.

13. the first subpixel and the second subpixel are aligned in a first direction, the first subpixel and the third subpixel are aligned in a second direction intersecting the first direction; 13. The display device according to any one of claims 9 to 12.

14. the first subpixel, the second subpixel, and the third subpixel are aligned in a first direction; 13. The display device according to any one of claims 9 to 12.

15. a first subpixel and a second subpixel; a partition wall including a first segment surrounding the first subpixel and a second segment surrounding the second subpixel; a first stacked film including an electrode disposed in the first subpixel and electrically connected to the first segment; a second stacked film including an electrode disposed in the second subpixel and electrically connected to the second segment; a first sealing layer formed of an inorganic insulating material and covering the first laminated film; a second sealing layer formed of an inorganic insulating material and covering the second laminated film; Equipped with the first segment and the second segment are separated by a slit, the first sealing layer has a first end located within the slit; a first gap formed below the first end; Display device.

16. further comprising a resin layer covering the first sealing layer and the second sealing layer; At least a portion of the first gap is filled with the resin layer. The display device according to claim 15.

17. the second sealing layer has a second end located within the slit. The display device according to claim 15.

18. a second gap is formed below the second end; The display device according to claim 17.

19. further comprising a resin layer covering the first sealing layer and the second sealing layer; At least a portion of the second gap is filled with the resin layer.

19. The display device according to claim 18.

20. the partition wall further includes a bottom layer overlapping the first segment, the second segment, and the slit in a plan view; Each of the first segment and the second segment comprises: a shaft layer disposed on the bottom layer; An upper portion disposed on the axial layer and having an end portion protruding beyond a side surface of the axial layer; Equipped with In the slit, the shaft layer and the upper portion of the first segment are spaced apart from the shaft layer and the upper portion of the second segment.

20. A display device according to any one of claims 15 to 19.

Images