Semiconductor light emitting device and method for manufacturing semiconductor light emitting device

Abstract

To improve reliability of a semiconductor light-emitting element.SOLUTION: The semiconductor light-emitting element 10 includes an n-type semiconductor layer 24, an active layer 26, a p-type semiconductor layer 28, a contact electrode in contact with an upper surface of the n-type semiconductor layer 24 or the p-type semiconductor layer 28, a current diffusion layer provided on the contact electrode and including an upper TiN layer made of titanium nitride in which a difference between an R value and a B value is less than 25 in RGB measurement values represented by numerical values of 0 or more and 255 or less, a protective layer having a pad opening provided on the current diffusion layer, covering the n-type semiconductor layer 24, the active layer 26, the p-type semiconductor layer 28, and the current diffusion layer at a location different from the pad opening, being in contact with the upper TiN layer, and being made of a dielectric material, and a pad electrode in contact with the current diffusion layer in the pad opening and provided on the protective layer outside the pad opening.SELECTED DRAWING: Figure 1

Description

[Technical Field]

[0001] The present invention relates to a semiconductor light-emitting device and a method for manufacturing the same. [Background technology]

[0002] A semiconductor light-emitting element has an n-type semiconductor layer, an active layer, and a p-type semiconductor layer stacked on a substrate, with an n-side electrode provided on the n-type semiconductor layer and a p-side electrode provided on the p-type semiconductor layer. A protective layer made of a dielectric material such as silicon oxide or silicon nitride is provided on the surface of the semiconductor light-emitting element (see, for example, Patent Document 1). [Prior art documents] [Patent documents]

[0003] [Patent Document 1] Japanese Patent Application Laid-Open No. 2016-171141 Summary of the Invention [Problem to be solved by the invention]

[0004] In order to further improve the reliability of the semiconductor light emitting device, it is preferable to improve the sealing properties of the protective layer.

[0005] The present invention has been made in view of these problems, and has an object to provide a technique for improving the reliability of semiconductor light-emitting devices. [Means for solving the problem]

[0006] A semiconductor light-emitting element according to one embodiment of the present invention comprises an n-type semiconductor layer, an active layer provided on a first upper surface of the n-type semiconductor layer, a p-type semiconductor layer provided on the active layer, a contact electrode in contact with a second upper surface of the n-type semiconductor layer different from the first upper surface or in contact with the upper surface of the p-type semiconductor layer, a current spreading layer provided on the contact electrode and including an upper TiN layer made of titanium nitride in which the difference between the R value and the B value is less than 25 in RGB measurement values ​​expressed as numerical values ​​between 0 and 255, a protective layer having a pad opening provided on the current spreading layer, covering the n-type semiconductor layer, the active layer, the p-type semiconductor layer and the current spreading layer at locations other than the pad opening, in contact with the upper TiN layer and made of a dielectric material, and a pad electrode in contact with the current spreading layer at the pad opening and provided on the protective layer above the pad opening.

[0007] Another aspect of the present invention is a method for manufacturing a semiconductor light-emitting device. This method includes the steps of forming an active layer on an n-type semiconductor layer, forming a p-type semiconductor layer on the active layer, removing portions of the p-type semiconductor layer and the active layer to expose an upper surface of the n-type semiconductor layer, forming a contact electrode in contact with the upper surface of the p-type semiconductor layer or the n-type semiconductor layer, forming a current spreading layer including an upper TiN layer on the contact electrode, forming a protective layer made of a dielectric material to cover the n-type semiconductor layer, the active layer, the p-type semiconductor layer, and the current spreading layer, removing the protective layer on the current spreading layer to form a pad opening, and forming a pad electrode in contact with the current spreading layer in the pad opening and disposed on the protective layer outside the pad opening. The upper TiN layer is formed by reactive sputtering under conditions where the flow rate ratio of nitrogen gas to argon gas is 8% or less. [Effects of the Invention]

[0008] According to the present invention, the reliability of the semiconductor light emitting element can be improved. [Brief explanation of the drawings]

[0009] [Figure 1]1 is a cross-sectional view schematically illustrating a configuration of a semiconductor light emitting device according to an embodiment. [Figure 2] 3 is a cross-sectional view schematically showing the configuration of a p-side contact electrode, a p-side current diffusion layer, and a p-side pad electrode. FIG. [Figure 3] 3 is a cross-sectional view schematically showing the configuration of an n-side contact electrode, an n-side current diffusion layer, and an n-side pad electrode. FIG. [Figure 4] 1 is a graph showing an example of film formation conditions for titanium nitride. [Figure 5] 1 is a graph showing an example of RGB measurement values ​​of titanium nitride. [Figure 6] 1 is a table showing an example of RGB measurement values ​​and sealing properties of titanium nitride. [Figure 7] 1A to 1C are diagrams schematically illustrating a manufacturing process of a semiconductor light-emitting element. [Figure 8] 1A to 1C are diagrams schematically illustrating a manufacturing process of a semiconductor light-emitting element. [Figure 9] 1A to 1C are diagrams schematically illustrating a manufacturing process of a semiconductor light-emitting element. [Figure 10] 1A to 1C are diagrams schematically illustrating a manufacturing process of a semiconductor light-emitting element. [Figure 11] 1A to 1C are diagrams schematically illustrating a manufacturing process of a semiconductor light-emitting element. [Figure 12] 1A to 1C are diagrams schematically illustrating a manufacturing process of a semiconductor light-emitting element. [Figure 13] 1A to 1C are diagrams schematically illustrating a manufacturing process of a semiconductor light-emitting element. [Figure 14] 1A to 1C are diagrams schematically illustrating a manufacturing process of a semiconductor light-emitting element. DETAILED DESCRIPTION OF THE INVENTION

[0010] Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings. In the description, the same elements are designated by the same reference numerals, and redundant explanations will be omitted as appropriate. To facilitate understanding of the description, the dimensional ratios of the components in each drawing do not necessarily correspond to the dimensional ratios of the actual light-emitting element.

[0011] The semiconductor light-emitting device according to this embodiment is configured to emit "deep ultraviolet light" with a central wavelength λ of about 360 nm or less, and is a so-called DUV-LED (Deep UltraViolet-Light Emitting Diode) chip. In order to output deep ultraviolet light of such a wavelength, an aluminum gallium nitride (AlGaN) - based semiconductor material with a bandgap of about 3.4 eV or more is used. In this embodiment, particularly, the case of emitting deep ultraviolet light with a central wavelength λ of about 240 nm to 320 nm is shown.

[0012] In this specification, the "AlGaN-based semiconductor material" refers to a semiconductor material containing at least aluminum nitride (AlN) and gallium nitride (GaN), and includes semiconductor materials containing other materials such as indium nitride (InN). Therefore, the "AlGaN-based semiconductor material" referred to in this specification can be represented by the composition of In 1-x-y Al x Ga y N (0 < x + y ≤ 1, 0 < x < 1, 0 < y < 1), and includes AlGaN or InAlGaN. The "AlGaN-based semiconductor material" in this specification, for example, has a molar fraction of each of AlN and GaN of 1% or more, preferably 5% or more, 10% or more, or 20% or more.

[0013] Also, in order to distinguish materials that do not contain AlN, there is sometimes referred to as a "GaN-based semiconductor material". The "GaN-based semiconductor material" includes GaN and InGaN. Similarly, in order to distinguish materials that do not contain GaN, there is sometimes referred to as an "AlN-based semiconductor material". The "AlN-based semiconductor material" includes AlN and InAlN.

[0014] 1 is a cross-sectional view schematically illustrating a configuration of a semiconductor light emitting device 10 according to an embodiment. The semiconductor light emitting device 10 includes a substrate 20, a base layer 22, an n-type semiconductor layer 24, an active layer 26, a p-type semiconductor layer 28, a p-side contact electrode 30, an n-side contact electrode 32, a p-side current spreading layer 34, an n-side current spreading layer 36, a first protective layer 38, a second protective layer 40, a p-side pad electrode 42, an n-side pad electrode 44, a p-side junction layer 46, and an n-side junction layer 48.

[0015] 1, the direction indicated by arrow A may be referred to as the "vertical direction" or "thickness direction." Furthermore, when viewed from the substrate 20, the direction away from the substrate 20 may be referred to as the upper side, and the direction toward the substrate 20 may be referred to as the lower side.

[0016] The substrate 20 has a first main surface 20a and a second main surface 20b opposite to the first main surface 20a. The first main surface 20a is a crystal growth surface for growing each layer from the base layer 22 to the p-type semiconductor layer 28. The substrate 20 is made of a material that is transparent to the deep ultraviolet light emitted by the semiconductor light emitting device 10, such as sapphire (Al2O3). A fine uneven pattern with a depth and pitch of submicron (1 μm or less) is formed on the first main surface 20a. Such a substrate 20 is also called a patterned sapphire substrate (PSS). The second main surface 20b is a light extraction surface for extracting the deep ultraviolet light emitted by the active layer 26 to the outside. The substrate 20 may be made of AlN or AlGaN. The substrate 20 may be a normal substrate in which the first main surface 20a is an unpatterned flat surface.

[0017] The base layer 22 is provided on the first main surface 20a of the substrate 20. The base layer 22 is an underlayer (template layer) for forming the n-type semiconductor layer 24. The base layer 22 is, for example, an undoped AlN layer, and more specifically, an AlN layer grown at high temperature (HT-AlN; High Temperature-AlN). The base layer 22 may include an undoped AlGaN layer formed on the AlN layer. When the substrate 20 is an AlN substrate or an AlGaN substrate, the base layer 22 may be composed of only an undoped AlGaN layer. That is, the base layer 22 includes at least one of an undoped AlN layer and an AlGaN layer.

[0018] The n-type semiconductor layer 24 is provided on the upper surface 22a of the base layer 22. The n-type semiconductor layer 24 is made of an n-type AlGaN-based semiconductor material and is doped with, for example, Si as an n-type impurity. The n-type semiconductor layer 24 has a composition ratio selected so as to transmit the deep ultraviolet light emitted by the active layer 26. For example, the n-type semiconductor layer 24 is configured so that the molar fraction of AlN is 25% or more, preferably 40% or more or 50% or more. The n-type semiconductor layer 24 has a band gap larger than the wavelength of the deep ultraviolet light emitted by the active layer 26, for example, the band gap is 4.3 eV or more. The n-type semiconductor layer 24 is preferably configured so that the molar fraction of AlN is 80% or less, i.e., the band gap is 5.5 eV or less, and more preferably, the molar fraction of AlN is 70% or less (i.e., the band gap is 5.2 eV or less). The n-type semiconductor layer 24 has a thickness of 1 μm or more and 3 μm or less, for example, a thickness of approximately 2 μm.

[0019] The n-type semiconductor layer 24 has an impurity concentration of Si of 1×10 18 / cm 3 5x10 or more 19 / cm 3 The n-type semiconductor layer 24 is configured so that the Si concentration is 5×10 18 / cm 3 3x10 or more 19 / cm 3 It is preferable to configure it so that it is 7×10 18 / cm3 Over 2×10 19 / cm 3 In one embodiment, the Si concentration of the n-type semiconductor layer 24 is preferably 1×10 19 / cm 3 It is around, specifically 8 x 10 18 / cm 3 Over 1.5 x 10 19 / cm 3 The range is as follows:

[0020] The n-type semiconductor layer 24 has a first upper surface 24a and a second upper surface 24b. The first upper surface 24a is a portion where the active layer 26 is formed, and the second upper surface 24b is a portion where the active layer 26 is not formed.

[0021] The active layer 26 is provided on the first upper surface 24a of the n-type semiconductor layer 24. The active layer 26 is made of an AlGaN-based semiconductor material, and is sandwiched between the n-type semiconductor layer 24 and the p-type semiconductor layer 28 to form a double heterostructure. The active layer 26 is configured to have a band gap of 3.4 eV or more in order to output deep ultraviolet light with a wavelength of 355 nm or less, and the AlN composition ratio is selected so that deep ultraviolet light with a wavelength of 320 nm or less can be output, for example.

[0022] The active layer 26 has, for example, a single-layer or multi-layer quantum well structure and includes a barrier layer made of an undoped AlGaN-based semiconductor material and a well layer made of an undoped AlGaN-based semiconductor material. The active layer 26 includes, for example, a first barrier layer in direct contact with the n-type semiconductor layer 24 and a first well layer provided on the first barrier layer. One or more pairs of a barrier layer and a well layer may be additionally provided between the first well layer and the p-type semiconductor layer 28. Each of the barrier layer and the well layer has a thickness of 1 nm or more and 20 nm or less, for example, a thickness of 2 nm or more and 10 nm or less.

[0023] An electron blocking layer may be further provided between the active layer 26 and the p-type semiconductor layer 28. The electron blocking layer is made of an undoped AlGaN-based semiconductor material, for example, with an AlN molar fraction of 40% or more, preferably 50% or more. The electron blocking layer may be made of an AlN-based semiconductor material that does not contain GaN, or may be made of an AlN-based semiconductor material with an AlN molar fraction of 80% or more. The electron blocking layer has a thickness of 1 nm or more and 10 nm or less, for example, a thickness of 2 nm or more and 5 nm or less.

[0024] The p-type semiconductor layer 28 is formed on the active layer 26. The p-type semiconductor layer 28 is a p-type AlGaN-based semiconductor material layer or a p-type GaN-based semiconductor material layer, for example, an AlGaN layer or a GaN layer doped with magnesium (Mg) as a p-type impurity. The p-type semiconductor layer 28 has a thickness of, for example, 20 nm or more and 400 nm or less.

[0025] The p-type semiconductor layer 28 may be composed of multiple layers. The p-type semiconductor layer 28 may have, for example, a p-type cladding layer and a p-type contact layer. The p-type cladding layer is a p-type AlGaN layer with a higher AlN ratio than the p-type contact layer, and is provided so as to be in direct contact with the active layer 26. The p-type contact layer is a p-type AlGaN layer or p-type GaN layer with a lower AlN ratio than the p-type cladding layer. The p-type contact layer is provided on the p-type cladding layer and is provided so as to be in direct contact with the p-side contact electrode 30. The p-type cladding layer may have a p-type first cladding layer and a p-side second cladding layer.

[0026] The composition ratio of the p-type first cladding layer is selected so as to transmit deep ultraviolet light emitted by the active layer 26. The p-type first cladding layer is configured, for example, so that the molar fraction of AlN is 25% or more, preferably 40% or more or 50% or more. The AlN ratio of the p-type first cladding layer is, for example, similar to or greater than the AlN ratio of the n-type semiconductor layer 24. The AlN ratio of the p-type cladding layer may be 70% or more, or 80% or more. The p-type first cladding layer has a thickness of 10 nm or more and 100 nm or less, for example, a thickness of 15 nm or more and 70 nm or less.

[0027] The p-type second cladding layer is provided on the p-type first cladding layer. The p-type second cladding layer is a p-type AlGaN layer with a medium AlN ratio, which is lower than that of the p-type first cladding layer and higher than that of the p-type contact layer. The p-type second cladding layer is formed, for example, so that the molar fraction of AlN is 25% or more, preferably 40% or more or 50% or more. The AlN ratio of the p-type second cladding layer is formed, for example, so that it is approximately ±10% of the AlN ratio of the n-type semiconductor layer 24. The p-type second cladding layer has a thickness of 5 nm or more and 250 nm or less, for example, a thickness of 10 nm or more and 150 nm or less. Note that the p-type second cladding layer does not necessarily have to be provided, and the p-type cladding layer may be composed of only the p-type first cladding layer.

[0028] The p-type contact layer is a p-type AlGaN layer or p-type GaN layer with a relatively low AlN ratio. The p-type contact layer is configured to have an AlN ratio of 20% or less to obtain good ohmic contact with the p-side contact electrode 30, and is preferably formed to have an AlN ratio of 10% or less, 5% or less, or 0%. That is, the p-type contact layer can be formed of a p-type GaN-based semiconductor material that is substantially free of AlN. As a result, the p-type contact layer can absorb deep ultraviolet light emitted by the active layer 26. The p-type contact layer is preferably formed thin to minimize the absorption of deep ultraviolet light emitted by the active layer 26. The p-type contact layer has a thickness of 5 nm to 30 nm, for example, a thickness of 10 nm to 20 nm.

[0029] The p-side contact electrode 30 is provided on the upper surface 28a of the p-type semiconductor layer 28. The p-side contact electrode 30 is made of a material that can make ohmic contact with the p-type semiconductor layer 28 (e.g., a p-type contact layer) and has high reflectivity for deep ultraviolet light emitted by the active layer 26. The p-side contact electrode 30 includes an Rh layer that is in direct contact with the upper surface 28a of the p-type semiconductor layer 28. The p-side contact electrode 30 is made of, for example, only an Rh layer. The thickness of the Rh layer included in the p-side contact electrode 30 is 50 nm or more and 200 nm or less, for example, 70 nm or more and 150 nm or less.

[0030] The n-side contact electrode 32 is provided on the second upper surface 24b of the n-type semiconductor layer 24. The n-side contact electrode 32 includes a first Ti layer, an Al layer, a second Ti layer, and a TiN layer that are stacked in this order. The configuration of the n-side contact electrode 32 will be described in detail later with reference to FIG. 3.

[0031] The p-side current spreading layer 34 is provided on the p-side contact electrode 30. The p-side current spreading layer 34 is in contact with the p-side contact electrode 30 and may cover the entire p-side contact electrode 30. The p-side current spreading layer 34 includes a laminated film in which lower TiN layers and Rh layers are alternately stacked, and an upper TiN layer provided on the laminated film. The p-side current spreading layer 34 has a p-side connection opening 34a where the upper TiN layer is partially removed to expose the Rh layer. The configuration of the p-side current spreading layer 34 will be described in detail later with reference to FIG. 2.

[0032] The n-side current spreading layer 36 is provided on the n-side contact electrode 32. The n-side current spreading layer 36 is in contact with the n-side contact electrode 32 and may cover the entire n-side contact electrode 32. The n-side current spreading layer 36 may have a structure similar to that of the p-side current spreading layer 34, including a laminated film in which lower TiN layers and Rh layers are alternately stacked, and an upper TiN layer provided on the laminated film. The n-side current spreading layer 36 has an n-side connection opening 36a where the upper TiN layer is partially removed to expose the Rh layer. The structure of the n-side current spreading layer 36 will be described in detail later with reference to FIG. 3.

[0033] The first protective layer 38 is provided to cover the entire upper surface of the device. The first protective layer 38 covers the n-type semiconductor layer 24, the active layer 26, the p-type semiconductor layer 28, the p-side current spreading layer 34, and the n-side current spreading layer 36. The first protective layer 38 has a first p-side pad opening 38p provided on the p-side current spreading layer 34 and a first n-side pad opening 38n provided on the n-side current spreading layer 36. The first protective layer 38 covers the p-side current spreading layer 34 at a location different from the first p-side pad opening 38p and covers the n-side current spreading layer 36 at a location different from the first n-side pad opening 38n. The first protective layer 38 is in contact with the base layer 22 on the outer periphery of the n-type semiconductor layer 24. The first protective layer 38 is in contact with the upper surface 22a of the base layer 22, in contact with the second upper surface 24b and the side surface 24c of the n-type semiconductor layer 24, in contact with the side surface 26b of the active layer 26, in contact with the upper surface 28a and the side surface 28b of the p-type semiconductor layer 28, in contact with the p-side current spreading layer 34, and in contact with the n-side current spreading layer 36.

[0034] The first protective layer 38 is made of an oxide dielectric material such as silicon oxide (SiO), aluminum oxide (AlO), or hafnium oxide (HfO). The first protective layer 38 is preferably made of SiO. The thickness of the first protective layer 38 is 300 nm or more and 1500 nm or less, for example, 600 nm or more and 1000 nm or less.

[0035] The second protective layer 40 is provided to cover the entire upper surface of the device and the entire surface of the first protective layer 38. The second protective layer 40 has a second p-side pad opening 40p provided on the p-side current spreading layer 34 and a second n-side pad opening 40n provided on the n-side current spreading layer 36. The second protective layer 40 covers the first protective layer 38 at locations different from the second p-side pad opening 40p and the second n-side pad opening 40n. The second protective layer 40 is also provided on the inside of each of the first p-side pad opening 38p and the first n-side pad opening 38n. The second protective layer 40 covers the inner circumferential surface 38a of the first protective layer 38 that defines the first p-side pad opening 38p and the inner circumferential surface 38b of the first protective layer 38 that defines the first n-side pad opening 38n. The second protective layer 40 contacts the base layer 22 at the outer periphery of the first protective layer 38. The second protective layer 40 is in contact with the upper surface 22a of the base layer 22, the inner circumferential surfaces 38a and 38b of the first protective layer 38, the upper surface 34b of the p-side current diffusion layer 34, and the upper surface 36b of the n-side current diffusion layer 36.

[0036] The second protective layer 40 is made of silicon nitride (SiN x The thickness of the second protective layer 40 is 50 nm or more and 500 nm or less, for example, 100 nm or more and 400 nm or less.

[0037] The p-side pad electrode 42 and the n-side pad electrode 44 are portions to be joined when the semiconductor light emitting element 10 is mounted on a submount or the like. The p-side pad electrode 42 and the n-side pad electrode 44 include, for example, a Ni / Au or Ti / Au laminate structure. The p-side pad electrode 42 and the n-side pad electrode 44 may be configured not to contain platinum group elements such as ruthenium (Ru), rhodium (Rh), palladium (Pd), osmium (Os), iridium (Ir), or platinum (Pt). The p-side pad electrode 42 and the n-side pad electrode 44 each have a thickness of 100 nm or more, for example, 200 nm or more and 1000 nm or less.

[0038] The p-side pad electrode 42 is provided on the p-side current diffusion layer 34 and is in contact with the upper surface 34b of the p-side current diffusion layer 34 at the second p-side pad opening 40p. The p-side pad electrode 42 is in contact with the Rh layer of the p-side current diffusion layer 34 at the p-side connection opening 34a. The p-side pad electrode 42 is electrically connected to the p-side contact electrode 30 via the p-side current diffusion layer 34. The p-side pad electrode 42 is provided so as to cover the second p-side pad opening 40p and is provided on the second protective layer 40 outside the second p-side pad opening 40p.

[0039] The n-side pad electrode 44 is provided on the n-side current diffusion layer 36 and is in contact with the upper surface 36b of the n-side current diffusion layer 36 at the second n-side pad opening 40n. The n-side pad electrode 44 is in contact with the Rh layer of the n-side current diffusion layer 36 at the n-side connection opening 36a. The n-side pad electrode 44 is electrically connected to the n-side contact electrode 32 via the n-side current diffusion layer 36. The n-side pad electrode 44 is provided so as to cover the second n-side pad opening 40n and is provided on the second protective layer 40 outside the second n-side pad opening 40n.

[0040] The p-side bonding layer 46 and the n-side bonding layer 48 are bonding layers for bonding the semiconductor light emitting element 10 to a submount. The p-side bonding layer 46 and the n-side bonding layer 48 contain, for example, Au and Sn. The p-side bonding layer 46 and the n-side bonding layer 48 may contain AuSn, which is a mixed crystal of Au and Sn, or may have a stacked structure of an Au layer and an Sn layer.

[0041] 2 schematically illustrates the configurations of the p-side contact electrode 30, p-side current spreading layer 34, and p-side pad electrode 42. The p-side current spreading layer 34 includes a stacked film 56 in which a Ti layer 50, a lower TiN layer 52, and a Rh layer 54 are alternately stacked, and an upper TiN layer 58. The p-side pad electrode 42 includes an adhesion layer 42a made of Ni or Ti, and an Au layer 42b.

[0042] The Ti layer 50 of the p-side current spreading layer 34 is in contact with the p-side contact electrode 30. The thickness of the Ti layer 50 of the p-side current spreading layer 34 is not less than 10 nm and not more than 200 nm, for example, not less than 20 nm and not more than 150 nm. The p-side current spreading layer 34 does not need to include the Ti layer 50, and the stacked film 56 of the p-side current spreading layer 34 (e.g., the lower TiN layer 52) may be in contact with the p-side contact electrode 30.

[0043] The stacked film 56 of the p-side current spreading layer 34 is provided on the Ti layer 50. The stacked film 56 of the p-side current spreading layer 34 includes a lower TiN layer 52 and a Rh layer 54. The stacked film 56 may have a plurality of lower TiN layers 52 and a plurality of Rh layers 54 that are alternately stacked. The lower TiN layer 52 is made of conductive TiN. The thickness of the lower TiN layer 52 is 10 nm to 200 nm, for example, 50 nm to 150 nm. The thickness of the Rh layer 54 is 10 nm to 200 nm, for example, 20 nm to 150 nm.

[0044] The upper TiN layer 58 of the p-side current spreading layer 34 is provided on the laminated film 56. The upper TiN layer 58 is in contact with the Rh layer 54 constituting the uppermost layer of the laminated film 56. The upper TiN layer 58 is made of conductive TiN. The thickness of the upper TiN layer 58 is 10 nm or more and 200 nm or less, for example, 50 nm or more and 150 nm or less. The upper TiN layer 58 has a p-side connection opening 34a that exposes the Rh layer 54 constituting the uppermost layer of the laminated film 56. The p-side connection opening 34a is provided at a position communicating with the first p-side pad opening 38p.

[0045] The lower TiN layer 52 of the p-side current spreading layer 34 is composed of titanium nitride with excellent barrier properties and a yellow or golden color. Meanwhile, the upper TiN layer 58 of the p-side current spreading layer 34 is composed of titanium nitride with excellent adhesion to dielectric materials and a white or gray color. The upper TiN layer 58 is composed of titanium nitride with a lower saturation than the lower TiN layer 52 and with properties similar to metallic titanium. When forming a TiN film by reactive sputtering, the film quality can be controlled by adjusting the flow rate of nitrogen gas, a reactive gas. For example, increasing the flow rate of nitrogen gas can produce titanium nitride with excellent barrier properties for the lower TiN layer 52. Decreasing the flow rate of nitrogen gas can produce titanium nitride with excellent adhesion for the upper TiN layer 58. The film formation conditions for titanium nitride are described separately below with reference to FIG. 4.

[0046] The first protective layer 38 is provided on the p-side current spreading layer 34 outside the p-side connection opening 34a. The first protective layer 38 is in contact with the upper TiN layer 58 of the p-side current spreading layer 34. The first protective layer 38 is not provided inside the p-side connection opening 34a and is not in contact with the upper surface 34b of the p-side current spreading layer 34 exposed at the p-side connection opening 34a (i.e., the uppermost Rh layer 54).

[0047] The second protective layer 40 is in contact with an inner circumferential surface 38a that defines the first p-side pad opening 38p of the first protective layer 38. The second protective layer 40 is in contact with an inner circumferential surface 34c that defines the p-side connection opening 34a of the p-side current spreading layer 34. The second protective layer 40 is in contact with an upper surface 34b of the p-side current spreading layer 34 (i.e., the uppermost Rh layer 54) that is exposed inside the p-side connection opening 34a.

[0048] The adhesive layer 42a of the p-side pad electrode 42 is in contact with the p-side current spreading layer 34 inside the second p-side pad opening 40p. The adhesive layer 42a of the p-side pad electrode 42 is in contact with the Rh layer 54 constituting the uppermost layer of the laminated film 56. The adhesive layer 42a of the p-side pad electrode 42 is not in contact with the upper TiN layer 58 of the p-side current spreading layer 34. The adhesive layer 42a of the p-side pad electrode 42 is not in contact with the first protective layer 38. The Au layer 42b of the p-side pad electrode 42 is provided on the adhesive layer 42a. The p-side bonding layer 46 (not shown in FIG. 2) is provided on the Au layer 42b of the p-side pad electrode 42.

[0049] 3 schematically illustrates the configurations of the n-side contact electrode 32, n-side current spreading layer 36, and n-side pad electrode 44. The n-side contact electrode 32 includes a first Ti layer 60, an Al layer 62, a second Ti layer 64, and a TiN layer 66. The n-side current spreading layer 36 includes a Ti layer 70, a stacked film 76 in which lower TiN layers 72 and Rh layers 74 are alternately stacked, and an upper TiN layer 78. The n-side pad electrode 44 includes an adhesion layer 44a made of Ni or Ti and an Au layer 44b.

[0050] The Ti layer 70 of the n-side current spreading layer 36 is in contact with the TiN layer 66 of the n-side contact electrode 32. The thickness of the Ti layer 70 of the n-side current spreading layer 36 is not less than 10 nm and not more than 200 nm, for example, not less than 20 nm and not more than 150 nm. The n-side current spreading layer 36 does not need to include the Ti layer 70, and the stacked film 76 of the n-side current spreading layer 36 (e.g., the lower TiN layer 72) may be in contact with the n-side contact electrode 32.

[0051] The stacked film 76 of the n-side current spreading layer 36 is provided on the Ti layer 70. The stacked film 76 of the n-side current spreading layer 36 includes a lower TiN layer 72 and a Rh layer 74. The stacked film 76 may have a plurality of lower TiN layers 72 and a plurality of Rh layers 74 that are alternately stacked. The lower TiN layer 72 is made of conductive TiN. The thickness of the lower TiN layer 72 is 10 nm to 200 nm, for example, 50 nm to 150 nm. The thickness of the Rh layer 74 is 10 nm to 200 nm, for example, 20 nm to 150 nm.

[0052] The upper TiN layer 78 of the n-side current spreading layer 36 is provided on the laminated film 76. The upper TiN layer 78 is made of conductive TiN. The thickness of the upper TiN layer 78 is 10 nm or more and 200 nm or less, for example, 50 nm or more and 150 nm or less. The upper TiN layer 78 has an n-side connection opening 36a that exposes the Rh layer 74 that constitutes the uppermost layer of the laminated film 76. The n-side connection opening 36a is provided at a position that communicates with the first n-side pad opening 38n.

[0053] The TiN layer 66 of the n-side contact electrode 32 and the lower TiN layer 72 of the n-side current spreading layer 36 are made of titanium nitride with excellent barrier properties and a yellow or golden color. On the other hand, the upper TiN layer 78 of the n-side current spreading layer 36 is made of titanium nitride with excellent adhesion to dielectric materials and a white or gray color. The upper TiN layer 78 is made of titanium nitride with a lower saturation than the lower TiN layer 72 and with a film quality relatively similar to metallic titanium. The film formation conditions for titanium nitride will be described later with reference to FIG. 4.

[0054] The first protective layer 38 is provided on the n-side current spreading layer 36 outside the n-side connection opening 36a. The first protective layer 38 is in contact with the upper TiN layer 78 of the n-side current spreading layer 36. The first protective layer 38 is not provided inside the n-side connection opening 36a and is not in contact with the upper surface 36b of the n-side current spreading layer 36 exposed at the n-side connection opening 36a (i.e., the uppermost Rh layer 74).

[0055] The second protective layer 40 is in contact with the inner circumferential surface 38b that defines the first n-side pad opening 38n of the first protective layer 38. The second protective layer 40 is in contact with the inner circumferential surface 36c that defines the n-side connection opening 36a of the n-side current spreading layer 36. The second protective layer 40 is in contact with the upper surface 36b of the n-side current spreading layer 36 (i.e., the uppermost Rh layer 74) that is exposed inside the n-side connection opening 36a.

[0056] The adhesive layer 44a of the n-side pad electrode 44 is in contact with the n-side current spreading layer 36 inside the second n-side pad opening 40n. The adhesive layer 44a of the n-side pad electrode 44 is in contact with the Rh layer 74 that constitutes the uppermost layer of the laminated film 76. The adhesive layer 44a of the n-side pad electrode 44 is not in contact with the upper TiN layer 78 of the n-side current spreading layer 36. The adhesive layer 44a of the n-side pad electrode 44 is not in contact with the first protective layer 38. The Au layer 44b of the n-side pad electrode 44 is provided on the adhesive layer 44a. The n-side bonding layer 48 (not shown in FIG. 3) is provided on the Au layer 44b of the n-side pad electrode 44.

[0057] Figure 4 is a graph showing an example of titanium nitride film formation conditions. Figure 4 shows the conditions for forming a titanium nitride film by reactive sputtering, using metallic titanium as the target material, nitrogen (N2) as the reactive gas, and argon (Ar) as the non-reactive gas. Figure 4 shows the film formation rate when the nitrogen gas flow rate is varied while the total flow rate of nitrogen and argon gas is fixed at 90 sccm. As shown in Figure 4, the film formation rate tends to decrease as the nitrogen gas flow rate is increased. Furthermore, comparing the first region A1, where the nitrogen gas flow rate is 7 sccm or less, and the second region A2, where the nitrogen gas flow rate is 8 sccm or more, the slope of the change in film formation rate with respect to the nitrogen gas flow rate is different. This is thought to be because a titanium-rich TiN film with film quality similar to metallic titanium is formed in the first region A1, while a titanium-poor TiN film with film quality far from metallic titanium is formed in the second region A2. The TiN film formed in the first region A1 is white or gray, with a pale yellow and a relatively low saturation color. On the other hand, the TiN film formed in the second region A2 has a yellow or golden yellow color, a deeper yellow, and a relatively more saturated color. As the nitrogen gas flow rate increases, the yellow color of the TiN film formed tends to become deeper and more saturated.

[0058] Figure 5 is a graph showing an example of RGB measurement values ​​for titanium nitride. Figure 5 also shows the RGB measurement values ​​for TiN film formed under the same deposition conditions as Figure 4. The RGB measurement values ​​are the red (R), green (G), and blue (B) measurements using standard RGB (sRGB), an international standard, expressed as values ​​between 0 and 255. As shown in Figure 5, in the first region A1 where the nitrogen gas flow rate is 7 sccm or less, the difference between the R, G, and B values ​​is small, indicating a color close to white or gray with low saturation. On the other hand, in the second region A2 where the nitrogen gas flow rate is 8 sccm or more, the difference between the R, G, and B values ​​is large, indicating a color close to yellow with a relatively large R value and a relatively small B value. Saturation is proportional to the difference between the maximum and minimum R, G, and B values. Therefore, the saturation of TiN can be evaluated by using the difference between the maximum R value and the minimum B value (i.e., R value - B value), and the film quality of TiN can be evaluated by the saturation of TiN.

[0059] FIG. 6 is a table showing an example of the RGB measurement values ​​and sealing performance of titanium nitride. FIG. 6 evaluates the sealing performance of the semiconductor light-emitting device 10 shown in FIG. 1 when the film quality of the upper TiN layer 58 of the p-side current diffusion layer 34 and the upper TiN layer 78 of the n-side current diffusion layer 36 is changed. The sealing performance was evaluated based on the lifespan of the semiconductor light-emitting device 10 when it was energized. A lifespan equal to or greater than a predetermined reference value was evaluated as OK, and a lifespan less than the predetermined reference value was evaluated as NG. As shown in FIG. 6, Examples 1 to 4, in which RB (the difference between the R value and the B value) was less than 25, achieved OK sealing performance, whereas Comparative Examples 1 to 4, in which RB was 25 or greater, achieved NG sealing performance. This is thought to be because, when titanium-rich TiN was formed in the first region A1, the adhesion between the upper TiN layers 58 and 78 and the first protective layer 38 was improved, resulting in improved sealing performance. Therefore, by using titanium nitride having a difference between the R value and the B value of less than 25 as the upper TiN layers 58, 78 of the semiconductor light emitting element 10, the sealing property of the semiconductor light emitting element 10 can be improved, and the reliability of the semiconductor light emitting element 10 can be increased.

[0060] The lower TiN layers 52, 72 that are not in contact with the first protective layer 38 may be titanium nitride having a difference between its R and B values ​​of 25 or more, since this is not related to the effect of improving adhesion to the first protective layer 38. Titanium-poor TiN having a difference between its R and B values ​​of 25 or more is known to have better barrier properties for preventing metal migration than titanium-rich TiN. Because the lower TiN layers 52, 72 are located between the metal layer included in the contact electrode and the metal layer included in the current spreading layer, titanium-poor TiN, which has excellent barrier properties, is preferred.

[0061] Next, a description will be given of a manufacturing method of the semiconductor light emitting device 10. Figures 7 to 14 are diagrams schematically showing the manufacturing process of the semiconductor light emitting device 10. First, in Figure 7, a base layer 22, an n-type semiconductor layer 24, an active layer 26, and a p-type semiconductor layer 28 are formed in this order on the first main surface 20a of the substrate 20.

[0062] The substrate 20 is, for example, a patterned sapphire substrate. The base layer 22 includes, for example, an HT-AlN layer and an undoped AlGaN layer. The n-type semiconductor layer 24, the active layer 26, and the p-type semiconductor layer 28 are semiconductor layers made of an AlGaN-based semiconductor material, an AlN-based semiconductor material, or a GaN-based semiconductor material, and can be formed using a well-known epitaxial growth method such as metal organic vapor phase epitaxy (MOVPE) or molecular beam epitaxy (MBE).

[0063] 7, a mask 80 is formed on the upper surface 28a of the p-type semiconductor layer 28 using, for example, a known lithography technique. With the mask 80 formed, the p-type semiconductor layer 28 and the active layer 26 in areas not overlapping with the mask 80 are removed by dry etching or the like to expose the second upper surface 24b of the n-type semiconductor layer 24. This etching process forms the side surface 28b of the p-type semiconductor layer 28, the side surface 26b of the active layer 26, and the second upper surface 24b of the n-type semiconductor layer 24. Thereafter, the mask 80 is removed.

[0064] 8, a p-side contact electrode 30 is formed on the upper surface 28a of the p-type semiconductor layer 28 using, for example, known lithography techniques. The p-side contact electrode 30 includes an Rh layer that is in direct contact with the upper surface 28a of the p-type semiconductor layer 28. The Rh layer of the p-side contact electrode 30 is formed by a vapor deposition method. Forming the Rh layer by a vapor deposition method can reduce damage to the upper surface 28a of the p-type semiconductor layer 28 compared to when a sputtering method is used, and can improve the contact resistance of the p-side contact electrode 30.

[0065] After the p-side contact electrode 30 is formed, the p-side contact electrode 30 is annealed. The p-side contact electrode 30 is annealed at a temperature of 500°C or higher and 650°C or lower by, for example, an RTA (Rapid Thermal Annealing) method. The annealing of the p-side contact electrode 30 reduces the contact resistance of the p-side contact electrode 30. The annealing of the p-side contact electrode 30 increases the film density of the p-side contact electrode 30, and improves the reflectivity of the p-side contact electrode 30.

[0066] Next, as shown in FIG. 8, an n-side contact electrode 32 is formed on the second upper surface 24b of the n-type semiconductor layer 24 using, for example, a known lithography technique. The n-side contact electrode 32 is in contact with the second upper surface 24b of the n-type semiconductor layer 24 and includes a first Ti layer 60, an Al layer 62, a second Ti layer 64, and a TiN layer 66 (see FIG. 3), which are stacked in this order. The first Ti layer 60, the Al layer 62, the second Ti layer 64, and the TiN layer 66 that constitute the n-side contact electrode 32 are formed by sputtering. The TiN layer 66 may be titanium-poor TiN, with a difference between the R value and the B value of 25 or more. The TiN layer 66 can be formed, for example, under deposition conditions with a nitrogen gas flow rate of 8 sccm or more (e.g., 10 sccm). The TiN layer 66 can be formed, for example, under deposition conditions with a nitrogen gas flow rate ratio of 9% or more, 10% or more, or 12% or more to argon gas.

[0067] After the n-side contact electrode 32 is formed, the n-side contact electrode 32 is annealed. The n-side contact electrode 32 is annealed at a temperature of 500° C. or higher and 650° C. or lower by, for example, an RTA method. By annealing the n-side contact electrode 32, the contact resistance of the n-side contact electrode 32 is reduced.

[0068] Next, as shown in FIG. 9 , a p-side current diffusion layer 34 is formed on the p-side contact electrode 30, and an n-side current diffusion layer 36 is formed on the n-side contact electrode 32, using, for example, known lithography techniques. The p-side current diffusion layer 34 and the n-side current diffusion layer 36 include a stacked film in which a Ti layer, a lower TiN layer, and a Rh layer are alternately stacked, and an upper TiN layer. The p-side current diffusion layer 34 and the n-side current diffusion layer 36 can be formed by sputtering. The lower TiN layer of the p-side current diffusion layer 34 and the n-side current diffusion layer 36 may be titanium-poor TiN having a difference between the R value and the B value of 25 or more. For example, the lower TiN layer can be formed under deposition conditions with a nitrogen gas flow rate of 8 sccm or more (e.g., 10 sccm). The lower TiN layer can be formed under deposition conditions with a nitrogen gas flow rate ratio to argon gas of 9% or more, 10% or more, or 12% or more. On the other hand, the upper TiN layers of the p-side current diffusion layer 34 and the n-side current diffusion layer 36 are made of titanium-rich TiN with a difference between the R value and the B value of less than 25 (e.g., 20 or less, 15 or less, 10 or less, or 5 or less), and can be formed under film formation conditions with a nitrogen gas flow rate of 7 sccm or less (e.g., 5 sccm). The upper TiN layer can be formed under film formation conditions with a nitrogen gas to argon gas flow rate ratio of 8% or less, 7% or less, or 6% or less. The p-side current diffusion layer 34 and the n-side current diffusion layer 36 may be formed separately.

[0069] 10 , a mask 82 is formed on the n-type semiconductor layer 24, the active layer 26, the p-type semiconductor layer 28, the p-side current diffusion layer 34, and the n-side current diffusion layer 36 using, for example, known lithography techniques. With the mask 82 formed, the n-type semiconductor layer 24 in an area not overlapping with the mask 82 is removed by dry etching or the like to expose the top surface 22a of the base layer 22. This etching process forms the side surface 24c of the n-type semiconductor layer 24. Thereafter, the mask 82 is removed.

[0070] 11, a first protective layer 38 is formed to cover the entire upper surface of the device. The first protective layer 38 may be made of SiO2 and may be formed using a plasma-enhanced chemical vapor deposition (PECVD) method. The first protective layer 38 is formed to be in contact with the upper surface 22a of the base layer 22, the second upper surface 24b and side surface 24c of the n-type semiconductor layer 24, the side surface 26c of the active layer 26, the upper surface 28a and side surface 28c of the p-type semiconductor layer 28, the p-side current spreading layer 34, and the n-side current spreading layer 36.

[0071] Next, as shown in FIG. 12 , a mask 84 is formed on the first protective layer 38 using, for example, a known lithography technique. The mask 84 is formed except for a formation area W1p for the first p-side pad opening 38p, a formation area W1n for the first n-side pad opening 38n, and a first peripheral area W1a that exposes the upper surface 22a of the base layer 22. With the mask 84 formed, the first protective layer 38 in an area that does not overlap with the mask 84 is removed by dry etching. By removing the first protective layer 38 on the p-side current diffusion layer 34, the first p-side pad opening 38p that exposes the p-side current diffusion layer 34 is formed. By removing the first protective layer 38 on the n-side current diffusion layer 36, the first n-side pad opening 38n that exposes the n-side current diffusion layer 36 is formed. Furthermore, by removing the peripheral portion of the first protective layer 38 in the first peripheral area W1a, the upper surface 22a of the base layer 22 is exposed.

[0072] 12, in the formation range W1p of the first p-side pad opening 38p, the p-side current diffusion layer 34 is dry-etched to remove the upper TiN layer 58 of the p-side current diffusion layer 34, thereby forming a p-side connection opening 34a that exposes the uppermost Rh layer 54. Furthermore, in the formation range W1n of the first n-side pad opening 38n, the n-side current diffusion layer 36 is dry-etched to remove the uppermost TiN layer 78 of the n-side current diffusion layer 36, thereby forming an n-side connection opening 36a that exposes the uppermost Rh layer 74. Thereafter, the mask 84 is removed.

[0073] 13, a second protective layer 40 is formed to cover the entire upper surface of the element. The second protective layer 40 is made of SiN x and can be formed using a PECVD method. The second protective layer 40 is formed so as to be in contact with the upper surface 22a of the base layer 22 and the surface of the first protective layer 38. At the first p-side pad opening 38p, the second protective layer 40 is in contact with the inner circumferential surface 38a of the first protective layer 38 that defines the first p-side pad opening 38p. The second protective layer 40 is in contact with the inner circumferential surface 34c of the p-side current spreading layer 34 (i.e., the upper TiN layer 58) that defines the p-side connection opening 34a, and is in contact with the upper surface 34b of the p-side current spreading layer 34 at the p-side connection opening 34a. At the first n-side pad opening 38n, the second protective layer 40 is in contact with the inner circumferential surface 38b of the first protective layer 38 that defines the first n-side pad opening 38n. The second protective layer 40 contacts the inner surface 36c of the n-side current diffusion layer 36 (i.e., the upper TiN layer 78) that defines the n-side connection opening 36a, and contacts the upper surface 36b of the n-side current diffusion layer 36 at the n-side connection opening 36a.

[0074] Next, as shown in FIG. 14 , a mask 86 is formed on the second protective layer 40 using, for example, a known lithography technique. The mask 86 is formed except for a formation area W2p for the second p-side pad opening 40p, a formation area W2n for the second n-side pad opening 40n, and a second peripheral area W2a for exposing the upper surface 22a of the base layer 22. With the mask 86 formed, the second protective layer 40 in the area not overlapping with the mask 86 is removed by dry etching or the like. By removing the second protective layer 40 on the p-side current diffusion layer 34, the second p-side pad opening 40p is formed, exposing the upper surface 34b of the p-side current diffusion layer 34. By removing the second protective layer 40 on the n-side current diffusion layer 36, the second n-side pad opening 40n is formed, exposing the upper surface 36b of the n-side current diffusion layer 36. Furthermore, by removing the outer peripheral portion of the second protective layer 40 in the second peripheral area W2a, the upper surface 22a of the base layer 22 is exposed. The second outer periphery range W2a becomes an element isolation region for separating elements by cutting the substrate 20 and the base layer 22. Thereafter, the mask 86 is removed.

[0075] Next, as shown in FIG. 1 , a p-side pad electrode 42 is formed in the second p-side pad opening 40p, connecting to the p-side current spreading layer 34, and an n-side pad electrode 44 is formed in the second n-side pad opening 40n, using, for example, a known lithography technique. The p-side pad electrode 42 is formed so as to overlap the second protective layer 40 outside the second p-side pad opening 40p. The n-side pad electrode 44 is formed so as to overlap the second protective layer 40 outside the second n-side pad opening 40n. The p-side pad electrode 42 and the n-side pad electrode 44 can be formed simultaneously or separately. Next, a p-side junction layer 46 is formed on the p-side pad electrode 42, and an n-side junction layer 48 is formed on the n-side pad electrode 44, using, for example, a known lithography technique. The p-side junction layer 46 and the n-side junction layer 48 can be formed simultaneously or separately.

[0076] Through the above steps, the semiconductor light emitting device 10 shown in FIG. 1 is completed.

[0077] According to this embodiment, the upper TiN layers 58, 78 in contact with the first protective layer 38 are made of titanium-rich titanium nitride, thereby improving adhesion to the first protective layer 38 and improving the sealing of the semiconductor light emitting element 10. This significantly increases the life of the semiconductor light emitting element 10 when in use with power applied.

[0078] The present invention has been described above based on the embodiments. It will be understood by those skilled in the art that the present invention is not limited to the above-described embodiments, and that various design changes and modifications are possible, and that such modifications are also within the scope of the present invention.

[0079] Several aspects of the present invention will now be described.

[0080] a current spreading layer provided on the contact electrode and including an upper TiN layer made of titanium nitride, the upper TiN layer having a difference between an R value and a B value of less than 25 in RGB measurement values ​​expressed as a numerical value between 0 and 255; a protective layer having a pad opening provided on the current spreading layer, the protective layer covering the n-type semiconductor layer, the active layer, the p-type semiconductor layer, and the current spreading layer at a position different from the pad opening, the protective layer being made of a dielectric material, and the protective layer being in contact with the upper TiN layer; and a pad electrode in contact with the current spreading layer at the pad opening and provided on the protective layer above the pad opening. According to the first aspect, by bringing the upper TiN layer made of titanium-rich titanium nitride having an R-value-B-value difference of less than 25 into contact with the protective layer, it is possible to improve the adhesion between the upper TiN layer and the protective layer and improve the sealing performance of the protective layer, thereby extending the life of the semiconductor light emitting element and improving the reliability of the semiconductor light emitting element.

[0081] A second aspect of the present invention is the semiconductor light-emitting device according to the first aspect, wherein the current spreading layer includes a lower TiN layer provided between the contact electrode and the upper TiN layer, and the lower TiN layer has a difference between its R value and its B value of 25 or more in RGB measurement values ​​expressed as a numerical value between 0 and 255. According to the second aspect, by providing a lower TiN layer made of titanium-poor titanium nitride having a difference between its R value and its B value of 25 or more, the barrier properties of the current spreading layer can be improved, and the reliability of the semiconductor light-emitting device can be improved.

[0082] A third aspect of the present invention is the semiconductor light-emitting device according to the second aspect, wherein the current spreading layer further includes a metal layer provided between the lower TiN layer and the upper TiN layer, the metal layer including a Rh layer. According to the third aspect, by inserting the Rh layer between the lower TiN layer and the upper TiN layer, the barrier properties of the current spreading layer can be improved, and the reliability of the semiconductor light-emitting device can be improved.

[0083] A fourth aspect of the present invention is the semiconductor light-emitting device according to any one of the first to third aspects, wherein the protective layer comprises a first protective layer in contact with the upper TiN layer and made of silicon oxide, and a second protective layer covering the first protective layer and made of silicon nitride. According to the fourth aspect, by making the first protective layer in contact with the upper TiN layer made of silicon oxide, the adhesion between the upper TiN layer and the first protective layer can be improved, and the sealing performance of the protective layer can be improved. Furthermore, by covering the first protective layer with the second protective layer made of silicon nitride, the sealing performance of the protective layer can be improved, and the reliability of the semiconductor light-emitting device can be improved.

[0084] a contact electrode in contact with the upper surface of the p-type semiconductor layer or the upper surface of the n-type semiconductor layer; a current spreading layer including an upper TiN layer on the contact electrode; a protective layer covering the n-type semiconductor layer, the active layer, the p-type semiconductor layer, and the current spreading layer and made of a dielectric material; a pad opening formed by removing the protective layer on the current spreading layer; and a pad electrode in contact with the current spreading layer in the pad opening and provided on the protective layer outside the pad opening, wherein the upper TiN layer is formed by reactive sputtering under conditions where a flow rate ratio of nitrogen gas to argon gas is 8% or less. According to the fifth aspect, the upper TiN layer made of titanium-rich titanium nitride can be brought into contact with the protective layer, improving the adhesion between the upper TiN layer and the protective layer and improving the sealing performance of the protective layer, thereby extending the life of the semiconductor light-emitting device and improving the reliability of the semiconductor light-emitting device.

[0085] A sixth aspect of the present invention is the method for manufacturing a semiconductor light-emitting device according to aspect 5, wherein the current spreading layer includes a lower TiN layer provided between the contact electrode and the upper TiN layer, and the lower TiN layer is formed by reactive sputtering under conditions where the flow rate ratio of nitrogen gas to argon gas is 9% or more. According to the sixth aspect, by providing the lower TiN layer made of titanium-poor titanium nitride, the barrier properties of the current spreading layer can be improved, and the reliability of the semiconductor light-emitting device can be improved. [Explanation of symbols]

[0086] 10...semiconductor light-emitting element, 24...n-type semiconductor layer, 24a...first upper surface, 24b...second upper surface, 26...active layer, 28...p-type semiconductor layer, 30...p-side contact electrode, 32...n-side contact electrode, 34...p-side current spreading layer, 36...n-side current spreading layer, 38...first protective layer, 38a...inner surface, 38p...first p-side pad opening, 38n...first n-side pad opening, 40...second protective layer, 40p...second p-side pad opening, 40n...second n-side pad opening, 42...p-side pad electrode, 44...n-side pad electrode, 52,72...lower TiN layer, 54,74...Rh layer, 58,78...upper TiN layer.

Claims

1. an n-type semiconductor layer; an active layer provided on a first upper surface of the n-type semiconductor layer; a p-type semiconductor layer provided on the active layer; a contact electrode in contact with a second upper surface different from the first upper surface of the n-type semiconductor layer or in contact with an upper surface of the p-type semiconductor layer; a current spreading layer provided on the contact electrode, the current spreading layer including an upper TiN layer made of titanium nitride, the difference between the R value and the B value being less than 25 in RGB measurement values ​​expressed as numerical values ​​of 0 to 255; a protective layer made of a dielectric material, the protective layer having a pad opening provided on the current spreading layer, covering the n-type semiconductor layer, the active layer, the p-type semiconductor layer, and the current spreading layer at locations different from the pad opening, and in contact with the upper TiN layer; a pad electrode in contact with the current spreading layer in the pad opening and provided on the protection layer above the pad opening. Semiconductor light emitting element.

2. the current spreading layer includes a lower TiN layer provided between the contact electrode and the upper TiN layer; the lower TiN layer is composed of titanium nitride having an R value and a B value difference of 25 or more in an RGB measurement value expressed as a numerical value of 0 to 255, The semiconductor light emitting device according to claim 1 .

3. the current spreading layer further includes a metal layer provided between the lower TiN layer and the upper TiN layer, the metal layer including a Rh layer; The semiconductor light emitting device according to claim 2 .

4. the protective layer includes a first protective layer in contact with the upper TiN layer and made of silicon oxide, and a second protective layer covering the first protective layer and made of silicon nitride. The semiconductor light-emitting device according to claim 1 .

5. forming an active layer on the n-type semiconductor layer; forming a p-type semiconductor layer on the active layer; removing a portion of each of the p-type semiconductor layer and the active layer to expose an upper surface of the n-type semiconductor layer; forming a contact electrode in contact with an upper surface of the p-type semiconductor layer or in contact with the upper surface of the n-type semiconductor layer; forming a current spreading layer including an upper TiN layer on the contact electrode; forming a protective layer made of a dielectric material to cover the n-type semiconductor layer, the active layer, the p-type semiconductor layer, and the current spreading layer; removing the protective layer on the current spreading layer to form a pad opening; forming a pad electrode in contact with the current spreading layer in the pad opening and provided on the protection layer outside the pad opening; The upper TiN layer is formed by reactive sputtering under the condition that the flow rate ratio of nitrogen gas to argon gas is 8% or less. A method for manufacturing a semiconductor light-emitting device.

6. the current spreading layer includes a lower TiN layer provided between the contact electrode and the upper TiN layer; The lower TiN layer is formed by reactive sputtering under the condition that the flow rate ratio of nitrogen gas to argon gas is 9% or more. The method for manufacturing a semiconductor light-emitting device according to claim 5 .

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