Semiconductor structure and manufacturing method thereof

Abstract

The invention provides a semiconductor structure. The semiconductor structure includes a substrate and a metal-insulator-metal (MIM) capacitor. The MIM capacitor includes a bottom electrode, a barrier interface layer, a dielectric layer, and a top electrode. The bottom electrode is located on the substrate and comprises titanium silicon nitride. The barrier interface layer is located on the bottom electrode, and in X-ray photoelectron spectroscopy analysis of the barrier interface layer, more than 50% of the Ti 2p peak signal corresponds to titanium oxide, and 10%-20% of the Ti 2p peak signal corresponds to titanium oxynitride. The dielectric layer is on the barrier interface layer and includes a high dielectric constant (high K) dielectric material. The top electrode is on the dielectric layer. The semiconductor structure can reduce the oxygen absorption effect, thereby reducing the oxygen vacancy and improving the leakage current problem.

Description

Technical Field

[0001] This invention relates to a semiconductor structure and a method for manufacturing the same. Background Technology

[0002] In recent decades, with the continuous advancement of electronic product technology, the demand for storage capacity has been increasing. To increase the storage capacity of storage devices (such as DRAM devices), more storage cells need to be integrated into the storage device. To increase the degree of integration, the size of the semiconductor structure needs to be reduced, which may lead to an increase in the resistance of the semiconductor structure. Summary of the Invention

[0003] According to some embodiments of the present invention, a method for manufacturing a semiconductor structure is provided. The method includes the following steps: Providing a substrate. Forming a bottom electrode on the substrate using a first precursor through a first deposition process, wherein the bottom electrode comprises titanium silicon nitride. Performing a first surface treatment to form an oxide layer on the bottom electrode, wherein the first surface treatment is an ozone treatment. Performing a second surface treatment to convert the oxide layer into a barrier interface layer, wherein the second surface treatment is a nitrogen plasma treatment, such that in X-ray photoelectron spectroscopy analysis of the barrier interface layer, more than 50% of the Ti 2p peak signal corresponds to titanium oxide, and 10%-20% of the Ti 2p peak signal corresponds to titanium oxynitride. Forming a dielectric layer on the barrier interface layer, wherein the dielectric layer comprises a high dielectric constant material. Forming a top electrode on the dielectric layer.

[0004] In some embodiments, in X-ray photoelectron spectroscopy analysis of the bottom electrode, 5%-20% of the Si 2p peak signal corresponds to the Si-N bond.

[0005] In some embodiments, the thickness of the barrier interface layer is from 5 Å to 20 Å.

[0006] In some embodiments, the thickness of the bottom electrode is 80 Å to 200 Å.

[0007] In some embodiments, the dielectric layer comprises zirconium oxide.

[0008] In some embodiments, the first precursor comprises titanium tetrachloride and ammonia.

[0009] In some embodiments, the first surface treatment is performed in the first chamber, and the second surface treatment is performed in a second chamber different from the first chamber.

[0010] In some embodiments, after performing a first surface treatment, a first purging process is performed in a first chamber, and after performing a second surface treatment, a second purging process is performed in a second chamber.

[0011] In some embodiments, during the second surface treatment, titanium chloride impurities in the bottom electrode are reduced to titanium nitride, such that after the second surface treatment, the remaining chlorine content in the bottom electrode is less than 0.7 atoms.

[0012] In some embodiments, the bottom electrode, dielectric layer, and top electrode form a metal-insulator-metal capacitor.

[0013] According to some embodiments of the present invention, a semiconductor structure is provided. The semiconductor structure includes a substrate and a metal-insulator-metal capacitor. The metal-insulator-metal capacitor is located on the substrate. The metal-insulator-metal capacitor includes a bottom electrode, a barrier interface layer, a dielectric layer, and a top electrode. The bottom electrode is located on the substrate, wherein the bottom electrode comprises titanium silicon nitride. The barrier interface layer is located on the bottom electrode, wherein in X-ray photoelectron spectroscopy analysis of the barrier interface layer, more than 50% of the Ti 2p peak signal corresponds to titanium oxide, and 10%-20% of the Ti 2p peak signal corresponds to titanium oxynitride. The dielectric layer is located on the barrier interface layer, wherein the dielectric layer comprises a high dielectric constant (high K) dielectric material. The top electrode is located on the dielectric layer.

[0014] In some embodiments, in X-ray photoelectron spectroscopy analysis of the bottom electrode, 5%-20% of the Si 2p peak signal corresponds to the Si-N bond.

[0015] In some embodiments, the thickness of the barrier interface layer is 5 Å to 20 Å.

[0016] In some embodiments, the thickness of the bottom electrode is 80 Å to 200 Å.

[0017] In some embodiments, the dielectric layer comprises zirconium oxide.

[0018] It should be understood that the above general description and the following detailed description are provided by way of example and are intended to further explain the disclosures made in the claims. Attached Figure Description

[0019] A more complete understanding of the present invention can be obtained by reading the following detailed description of the embodiments in conjunction with the accompanying drawings: Figure 1 This is a schematic cross-sectional view of a semiconductor structure with a bottom electrode according to some embodiments.

[0020] Figure 2 This is a schematic cross-sectional view of a semiconductor structure with an oxide layer formed according to some embodiments.

[0021] Figure 3 This is a cross-sectional schematic diagram of a semiconductor structure after the oxide layer has been converted into a barrier interface layer according to some embodiments.

[0022] Figure 4 This is a schematic cross-sectional view of a semiconductor structure after the dielectric layer has been formed, according to some embodiments.

[0023] Figure 5 This is a schematic cross-sectional view of a semiconductor structure after the top electrode has been formed, according to some embodiments.

[0024] Figure 6 This is a flowchart of a method for manufacturing a semiconductor structure according to some embodiments. Detailed Implementation

[0025] Reference will now be made in detail to embodiments of the invention, examples of which are shown in the accompanying drawings. Where possible, the same reference numerals are used in the drawings and description to refer to the same or similar parts.

[0026] It should be understood that the following disclosure provides many different embodiments or examples for implementing different features of the invention. Specific embodiments or examples of components and configurations are described below to simplify the invention. Of course, these are merely examples and are not intended to be limiting. For example, forming a first feature on or above a second feature in the following description may include embodiments where the first and second features are formed in direct contact, or embodiments where an additional feature is formed between the first and second features such that the first and second features do not need to be in direct contact. Furthermore, reference numerals and / or symbols may be repeated in various examples. This repetition is for simplicity and clarity and does not in itself define the relationship between the various embodiments and / or configurations discussed.

[0027] Furthermore, for ease of description, the present invention may use spatial relative terms, such as "below," "under," "lower," "above," "upper," etc., to describe the relationship of an element or feature to one or more other elements or features, as shown in the accompanying drawings. The spatial relative terms are intended to cover not only the orientation illustrated in the drawings but also different orientations of the device during use or operation. The device may be oriented in other ways (rotated 90 degrees or in other orientations), and the spatial relative descriptive terms used herein shall be interpreted accordingly.

[0028] It should be understood that when a component or layer is referred to as being "connected to" or "coupled to" another component or layer, it can be directly connected to or coupled to another component or layer, or there can be intermediate components or layers.

[0029] Figures 1 to 5This is a schematic diagram illustrating various intermediate stages in the formation process of a semiconductor structure 100 according to some embodiments. The semiconductor structure 100 can be applied to or as part of an integrated circuit (IC), such as logic circuits, resistors, capacitors, inductors, memory (e.g., dynamic random access memory (DRAM)), etc. It should be understood that, for the sake of simplicity, [the accompanying drawings are omitted]. Figures 1 to 5 Some elements of the semiconductor structure 100 are not shown in the diagram, and additional elements may be included in other embodiments of the semiconductor structure 100. Figure 6 This is a flowchart of the manufacturing method 200 for the semiconductor structure 100.

[0030] refer to Figure 1 The semiconductor structure 100 includes a substrate 110. In some embodiments, the substrate 110 may be a semiconductor substrate, such as a host semiconductor substrate, a semiconductor-on-insulator (SOI) substrate, etc., wherein the insulator may be a buried oxide (BOX) layer, a silicon oxide layer, etc. In some embodiments, the substrate 110 may be doped (e.g., containing p-type or n-type dopants) or undoped. In some embodiments, the semiconductor material of the substrate 110 may include silicon, germanium, compound semiconductors (including silicon carbide, gallium arsenide, gallium phosphide, indium phosphide, indium arsenide, and / or indium antimonide), alloy semiconductors, or combinations thereof. The substrate 110 may also be formed of other materials, such as sapphire, indium tin oxide, etc.

[0031] like Figure 1 and Figure 6 As shown in step 210, a bottom electrode 120 is formed on the substrate 110. In some embodiments, the bottom electrode 120 may include a suitable conductive material. In some embodiments, the bottom electrode 120 may include titanium silicon nitride (TiSiN). In some embodiments, the bottom electrode 120 may be formed by a suitable deposition process, such as chemical vapor deposition (CVD), plasma-enhanced chemical vapor deposition (PECVD), atomic layer deposition (ALD), etc.

[0032] The bottom electrode 120 is formed by a first deposition process D1 and a first precursor P1. In some embodiments, the first deposition process D1 is atomic layer deposition (ALD), and the first precursor P1 of the first deposition process D1 comprises gaseous titanium tetrachloride (TiCl4) and ammonia (NH3). Furthermore, the silicon in the bottom electrode 120 can be in-situ doped or ex-situ doped. If the silicon in the bottom electrode 120 is in-situ doped, the first precursor P1 may also comprise gaseous silane (SiH4) or disilane (Si2H6). If the silicon in the bottom electrode 120 is ex-situ doped, it can be doped by ion implantation or other suitable doping processes. Since the bottom electrode 120 is formed from a precursor gas containing titanium tetrachloride (TiCl4), the bottom electrode 120 inevitably contains some impurities, such as TiCl4.

[0033] X-ray photoelectron spectroscopy (XPS) analysis of the bottom electrode 120 revealed that approximately 5% to 20% of the Si 2p peak signal corresponds to Si-N bonds. This composition indicates that the bottom electrode 120 is primarily TiN as the conductive phase, and that silicon enhances its thermal stability and diffusion-blocking properties through partial Si-N bonding. In some embodiments, the thickness T120 of the bottom electrode 120 is 80 Å to 200 Å, achieving a balance between conductivity and reliability.

[0034] refer to Figure 2 and Figure 6 In step 220, a first surface treatment S1 is performed on the bottom electrode 120 using a first gas G1, and an oxide layer 130 is formed on the bottom electrode 120. In some embodiments, the first surface treatment S1 is performed in a first chamber C1. In some embodiments, the first surface treatment S1 is an ozone treatment, and the first gas G1 is ozone (O3). In the ozone treatment, ozone decomposes into oxygen (O2) and atomic oxygen (O), wherein atomic oxygen is more reactive than molecular oxygen. These reactive atomic oxygens oxidize the corresponding metals into metal oxides.

[0035] When the bottom electrode 120 contains a metallic conductive material, the oxide layer 130 may contain a metal oxide. In some embodiments, when the bottom electrode 120 contains titanium silicon nitride (TiSiN), the oxide layer 130 formed by the first surface treatment S1 may contain titanium oxide (TiO2). x ).

[0036] In some embodiments, after the oxide layer 130 is formed, a purging process is performed in the first chamber C1 to remove byproducts. Ozone treatment can be performed at relatively low temperatures, thus avoiding thermal damage caused by thermal oxidation. Compared to conventional thermal oxidation, ozone treatment offers better controllability and uniformity.

[0037] refer to Figure 3 and Figure 6 In step 230, a second surface treatment S2 is performed using a second gas G2 to transform the oxide layer 130 into a barrier interface layer 132. In some embodiments, the second surface treatment S2 is performed in a second chamber C2, different from the first chamber C1. In some embodiments, the second surface treatment S2 is a nitrogen plasma treatment, and the second gas G2 is nitrogen. Nitrogen gas (N2) is ionized by an electric current to generate a plasma containing various high-energy particles, such as excited-state nitrogen molecules, nitrogen ions, or atomic nitrogen.

[0038] In some embodiments, when the bottom electrode 120 comprises titanium silicon nitride (TiSiN) and the oxide layer 130 comprises titanium oxide (TiO2) x When the barrier interface layer 132 contains titanium oxide (TiO2), the barrier interface layer 132 may contain titanium oxide (TiO2). x ) and titanium oxynitride (TiO2) x N y A mixture of ( ). In some embodiments, the thickness T132 of the barrier interface layer 132 is in the range of 5 Å to 10 Å, which can achieve a balance between improving leakage performance and reducing resistance.

[0039] X-ray photoelectron spectroscopy (XPS) analysis of the barrier interface layer 132 revealed that approximately 50% or more of the Ti 2p signal corresponded to titanium oxide (TiO2). x The 10%-20% Ti 2p peak signal corresponds to titanium oxynitride (TiO2). x N y Alternatively, in other words, based on X-ray photoelectron spectroscopy (XPS) analysis of the barrier interface layer 132, the composition of the barrier interface layer 132 contains more than 50 molecular percentages of titanium oxide (TiO2). x ) and 10-20 molecule percent titanium oxynitride (TiO2) x N y ).

[0040] During the second surface treatment S2 (nitrogen plasma treatment), due to the high energy of the N2 plasma, impurities in the bottom electrode 120, such as titanium chloride (TiCl), are removed. xThe chlorine (Cl) atoms can be reduced to TiN, causing them to combine into gaseous chlorine (Cl2) and readily disperse into the second chamber C2. Therefore, according to X-ray photoelectron spectroscopy (XPS) analysis, after the second surface treatment S2 (nitrogen plasma treatment), the amount of residual chlorine (Cl) atoms in the bottom electrode can be less than 0.7 atomic%. In some embodiments, after forming the barrier interface layer 132, a purging process can be performed in the second chamber C2 to remove byproducts (e.g., gaseous chlorine). This can improve leakage current problems caused by impurities in the bottom electrode.

[0041] refer to Figure 4 and Figure 6 Step 240 involves forming a dielectric layer 140 on the barrier interface layer 132. The dielectric layer 140 may be the insulating layer of a metal-insulator-metal (MIM) capacitor. In some embodiments, the dielectric layer 140 may include a high dielectric constant (high K) material. Here, the high dielectric constant material may be an insulating material with a dielectric constant greater than 3.9 to reduce leakage current and maintain capacitance. For example, the high dielectric constant material may include hafnium oxide (HfO2), zirconium oxide (ZrO2), aluminum oxide (Al2O3), tantalum pentoxide (Ta2O5), lanthanum oxide (La2O3), yttrium oxide (Y2O3), or other suitable materials. In a preferred embodiment, the dielectric layer 140 may include zirconium oxide (ZrO2). In some embodiments, the dielectric layer 140 may be formed using a suitable deposition process, such as chemical vapor deposition (CVD), plasma-enhanced chemical vapor deposition (PECVD), atomic layer deposition (ALD), etc.

[0042] Previously, when the bottom electrode layer was made of TiN, the strong oxidation potential of TiN led to oxygen scavenging effect (OSE), which generated oxygen vacancy defects near the interface with the high dielectric constant layer. However, when the bottom electrode 120 was made of TiSiN and a barrier interface layer 132 was provided, the removal of oxygen atoms from the high dielectric constant layer (such as ZrO2) by titanium could be suppressed, thereby inhibiting the formation of oxygen vacancies and improving the leakage current problem.

[0043] refer to Figure 5 and Figure 6In step 250, a top electrode 150 is formed on the dielectric layer 140. The bottom electrode 120, dielectric layer 140, and top electrode 150 can constitute a metal-insulator-metal (MIM) capacitor. In some embodiments, the top electrode 150 may contain the same material as the bottom electrode 120. In other embodiments, the top electrode 150 may contain copper (Cu), tungsten (W), aluminum (Al), titanium (Ti), tantalum (Ta), gold (Au), silver (Ag), combinations thereof, oxides thereof, nitrides thereof, or other suitable conductive materials. In some embodiments, the top electrode 150 may be formed using a suitable deposition process, such as chemical vapor deposition (CVD), plasma-enhanced chemical vapor deposition (PECVD), atomic layer deposition (ALD), etc.

[0044] refer to Figures 1 to 5 and Figure 6 The present invention provides a method 200 for manufacturing a semiconductor structure 100. Method 200 includes the following steps. In step 210, a substrate 110 is provided, and a bottom electrode 120 is formed on the substrate 110 using a first precursor P1 through a first deposition process D1, wherein the bottom electrode 120 comprises silicon titanium nitride.

[0045] In step 220, a first surface treatment S1 is performed to form an oxide layer 130 on the bottom electrode 120, wherein the first surface treatment S1 is an ozone treatment. In step 230, a second surface treatment S2 is performed to transform the oxide layer 130 into a barrier interface layer 132, wherein the second surface treatment S2 is a nitrogen plasma treatment, such that when X-ray photoelectron spectroscopy (XPS) analysis is performed on the barrier interface layer 132, more than 50% of the Ti 2p peak signal corresponds to titanium oxide, and 10% to 20% of the Ti 2p peak signal corresponds to titanium oxynitride. In step 240, a dielectric layer 140 is formed on the barrier interface layer 132, wherein the dielectric layer 140 comprises a high dielectric constant (high K) dielectric material. In step 250, a top electrode 150 is formed on the dielectric layer 140. The bottom electrode 120, the dielectric layer 140, and the top electrode 150 form a metal-insulator-metal (MIM) capacitor 160.

[0046] This invention provides a semiconductor structure and its manufacturing method. In the method of this invention, the bottom electrode is made of TiSiN, and the barrier interface layer comprises titanium oxide (TiO₂). x ) and titanium oxynitride (TiO2) x N yThis mixture prevents titanium (TiN) from abstracting oxygen atoms from high-dielectric-constant layers (such as ZrO2), thereby reducing the oxygen absorption effect (OSE), reducing oxygen vacancies, and improving leakage current. Nitrogen plasma treatment during the formation of the barrier interface layer can reduce the impurity content in the bottom electrode, which also helps improve leakage current.

[0047] While the invention has been described in considerable detail with reference to certain embodiments thereof, other embodiments are also possible. Therefore, the spirit and scope of the appended claims should not be limited to the embodiments described herein.

[0048] It will be apparent to those skilled in the art that various modifications and alterations can be made to the structure of the present invention without departing from the scope or spirit of the invention. In view of the foregoing, the present invention is intended to cover various modifications and variations thereof, provided that such modifications and variations fall within the scope of the appended claims.

[0049] [Symbol Explanation] 100: Semiconductor Structure 110:Substrate 120: Bottom electrode 130: Oxide layer 132: Blocking Interface Layer 140: Dielectric layer 150: Top electrode 160: Capacitor 200: Method 210: Steps 220: Steps 230: Steps 240: Steps 250: Steps C1: First Chamber C2: Second Chamber D1: First deposition process G1: First Gas G2: Second gas P1: First precursor S1: First surface treatment S2: Second surface treatment T120: Thickness T132: Thickness.

Claims

1. A method for manufacturing a semiconductor structure, characterized in that, include: Provide substrate; A bottom electrode is formed on the substrate using a first deposition process and a first precursor, wherein the bottom electrode comprises silicon titanium nitride. A first surface treatment is performed to form an oxide layer on the bottom electrode, wherein the first surface treatment is an ozone treatment; A second surface treatment is performed to convert the oxide layer into a barrier interface layer, wherein the second surface treatment is a nitrogen plasma treatment, such that in X-ray photoelectron spectroscopy analysis of the barrier interface layer, more than 50% of the Ti 2p peak signals correspond to titanium oxide, and 10%-20% of the Ti 2p peak signals correspond to titanium oxynitride. A dielectric layer is formed on the barrier interface layer, wherein the dielectric layer comprises a material with a high dielectric constant; and A top electrode is formed on this dielectric layer.

2. The method according to claim 1, characterized in that, In X-ray photoelectron spectroscopy analysis of the bottom electrode, 5%–20% of the Si 2p peak signal corresponds to Si-N bonding.

3. The method according to claim 1, characterized in that, The thickness of the barrier interface layer ranges from 5 Å to 20 Å.

4. The method according to claim 1, characterized in that, The thickness of the bottom electrode ranges from 80 Å to 200 Å.

5. The method according to claim 1, characterized in that, The dielectric layer contains zirconium oxide.

6. The method according to claim 1, characterized in that, The first precursor contains titanium tetrachloride and ammonia.

7. The method according to claim 1, characterized in that, The first surface treatment is performed in the first chamber, and the second surface treatment is performed in a second chamber, which is different from the first chamber.

8. The method according to claim 7, characterized in that, After performing the first surface treatment, a first purging process is performed in the first chamber, and after performing the second surface treatment, a second purging process is performed in the second chamber.

9. The method according to claim 8, characterized in that, During the second surface treatment, the titanium chloride impurities in the bottom electrode are reduced to titanium nitride, so that after the second surface treatment, the remaining chlorine content in the bottom electrode is less than 0.7 atoms.

10. The method according to claim 1, characterized in that, The bottom electrode, the dielectric layer, and the top electrode form a metal-insulator-metal capacitor.

11. A semiconductor structure, characterized in that, include: substrate; and A metal-insulator-metal capacitor is located on the substrate, and the metal-insulator-metal capacitor includes: A bottom electrode is located on the substrate, wherein the bottom electrode comprises silicon titanium nitride; A barrier interface layer is located on the bottom electrode, wherein in the X-ray photoelectron spectroscopy analysis of the barrier interface layer, more than 50% of the Ti 2p peak signals correspond to titanium oxide, and 10%-20% of the Ti 2p peak signals correspond to titanium oxynitride. A dielectric layer, located on the barrier interface layer, wherein the dielectric layer comprises a high dielectric constant dielectric material; and The top electrode is located on the dielectric layer.

12. The semiconductor structure according to claim 11, characterized in that, In X-ray photoelectron spectroscopy analysis of the bottom electrode, 5%–20% of the Si 2p peak signal corresponds to Si-N bonding.

13. The semiconductor structure according to claim 11, characterized in that, The thickness of the barrier interface layer ranges from 5 Å to 20 Å.

14. The semiconductor structure according to claim 11, characterized in that, The thickness of the bottom electrode ranges from 80 Å to 200 Å.

15. The semiconductor structure according to claim 11, characterized in that, The dielectric layer contains zirconium oxide.

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