Fan-out package including bridge structure and method of manufacturing the same

Abstract

An aspect of the present disclosure may provide a fan-out package including a bridge structure capable of alleviating routing density of traces and improving electrical performance by including a passive element in a fan-out packaging process, and a method of manufacturing the same.SOLUTION: A fan-out package 100 in which two or more dies 110 are integrated in a fan-out packaging process includes a bridge substrate 220 formed on one side of the fan-out package, a redistribution layer 240 formed on the bridge substrate 220, including one or more traces 242, and electrically connecting the dies 110 to each other, and a passive device 260 patterned and formed on the redistribution layer 240.SELECTED DRAWING: Figure 2

Description

[Technical Field]

[0001] The present invention relates to a fan-out package and a manufacturing method thereof, which includes a bridge structure that increases the degree of freedom in trace design and improves electrical performance, and a manufacturing method thereof. [Background technology]

[0002] Generally, the semiconductor packaging process includes the steps of wafer dicing, die attach, chip interconnection, molding, and packaging test.

[0003] While the traditional semiconductor packaging process involves cutting wafers and then carrying out the packaging process, the recent trend is to carry out the "wafer level packaging" process while maintaining the die in the wafer state. This process involves carrying out the packaging process and testing at once in the wafer state, and then cutting the chips, which has the advantage of reducing package production costs compared to the conventional method.

[0004] As semiconductor devices become more highly integrated, perform better, and smaller, various packaging technologies have evolved based on the wafer level packaging method, and in particular, fan-in wafer level packaging (Fan-In Wafer Level Packaging) and fan-out wafer level packaging (Fan-Out Wafer Level Packaging) technologies are being actively researched.

[0005] In recent years, with the rapid increase in data processing volume, the concept of chiplet, which is different from the existing concept of SoC (System on Chip), has been introduced. This involves manufacturing different chips (modules) from different wafers and integrating them to form a chip. The concept of chiplet is to form an SoC with a certain function by connecting chips manufactured from different wafers.

[0006] In addition, in order to further increase the degree of integration in this wafer-level packaging method, heterogeneous integration techniques, which package different chips that perform different functions, such as 2D packaging, 2.5D packaging, and 3D packaging, on a single substrate, are being actively researched.

[0007] The concept of chiplet packaging has been studied from various angles due to the increase in data processing volume and processing speed caused by the recent surge in the semiconductor market, but as shown in Figure 1, it has been restricted by space limitations in trace design.

[0008] In other words, the increased density of trace routing makes it difficult to connect chips, and the increased interference between traces increases the likelihood of short circuits and signal transmission errors, resulting in limitations on I / O counts.

[0009] Meanwhile, when designing a fan-out package, a large number of various passive elements are required to improve electrical performance. However, due to space limitations in the packaging process, which has recently seen a high level of integration, it is difficult to arrange the passive elements.

[0010] The limited space for arranging such passive elements increases the complexity of package design and manufacturing costs. In particular, the passive elements 260 inside a densely packed package may limit heat dissipation paths, and complex trace routing paths increase design time and increase the likelihood of errors in the manufacturing process.

[0011] That is, forming passive elements or passive circuits such as resistors, capacitors, and inductors on a semiconductor substrate increases the complexity of the process, which can result in additional costs. Summary of the Invention [Problem to be solved by the invention]

[0012] The present invention has been derived from the above-mentioned need, and aims to provide a fan-out package including a bridge structure that reduces trace routing congestion during the fan-out packaging process and includes passive elements to improve electrical performance, and a method for manufacturing the same. [Means for solving the problem]

[0013] To achieve the above object, the technical gist of the present invention is a fan-out package integrating two or more dies, the fan-out package including a bridge structure including: a bridge substrate formed on one side of the fan-out package; a redistribution layer formed on the bridge substrate, including one or more traces, electrically connecting the dies; and passive elements patterned and formed on the redistribution layer.

[0014] Another technical feature of the present invention is a method for manufacturing a fan-out package, which includes forming a fan-out package integrating two or more dies, and positioning a bridge structure on one side of the fan-out package, the bridge structure including a bridge substrate, a redistribution layer including one or more traces and electrically connecting the dies, and passive elements formed on the redistribution layer, the passive elements being formed by patterning the redistribution layer through a thin film deposition and patterning process on the bridge substrate.

[0015] Preferably, the redistribution layer is formed of one or more layers, with a passivation layer formed between the layers.

[0016] Preferably, the rewiring layer includes traces and connecting terminals formed at the ends of the traces.

[0017] Preferably, solder balls are formed on the connection terminals, and the solder balls are connected to solder balls formed on the fan-out package.

[0018] The rewiring layer is preferably formed on one or both surfaces of the bridge substrate.

[0019] Preferably, the passive elements include at least one of a resistor, a capacitor, and an inductor.

[0020] The resistor is preferably formed by forming a thin film resistive layer on the bridge substrate and patterning it onto the redistribution layer through a patterning process.

[0021] The resistors are preferably made from nichrome (NiCr) or tantalum nitride (TaN) materials.

[0022] Preferably, the inductor is formed by forming a thin film metal layer on the bridge substrate and patterning it into a spiral shape.

[0023] Preferably, the redistribution layer is formed of one or more layers, and a passivation layer is formed between the layers to form different passive circuits, or a capacitor 264 or a balun. [Effects of the Invention]

[0024] The present invention provides a fan-out package including a bridge structure that can improve electrical performance by introducing a bridge structure for auxiliary connection between chips in a fan-out packaging process, thereby reducing trace routing congestion and improving trace design flexibility, and by providing passive elements in a rewiring layer.

[0025] In addition, the present invention integrates passive elements such as resistors, capacitors, and inductors directly into the redistribution layer on the bridge substrate, thereby effectively reducing parasitic resistance, parasitic inductance, and parasitic capacitance, improving signal integrity, and minimizing performance degradation in high-frequency and high-speed signal processing applications.

[0026] Furthermore, by patterning and integrating the passive elements of the present invention into the redistribution layer 240 of the bridge structure, space within the package can be saved, miniaturizing the semiconductor device, and achieving highly integrated packaging.

[0027] Furthermore, the high thermal conductivity and mechanical stability of the bridge structure according to the present invention provide excellent heat dissipation, solving the thermal management problems of high-performance semiconductor devices, and optimizing the heat dissipation path to improve the reliability and lifespan of the device. [Brief explanation of the drawings]

[0028] [Figure 1] FIG. 1 is a schematic diagram of an existing fan-out package. [Figure 2] 1 is a schematic diagram of a fan-out package including a bridge structure according to one embodiment of the present invention. [Figure 3] FIG. 3 is a schematic diagram of the embodiment of FIG. 2; [Figure 4] 10 is a schematic diagram of a fan-out package including a bridge structure according to another embodiment of the present invention. [Figure 5] 1 is a schematic diagram illustrating a state in which a fan-out package and a bridge structure according to an embodiment of the present invention are connected to each other by solder balls; [Figure 6] 1 is a schematic diagram illustrating a state in which a fan-out package and a bridge structure according to an embodiment of the present invention are connected to each other by solder balls; DETAILED DESCRIPTION OF THE INVENTION

[0029] The present invention relates to a fan-out package including a bridge structure, which can improve the flexibility of trace design by introducing a bridge structure for auxiliary connection between dies (chips) in a fan-out packaging process, and can improve electrical performance by providing passive elements in a rewiring layer, and a method for manufacturing the same.

[0030] Hereinafter, embodiments of the present invention will be described in detail with reference to the accompanying drawings.

[0031] Figure 2 is a schematic diagram of a fanout package including a bridge structure according to one embodiment of the present invention, Figure 3 is a schematic diagram of the combination of the embodiment of Figure 2, Figure 4 is a schematic diagram of a fanout package including a bridge structure according to another embodiment of the present invention, and Figures 5 and 6 are schematic diagrams showing the fanout package according to an embodiment of the present invention and the bridge structure connected to each other by solder balls.

[0032] As shown in the figure, the fan-out package using the bridge structure according to the present invention is a fan-out package integrating two or more dies 110, and includes a bridge substrate 220 formed on one side of the fan-out package 100, a redistribution layer 240 formed on the bridge substrate 220 and including one or more traces to electrically connect the dies 110, and passive elements 260 patterned and formed on the redistribution layer 240.

[0033] As a result, the present invention introduces a bridge structure for auxiliary connections between chips in the fan-out packaging process, thereby reducing trace routing congestion and improving trace design flexibility, and provides passive elements 260 in the redistribution layer 240 to improve electrical performance.

[0034] The present invention includes a bridge substrate 220 formed on one side of a fan-out package 100 in which two or more dies 110 are integrated, one or more traces 242 formed on the bridge substrate 220, a redistribution layer 240 on which passive elements 260 are patterned, and connection terminals 244 formed at the ends of the traces 242 and in contact with contact terminals 112 of the fan-out package 100, thereby electrically connecting different dies 110 integrated in the fan-out package 100 to each other.

[0035] The fan-out package 100 according to one embodiment of the present invention is an integrated package of two or more dies (chips) 110, and can be implemented in various ways, such as as a molded and embedded fan-out package 100, or as a surface mount type.

[0036] In the present invention, the die 110 and the chip are generally used as the same concept and are appropriately selected for each part.

[0037] Meanwhile, the embedded fan-out package 100 is generally produced by dicing chips formed on a silicon wafer, reconstituting and positioning chips that are confirmed to be operating normally on a carrier wafer, forming a chip redistribution layer (RDL) in the chip and fan-out areas, forming solder bumps or solder pads, and dicing each chip or chiplet unit (module).

[0038] The solder bumps or solder pads formed by the redistribution layer form input / output (I / O) terminals in the fan-out package 100 and serve as contact terminals 112 for connecting different modules or chips.

[0039] As electronic devices become more powerful and data processing becomes more common, the number of chips for data processing increases, and the number of I / Os increases. As a result, fan-out packages are being used to integrate one or more chips and provide a highly integrated multi-function module or package.

[0040] As shown in Figure 1, in the case of existing fan-out packages that contain two or more dies, even if the I / O is redistributed, there are limitations on trace routing due to the space limitations, making it difficult to connect the dies (chips). This requires a lot of effort and cost in the design process, and depending on the type of die, the density can become so high that it increases the possibility of short circuits or signal transmission errors.

[0041] For this reason, the present invention introduces a bridge structure for connecting chips to one side of the fan-out package 100. The bridge substrate 220 according to one embodiment of the present invention is formed on one side of the fan-out package 100, preferably on the top of the chip or chip redistribution layer. That is, it is formed on the bottom side of the packaging in the case of a package with a chip front structure, and on the top side of the package in the case of a package with a chip back structure, and can also be formed on the top or bottom side as necessary.

[0042] In addition, the bridge substrate 220 according to one embodiment of the present invention may be formed between the chips, on the entire surface of the chip, or wider or smaller than the entire surface of the chip, depending on the shape of the die 110, the arrangement and position of the input / output terminals, etc.

[0043] The bridge substrate 220 according to one embodiment of the present invention is formed of an electrically insulating material, and a material that is electrochemically stable and easy to process is used, and can be formed in various shapes depending on the shape of the die 110 or the arrangement of the input / output terminals for electrically connecting them to each other.

[0044] Preferably, the substrate may be formed in a rectangular thin plate shape and may be made of a rigid material or a flexible material, such as an inorganic material, an organic material, or an organic-inorganic composite material.

[0045] In one embodiment of the present invention, the bridge substrate 220 may be made of any one of a silicon substrate, a polymer substrate, a ceramic substrate, an organic / inorganic composite material substrate, and a glass fiber impregnated substrate.

[0046] In addition, the bridge substrate 220 may include a polymer resin in the substrate, and the polymer resin may include an epoxy-based insulating resin or a polyimide-based resin.

[0047] Here, when a polymer resin is included, it may include an epoxy insulating resin such as FR-4, BT (Bismaleimide Triazine), or ABF (Ajinomoto Build-up Film).

[0048] The bridge substrate 220 for assisting in such inter-chip connection can be packaged simultaneously during the die molding packaging process if necessary, and can be placed in a predetermined position for inter-chip connection after die molding is completed.

[0049] Also, a redistribution layer 240 including one or more traces 242 for electrically connecting the dies is formed on the bridge substrate 220 according to the present invention. The traces 242 may be formed in one or more wiring forms in consideration of the signal transmission speed according to the arrangement of the contact terminals 112 of the chips to be connected.

[0050] The traces 242 may be formed in a plurality of rows or columns and may be formed in various patterns such as straight lines, curved lines, bent lines, lines branching into two or more branches, and lines combining these in various ways.

[0051] The traces 242 may be formed on the substrate by a vacuum deposition method such as sputtering, and may be formed on one or both sides of the bridge substrate 220, or may be molded onto the substrate or mounted on the surface.

[0052] The redistribution layer 240 may be formed as one or more layers depending on the complexity of trace routing for chip connection, with a passivation layer 280 formed therebetween (see FIG. 4). The redistribution layer 240 may be formed on one or both sides of the bridge substrate 220.

[0053] The passive element 260 according to the present invention is formed by patterning the redistribution layer 240 .

[0054] The passive element 260 is formed on the bridge substrate 220, which in one embodiment of the present invention is a silicon bridge substrate 220 on which a redistribution layer 240 is formed.

[0055] That is, by integrating passive elements 260 such as resistors 262, capacitors 264, and inductors 266 into the redistribution layer 240 according to the present invention, electrical performance can be improved, and by forming the passive elements 260 in a bridge structure in the fan-out package 100, space can be saved. By forming such passive elements in the redistribution layer 240, signal integrity can be improved and parasitic elements can be reduced, and since the passive elements 260 are dispersed in the bridge structure, heat management during device operation is effective.

[0056] The resistor 262 according to the embodiment of the present invention may be formed by forming a thin film resistive layer on the bridge substrate 220 and patterning it on the redistribution layer 240 through a patterning process. The resistor 262 may be formed of nichrome (NiCr) or tantalum nitride (TaN) material and formed by forming a thin film layer on the bridge substrate 220 through a sputtering process or the like and then patterning the thin film layer.

[0057] The inductor 266 according to an embodiment of the present invention may be formed by forming a thin metal layer on the bridge substrate 220 and patterning it into a spiral shape. Generally, copper or aluminum, which have excellent conductivity, is used, and the spiral or maze-shaped inductor is patterned on the redistribution layer 240. Such an inductor 266 is suitable for RF applications and provides compact and efficient inductance.

[0058] The capacitor 264 according to the embodiment of the present invention has a metal / insulator (passivation layer 280) / metal structure, and is formed by stacking a dielectric between metal layers. Typical dielectric materials include SiO2 and Si3N4. Meanwhile, the redistribution layer 240 is formed of one or more layers, and a passivation layer 280 is formed between the layers to form different passive circuits, or a capacitor 264 or a balun. That is, the bridge structure has a metal / insulator (passivation layer 280) / metal structure, and the capacitor 264 is naturally formed.

[0059] Also, a balun can be designed using coupled inductor 266 and capacitor 264, which is optimized for signal matching and transformation by using the same materials and processes as inductor 266 and capacitor 264.

[0060] That is, high performance passive elements 260 such as metal-insulator-metal (MIM) structure capacitors 264 and spiral inductors 266 can be integrated to provide superior electrical performance in high frequency and RF applications, reducing signal interference and crosstalk to optimize overall system performance.

[0061] Furthermore, the passivation layer 280 protects the metal layers of the substrate and the passive elements 260, thereby protecting the system from environmental stress and physical damage, improving the durability of the semiconductor package, and ensuring long-term reliability.

[0062] At the end of the trace 242, a connection terminal 244 for connection to the contact terminal 112 of the fan-out package 100 may be formed.

[0063] The contact terminals 112 of the fan-out package 100 are generally formed by solder pads or solder bumps through a chip redistribution layer (RDL) for connecting chips in the chip region and the fan-out region, and the solder bumps or solder pads themselves can serve as input / output terminals.

[0064] The chip redistribution layer can be formed by routing traces 114 for input / output terminals to the chip area or fan-out area according to the routing design of traces 114 for connection between chips, and the ends of the traces 114 can be finished with solder bumps or solder pads.

[0065] The connection terminal 244 is electrically connected to the contact terminal 112 of the fan-out package 100, and may be any one or a combination of a metal connection part (e.g., a through silicon via (TSV)), a solder bump, and a solder bump pillar) depending on the shape of the contact terminal 112 of the fan-out package 100, the shape of the die 110, the height of the chip and bridge substrate 220, and the contact distance with the packaging substrate or silicon interposer.

[0066] Here, the connection terminals 244 may be formed on vias formed in the bridge substrate 220 or on solder pads formed on the bridge substrate 220 depending on the mounting form of the traces 242 .

[0067] In one embodiment of the present invention shown in Figures 2 to 4, traces 242 arranged at a fixed pitch are formed on one side (upper or / and lower side) of the bridge substrate 220, and connecting terminals 244 are formed on both ends of the traces 242.

[0068] In the embodiment of Figures 2 and 3, a bridge substrate 220 is formed to be almost the same size as the entire surface of the package for connecting chips, and three rows of traces 242 are formed in straight lines of the same size on the bridge substrate 220.

[0069] In the embodiment of FIG. 4, the redistribution layer 240 is formed in one or more layers with a passivation layer 280 formed therebetween.

[0070] In each embodiment, passive elements 260 such as resistors 262, capacitors 264, and inductors 266 are formed in the redistribution layer 240, and in the case of Fig. 4, passive elements are formed in both of the two redistribution layers 240. This allows for the realization of new passive circuits or passive elements, further improving electrical performance, and forming the passive elements 260 in a bridge structure in the fan-out package 100 can provide a space saving effect.

[0071] In the above embodiment, the outermost contact terminals 112 are designed to be connected to the connection terminals 244 of the traces 242 formed on the bridge substrate 220 for connection between chips, so that all contact terminals 112 of the chips are connected to each other, and the traces are distributed on the bridge substrate 220, reducing trace routing congestion.

[0072] In this embodiment of the present invention, the connection terminals 244 formed at both ends of the trace 242 are formed by forming vias in the bridge substrate 220 and implementing solder pads on the outer surfaces of the vias.

[0073] If the trace 242 is formed on the underside of the bridge substrate 220, a via need not be formed, and the connection terminal 244 can be realized by a combination of a solder pad and a solder bump, and it is not necessary to form a via and a metal connection portion to increase utilization.

[0074] As described above, the structure of such a connecting terminal 244 is designed taking into consideration the shape of the contact terminal 112 of the fan-out package 100, the shape of the die 110, the height of the chip and bridge substrate 220, and the contact distance with the packaging substrate or silicon interposer, etc.

[0075] The traces 242 and the connecting terminals 244 may be formed of a conductive metal such as copper, and may be fabricated simultaneously or sequentially. That is, depending on the design of the bridge substrate 220, the traces 242 may be formed after the connecting terminals 244 are formed, or the traces 242 may be formed before the connecting terminals 244 are formed.

[0076] Furthermore, the connection terminals 244 may be located on the outside or inside of the die 110 in the fan-out package 100. When located on the outside of the die 110, the routing density of the traces 242 can be further reduced. This should be appropriately designed taking into consideration the type of chip and the signal transmission distance.

[0077] The design of the trace routing formed on such a bridge substrate 220 can take various forms depending on the arrangement and number of traces 114 for direct connection between the contact terminals (or input / output terminals) 112 of the chip or packaging and the chip.

[0078] Furthermore, as described above, the trace 242 can be molded on one or both sides of the bridge substrate 220 or inside the bridge substrate 220, which provides an advantage of allowing a high degree of freedom in trace design.

[0079] As shown in FIGS. 5 and 6, the bridge structure contacts the fan-out package by solder balls 116, 246, solder pads or solder bumps.

[0080] For example, when the solder balls 116, 246 formed on the bridge structure and the fan-out package 100 come into contact with each other, the solder ball 246 of the bridge structure and the corresponding solder ball 116 of the fan-out package 100 are electrically connected by the rewiring layer (trace) 240 of the bridge structure. This reduces the trace density in the fan-out package 100, reducing the short circuit failure rate and minimizing signal transmission errors.

[0081] 5 shows a bridge structure in which two redistribution layers 240 are formed on a bridge substrate with a passivation layer 280 formed therebetween, with the redistribution layers 240 being formed in one or more layers and the passivation layer 280 being formed therebetween, and solder balls 246 are formed on the connection terminals of the lower redistribution layer 240 to provide a bridge structure. This bridge structure is bonded onto the fan-out package 100, and the solder balls 246 of the redistribution layers 240 and the solder balls 116 formed on the fan-out package 100 come into contact with each other and are electrically connected. FIG. 6 shows a bridge structure implemented with a single redistribution layer 240.

[0082] In this way, in a fan-out package, when it is difficult to connect chips due to the chip's function, shape, or large I / O count, or when the trace routing density is too high, the present invention introduces a bridge for connecting chips, thereby distributing some of the routing to the bridge, improving the design freedom of the trace routing and thereby increasing production efficiency.

[0083] Furthermore, by integrating passive elements such as resistors, capacitors, and inductors into the redistribution layer (RDL) of the present invention, electrical performance can be improved, and by forming the passive elements in a bridge structure in a fan-out package, space can be saved. By forming such passive elements in the redistribution layer, signal integrity can be improved and parasitic elements can be reduced, and since the passive elements are distributed in the bridge structure, heat management during device operation is effective.

Claims

1. A fan-out package in which two or more dies are integrated, a bridge substrate formed on one side of the fan-out package; a redistribution layer formed on the bridge substrate, the redistribution layer including one or more traces for electrically connecting between the dies; and a passive element formed by patterning on the rewiring layer.

2. 2. The fan-out package including the bridge structure according to claim 1, wherein the redistribution layer is formed by one or more layers, with a passivation layer formed between the layers.

3. 2. The fan-out package including the bridge structure according to claim 1, wherein the redistribution layer includes traces and connection terminals formed at ends of the traces.

4. 4. The fan-out package including the bridge structure according to claim 3, wherein solder balls are formed on the connection terminals, and the solder balls are connected to solder balls formed on the fan-out package.

5. 2. The fan-out package including the bridge structure according to claim 1, wherein the redistribution layer is formed on one or both sides of the bridge substrate.

6. 2. The fan-out package including the bridge structure according to claim 1, wherein the passive elements include at least one of a resistor, a capacitor, and an inductor.

7. 7. The fan-out package including the bridge structure according to claim 6, wherein the resistor is formed by forming a thin-film resistive layer on the bridge substrate and patterning it onto the redistribution layer through a patterning process.

8. 8. The fan-out package including a bridge structure according to claim 7, wherein the resistor is made of nichrome (NiCr) or tantalum nitride (TaN) material.

9. 7. The fan-out package including the bridge structure according to claim 6, wherein the inductor is formed by forming a thin-film metal layer on the bridge substrate and patterning it in a spiral shape.

10. 2. The fan-out package including the bridge structure according to claim 1, wherein the redistribution layer is formed of one or more layers, and a passivation layer is formed between the redistribution layers to form different passive circuits, or to form a capacitor 264 or a balun.

11. forming a fan-out package in which two or more dies are integrated; a bridge structure is positioned on one side of the fan-out package; the bridge structure includes a bridge substrate, a redistribution layer including one or more traces and electrically connecting between the dies, and passive elements formed in the redistribution layer; The method for manufacturing a fan-out package including a bridge structure, wherein the passive elements are formed by patterning a redistribution layer on the bridge substrate through a thin film deposition and patterning process.

12. 12. The method for manufacturing a fan-out package including a bridge structure according to claim 11, further comprising forming one or more redistribution layers on the bridge substrate, and forming a passivation layer between each redistribution layer.

13. 12. The method of claim 11, wherein the redistribution layer includes traces and connection terminals formed at ends of the traces.

14. 14. The method of claim 13, wherein solder balls are formed on the connection terminals, and the solder balls are connected to solder balls formed on the fan-out package.

15. 12. The method of manufacturing a fan-out package including a bridge structure according to claim 11, wherein the redistribution layer is formed on one or both sides of the bridge substrate.

16. 12. The method of claim 11, wherein the passive elements include at least one of a resistor, a capacitor, and an inductor.

17. 17. The method for manufacturing a fan-out package including a bridge structure according to claim 16, wherein the resistor is formed by forming a thin film resistive layer on the bridge substrate and patterning it onto the redistribution layer through a patterning process.

18. 18. The method for manufacturing a fan-out package including a bridge structure according to claim 17, wherein the resistor is made of nichrome (NiCr) or tantalum nitride (TaN) material.

19. 17. The method for manufacturing a fan-out package including a bridge structure according to claim 16, wherein the inductor is formed by forming a thin film metal layer on the bridge substrate and patterning it in a spiral shape.

20. 12. The method for manufacturing a fan-out package including a bridge structure according to claim 11, wherein the redistribution layer is formed of one or more layers, and a passivation layer is formed between the redistribution layers to form different passive circuits, or to form a capacitor or a balun.

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