Thin film transistor unit and display apparatus including the same

Abstract

To provide a thin film transistor unit and a display apparatus that reduce the risk of heat generation while maintaining the total amount of current by distributing current paths.SOLUTION: The thin film transistor unit 100 includes a base substrate 110, a first bottom thin film transistor 21 and a second bottom thin film transistor 22 disposed on the base substrate and connected to each other in parallel, and a first top thin film transistor 11 and a second top thin film transistor 12 disposed on the first bottom thin film transistor and the second bottom thin film transistor and connected to each other in parallel, wherein the first top thin film transistor includes a first top active layer 131a and first top gate electrodes 151 disposed on the first top active layer. The second upper electrodes may include a second upper active layer 131b and a second upper gate thin film transistor 152 disposed on the second upper active layer LA.SELECTED DRAWING: Figure 2

Description

[Technical Field]

[0001] The present invention relates to a thin film transistor unit and a display device including the thin film transistor unit. [Background technology]

[0002] As the information society develops, the demand for display devices for displaying images is increasing in various forms, and in recent years, various display devices such as liquid crystal displays (LCDs), plasma display panels (PDPs), and organic light emitting diode display devices (OLEDs) have been used.

[0003] In general, a display device includes a driving circuit for driving a display panel, which includes a gate driving circuit for sequentially applying scan signals to gate lines and a data driving circuit for applying image information to pixels via data lines in response to the scan signals of the gate driving circuit.

[0004] In the case of a transistor in a gate drive circuit, a high bias voltage is applied to the gate electrode and the drain electrode, and the transistor may have characteristics that make it vulnerable to heat generation.

[0005] Therefore, in recent years, research has been continuously conducted to reduce the risk of heat generation in transistors of gate drive circuits. Summary of the Invention [Problem to be solved by the invention]

[0006] One embodiment of the present invention provides a thin film transistor unit with distributed current paths, reducing the risk of heat generation while maintaining the total current flow rate.

[0007] One embodiment of the present invention provides a thin film transistor unit in which gate electrodes are arranged in parallel at the upper and lower ends, and the channel width is reduced while the channel length is maintained, thereby ensuring a process margin. [Means for solving the problem]

[0008] In order to achieve the above technical object, one embodiment of the present invention provides a thin film transistor unit including: a base substrate; a first lower thin film transistor and a second lower thin film transistor disposed on the base substrate and connected in parallel to each other; a first upper thin film transistor and a second upper thin film transistor disposed on the first lower thin film transistor and the second lower thin film transistor and connected in parallel to each other; the first upper thin film transistor includes a first upper active layer and a first upper gate electrode disposed on the first upper active layer; the second upper thin film transistor includes a second upper active layer and a second upper gate electrode disposed on the second upper active layer; the first upper gate electrode and the second upper gate electrode are electrically connected with a first upper drain electrode interposed therebetween; the first lower thin film transistor includes a first lower gate electrode and a first lower active layer disposed on the first lower gate electrode; the second lower thin film transistor includes a second lower gate electrode and a second lower active layer disposed on the second lower gate electrode; the first lower gate electrode and the second lower gate electrode are electrically connected with a first lower drain electrode interposed therebetween.

[0009] The first upper gate electrode, the second upper gate electrode, and the first upper drain electrode may be integrally formed, and the first lower gate electrode, the second lower gate electrode, and the first lower drain electrode may be integrally formed.

[0010] The first upper active layer of the first upper thin film transistor and the second upper active layer of the second upper thin film transistor may be spaced apart with a first connection therebetween, and the first lower active layer of the first lower thin film transistor and the second lower active layer of the second lower thin film transistor may be spaced apart with a second connection therebetween.

[0011] A first upper active layer of the first upper thin film transistor and a second upper active layer of the second upper thin film transistor are integrally formed with the first connecting portion, and a first lower active layer of the first lower thin film transistor and a second lower active layer of the second lower thin film transistor are integrally formed with the second connecting portion.

[0012] In a plan view, the first upper gate electrode can overlap the first lower gate electrode, and the second upper gate electrode can overlap the second lower gate electrode.

[0013] In a plan view, a first upper active layer of the first upper thin film transistor may overlap with a first lower active layer of the first lower thin film transistor, and a second upper active layer of the second upper thin film transistor may overlap with a second lower active layer of the second lower thin film transistor.

[0014] The first connection part may contact the first upper drain electrode, and the second connection part may contact the first lower drain electrode.

[0015] The display device may further include a first buffer layer disposed between the first lower thin film transistor and the first upper thin film transistor and between the second lower thin film transistor and the second upper thin film transistor.

[0016] A first upper active layer of the first upper thin film transistor may be disposed between the first buffer layer and the first upper gate electrode, and a second upper active layer of the second upper thin film transistor may be disposed between the first buffer layer and the second upper gate electrode.

[0017] A first lower active layer of the first lower thin film transistor may be disposed between the first buffer layer and the first lower gate electrode, and a second lower active layer of the second lower thin film transistor may be disposed between the first buffer layer and the second lower gate electrode.

[0018] The semiconductor device may further include a second buffer layer disposed between the base substrate and the first buffer layer, the first buffer layer being formed by patterning, and the second buffer layer being disposed over the entire upper surface of the base substrate.

[0019] The thin film transistor may include a first source electrode and a second source electrode spaced apart from each other, the first source electrode being spaced apart from the first upper drain electrode with a first upper active layer of the first upper thin film transistor therebetween and the first lower drain electrode being spaced apart from the first lower active layer of the first lower thin film transistor therebetween, and the second source electrode being spaced apart from the first upper drain electrode with a second upper active layer of the second upper thin film transistor therebetween and the first lower drain electrode being spaced apart from the second lower active layer of the second lower thin film transistor therebetween.

[0020] The first source electrode may be in contact with a first upper active layer of the first upper thin film transistor and a first lower active layer of the first lower thin film transistor, respectively, and the second source electrode may be in contact with a second upper active layer of the second upper thin film transistor and a second lower active layer of the second lower thin film transistor, respectively.

[0021] The first upper drain electrode and the first lower drain electrode may be connected to each other through a first contact hole formed in the first buffer layer.

[0022] The first upper thin film transistor may further include a first gate insulating film disposed between a first upper active layer of the first upper thin film transistor and the first upper gate electrode, and the second upper thin film transistor may further include a second gate insulating film disposed between a second upper active layer of the second upper thin film transistor and the second upper gate electrode, the first gate insulating film and the second gate insulating film being spaced apart with a second contact hole interposed therebetween, the first lower thin film transistor may further include a third gate insulating film disposed between the first lower active layer of the first lower thin film transistor and the first lower gate electrode, and the second lower thin film transistor may further include a fourth gate insulating film disposed between a second lower active layer of the second lower thin film transistor and the second lower gate electrode, the third gate insulating film and the fourth gate insulating film being spaced apart with a third contact hole interposed therebetween.

[0023] The first upper drain electrode may be formed in the second contact hole.

[0024] In a plan view, the second contact hole and the third contact hole can be arranged to overlap each other.

[0025] In a plan view, a first lower active layer of the first lower thin film transistor may have a larger area than a first upper active layer of the first upper thin film transistor.

[0026] In a plan view, the second lower active layer of the second lower thin film transistor may have a larger area than the second upper active layer of the second upper thin film transistor.

[0027] the first upper thin film transistor and the second upper thin film transistor are arranged along a first direction, the first lower thin film transistor and the second lower thin film transistor are arranged along the first direction, and a direction intersecting the first direction is a second direction, The pixel may further include a third upper thin film transistor arranged in the second direction with respect to the first upper thin film transistor, a fourth upper thin film transistor arranged in the second direction with respect to the second upper thin film transistor, a third lower thin film transistor arranged in the second direction with respect to the first lower thin film transistor, and a fourth lower thin film transistor arranged in the second direction with respect to the second lower thin film transistor, wherein the third upper thin film transistor and the fourth upper thin film transistor are connected in parallel to each other, and the third lower thin film transistor and the fourth lower thin film transistor are connected in parallel to each other.

[0028] The third upper thin film transistor includes a third upper active layer and a third upper gate electrode disposed on the third upper active layer, the fourth upper thin film transistor includes a fourth upper active layer and a fourth upper gate electrode disposed on the fourth upper active layer, the third upper gate electrode and the fourth upper gate electrode being electrically connected to each other via a second upper drain electrode, the third lower thin film transistor includes a third lower gate electrode and a third lower active layer disposed on the third lower gate electrode, and the fourth lower thin film transistor includes a fourth lower gate electrode and a fourth lower active layer disposed on the fourth lower gate electrode, the third lower gate electrode and the fourth lower gate electrode being electrically connected to each other via a second lower drain electrode.

[0029] The first upper drain electrode and the second upper drain electrode are electrically connected with an upper bridge electrode interposed therebetween, and the first lower drain electrode and the second lower drain electrode are electrically connected with a lower bridge electrode interposed therebetween, and the upper bridge electrode and the lower bridge electrode can overlap in a planar view.

[0030] An embodiment of the present invention provides a display device including the thin film transistor unit.

[0031] In the thin film transistor unit according to an embodiment of the present invention, the gate electrodes are arranged in parallel at the upper and lower ends, thereby distributing the current paths.

[0032] In the thin film transistor unit according to an embodiment of the present invention, the gate electrodes are arranged in parallel at the upper and lower ends, thereby reducing the risk of heat generation.

[0033] In the thin film transistor unit according to an embodiment of the present invention, the gate electrodes are arranged in parallel at the upper and lower ends, thereby reducing the channel width while maintaining the channel length, thereby ensuring a process margin.

[0034] In addition to the above-mentioned effects, other features and advantages of the present invention will be clearly understood by those skilled in the art from the following description or from such description and explanation. [Brief explanation of the drawings]

[0035] [Figure 1] 1 is a plan view of a thin film transistor unit according to an embodiment of the present invention; [Figure 2] FIG. 2 is a cross-sectional view taken along II' in FIG. [Figure 3] FIG. 2 is a cross-sectional view taken along line II-II' in FIG. [Figure 4] FIG. 10 is a plan view of a thin film transistor unit according to another embodiment of the present invention. [Figure 5] FIG. 5 is a cross-sectional view taken along the line III-III' in FIG. [Figure 6] FIG. 4 is a cross-sectional view taken along line IV-IV′ of FIG. [Figure 7A] 5A to 5C are process diagrams illustrating a manufacturing process of a thin film transistor unit according to an embodiment of the present invention. [Figure 7B] 5A to 5C are process diagrams illustrating a manufacturing process of a thin film transistor unit according to an embodiment of the present invention. [Figure 7C] 5A to 5C are process diagrams illustrating a manufacturing process of a thin film transistor unit according to an embodiment of the present invention. [Figure 7D] 5A to 5C are process diagrams illustrating a manufacturing process of a thin film transistor unit according to an embodiment of the present invention. [Figure 7E] 5A to 5C are process diagrams illustrating a manufacturing process of a thin film transistor unit according to an embodiment of the present invention. [Figure 7F] 5A to 5C are process diagrams illustrating a manufacturing process of a thin film transistor unit according to an embodiment of the present invention. [Figure 7G] 5A to 5C are process diagrams illustrating a manufacturing process of a thin film transistor unit according to an embodiment of the present invention. [Figure 7H] 5A to 5C are process diagrams illustrating a manufacturing process of a thin film transistor unit according to an embodiment of the present invention. [Figure 7I] 5A to 5C are process diagrams illustrating a manufacturing process of a thin film transistor unit according to an embodiment of the present invention. [Figure 8] 1 is a schematic diagram of a display device according to an embodiment of the present invention; [Figure 9] FIG. 1 is a schematic diagram of a shift register. [Figure 10] FIG. 10 is a circuit diagram of an embodiment of a stage provided in the shift register of FIG. 9. [Figure 11] 2 is a circuit diagram of a thin film transistor unit according to an embodiment of the present invention; Modes for embodying the invention

[0036] The advantages and features of the present invention, and the methods for achieving them, will become clearer with reference to the following detailed examples, which are described in conjunction with the accompanying drawings. However, the present invention is not limited to the examples disclosed below, and may be embodied in various different forms. The examples are provided solely to ensure that the disclosure of the present invention is complete and to fully convey the scope of the invention to those skilled in the art.

[0037] The shapes, sizes, ratios, angles, numbers, etc. disclosed in the drawings for explaining examples of the present invention are merely illustrative and are not limited to the matters shown in the drawings of the present invention. The same components may be designated by the same reference numerals throughout the specification. Furthermore, when describing examples of the present invention, if it is determined that a detailed description of related prior art may unnecessarily obscure the gist of the application, such a detailed description will be omitted.

[0038] When the terms "comprise," "have," "consist of," etc. are used in the present specification, other parts may be added unless "only" is used. When an element is expressed in the singular, it also includes the plural unless otherwise expressly stated.

[0039] When interpreting elements, they are interpreted as including a margin of error even if there is no other explicit description.

[0040] For example, when the location of two parts is described using terms such as "above," "on top," "below," or "beside," one or more other parts may be located between the two parts unless the terms "immediately" or "directly" are used.

[0041] Spatially relative terms such as "below," "beneath," "lower," "above," "upper," and the like may be used to easily describe the relationship between one element or component and another, as illustrated in the figures. Spatially relative terms should be understood to encompass different orientations in use or operation in addition to the orientations depicted in the figures. For example, if an element depicted in a figure is flipped over, an element described as "below" or "below" another element may then be positioned "above" the other element. Thus, the exemplary term "below" can encompass both an orientation of below and above. Similarly, the exemplary terms "upper" or "top" can encompass both an orientation of above and below.

[0042] When describing a temporal relationship, for example, when the temporal precedence is described using "after," "following," "next to," or "before," it can also include cases where the relationship is not consecutive, unless "immediately" or "directly" is used.

[0043] Although terms such as "first" and "second" are used to describe various components, these components are not limited by these terms. These terms are used merely to distinguish one component from another. Therefore, a first component referred to below may also be a second component within the technical spirit of the present invention.

[0044] The term "at least one" should be understood to include all combinations that can be presented from one or more of the associated items. For example, "at least one of the first, second, and third items" can mean not only the first, second, or third item, but also all combinations of items that can be presented from two or more of the first, second, and third items.

[0045] The features of the various examples of the present invention may be partially or fully combined or combined with each other, and may be technically interlocked and driven in various ways, and each example may be implemented independently of the other, or may be implemented together in association with each other.

[0046] When adding reference numerals to components in each drawing illustrating an embodiment of the present invention, the same components may be assigned the same numerals as far as possible even if they are displayed in different drawings.

[0047] In the embodiments of the present invention, the source electrode and the drain electrode are distinguished only for the convenience of explanation, and the source electrode and the drain electrode may be interchangeable. A source electrode may be a drain electrode, and a drain electrode may be a source electrode. Furthermore, a source electrode in any embodiment may be a drain electrode in another embodiment, and a drain electrode in any embodiment may be a source electrode in another embodiment.

[0048] In some embodiments of the present invention, for convenience of explanation, a source region and a source electrode may be distinguished, and a drain region and a drain electrode may be distinguished, but the embodiments of the present invention are not limited thereto. The source region may be the source electrode, and the drain region may be the drain electrode. Furthermore, the source region may be the drain electrode, and the drain region may be the source electrode.

[0049] Fig. 1 is a plan view of a thin film transistor unit 100 according to an embodiment of the present invention. Fig. 2 is a cross-sectional view taken along line II' in Fig. 1. Fig. 3 is a cross-sectional view taken along line II' in Fig. 1.

[0050] Referring to Figures 1, 2 and 3, a thin film transistor unit 100 according to one embodiment of the present invention includes a first lower thin film transistor 21 and a second lower thin film transistor 22 connected in parallel to each other, and a first upper thin film transistor 11 and a second upper thin film transistor 12 connected in parallel to each other.

[0051] Specifically, referring to Figures 1 to 3, the figures show a first lower thin film transistor 21 and a second lower thin film transistor connected in parallel to each other on a base substrate 110, and a first upper thin film transistor 11 and a second upper thin film transistor 12 connected in parallel to each other and arranged on the first lower thin film transistor 21 and the second lower thin film transistor.

[0052] Hereinafter, components of the thin film transistor unit 100 according to an embodiment of the present invention will be described in detail.

[0053] Glass or plastic can be used for the base substrate 110. As the plastic, a transparent plastic having flexible properties, such as polyimide, can be used.

[0054] When polyimide is used as the base substrate 110, a heat-resistant polyimide that can withstand high temperatures can be used, considering that a high-temperature deposition process is performed on the base substrate 110. In this case, to form a thin film transistor, processes such as deposition and etching can be performed in a state where the polyimide substrate is placed on a carrier substrate made of a highly durable material such as glass.

[0055] Although not shown in the figure, a light blocking layer (not shown) may be disposed on the base substrate 110 .

[0056] A light blocking layer (not shown) may be disposed between the base substrate 110 and the second buffer layer 122 .

[0057] The light-blocking layer (not shown) may be made of a material having light-blocking properties. The light-blocking layer (not shown) may include at least one of aluminum-based metals such as aluminum (Al) and aluminum alloys, molybdenum-based metals such as molybdenum (Mo) and molybdenum alloys, chromium (Cr), tantalum (Ta), neodymium (Nd), titanium (Ti), and iron (Fe). According to one embodiment of the present invention, the light-blocking layer (not shown) may be electrically conductive.

[0058] Referring to FIGS. 2 and 3, a second buffer layer 122 may be disposed on the base substrate 110. As shown in FIG.

[0059] The second buffer layer 122 is formed on the base substrate 110 and may be made of an inorganic or organic material, such as an insulating oxide such as silicon oxide (SiOx) or aluminum oxide (Al2O3).

[0060] The second buffer layer 122 serves to protect the first active layer 131 and the second active layer 231 by blocking impurities such as moisture and oxygen that flow in from the base substrate 110, and to planarize the top surface of the base substrate 110, and may be formed as a single layer or multiple layers.

[0061] When the second buffer layer 122 is a multi-layer structure, each of the multi-layer structures may be made of a different material.

[0062] 1 to 3, a first upper thin film transistor 11, a second upper thin film transistor 12, a first lower thin film transistor 21, and a second lower thin film transistor are arranged in parallel.

[0063] The first upper thin film transistor 11 includes a first upper active layer 131a and a first upper gate electrode 151 disposed on the first upper active layer 131a.

[0064] The second upper thin film transistor 12 includes a second upper active layer 131b and a second upper gate electrode 152 disposed on the second upper active layer 131b.

[0065] The first lower thin film transistor 21 includes a first lower gate electrode 153 and a first lower active layer 231 a disposed on the first lower gate electrode 153 .

[0066] The second lower thin film transistor 22 includes a second lower gate electrode 154 and a second lower active layer 231 b disposed on the second lower gate electrode 154 .

[0067] 1 and 2, the first upper gate electrode 151 and the second upper gate electrode 152 are spaced apart by a first upper drain electrode 171. Specifically, the first upper gate electrode 151 and the second upper gate electrode 152 are electrically connected with the first upper drain electrode 171 interposed therebetween.

[0068] Specifically, the first upper gate electrode 151 and the second upper gate electrode 152 are integrally formed with the first upper drain electrode 171. More specifically, the first upper gate electrode 151, the second upper gate electrode 152, and the first upper drain electrode 171 are formed using the same material and in the same process.

[0069] According to an embodiment of the present invention, the first upper gate electrode 151, the second upper gate electrode 152, and the first upper drain electrode 171 are defined by an area overlapping with a surface in contact with the first connector 131c. Specifically, the area overlapping with the surface in contact with the first connector 131c may be the first upper drain electrode 171, and the structure arranged on one side of the first upper drain electrode 171 while in contact with the first upper gate electrode 151 may be the first upper drain electrode 171 and the second upper gate electrode 152.

[0070] 1 and 2, the first bottom gate electrode 153 and the second bottom gate electrode 154 are spaced apart by a first bottom drain electrode 172. Specifically, the first bottom gate electrode 153 and the second bottom gate electrode 154 are electrically connected with the first bottom drain electrode 172 interposed therebetween.

[0071] Specifically, the first lower gate electrode 153 and the second lower gate electrode 154 are integrally formed with the first lower drain electrode 172. More specifically, the first lower gate electrode 153, the second lower gate electrode 154, and the first lower drain electrode 172 are formed of the same material and in the same process.

[0072] According to an embodiment of the present invention, the first bottom gate electrode 153, the second bottom gate electrode 154, and the first bottom drain electrode 172 are defined by an area overlapping with a surface in contact with the second connector 231c. Specifically, the area overlapping with the surface in contact with the second connector 231c may be the first bottom drain electrode 172, a structure in contact with the first bottom drain electrode 172 and disposed on one side may be the first bottom gate electrode 153, and a structure in contact with the first bottom drain electrode 172 and disposed on the other side may be the second bottom gate electrode 154.

[0073] According to an embodiment of the present invention, the first upper active layer 131a of the first upper thin film transistor 11 and the second upper active layer 131b of the second upper thin film transistor 12 are spaced apart with the first connecting portion 131c therebetween.

[0074] Specifically, the first upper active layer 131a of the first upper thin film transistor 11 and the second upper active layer 131b of the second upper thin film transistor 12 are integrally formed with the first connecting portion 131c. More specifically, the first upper active layer 131a of the first upper thin film transistor 11 and the second upper active layer 131b of the second upper thin film transistor 12 are formed of the same material and in the same process as the first connecting portion 131c.

[0075] According to one embodiment of the present invention, the first upper active layer 131a of the first upper thin film transistor 11, the second upper active layer 131b of the second upper thin film transistor 12, and the first connecting portion 131c may be collectively referred to as the first active layer 131.

[0076] According to an embodiment of the present invention, the first lower active layer 231a of the first lower thin film transistor 21 and the second lower active layer 231b of the second lower thin film transistor 22 are spaced apart with the second connecting portion 231c therebetween.

[0077] Specifically, the first lower active layer 231a of the first lower thin film transistor 21 and the second lower active layer 231b of the second lower thin film transistor 22 are integrally formed with the second connecting part 231c. More specifically, the first lower active layer 231a of the first lower thin film transistor 21 and the second lower active layer 231b of the second lower thin film transistor 22 are formed of the same material and in the same process as the second connecting part 231c.

[0078] According to one embodiment of the present invention, the first lower active layer 231a of the first lower thin film transistor 21, the second lower active layer 231b of the second lower thin film transistor 22, and the second connecting part 231c may be collectively referred to as the second active layer 231.

[0079] According to an embodiment of the present invention, the first connection part 131c may contact the first upper drain electrode 171, and the second connection part 231c may contact the first lower drain electrode 172.

[0080] According to an embodiment of the present invention, the first upper active layer 131a of the first upper thin film transistor 11 is electrically connected to the first upper drain electrode 171 through the first connection part 131c.

[0081] According to an embodiment of the present invention, the second upper active layer 131b of the second upper thin film transistor 12 is electrically connected to the first upper drain electrode 171 through the first connection part 131c.

[0082] According to an embodiment of the present invention, the first lower active layer 231a of the first lower thin film transistor 21 is electrically connected to the first lower drain electrode 172 through the second connection part 231c.

[0083] According to an embodiment of the present invention, the second lower active layer 231b of the second lower thin film transistor 22 is electrically connected to the first lower drain electrode 172 through the second connection part 231c.

[0084] 1 to 3, the first upper gate electrode 151 can overlap with the first lower gate electrode 153, and the second upper gate electrode 152 can overlap with the second lower gate electrode 154 in plan view.

[0085] Specifically, in plan view, the entire region of the first upper gate electrode 151 can overlap with the first lower gate electrode 153, and the entire region of the second upper gate electrode 152 can overlap with the second lower gate electrode 154.

[0086] 1 to 3, the first upper drain electrode 171 can overlap with the first lower drain electrode 172 in a plan view.

[0087] 1 to 3 show how the first upper drain electrode 171 overlaps with the first lower drain electrode 172. In FIG.

[0088] According to an embodiment of the present invention, the first upper active layer 131a of the first upper thin film transistor 11 can overlap the first lower active layer 231a of the first lower thin film transistor 21 in a plan view.

[0089] Furthermore, the second upper active layer 131b of the second upper thin film transistor 12 can overlap the second lower active layer 231b of the second lower thin film transistor 22 in plan view.

[0090] 1 and 2 show that, in a plan view, the first upper active layer 131a of the first upper thin film transistor 11 overlaps with the first lower active layer 231a of the first lower thin film transistor 21, and the second upper active layer 131b of the second upper thin film transistor 12 overlaps with the second lower active layer 231b.

[0091] 1 to 3, the first connecting portion 131c and the second connecting portion 231c can overlap each other in a plan view.

[0092] Specifically, the first upper drain electrode 171, the first connecting portion 131c, the second connecting portion 231c, and the first lower drain electrode 172 can be overlapped at the same time in a plan view.

[0093] 2 and 3, the thin film transistor unit 100 may further include a first buffer layer 121 disposed between the first upper thin film transistor 11 and the first lower thin film transistor 21 and between the second upper thin film transistor 12 and the second lower thin film transistor 22. The second buffer layer 122 may be disposed between the base substrate 110 and the first buffer layer 121. The first buffer layer 121 may be formed by patterning, and the second buffer layer 122 may be disposed over the entire upper surface of the base substrate 110.

[0094] The first buffer layer 121 may be formed of an inorganic or organic material. For example, it may include an insulating oxide such as silicon oxide (SiOx) or aluminum oxide (Al2O3). The first buffer layer 121 may be formed as a single layer or multiple layers. The first buffer layer 121 may be made of the same material as the second buffer layer 122, or may be made of different materials.

[0095] According to one embodiment of the present invention, the first upper active layer 131a of the first upper thin film transistor 11 is disposed between the first buffer layer 121 and the first upper gate electrode 151, and the second upper active layer 131b of the second upper thin film transistor 12 is disposed between the first buffer layer 121 and the second upper gate electrode 152.

[0096] According to one embodiment of the present invention, the first lower active layer 231a of the first lower thin film transistor 21 is disposed between the first buffer layer 121 and the first lower gate electrode 153, and the second lower active layer 231b of the second lower thin film transistor 22 is disposed between the first buffer layer 121 and the second lower gate electrode 154.

[0097] FIG. 2 shows that the first buffer layer 121 is disposed between the first active layer 131 and the second active layer 231 .

[0098] According to an embodiment of the present invention, the thin film transistor unit 100 includes a first source electrode 161a and a second source electrode 162a that are spaced apart from each other.

[0099] Referring to FIG. 2, the first source electrode 161a is disposed spaced apart from the first upper drain electrode 171 with the first upper active layer 131a of the first upper thin film transistor 11 therebetween, and is disposed spaced apart from the first lower drain electrode 172 with the first lower active layer 231a of the first lower thin film transistor 21 therebetween.

[0100] Specifically, the first source electrode 161a is electrically connected to the first upper drain electrode 171 through the first upper active layer 131a and the first connector 131c. In addition, the first source electrode 161a is electrically connected to the first lower drain electrode 172 through the first lower active layer 231a and the second connector 231c.

[0101] Referring to FIG. 2, the second source electrode 162a is disposed apart from the first upper drain electrode 171 with the second upper active layer 131b of the second upper thin film transistor 12 therebetween, and is disposed apart from the first lower drain electrode 172 with the second lower active layer 231b of the second lower thin film transistor 22 therebetween.

[0102] Specifically, the second source electrode 162a is electrically connected to the first upper drain electrode 171 via the second upper active layer 131b and the first connector 131c. In addition, the second source electrode 162a is electrically connected to the first lower drain electrode 172 via the second lower active layer 231b and the second connector 231c.

[0103] 1 and 2, the first source electrode 161a contacts the first upper active layer 131a of the first upper thin film transistor 11 and the first lower active layer 231a of the first lower thin film transistor 21, respectively.

[0104] Specifically, referring to FIG. 2, the first source electrode 161a may cover part of the side and top surface of the first upper active layer 131a of the first upper thin film transistor 11.

[0105] 1 and 2, the second source electrode 162a contacts the second upper active layer 131b of the second upper thin film transistor 12 and the second lower active layer 231b of the second lower thin film transistor 22, respectively.

[0106] Specifically, referring to FIG. 2, the second source electrode 162a may cover part of the side and top surface of the second upper active layer 131b of the second upper thin film transistor 12.

[0107] According to an embodiment of the present invention, the first upper drain electrode 171 and the first lower drain electrode 172 are connected to each other through a first contact hole (CNT1) formed in the first buffer layer 121.

[0108] FIG. 3 shows a state in which the first upper drain electrode 171 and the first lower drain electrode 172 are connected via a first contact hole (CNT1) formed in the first buffer layer 121.

[0109] According to one embodiment of the present invention, the first upper thin film transistor 11 may further include a first gate insulating film 141a disposed between the first upper active layer 131a of the first upper thin film transistor 11 and the first upper gate electrode 151.

[0110] The first gate insulating film 141a may include at least one of silicon oxide, silicon nitride, and metal oxide, and may have a single layer structure or a multi-layer structure.

[0111] The first gate insulating film 141a may cover a portion of the first upper active layer 131a and expose a portion of the first upper active layer 131a.

[0112] The region of the first upper active layer 131a exposed by the first gate insulating film 141a can be formed by selective conductivization.

[0113] According to one embodiment of the present invention, the second upper thin film transistor 12 may further include a second gate insulating film 141b disposed between the second upper active layer 131b of the second upper thin film transistor 12 and the second upper gate electrode 152.

[0114] The second gate insulating film 141b may be made of the same material as the first gate insulating film 141a, or may be made of a different material from the first gate insulating film 141a.

[0115] The region of the second upper active layer 131b exposed by the second gate insulating film 141b can be formed by selective conductivization.

[0116] Referring to FIG. 2, the first gate insulating film 141a and the second gate insulating film 141b may be spaced apart from each other by a second contact hole CNT2.

[0117] According to one embodiment of the present invention, the second contact hole (CNT2) is formed by patterning to form the first gate insulating film 141a and the second gate insulating film 141b. Also, the second contact hole (CNT2) is formed to be surrounded by the first gate insulating film 141a and the second gate insulating film 141b.

[0118] According to an embodiment of the present invention, the first upper drain electrode 171 is formed in the second contact hole CNT2.

[0119] FIG. 2 shows the first upper drain electrode 171 being formed in the second contact hole (CNT2).

[0120] According to one embodiment of the present invention, the first lower thin film transistor 21 may further include a third gate insulating film 141c disposed between the first lower active layer 231a of the first lower thin film transistor 21 and the first lower gate electrode 153.

[0121] The third gate insulating film 141c may be made of the same material as the first gate insulating film 141a and the second gate insulating film 141b, or may be made of a different material.

[0122] According to one embodiment of the present invention, the second lower thin film transistor 22 may further include a fourth gate insulating film 141d disposed between the second lower active layer 231b of the second lower thin film transistor 22 and the second lower gate electrode 154.

[0123] The fourth gate insulating film 141d may be made of the same material as the first gate insulating film 141a, the second gate insulating film 141b, and the third gate insulating film 141c, or may be made of a different material from each other.

[0124] Referring to FIG. 2, the third gate insulating film 141c and the fourth gate insulating film 141d may be spaced apart from each other by a third contact hole CNT3.

[0125] According to one embodiment of the present invention, the third contact hole (CNT3) is formed by patterning to form the third gate insulating film 141c and the fourth gate insulating film 141d. The third contact hole (CNT3) is formed to be surrounded by the third gate insulating film 141c and the fourth gate insulating film 141d.

[0126] According to an embodiment of the present invention, the second active layer 231 is formed in the third contact hole (CNT3). Specifically, the second connection part 231c is formed in the third contact hole (CNT3).

[0127] According to an embodiment of the present invention, the second contact hole (CNT2) and the third contact hole (CNT3) are arranged to overlap each other.

[0128] Specifically, referring to FIGS. 1 to 3, the second contact hole (CNT2) and the third contact hole (CNT3) are arranged to overlap each other.

[0129] According to an embodiment of the present invention, the first upper active layer 131a, the second upper active layer 131b, and the first connecting portion 131c of the first active layer 131 are defined based on both ends of the bottom surface of the second contact hole (CNT2).

[0130] The first lower active layer 231a, the second lower active layer 231b, and the second connecting portion 231c of the second active layer 231 are defined based on both ends of the bottom surface of the third contact hole CNT3.

[0131] According to an embodiment of the present invention, the first lower active layer 231a of the first lower thin film transistor 21 may have a larger area than the first upper active layer 131a of the first upper thin film transistor 11 in a plan view.

[0132] FIG. 1 shows that the first lower active layer 231a of the first lower thin film transistor 21 has a larger area than the first upper active layer 131a of the first upper thin film transistor 11.

[0133] The second lower active layer 231b of the second lower thin film transistor 22 can have a larger area than the second upper active layer 131b of the second upper thin film transistor 12 in a plan view.

[0134] According to one embodiment of the present invention, the first lower gate electrode 153 may have a larger area than the first upper gate electrode 151 in a plan view. Also, the second lower gate electrode 154 may have a larger area than the second upper gate electrode 152 in a plan view.

[0135] According to one embodiment of the present invention, the first upper thin film transistor 11 and the second upper thin film transistor 12 are arranged along the first direction (X), and the first lower thin film transistor 21 and the second lower thin film transistor 22 are arranged along the first direction (X).

[0136] According to an embodiment of the present invention, the first direction (X) refers to the direction that connects the first source electrode 161a and the second source electrode 162a in the shortest distance in a plan view.

[0137] Specifically, referring to FIG. 1, the first upper gate electrode 151 and the second upper gate electrode 152 are arranged along the first direction (X), and the first lower gate electrode 153 and the second lower gate electrode 154 are arranged along the first direction (X).

[0138] More specifically, referring to FIG. 1, the first upper active layer 131a and the second upper active layer 131b are arranged along the first direction (X), and the first lower active layer 231a and the second lower active layer 231b are arranged along the first direction (X).

[0139] 1, the first contact hole (CNT1) and the second contact hole (CNT2) are arranged along a second direction (Y) intersecting the first direction (X), and the first contact hole (CNT1) and the third contact hole (CNT3) are arranged along the second direction (Y).

[0140] According to one embodiment of the present invention, the second direction (Y) may be perpendicular to the first direction (X).

[0141] According to one embodiment of the present invention, the first upper gate electrode 151, the second upper gate electrode 152, the first lower gate electrode 153, and the second lower gate electrode 154 may each include at least one of an aluminum-based metal such as aluminum (Al) or an aluminum alloy, a silver-based metal such as silver (Ag) or a silver alloy, a copper-based metal such as copper (Cu) or a copper alloy, a molybdenum-based metal such as molybdenum (Mo) or a molybdenum alloy, chromium (Cr), tantalum (Ta), neodymium (Nd), and titanium (Ti). Specifically, the first upper gate electrode 151, the second upper gate electrode 152, the first lower gate electrode 153, and the second lower gate electrode 154 may have a multilayer structure including at least two conductive films with different physical properties.

[0142] According to an embodiment of the present invention, the first source electrode 161 a and the second source electrode 162 a may each include at least one of an aluminum-based metal such as aluminum (Al) or an aluminum alloy, a silver-based metal such as silver (Ag) or a silver alloy, a copper-based metal such as copper (Cu) or a copper alloy, a molybdenum-based metal such as molybdenum (Mo) or a molybdenum alloy, chromium (Cr), tantalum (Ta), neodymium (Nd), and titanium (Ti). Specifically, the first source electrode 161 a and the second source electrode 162 a may have a multilayer structure including at least two conductive films with different physical properties.

[0143] According to one embodiment of the present invention, the first upper drain electrode 171 is made of the same material as the first upper gate electrode 151 and the second upper gate electrode 152. Also, the first lower drain electrode 172 is made of the same material as the first lower gate electrode 153 and the second lower gate electrode 154.

[0144] According to one embodiment of the present invention, when the first upper thin film transistor 11 and the second upper thin film transistor 12 are connected in parallel to a common first upper drain electrode 171, and the first lower thin film transistor 21 and the second lower thin film transistor 22 are connected in parallel to a common first lower drain electrode 172, the current path can be distributed to the first sub-active layer (i.e., the first upper active layer 131a and the first lower active layer 231a) and the second sub-active layer (i.e., the second upper active layer 131b and the second lower active layer 231b).

[0145] Specifically, by arranging the first upper gate electrode 151 and the second upper gate electrode 152 at the upper end and the first lower gate electrode 153 and the second lower gate electrode 154 at the lower end, the current path can be distributed to the first sub-active layer 131a, 231a and the second sub-active layer 131b, 231b.

[0146] This reduces the amount of current flowing through one current path by designing the channel width smaller than the standard, thereby reducing the amount of heat generated in the thin film transistor unit, thereby reducing the risk of heat generation in the thin film transistor unit.

[0147] Generally, if the channel width is reduced to reduce the amount of heat generated in the thin film transistor unit, the amount of heat generated can be reduced, but the total amount of current can also be reduced.

[0148] However, in the thin film transistor unit 100 according to one embodiment of the present invention, instead of reducing the channel width, the current path is distributed to the first sub-active layer 131a, 231a and the second sub-active layer 131b, 231b, thereby maintaining the total amount of current.

[0149] Furthermore, by arranging the gate electrodes in parallel at the upper and lower ends, it is possible to reduce the channel width while maintaining the channel length, thereby ensuring a process margin.

[0150] Fig. 4 is a plan view of a thin film transistor unit 200 according to another embodiment of the present invention. Fig. 5 is a cross-sectional view taken along line III-III' in Fig. 4. Fig. 6 is a cross-sectional view taken along line IV-IV' in Fig. 4.

[0151] According to an embodiment of the present invention, the thin film transistor unit 200 may further include a third upper thin film transistor 13, a fourth upper thin film transistor 14, a third lower thin film transistor 23, and a fourth lower thin film transistor 24. Specifically, the thin film transistor unit 200 according to FIG.

[0152] Referring to FIG. 4, the first upper thin film transistor 11 and the third upper thin film transistor 13 are arranged along the second direction (Y), the second upper thin film transistor 12 and the fourth upper thin film transistor 14 are arranged along the second direction (Y), the first lower thin film transistor 21 and the third lower thin film transistor 23 are arranged along the second direction (Y), and the second lower thin film transistor 22 and the fourth lower thin film transistor 24 are arranged along the second direction (Y).

[0153] Specifically, referring to FIG. 4, in a plan view, the third upper thin film transistor 13, the fourth upper thin film transistor 14, the third lower thin film transistor 23, and the fourth lower thin film transistor 24 are arranged in different rows from the first upper thin film transistor 11, the second upper thin film transistor 12, the first lower thin film transistor 21, and the second lower thin film transistor 22.

[0154] According to one embodiment of the present invention, the third upper thin film transistor 13 includes a third upper active layer 132a and a third upper gate electrode 155 disposed on the third upper active layer 132a, and the fourth upper thin film transistor 14 includes a fourth upper active layer 132b and a fourth upper gate electrode 156 disposed on the fourth upper active layer 132b.

[0155] According to an embodiment of the present invention, the third top gate electrode 155 and the fourth top gate electrode 156 are spaced apart from each other by the second top drain electrode 173. Specifically, the third top gate electrode 155 and the fourth top gate electrode 156 are electrically connected to each other with the second top drain electrode 173 interposed therebetween. Specifically, the third top gate electrode 155 and the fourth top gate electrode 156 may be formed integrally with the second top drain electrode 173.

[0156] The first upper thin film transistor 11, the second upper thin film transistor 12, the first lower thin film transistor 21, and the second lower thin film transistor 22 shown in FIG. 4 overlap with the first upper thin film transistor 11, the second upper thin film transistor 12, the first lower thin film transistor 21, and the second lower thin film transistor 22 shown in FIG. 1.

[0157] The description of the configurations of the third upper thin film transistor 13 and the fourth upper thin film transistor 14 shown in FIG. 5 overlaps with the description of the configurations of the first upper thin film transistor 11 and the second upper thin film transistor 12 shown in FIG.

[0158] According to one embodiment of the present invention, the third lower thin film transistor 23 includes a third lower gate electrode 157 and a third lower active layer 232a disposed on the third lower gate electrode 157, and the fourth upper thin film transistor 14 includes a fourth lower gate electrode 158 and a fourth lower active layer 232b disposed on the fourth lower gate electrode 158.

[0159] According to an embodiment of the present invention, the third bottom gate electrode 157 and the fourth bottom gate electrode 158 are spaced apart by the second bottom drain electrode 174. Specifically, the third bottom gate electrode 157 and the fourth bottom gate electrode 158 are electrically connected to each other with the second bottom drain electrode 174 interposed therebetween. Specifically, the third bottom gate electrode 157 and the fourth bottom gate electrode 158 may be formed integrally with the second bottom drain electrode 174.

[0160] The description of the configurations of the third lower thin film transistor 23 and the fourth lower thin film transistor 24 shown in FIG. 5 overlaps with the description of the configurations of the first lower thin film transistor 21 and the second lower thin film transistor 22 shown in FIG.

[0161] The descriptions of the fifth gate insulating film 142a, the sixth gate insulating film 142b, the seventh gate insulating film 142c, and the eighth gate insulating film 142d shown in FIG. 5 overlap with the descriptions of the first gate insulating film 141a, the second gate insulating film 141b, the third gate insulating film 141c, and the fourth gate insulating film 141d shown in FIG. 2.

[0162] 5 are separated from each other by a fourth contact hole (CNT4). The description of the fourth contact hole (CNT4) overlaps with the description of the second contact hole (CNT2) shown in FIG. 2, and therefore will be omitted.

[0163] 5 are separated from each other by a fifth contact hole (CNT5). The description of the fifth contact hole (CNT5) overlaps with the description of the third contact hole (CNT3) shown in FIG. 2, and will be omitted.

[0164] Referring to Figure 4, in a plan view, the first contact hole (CNT1), the second contact hole (CNT2), the third contact hole (CNT3), the fourth contact hole (CNT4), and the fifth contact hole (CNT5) are arranged along the second direction (Y).

[0165] 4 and 5, the first source electrode 161b is disposed apart from the first upper drain electrode 171 with the first upper active layer 131a of the first upper thin film transistor 11 therebetween, the first lower drain electrode 172 with the first lower active layer 231a of the first lower thin film transistor 21 therebetween, the second upper drain electrode 173 with the third upper active layer 132a of the third upper thin film transistor 13 therebetween, and the second lower drain electrode 174 with the third lower active layer 232a of the third lower thin film transistor 23 therebetween.

[0166] Specifically, the first source electrode 161b is electrically connected to the first upper drain electrode 171 via the first upper active layer 131a and the first connecting part 131c, the first source electrode 161b is electrically connected to the first lower drain electrode 172 via the first lower active layer 231a and the second connecting part 231c, the first source electrode 161b is electrically connected to the second upper drain electrode 173 via the third upper active layer 132a and the third connecting part 132c, and the first source electrode 161b is electrically connected to the third lower active layer 232a and the fourth connecting part 232c.

[0167] According to one embodiment of the present invention, the third upper active layer 132a of the third upper thin film transistor 13, the fourth upper active layer 132b of the fourth upper thin film transistor 14, and the third connecting portion 132c may be collectively referred to as the third active layer 132.

[0168] According to one embodiment of the present invention, the third lower active layer 232a of the third lower thin film transistor 23, the fourth lower active layer 232b of the fourth lower thin film transistor 24, and the fourth connecting part 232c may be collectively referred to as the fourth active layer 232.

[0169] 4 and 5, the second source electrode 162b is disposed apart from the first upper drain electrode 171 with the second upper active layer 131b of the second upper thin film transistor 12 interposed therebetween, the second source electrode 162b is disposed apart from the first lower drain electrode 172 with the second lower active layer 231b of the second lower thin film transistor 22 interposed therebetween, the second upper drain electrode 173 with the fourth upper active layer 132b of the fourth upper thin film transistor 14 interposed therebetween, and the second lower drain electrode 174 with the fourth lower active layer 232b of the fourth lower thin film transistor 24 interposed therebetween.

[0170] Specifically, the second source electrode 162b is electrically connected to the first upper drain electrode 171 via the second upper active layer 131b and the first connector 131c, and the second source electrode 162b is electrically connected to the first lower drain electrode 172 via the second lower active layer 231b and the second connector 231c. In addition, the second source electrode 162b is electrically connected to the second upper drain electrode 173 via the fourth upper active layer 132b and the third connector 132c, and the second source electrode 162b is electrically connected to the second lower drain electrode 174 via the fourth lower active layer 232b and the fourth connector 232c.

[0171] According to one embodiment of the present invention, the first upper drain electrode 171 and the second upper drain electrode 173 are spaced apart by an upper bridge electrode 170a. The first lower drain electrode 172 and the second lower drain electrode 174 are spaced apart by a lower bridge electrode 170b. Specifically, the first upper drain electrode 171 and the second upper drain electrode 173 are electrically connected with the upper bridge electrode 170a interposed therebetween, and the first lower drain electrode 172 and the second lower drain electrode 174 are electrically connected with the lower bridge electrode 170b interposed therebetween.

[0172] 4 and 6, the first upper drain electrode 171 and the second upper drain electrode 173 are integrally formed with the upper bridge electrode 170a. Specifically, the first upper drain electrode 171 and the second upper drain electrode 173 may be formed using the same material and process as the upper bridge electrode 170a.

[0173] In addition, the first lower drain electrode 172 and the second lower drain electrode 174 are integrally formed with the lower bridge electrode 170b. Specifically, the first lower drain electrode 172 and the second lower drain electrode 174 may be formed using the same material and process as the lower bridge electrode 170b.

[0174] According to one embodiment of the present invention, the upper bridge electrode 170a and the lower bridge electrode 170b are arranged to overlap each other in a plan view.

[0175] Referring to FIGS. 4 and 6, the first upper drain electrode 171 and the second upper drain electrode 173 may be electrically connected to the first lower drain electrode 172 and the second lower drain electrode 174 through the first contact holes CNT1.

[0176] 1 to 3, the thin film transistor unit 200 shown in FIGS. 4 to 6 also has a first upper thin film transistor 11 and a second upper thin film transistor 12 connected in parallel to a common first upper drain electrode 171, a third upper thin film transistor 13 and a fourth upper thin film transistor 14 connected in parallel to a common second upper drain electrode 173, a first lower thin film transistor 21 and a second lower thin film transistor 22 connected in parallel to a common first lower drain electrode 172, and a third lower thin film transistor 23 connected in parallel to a common first lower drain electrode 173. When the thin film transistor 23 and the fourth lower thin film transistor 24 are connected in parallel and commonly to the second lower drain electrode 174, the current path can be distributed to the first sub-active layer (i.e., the first upper active layer 131a, the third upper active layer 132a, the first lower active layer 231a, and the third lower active layer 232a) and the second sub-active layer (i.e., the second upper active layer 131b, the fourth upper active layer 132b, the second lower active layer 231b, and the fourth lower active layer 232b).

[0177] 7A to 7I are process diagrams showing a manufacturing process of the thin film transistor unit 100 according to one embodiment of the present invention.

[0178] The cross-sectional views of the thin film transistor unit 100 shown in FIGS. 7A to 7I correspond to the cross-sectional view of the thin film transistor unit 100 shown in FIG.

[0179] 7A, after the base substrate 110 and the second buffer layer 122 are formed in order, a lower metal layer (BM) may be formed on the second buffer layer 122 and then patterned. The lower metal layer (BM) may correspond to the first lower gate electrode 153, the second lower gate electrode 154, and the first lower drain electrode 172.

[0180] According to one embodiment of the present invention, the bottom metal layer (BM) may include at least one of an aluminum-based metal such as aluminum (Al) or an aluminum alloy, a silver-based metal such as silver (Ag) or a silver alloy, a copper-based metal such as copper (Cu) or a copper alloy, a molybdenum-based metal such as molybdenum (Mo) or a molybdenum alloy, chromium (Cr), tantalum (Ta), neodymium (Nd), and titanium (Ti).

[0181] Referring to FIG. 7B, a first gate insulating material layer 141m may be formed on the lower metal layer (BM) and the second buffer layer 122.

[0182] According to an embodiment of the present invention, the first gate insulating material layer 141m may include at least one of silicon oxide, silicon nitride, and metal-based oxide.

[0183] Referring to FIG. 7C, the first gate insulating material layer 141m may be patterned to form a third contact hole CNT3 exposing the lower metal layer BM.

[0184] The third contact hole (CNT3) shown in FIG. 7C corresponds to the third contact hole (CNT3) shown in FIG.

[0185] Specifically, the first gate insulating material layer 141m may be patterned to form a third gate insulating layer 141c and a fourth gate insulating layer 141d. The third gate insulating layer 141c and the fourth gate insulating layer 141d are spaced apart by a third contact hole CNT3.

[0186] Referring to FIG. 7D, a second active layer 231 may be formed on the bottom metal layer (BM), the third gate insulating layer 141c, and the fourth gate insulating layer 141d.

[0187] Referring to FIG. 7D, the second active layer 231 is formed by patterning.

[0188] Referring to FIG. 7E, a first buffer layer 121 may be formed on the third gate insulating layer 141c, the fourth gate insulating layer 141d, and the second active layer 231.

[0189] According to an embodiment of the present invention, the first buffer layer 121 is disposed on the entire upper surface of the third gate insulating film 141c, the fourth gate insulating film 141d, and the second active layer 231.

[0190] 7F, a first active layer 131 may be formed on the first buffer layer 121. The first active layer 131 may be formed by patterning.

[0191] Referring to FIG. 7G, the first buffer layer 121 may be patterned to form holes.

[0192] Referring to FIG. 7G, by patterning the first buffer layer 121, a portion of the second active layer 231 and a portion of the third gate insulating film 141c and the fourth gate insulating film 141d can be exposed.

[0193] 7H, a first gate insulating layer 141a and a second gate insulating layer 141b may be formed on the first active layer 131. The first gate insulating layer 141a and the second gate insulating layer 141b may be formed by patterning and may be spaced apart by a second contact hole (CNT2).

[0194] 7I, a first upper gate electrode 151, a second upper gate electrode 152, and a first upper drain electrode 171 may be formed on the first gate insulating layer 141a and the second gate insulating layer 141b. Also, a first source electrode 161a and a second source electrode 162a may be formed in holes formed by patterning the first buffer layer 121.

[0195] FIG. 8 is a schematic diagram of a display device 1000 according to yet another embodiment of the present invention.

[0196] A display device 1000 according to another embodiment of the present invention may include a display panel 310, a gate driver 320, a data driver 330, and a controller 340, as shown in FIG.

[0197] The display panel 310 includes gate lines (GL) and data lines (DL), and pixels (P) are arranged at the intersections of the gate lines (GL) and the data lines (DL). Images are displayed by driving the pixels (P). The gate lines (GL), data lines (DL), and pixels (P) may be arranged on a base substrate 110.

[0198] The control unit 340 controls the gate driver 320 and the data driver 330 .

[0199] The control unit 340 uses a signal supplied from an external system (not shown) to output a gate control signal (GCS) for controlling the gate driver 320 and a data control signal (DCS) for controlling the data driver 330. The control unit 340 also samples input image data received from the external system, realigns the sampled data, and supplies the realigned digital image data (RGB) to the data driver 330.

[0200] The gate control signal (GCS) includes a gate start pulse (GSP), a gate shift clock (GSC), a gate output enable signal (GOE), a start signal (Vst), and a gate clock (GCLK), etc. Furthermore, the gate control signal (GCS) may include a control signal for controlling a shift register, etc.

[0201] The data control signal (DCS) includes a source start pulse (SSP), a source shift clock signal (SSC), a source output enable signal (SOE), a polarity control signal (POL), and the like.

[0202] The data driver 330 supplies data voltages to the data lines (DL) of the display panel 310. Specifically, the data driver 330 converts the video data (RGB) input from the control unit 340 into analog data voltages, and supplies the data voltages to the data lines (DL).

[0203] According to one embodiment of the present invention, the gate driver 320 may be mounted on the display panel 310. Such a structure in which the gate driver 320 is directly mounted on the display panel 310 is called a Gate In Panel (GIP) structure. Specifically, in the Gate In Panel (GIP) structure, the gate driver 320 may be disposed on the base substrate 110.

[0204] A display device 1000 according to an embodiment of the present invention may include the above-described thin film transistor units 100 and 200. According to an embodiment of the present invention, a gate driver 320 may include the above-described thin film transistor units 100 and 200.

[0205] The gate driver 320 may include a shift register 350 .

[0206] The shift register 350 sequentially supplies gate pulses to the gate lines GL for one frame using a start signal and a gate clock transmitted from the control unit 340. Here, one frame refers to a period during which one image is output through the display panel 310. The gate pulse has a turn-on voltage that can turn on a switching element (thin film transistor) disposed in the pixel P.

[0207] In addition, the shift register 350 supplies a gate-off signal to the gate line (GL) during the remaining period in one frame when no gate pulse is supplied, which can turn off the switching element. Hereinafter, the gate pulse and the gate-off signal are collectively referred to as a scan signal (SS or Scan).

[0208] The shift register 350 may include the thin film transistor units 100 and 200 described above.

[0209] FIG. 9 is a schematic diagram of a shift register 350.

[0210] Referring to FIG. 9, the shift register 350 can include g stages 351 (ST1 to STg).

[0211] The shift register 350 transmits one scan signal (SS) to a pixel (P) connected to one gate line (GL) via one gate line (GL). Each stage 351 can be connected to one gate line (GL). If g gate lines (GL) are formed on the display panel 310, the shift register 350 can include g stages 351 (ST1 to STg) and generate g scan signals (SS1 to SSg).

[0212] Generally, each stage 351 outputs a gate pulse (GP) once during one frame, and the gate pulse (GP) is output sequentially from each stage 351.

[0213] FIG. 10 is a circuit diagram of one embodiment of a stage 351 included in the shift register 350 of FIG.

[0214] Referring to FIG. 10, a stage (ST) according to an embodiment of the present invention includes an M_o node, a Q_o node, a Q_e node, a Qb_o node, a Qb_e node, and a Qh_o node.

[0215] Referring to FIG. 10, the stage (ST) includes a first sensing control block (BK1a), a second sensing control block (BK1b), an input block (BK2), an inverter block (BK3), and an output block (BK4).

[0216] The first sensing control block (BK1a) applies a carry signal (C(n-2)) to the node (M_o) according to the line sampling signals (LSP1, LSP2) to activate the potential of the node (M_o) to the high potential power supply voltage (GVDD), and activates the potential of the node (Q_o) to the high potential power supply voltage (GVDD) according to the activation potential of the node (M_o) and the global reset signal (RESET).

[0217] For this purpose, the first sensing control block BK1a includes a plurality of transistors Ta, Tb, Tc, T1b, and T1c and a capacitor Cst1.

[0218] The transistor (Ta) includes a gate electrode to which the line sampling signals (LSP1, LSP2) are applied, a drain electrode to which the carry signal (C(n-2)) is applied, and a source electrode connected to the node (N1). The transistor (Tb) includes a gate electrode to which the line sampling signals (LSP1, LSP2) are applied, a drain electrode connected to the node (N1), and a source electrode connected to the node (M_o). The transistor (Tc) includes a gate electrode connected to the node (N2), a drain electrode to which the high potential power supply voltage (GVDD) is applied, and a source electrode connected to the node (N1). The transistor (T1b) includes a gate electrode connected to the node (N2), a drain electrode to which the high potential power supply voltage (GVDD) is applied, and a source electrode connected to the drain electrode of the transistor (T1c). The capacitor (Cst1) is connected between the input terminal of the high potential power supply voltage (GVDD) and the node (N2) and maintains the activation potential of the node (M_o). The transistor (T1c) includes a gate electrode to which a global reset signal (RESET) is applied, a drain electrode connected to the source electrode of the transistor (T1b), and a source electrode connected to the node (Q_o).

[0219] The second sensing control block (BK1b) inactivates the potential of the node (Qb_o) to the low potential power supply voltage (GVSS2) according to the global reset signal (RESET) and the potential of the node (M).

[0220] To this end, the second sensing control block (BK1b) includes a plurality of transistors (T5a, T5b, T5c, T5d, and T5e). The transistor (T5a) has a gate electrode to which a global reset signal (RESET) is applied, a drain electrode connected to a node (Qb_o), and a source electrode connected to a node (N3). The transistor (T5b) has a gate electrode connected to a node (M), a drain electrode connected to the node (N3), and a source electrode to which a low-potential power supply voltage (GVSS2) is applied. The transistor (T5c) has a gate electrode to which a second global reset signal (RESET2) is applied, a drain electrode connected to a node (Q_o), and a source electrode connected to the drain electrode of the transistor (T5d). The transistor (T5d) has a gate electrode to which a second global reset signal (RESET2) is applied, a drain electrode connected to the source electrode of the transistor (T5c), and a source electrode connected to a node (Qh_o). The transistor (T5e) includes a gate electrode to which the second global reset signal (RESET2) is applied, a drain electrode connected to the node (Qh_o), and a source electrode connected to the node (N3).

[0221] The input block (BK2) applies a carry signal (C(n-3)) to the node (Q_o) to activate the potential of the node (Qh_o) to the high-potential power supply voltage (GVDD). The second sensing control block (BK1b) deactivates the potential of the node (Q_o) to the low-potential power supply voltage (GVSS2) according to the carry signal (C(n+3)). The second sensing control block (BK1b) deactivates the potential of the node (Q_o) to the low-potential power supply voltage (GVSS2) according to the potential of the node (Qb_o or Qb_e). The second sensing control block (BK1b) deactivates the potential of the node (Q_o) to the low-potential power supply voltage (GVSS2) according to the global start pulse (Vsp).

[0222] To this end, the input block (BK2) includes a plurality of transistors (T1, T1a, T3q, T3q', T3n, T3na, T3, T3a, T31a, T31b, T3nb, T3nc). The transistor (T1) includes a gate electrode to which a carry signal (C(n-3)) is applied, a drain electrode, and a source electrode connected to a node (Qh_o). The transistor (T1a) includes a gate electrode to which a carry signal (C(n-3)) is applied, a drain electrode connected to a node (Qh_o), and a source electrode connected to a node (Q_o). The transistor (T3q) includes a gate electrode connected to a node (Q_o), a drain electrode to which a high-potential power supply voltage (GVDD) is applied, and a source electrode connected to the drain electrode of the transistor (T3q'). The transistor (T3q') has a gate electrode connected to the node (Q_o), a drain electrode connected to the source electrode of the transistor (T3q), and a source electrode connected to the node (Qh_o). The transistor (T3n) has a gate electrode to which the carry signal (C(n+3)) is applied, a drain electrode connected to the node (Q_o), and a source electrode connected to the node (Qh_o). The transistor (T3na) has a gate electrode to which the carry signal (C(n+3)) is applied, a drain electrode connected to the node (Qh_o), and a source electrode to which the low-potential power supply voltage (GVSS2) is applied. The transistor (T3) has a gate electrode connected to the node (Qb_o), a drain electrode connected to the node (Q_o), and a source electrode connected to the node (Qh_o). The transistor (T3a) has a gate electrode connected to the node (Qb_o), a drain electrode connected to the node (Qh_o), and a source electrode to which the low-potential power supply voltage (GVSS2) is applied. The transistor (T31a) includes a gate electrode connected to the node (Qb_e), a drain electrode connected to the node (Q_o), and a source electrode connected to the node (Qh_o). The transistor (T31b) includes a gate electrode connected to the node (Qb_e), a drain electrode connected to the node (Qh_o), and a source electrode to which the low-potential power supply voltage (GVSS2) is applied.The transistor (T3nb) includes a gate electrode to which a global start pulse (Vsp) is applied, a drain electrode connected to the node (Q_o), and a source electrode connected to the node (Qh_o). The transistor (T3nc) includes a gate electrode to which a global start pulse (Vsp) is applied, a drain electrode connected to the node (Qh_o), and a source electrode connected to the low potential power supply voltage (GVSS2).

[0223] The inverter block (BK3) deactivates the potential of the node (Qb_o) to the low potential power supply voltage (GVSS2) using the carry signal (C(n-3)). The inverter block (BK3) deactivates the potential of the node (Qb_o) to the low potential power supply voltage (GVSS2) using the active potential of the node (Q_o). The inverter block (BK3) applies the power supply voltage (GVDD_o) to the node (N4) to activate the potential of the node (Qb_o) to the power supply voltage (GVDD_o). The inverter block (BK3) deactivates the potential of the node (N4) to the low potential power supply voltage (GVSS2) using the active potential of the node (Q_e).

[0224] To this end, the inverter block (BK3) includes a plurality of transistors (T4, T41, T4q, T4q', T5, T5q). The transistor (T4) includes a gate electrode connected to the node (N4), a drain electrode to which the power supply voltage (GVDD_o) is applied, and a source electrode connected to the node (Qb_o). The transistor (T41) includes a gate electrode to which the power supply voltage (GVDD_o) is applied, a drain electrode, and a source electrode connected to the node (N4). The transistor (T4q) includes a gate electrode connected to the node (Q_o), a drain electrode connected to the node (N4), and a source electrode connected to the low-potential power supply voltage (GVSS1). The transistor (T4q') includes a gate electrode connected to the node (Q_e), a drain electrode connected to the node (N4), and a source electrode to which the low-potential power supply voltage (GVSS1) is applied. The transistor (T5) includes a gate electrode to which the carry signal (C(n-3)) is applied, a drain electrode connected to the node (Qb_o), and a source electrode to which the low potential power supply voltage (GVSS2) is applied. The transistor (T5q) includes a gate electrode connected to the node (Q_o), a drain electrode connected to the node (Qb_o), and a source electrode to which the low potential power supply voltage (GVSS2) is applied.

[0225] According to an embodiment of the present invention, the transistor T41 may include thin film transistor units 100 and 200 according to an embodiment of the present invention.

[0226] The output block (BK4) outputs the carry shift clock (CRCLK(n)) as a carry signal (C(n)) when the potential of the node (Q_o) is boosted from the voltage level (L2) to the voltage level (L3), and outputs the low potential power supply voltage (GVSS2) as a carry signal (C(n)) when the potential of the node (Qb_o) is activated to the voltage level (L2) or when the potential of the node (Qb_e) is activated to the voltage level (L2). The output block (BK4) outputs the scan shift clock (SCCLK(n)) as a gate pulse (SCOUT(n)) for image display when the potential of the node (Q_o) is boosted from level (L2) to level (L3), and outputs the low potential power supply voltage (GVSSO) as a gate pulse (SCOUT(n)) for image display when the potential of the node (Qb_o) is activated to voltage level (L2) or the potential of the node (Qb_e) is activated to voltage level (L2). The output block (BK4) outputs the sense shift clock (SECLK(n)) as a sense signal (SEOUT(n)) when the potential of the node (Q_o) is boosted from level (L2) to level (L3), and outputs the low potential power supply voltage (GVSSO) as a sense signal (SECOUT(n)) when the potential of the node (Qb_o) is activated to voltage level (L2) or the potential of the node (Qb_e) is activated to voltage level (L2).

[0227] To this end, the output block (BK4) includes a plurality of pull-up transistors (T6a, T6b, T6c), a plurality of pull-down transistors (T7a, T7a', T7b, T7b', T7c, T7c'), and a plurality of capacitors (Cap_CR, Cap_SC, Cap_SE). The pull-up transistor (T6a) has a gate electrode connected to the node (Q_o), a drain electrode to which the carry shift clock (CRCLK(n)) is applied, and a source electrode connected to the node (N5). The capacitor (Cap_CR) is connected between the node (Q_o) and the node (N5). The pull-up transistor (T6b) has a gate electrode connected to the node (Q_o), a drain electrode to which the scan shift clock (SCCLK(n)) is applied, and a source electrode connected to the node (N6). The capacitor (Cap_SC) is connected between the node (Q_o) and the node (N6). The pull-up transistor (T6c) has a gate electrode connected to the node (Q_o), a drain electrode to which the sense shift clock (SECLK(n)) is applied, and a source electrode connected to the node (N7). The capacitor (Cap_SE) is connected between the node (Q_o) and the node (N7). The pull-down transistor (T7a) has a gate electrode connected to the node (Qb_o), a drain electrode connected to the node (N5), and a source electrode connected to the low-potential power supply voltage (GVSS2). The pull-down transistor (T7a') has a gate electrode connected to the node (Qb_e), a drain electrode connected to the node (N5), and a source electrode connected to the low-potential power supply voltage (GVSS2). The pull-down transistor (T7b) has a gate electrode connected to the node (Qb_o), a drain electrode connected to the node (N6), and a source electrode connected to the low-potential power supply voltage (GVSS0). The pull-down transistor (T7b') has a gate electrode connected to the node (Qb_e), a drain electrode connected to the node (N6), and a source electrode connected to the low potential power supply voltage (GVSS0). The pull-down transistor (T7c) has a gate electrode connected to the node (Qb_o), a drain electrode connected to the node (N7), and a source electrode connected to the low potential power supply voltage (GVSS0).The pull-down transistor (T7c') has a gate electrode connected to the node (Qb_e), a drain electrode connected to the node (N7), and a source electrode connected to the low potential power supply voltage (GVSS0).

[0228] 11 is a circuit diagram of a thin film transistor unit 200 according to an embodiment of the present invention. Specifically, FIG. 11 may be a diagram illustrating the state of region A shown in FIG.

[0229] FIG. 11 shows eight transistors (T41a, T41b, T41c, T41d, T41e, T41f, T41g, and T41h) arranged in parallel.

[0230] The eight transistors (T41a, T41b, T41c, T41d, T41e, T41f, T41g, T41h) each include a gate electrode (Ga, Gb, Gc, Gd, Ge, Gf, Gg, Gh), a source electrode (Sa, Sb, Sc, Sd, Se, Sf, Sg, Sh), and a drain electrode (Da, Db, Dc, Dd, De, Df, Dg, Dh).

[0231] In one embodiment of the present invention, the thin film transistor unit may include 4 thin film transistors, 12 thin film transistors, or more specifically, 4N thin film transistors.

[0232] According to FIG. 11, the gate electrodes (Ga, Gb, Gc, Gd, Ge, Gf, Gg, Gh) and the drain electrodes (Da, Db, Dc, Dd, De, Df, Dg, Dh) are connected to each other and a high potential power supply voltage (GVDD_o) is applied.

[0233] According to one embodiment of the present invention, eight transistors (T41a, T41b, T41c, T41d, T41e, T41f, T41g, and T41h) shown in FIG. 11 may correspond to the first upper thin film transistor 11, the second upper thin film transistor 12, the third upper thin film transistor 13, the fourth upper thin film transistor 14, the first lower thin film transistor 21, the second lower thin film transistor 22, the third lower thin film transistor 23, and the fourth lower thin film transistor 24 shown in FIGS. 4 to 6.

[0234] The present invention described above is not limited to the above-mentioned embodiments and the accompanying drawings, and various substitutions, modifications, and alterations are possible within the scope of the technical subject matter of the present invention, as will be apparent to those skilled in the art to which the present invention pertains. Therefore, the scope of the present invention is defined by the following claims, and all modifications and alterations derived from the meaning and scope of the claims and their equivalents should be construed as being included in the scope of the present invention. [Explanation of symbols]

[0235] 11, 12, 13, 14: 1st, 2nd, 3rd, 4th upper thin film transistors 21, 22, 23, 24: 1st, 2nd, 3rd, 4th lower thin film transistors 110: Base board 121, 122: First and second buffer layers 131, 231, 132, 232: 1st, 2nd, 3rd, 4th active layers 131a, 131b, 132a, 132b: 1st, 2nd, 3rd, 4th upper active layers 231a, 231b, 232a, 232b: 1st, 2nd, 3rd, 4th lower active layers 131c, 231c, 132c, 232c: 1st, 2nd, 3rd, 4th connection part 141a, 141b, 141c, 141d: first, second, third, fourth gate insulating films 142a, 142b, 142c, 142d: 5th, 6th, 7th, 8th gate insulating films 151, 152, 155, 156: first, second, third, fourth upper gate electrodes 152, 153, 157, 158: 1st, 2nd, 3rd, 4th lower gate electrodes 161a, 161b: first source electrode 162a, 162b: second source electrodes 171, 173: First and second upper drain electrodes 172, 174: First and second lower drain electrodes CNT1, CNT2, CNT3, CNT4, CNT5: 1st, 2nd, 3rd, 4th, 5th contact holes

Claims

1. Base substrate, a first lower thin film transistor and a second lower thin film transistor disposed on the base substrate and connected in parallel to each other; and a first upper thin film transistor and a second upper thin film transistor disposed on the first lower thin film transistor and the second lower thin film transistor and connected in parallel to each other; the first upper thin film transistor includes a first upper active layer and a first upper gate electrode disposed on the first upper active layer; the second upper thin film transistor includes a second upper active layer and a second upper gate electrode disposed on the second upper active layer; the first upper gate electrode and the second upper gate electrode are electrically connected with a first upper drain electrode therebetween; the first lower thin film transistor includes a first lower gate electrode and a first lower active layer disposed on the first lower gate electrode; the second lower thin film transistor includes a second lower gate electrode and a second lower active layer disposed on the second lower gate electrode; The first lower gate electrode and the second lower gate electrode are electrically connected with a first lower drain electrode interposed therebetween, in the thin film transistor unit.

2. the first upper gate electrode, the second upper gate electrode, and the first upper drain electrode are integrally formed; The thin film transistor unit of claim 1 , wherein the first lower gate electrode, the second lower gate electrode, and the first lower drain electrode are integrally formed.

3. the first upper active layer of the first upper thin film transistor and the second upper active layer of the second upper thin film transistor are spaced apart with a first connection therebetween; The thin film transistor unit of claim 1 , wherein the first lower active layer of the first lower thin film transistor and the second lower active layer of the second lower thin film transistor are spaced apart with a second connection therebetween.

4. the first upper active layer of the first upper thin film transistor and the second upper active layer of the second upper thin film transistor are integrally formed with the first connection part; The thin film transistor unit of claim 3 , wherein the first lower active layer of the first lower thin film transistor and the second lower active layer of the second lower thin film transistor are integrally formed with the second connection part.

5. The thin film transistor unit according to claim 1 , wherein, in a plan view, the first upper gate electrode overlaps the first lower gate electrode, and the second upper gate electrode overlaps the second lower gate electrode.

6. 2. The thin film transistor unit according to claim 1, wherein, in a plan view, the first upper active layer of the first upper thin film transistor overlaps with the first lower active layer of the first lower thin film transistor, and the second upper active layer of the second upper thin film transistor overlaps with the second lower active layer of the second lower thin film transistor.

7. the first connection part contacts the first upper drain electrode; The thin film transistor unit of claim 3 , wherein the second connection part contacts the first lower drain electrode.

8. 2. The thin film transistor unit of claim 1, further comprising a first buffer layer disposed between the first lower thin film transistor and the first upper thin film transistor and between the second lower thin film transistor and the second upper thin film transistor.

9. the first upper active layer of the first upper thin film transistor is disposed between the first buffer layer and the first upper gate electrode; The thin film transistor unit of claim 8 , wherein the second upper active layer of the second upper thin film transistor is disposed between the first buffer layer and the second upper gate electrode.

10. the first lower active layer of the first lower thin film transistor is disposed between the first buffer layer and the first lower gate electrode; The thin film transistor unit of claim 8 , wherein the second lower active layer of the second lower thin film transistor is disposed between the first buffer layer and the second lower gate electrode.

11. further comprising a second buffer layer disposed between the base substrate and the first buffer layer; The first buffer layer is formed by patterning, The thin film transistor unit according to claim 8 , wherein the second buffer layer is disposed on the entire upper surface of the base substrate.

12. a first source electrode and a second source electrode spaced apart from each other; the first source electrode is disposed apart from the first upper drain electrode with the first upper active layer of the first upper thin film transistor interposed therebetween, and is disposed apart from the first lower drain electrode with the first lower active layer of the first lower thin film transistor interposed therebetween; 2. The thin film transistor unit of claim 1, wherein the second source electrode is disposed apart from the first upper drain electrode with the second upper active layer of the second upper thin film transistor interposed therebetween, and the second source electrode is disposed apart from the first lower drain electrode with the second lower active layer of the second lower thin film transistor interposed therebetween.

13. the first source electrode contacts the first upper active layer of the first upper thin film transistor and the first lower active layer of the first lower thin film transistor, respectively; The thin film transistor unit of claim 12 , wherein the second source electrode contacts the second upper active layer of the second upper thin film transistor and the second lower active layer of the second lower thin film transistor, respectively.

14. The thin film transistor unit according to claim 8 , wherein the first upper drain electrode and the first lower drain electrode are connected to each other through a first contact hole formed in the first buffer layer.

15. the first upper thin film transistor further includes a first gate insulating layer disposed between the first upper active layer and the first upper gate electrode of the first upper thin film transistor; the second upper thin film transistor further includes a second gate insulating layer disposed between the second upper active layer and the second upper gate electrode of the second upper thin film transistor; the first gate insulating film and the second gate insulating film are spaced apart with a second contact hole therebetween; the first lower thin film transistor further includes a third gate insulating layer disposed between the first lower active layer and the first lower gate electrode of the first lower thin film transistor; the second lower thin film transistor further includes a fourth gate insulating layer disposed between the second lower active layer and the second lower gate electrode of the second lower thin film transistor; The thin film transistor unit of claim 1 , wherein the third gate insulating film and the fourth gate insulating film are spaced apart with a third contact hole therebetween.

16. The thin film transistor unit of claim 15 , wherein the first upper drain electrode is formed in the second contact hole.

17. The thin film transistor unit according to claim 15 , wherein the second contact hole and the third contact hole are arranged to overlap each other in a plan view.

18. The thin film transistor unit according to claim 1 , wherein, in a plan view, the first lower active layer of the first lower thin film transistor has a larger area than the first upper active layer of the first upper thin film transistor.

19. The thin film transistor unit according to claim 1 , wherein, in a plan view, the second lower active layer of the second lower thin film transistor has a larger area than the second upper active layer of the second upper thin film transistor.

20. the first upper thin film transistor and the second upper thin film transistor are arranged along a first direction; the first lower thin film transistor and the second lower thin film transistor are arranged along the first direction; When a direction intersecting the first direction is defined as a second direction, a third upper thin film transistor disposed in the second direction relative to the first upper thin film transistor, a fourth upper thin film transistor disposed in the second direction relative to the second upper thin film transistor, a third lower thin film transistor disposed in the second direction relative to the first lower thin film transistor, and a fourth lower thin film transistor disposed in the second direction relative to the second lower thin film transistor, The thin film transistor unit of claim 1 , wherein the third upper thin film transistor and the fourth upper thin film transistor are connected in parallel, and the third lower thin film transistor and the fourth lower thin film transistor are connected in parallel.

21. the third upper thin film transistor includes a third upper active layer and a third upper gate electrode disposed on the third upper active layer; the fourth upper thin film transistor includes a fourth upper active layer and a fourth upper gate electrode disposed on the fourth upper active layer; the third upper gate electrode and the fourth upper gate electrode are electrically connected with a second upper drain electrode therebetween; the third lower thin film transistor includes a third lower gate electrode and a third lower active layer disposed on the third lower gate electrode; the fourth lower thin film transistor includes a fourth lower gate electrode and a fourth lower active layer disposed on the fourth lower gate electrode; The thin film transistor unit of claim 20 , wherein the third lower gate electrode and the fourth lower gate electrode are electrically connected with a second lower drain electrode therebetween.

22. the first upper drain electrode and the second upper drain electrode are electrically connected with an upper bridge electrode therebetween; the first lower drain electrode and the second lower drain electrode are electrically connected to each other with a lower bridge electrode interposed therebetween; The thin film transistor unit according to claim 21 , wherein the upper bridge electrode and the lower bridge electrode overlap each other in a plan view.

23. A display device comprising the thin film transistor unit according to any one of claims 1 to 22.

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