Data storage device and method for combining prediction models for read threshold calibration

Abstract

To provide a data storage device comprising a memory and one or more processors for combining prediction models for read threshold calibration, and a method.SOLUTION: The method combines the outputs of the binary tree model and the linear regression model to generate recommended read thresholds. Binary tree models can describe complex output functions, but can be limited to a finite set of output values, whereas linear regression models provide the best results in both worlds because they have continuous-valued outputs.SELECTED DRAWING: Figure 4

Description

[Technical Field]

[0001] One of the main challenges posed by NAND process shrinking and three-dimensional stacking is maintaining process uniformity. In addition, data storage devices may need to support a wide range of operating conditions (such as different program / erase cycles, retention times, and temperatures), which can lead to increased variability between memory dies, blocks, and pages across different operating conditions. Due to these variations, the read threshold (RT) used to read a memory page in some data storage devices is not fixed and can vary significantly as a function of physical location and operating conditions, especially for less mature memory nodes. [Brief explanation of the drawings]

[0002] [Figure 1A] FIG. 2 is a block diagram of a data storage device according to an embodiment. [Figure 1B] FIG. 2 is a block diagram illustrating a storage module of one embodiment. [Figure 1C] FIG. 1 is a block diagram illustrating a hierarchical storage system of one embodiment. [Figure 2A] 1B is a block diagram illustrating components of a controller of the data storage device illustrated in FIG. 1A according to one embodiment. [Figure 2B] 1B is a block diagram illustrating components of the data storage device illustrated in FIG. 1A, according to one embodiment. [Figure 3] FIG. 2 is a block diagram of a host and a data storage device of one embodiment. [Figure 4] 1 is a flowchart of an embodiment method for training a model that combines both a linear regression model and a tree-based model. [Figure 5] 1 is a flowchart of a method of inference using a model provided by one embodiment. [Figure 6] FIG. 1 is an illustrative diagram of machine learning hardware in one embodiment. [Figure 7] FIG. 1 is an illustrative diagram of an implementation of a linear regression model in one embodiment. [Figure 8] 10 is a graph showing results of one embodiment. DETAILED DESCRIPTION OF THE INVENTION

[0003] The following embodiments generally relate to data storage devices and methods for combining predictive models for read threshold calibration. In one embodiment, a data storage device is provided that includes a memory and one or more processors configured to input, individually or in combination, a plurality of previously generated read thresholds into a linear regression model and a binary tree model, input a plurality of features of the memory into the binary tree model, generate a recommended read threshold from the output of the linear regression model and the binary tree model, and read the memory using the recommended read threshold.

[0004] In another embodiment, a method is provided for execution in a data storage device including a memory, the method including: inputting previously generated read thresholds into a linear regression model, the linear regression model configured to output predicted corrections to the previously generated read thresholds; inputting a plurality of features related to the memory into a binary symmetric tree model, the binary symmetric tree model configured to output a plurality of read thresholds; determining a recommended read threshold by combining the previously generated read thresholds output from the linear regression model and the predicted corrections to the plurality of read thresholds output from the binary symmetric tree model; and reading the memory using the recommended read threshold.

[0005] In yet another embodiment, a data storage device is provided comprising: a memory; and means for combining a plurality of different inference models, each inference model configured to use a different subset of memory features, and combining predictions of the plurality of different inference models to generate a final read threshold.

[0006] Other embodiments are possible, and each of the embodiments can be used alone or together in combination. Accordingly, various embodiments will now be described with reference to the accompanying drawings.

[0007] Embodiment The following embodiments relate to data storage devices (DSDs). As used herein, "data storage device" refers to a non-volatile device that stores data. Examples of DSDs include, but are not limited to, hard disk drives (HDDs), solid state drives (SSDs), tape drives, hybrid drives, etc. Details of exemplary DSDs are provided below.

[0008] Examples of data storage devices suitable for use in implementing aspects of these embodiments are shown in FIGS. 1A-1C. Note that these are examples only and other implementations may be used. FIG. 1A is a block diagram illustrating a data storage device 100 according to one embodiment. Referring to FIG. 1A, the data storage device 100 in this example includes a controller 102 coupled to nonvolatile memory, which may be comprised of one or more nonvolatile memory dies 104. As used herein, the term die refers to a collection of nonvolatile memory cells and associated circuitry for managing the physical operation of those nonvolatile memory cells formed on a single semiconductor substrate. The controller 102 interfaces with a host system and sends command sequences for read, program, and erase operations to the nonvolatile memory dies 104. Also, as used herein, the phrases "communicating with" or "coupled with" can mean communicating / coupled directly or communicating / coupled indirectly through one or more components, which may or may not be shown or described herein. The communication / coupling may be wired or wireless.

[0009] The controller 102 (which may be a non-volatile memory controller (e.g., flash, resistive random-access memory (ReRAM), phase-change memory (PCM), or magnetoresistive random-access memory (MRAM) controller)) may include one or more components, individually or in combination, configured to perform certain functions, including but not limited to, those described herein and illustrated in the flowcharts. For example, as shown in FIG. 2A , the controller 102 may include one or more processors 138, individually or in combination, configured to perform functions, including but not limited to, those described herein and illustrated in the flowcharts, by executing computer-readable program code stored in one or more non-transitory memories 139 (e.g., random access memory (RAM) 116 or read-only memory (ROM) 118) internal to the controller 102 and / or external to the controller 102. As another example, one or more components may include circuits such as, but not limited to, logic gates, switches, application specific integrated circuits (ASICs), programmable logic controllers, and embedded microcontrollers.

[0010] In one exemplary embodiment, the non-volatile memory controller 102 is a device that manages data stored in non-volatile memory and communicates with a host, such as a computer or electronic device having any suitable operating system. The non-volatile memory controller 102 can have a variety of functions in addition to the specific functions described herein. For example, the non-volatile memory controller can format the non-volatile memory to ensure that the memory is operating properly, map out bad non-volatile memory cells, and allocate spare cells to replace future failed cells. Some of the spare cells can be used to hold firmware (and / or other metadata used for housekeeping and tracking) to operate the non-volatile memory controller and implement other features. During operation, the host can communicate with the non-volatile memory controller when it needs to read data from or write data to the non-volatile memory. If the host provides a logical address where data is to be read / written, the non-volatile memory controller can translate the logical address received from the host into a physical address within the non-volatile memory. The non-volatile memory controller may also perform various memory management functions such as, but not limited to, wear leveling (distributing writes to avoid wearing out particular blocks of memory that would otherwise be repeatedly written to) and garbage collection (moving only valid pages of data to a new block after a block becomes full so that the full block can be erased and reused).

[0011] The non-volatile memory die 104 may include any suitable non-volatile storage medium, including resistive random access memory (ReRAM), magnetoresistive random access memory (MRAM), phase change memory (PCM), NAND flash memory cells, and / or NOR flash memory cells. The memory cells may take the form of solid-state (e.g., flash) memory cells and may be programmable once, a few times, or many times. The memory cells may also be single-level cells (SLC), multi-level cells (MLC) (e.g., dual-level cells, triple-level cells (TLC), quad-level cells (QLC), etc.), or may use other memory cell level technologies now known or later developed. The memory cells may also be fabricated using two-dimensional or three-dimensional methods.

[0012] The interface between the controller 102 and the non-volatile memory die 104 may be any suitable flash interface, such as toggle mode 200, 400, or 800. In one embodiment, the data storage device 100 may be a card-based system, such as a secure digital (SD) or micro-secure digital (microSD) card. In another embodiment, the data storage device 100 may be part of an embedded data storage device.

[0013] 1A, data storage device 100 (sometimes referred to herein as a storage module) includes a single channel between controller 102 and non-volatile memory die 104, although the subject matter described herein is not limited to having a single memory channel. For example, in some architectures (such as those shown in FIGS. 1B and 1C), two, four, eight, or more memory channels may exist between the controller and the memory device, depending on the capabilities of the controller. In any of the embodiments described herein, even when a single channel is shown in the drawings, there may be two or more channels between the controller and the memory die.

[0014] 1B illustrates a storage module 200 including multiple non-volatile data storage devices 100. Accordingly, the storage module 200 may include a storage controller 202 that interfaces with a host and a data storage device 204 including multiple data storage devices 100. The interface between the storage controller 202 and the data storage device 100 may be a bus interface such as a serial advanced technology attachment (SATA), a peripheral component interconnect express (PCIe) interface, a double-data-rate (DDR) interface, or a serial attached small scale compute interface (SAS / SCSI). The storage module 200, in one embodiment, may be a solid-state drive (SSD) or a non-volatile dual in-line memory module (NVDIMM) such as those found in server PCs or portable computing devices such as laptop and tablet computers.

[0015] FIG. 1C is a block diagram illustrating a hierarchical storage system. The hierarchical storage system 250 includes multiple storage controllers 202, each of which controls a respective data storage device 204. A host system 252 may access memory in the storage system 250 through a bus interface. In one embodiment, the bus interface may be a Non-Volatile Memory Express (NVMe) or Fibre Channel over Ethernet (FCoE) interface. In one embodiment, the system illustrated in FIG. 1C may be a rack-mountable mass storage system accessible by multiple host computers, such as those found in data centers or other locations where mass storage is needed.

[0016] Referring again to FIG. 2A , the controller 102 in this example also includes a front-end module 108 that interfaces with the host, a back-end module 110 that interfaces with one or more non-volatile memory dies 104, and various other components or modules, such as, but not limited to, a buffer manager / bus controller module that manages buffers in RAM 116 and controls internal bus arbitration for the controller 102. The modules may include one or more processors or components, as discussed above. ROM 118 may store system boot code. While illustrated in FIG. 2A as being located separately from the controller 102, in other embodiments, one or both of the RAM 116 and the ROM 118 may be located within the controller 102. In still other embodiments, portions of the RAM 116 and the ROM 118 may be located both within and outside the controller 102.

[0017] The front-end module 108 includes a host interface 120 and a physical layer interface (PHY) 122 that provide an electrical interface with a host or next-level storage controller. The choice of host interface 120 type may depend on the type of memory being used. Examples of host interfaces 120 include, but are not limited to, SATA, SATA Express, serially attached small computer system interface (SAS), Fibre Channel, universal serial bus (USB), PCIe, and NVMe. The host interface 120 typically facilitates the transfer of data, control signals, and timing signals.

[0018] The back-end module 110 includes an error correction code (ECC) engine 124 that encodes data bytes received from the host and decodes and corrects errors in data bytes read from the non-volatile memory. A command sequencer 126 generates command sequences, such as program and erase command sequences, that are sent to the non-volatile memory die 104. A redundant array of independent drives (RAID) module 128 manages the generation of RAID parity and the recovery of failed data. RAID parity can be used as an additional level of integrity protection for data being written to the memory device 104. In some cases, the RAID module 128 can be part of the ECC engine 124. A memory interface 130 provides command sequences to the non-volatile memory die 104 and receives status information from the non-volatile memory die 104. In one embodiment, the memory interface 130 can be a double data rate (DDR) interface, such as a toggle mode 200, 400, or 800 interface. The controller 102 in this example also includes a media management layer 137 and a flash control layer 132 that controls the overall operation of the backend module 110 .

[0019] Data storage device 100 also includes other discrete components 140, such as an external electrical interface, external RAM, resistors, capacitors, or other components that may interface with controller 102. In alternative embodiments, one or more of physical layer interface 122, RAID module 128, media management layer 138, and buffer management / bus controller are optional components not required for controller 102.

[0020] FIG. 2B is a block diagram illustrating the components of the non-volatile memory die 104 in more detail. The non-volatile memory die 104 includes peripheral circuitry 141 and non-volatile memory array 142. The non-volatile memory array 142 includes non-volatile memory cells used to store data. The non-volatile memory cells may be any suitable non-volatile memory cells, including ReRAM, MRAM, PCM, NAND flash memory cells, and / or NOR flash memory cells in two-dimensional and / or three-dimensional configurations. The non-volatile memory die 104 also includes a data cache 156 that caches data and address decoders 148, 150. The peripheral circuitry 141 in this example includes a state machine 152 that provides status information to the controller 102. The peripheral circuitry 141 may also include one or more components, individually or in combination, configured to perform certain functions, including, but not limited to, the functions described and illustrated in the flowcharts herein. 2B, memory die 104 may include one or more processors 168 individually or in combination configured to execute computer-readable program code stored in one or more non-transitory memories 169, stored in memory array 142, or stored external to memory die 104. As another example, the one or more components may include circuits such as, but not limited to, logic gates, switches, application specific integrated circuits (ASICs), programmable logic controllers, and embedded microcontrollers.

[0021] In addition to or instead of one or more processors 138 (or, more generally, components) in the controller 102 and one or more processors 168 (or, more generally, components) in the memory die 104, the data storage device 100 may include another set of one or more processors (or, more generally, components). Generally, one or more processors (or, more generally, components) in the data storage device 100, wherever they are located and however many there are, may be configured, individually or in combination, to perform various functions, including, but not limited to, the functions described herein and illustrated in the flowcharts. For example, one or more processors (or components) may be in the controller 102, the memory device 104, and / or elsewhere in the data storage device 100. Also, different functions may be performed using different processors (or components) or combinations of processors (or components). Furthermore, means for performing a function may be implemented using a controller that includes one or more components (e.g., the processors or other components described above).

[0022] Returning again to FIG. 2A , flash control layer 132 (referred to herein as flash translation layer (FTL)) handles flash errors and interfaces with the host. In particular, the FTL, which may be an algorithm in firmware, handles the internals of memory management and translates writes from the host into writes to memory 104. The FTL may be needed because memory 104 may have limited endurance, may only be written to multiple pages, and / or may not be written to unless erased as a block. The FTL understands these potential limitations of memory 104, which may be invisible to the host. Thus, the FTL attempts to translate writes from the host into writes to memory 104.

[0023] The FTL may include a logical-to-physical address (L2P) map (sometimes referred to herein as a table or data structure) and allocated cache memory. In this manner, the FTL translates logical block addresses ("LBA") from the host into physical addresses in memory 104. The FTL may include other features such as, but not limited to, power-off recovery (so that the FTL's data structures can be recovered in the event of a sudden power loss) and wear leveling (so that wear across memory blocks is uniform to prevent excessive wear in any one block that would result in a greater likelihood of failure).

[0024] Referring again to the drawings, FIG. 3 is a block diagram of a host 300 and a data storage device 100 in one embodiment. The host 300 may take any suitable form, including, but not limited to, a computer, a mobile phone, a tablet, a wearable device, a digital video recorder, a surveillance system, etc. The host 300 (here, a computing device) in this embodiment comprises one or more processors 330 and one or more memories 340. In one embodiment, computer-readable program code stored in the one or more memories 340 configures the one or more processors 330 to perform the operations described herein as being performed by the host 300. Accordingly, actions performed by the host 300 may be referred to herein as being performed by an application (computer-readable program code) executing on the host 300. For example, the host 300 may be configured to send data (e.g., initially stored in the host's memory 340) to the data storage device 100 for storage in the data storage device's memory 104.

[0025] As mentioned above, one of the main challenges posed by NAND process shrinking and three-dimensional stacking is maintaining process uniformity. In addition, data storage devices may need to support a wide range of operating conditions (such as different program / erase cycles, retention times, and temperatures), which can lead to increased variability between memory dies, blocks, and pages across different operating conditions. Due to these variations, the read threshold (RT) used to read a memory page in some data storage devices is not fixed and can vary significantly as a function of physical location and operating conditions, especially for newer, less mature memory nodes.

[0026] Reads using an inaccurate read threshold can lead to a higher bit error rate (BER), which can degrade performance and quality of service (QoS) due to decoding failures, which may require invoking high-latency recovery flows that can cause delays and hiccups in performance. The challenge of maintaining an optimal read threshold can be particularly important for enterprise memory systems with very stringent quality of service requirements, as well as for mobile, internet of things (IoT), and automotive memory systems, where the required range of operating conditions is wide and the frequency of condition changes (e.g., temperature) can be high. This problem is even more difficult during the transition to newer, less mature memory nodes.

[0027] Current solutions for read threshold calibration, such as scanning the RT for the threshold that induces the lowest estimated bit error rate (a.k.a., BER Estimation Scan—BES) or generating a Cell Voltage Distribution (CVD) through multiple reads and setting the RT to the valley of the CVD (a.k.a., Valley Seeking—VS), are high-latency operations aimed at optimizing the read threshold for a particular word line, which are good for infrequent read recovery flows in case of data decoding failures but may not be suitable for frequent operations in case of frequent read threshold changes. Therefore, to address this issue, flash memory systems can implement a read threshold management scheme that attempts to track read threshold changes in the background via a maintenance process to ensure that the appropriate read threshold is used when the host issues a read command.

[0028] One approach is to track read thresholds for groups of blocks that share the same conditions. More specifically, blocks that are written at approximately the same time and temperature are grouped into time and temperature (TT) groups. Read thresholds are tracked for each time-temperature group, typically taken for several representative word lines from the blocks in the group. When the host performs a read operation, the read threshold associated with the time-temperature group corresponding to the read block is used, and additional adaptation to the read threshold by the specific read word line is performed based on a pre-calibrated word line zoning table.

[0029] Some read threshold management schemes may not adequately track the read threshold under frequently changing conditions and high variation between memory pages. Various solutions to address this issue are possible. For example, U.S. Patent Application No. 17 / 838,481, filed June 13, 2022, which is incorporated herein by reference, describes a read threshold calibration method that applies a machine learning (ML) predictive model, specifically including a system and method for inferring optimal read thresholds from various available information, including time and temperature group information, temperature information, bit error rate (BER) information, program-erase count (PEC) information, and physical page location.

[0030] As another example, U.S. Patent Application Nos. 17 / 899,073, filed August 30, 2022, 18 / 220,363, filed July 11, 2023, and 18 / 242,061, filed September 5, 2023, which are incorporated herein by reference, describe methods that enable implementation of an inference engine for faster and more accurate acquisition of read thresholds. In one embodiment described therein, a binary tree model is used to efficiently store only a subset of relevant correction data. Furthermore, it does not require direct reads from memory to perform threshold calibration, and is therefore much faster than BES / VS-based calibration. The unique structure of the binary tree enables a fast, low-area, and low-power solution.

[0031] Furthermore, U.S. Patent Application No. 18 / 658,074, filed May 8, 2024, which is incorporated herein by reference, describes hardware implementations. Hardware implementations may impose severe limitations on the complexity of the implemented predictive models. Therefore, as described in the references of the above-mentioned patent application, efficient predictive model-based ensembles of symmetric trees may be used. However, while symmetric predictive tree models may be capable of describing complex nonlinear functions of input features, they may have the inherent drawback of being discrete (non-continuous). This characteristic of random forest models may limit their predictive accuracy, as they have only a finite number of potential output values. The impact of this limitation on model performance may increase as hardware requirements become more stringent.

[0032] Linear regression (LR) is a statistical model that estimates a linear relationship between a scalar response and one or more explanatory variables (also known as the dependent and independent variables). In linear regression, the relationship is modeled using a linear predictive function, where unknown model parameters are estimated from data. The advantage of linear regression in this context is its ability to describe a wide continuous range of output values, where the output values ​​are a linear function of the input values. Linear regression can be particularly useful because it can easily predict identity functions, which often holds advantages when estimating optimal read thresholds.

[0033] As mentioned above, the basic hardware implementation of a tree-model-based predictive model may be limited by being discrete (i.e., having a finite, limited number of optional outputs). The following embodiments recognize that it may be beneficial to improve the capabilities of this predictive model without requiring the addition of extensive, complex hardware. The following embodiments can achieve this goal by combining predictions from different model types: a symmetric tree, a random forest model (which is nonlinear, discrete, and relatively simple to implement in hardware), and a simple continuous model such as a linear regression model. This leverages the capabilities of a random forest model (in its symmetric tree configuration, as described above) by combining a nonlinear tree model with another simplified linear regression predictive model. Such a model configuration enables the read threshold calibration model to provide a continuous output while still maintaining the efficiency provided by the basic principles of the symmetric tree model.

[0034] As mentioned above, these embodiments present a new approach for a hardware engine to perform read threshold calibration by combining two different predictive models: a binary tree hardware module and a simple linear regression model. The first model (e.g., a random forest with a symmetric tree model) is a powerful nonlinear model that can be implemented in hardware with a relatively small footprint, but can be limited to a finite set of output values. The other (linear) model itself has continuous-valued outputs, but may be overly simplistic and unable to describe complex output functions. The combination of both approaches provides a nonlinear continuous model that can provide excellent read threshold calibration capabilities with a low hardware footprint.

[0035] Referring again to the drawings, FIG. 4 is a flowchart 400 of an embodiment method for training a model that combines both a linear regression model and a tree-based model. This method can be used to adjust the parameters of the model to generate an optimized read threshold. As shown in FIG. 4, the controller 102 of the data storage device 100 obtains 410 input features to the overall model. Examples of input features include, but are not limited to, the physical address (Page Index, WL#, String#, Plane#, ...), program temperature (“Prog-Temp”), read temperature (“Read-Temp”), the difference between the Prog-Temp of a representative word line stored in the TT table and the current Prog-Temp (also referred to as “X-Temp”), NAND cycling level, data retention level (also related to cumulative exposure to high temperatures and time elapsed since data refresh), and time tag / read audit input read threshold.

[0036] The controller 102 can take a subset of the input features (420) to simplify hardware design and for efficiency analysis. If a linear regression model is provided with the currently used read thresholds (430), it can provide a correction to those read thresholds (440) without considering all the extra information in the system. Also, due to the simplicity of the model, the extra information may not provide a significant improvement to the read thresholds and may even cause some overfitting in some cases. All of the corrected amounts of input features are provided to a binary symmetric tree model (450), which outputs a binary tree (460). The outputs of the binary tree and linear regression model are combined to provide a recommended read threshold (470).

[0037] Figure 5 is a flowchart 500 for using an inference model provided by one embodiment. As shown in Figure 5, the controller 102 of the data storage device 100 obtains input features (510). The controller 102 can then take only a portion of the input features (520). If a linear regression model is provided with the currently used read threshold (530), the controller 102 can predict a correction to the default read threshold (540). All input features can then be provided to a binary symmetric tree model (550), which outputs a binary tree (560). The outputs of the binary tree and the linear regression model are combined (570) to yield a recommended read threshold (580).

[0038] These embodiments can be implemented in any suitable manner, such as using the hardware implementations shown in FIGS. 6 and 7. FIG. 6 is a schematic design of machine learning hardware for one embodiment. As shown in FIG. 6, threshold features 600 are provided to both a linear regression model 620 and a tree model 630, while regular features 610 are provided only to the tree model 630. The outputs of both models are combined in a combiner 650 to output a new threshold. FIG. 7 is an illustrative diagram of an exemplary hardware implementation of a linear regression model 700 for one embodiment. As discussed above, the hardware can include a random forest model and a linear regression model. The linear regression model can be a weighted sum of all computed features, and each THi* at the output is a linear combination of the thresholds at the input (e.g., 15 in the quad-level cell (QLC) example).

[0039] FIG. 8 is a graph illustrating the results of one embodiment, specifically a sigma plot display of failed bit count (FBC) distributions. The probability of obtaining a corresponding FBC on the x-axis is shown on the y-axis in sigma, where 0-sigma represents the median FBC and higher sigma represents a rarer FBC. "BES" represents the FBC provided by reading at the optimal threshold, "Reference" represents the reference result, "Symmetric Trees" represents a symmetric tree implementation, and "Linear Regression+Symmetric Trees" represents an exemplary implementation of one embodiment. In the exemplary implementation, only a portion of the optional features were used as input to the linear regression model, and quantization was applied to the unbiased linear regression model calculation. The graph shows that the resulting FBC distribution provided by using this embodiment is lower than the reference case.

[0040] There are several advantages associated with these embodiments. For example, by combining two different types of predictive models, additional description capabilities of a continuous output space can be provided. These embodiments can thereby provide improved read thresholds with only minor additional hardware complexity. Furthermore, by providing better read thresholds, these embodiments can provide improved throughput, quality of service (QoS), and power consumption, which may be desirable for data storage device operation.

[0041] Finally, as mentioned above, any suitable type of memory can be used. Semiconductor memory devices include volatile memory devices such as dynamic random access memory ("DRAM") or static random access memory ("SRAM") devices, non-volatile memory devices such as resistive random access memory ("ReRAM"), electrically erasable programmable read only memory ("EEPROM"), flash memory (which can also be considered a subset of EEPROM), ferroelectric random access memory ("FRAM"), and magnetoresistive random access memory ("MRAM"), as well as other semiconductor elements capable of storing information. Each type of memory device can have a different configuration. For example, flash memory devices can be configured in a NAND or NOR configuration.

[0042] Memory devices can be formed from passive and / or active elements in any combination. By way of non-limiting example, passive semiconductor memory elements include ReRAM device elements, which in some embodiments include a resistivity-switching storage element such as an antifuse, a phase-change material, and optionally a steering element such as a diode. Further, by way of non-limiting example, active semiconductor memory elements include EEPROM and flash memory device elements, which in some embodiments include elements that include charge storage regions such as floating gates, conductive nanoparticles, or charge storage dielectric materials.

[0043] Multiple memory elements may be configured so that they are connected in series or so that each element is individually accessible. As a non-limiting example, a NAND-configured flash memory device (NAND memory) typically includes memory elements connected in series. A NAND memory array may be configured so that the array is made up of multiple strings of memory, where a string is made up of multiple memory elements that share a single bit line and are accessed as a group. Alternatively, the memory elements may be configured so that each element is individually accessible (e.g., a NOR memory array). NAND and NOR memory configurations are examples, and memory elements may be configured in other ways.

[0044] The semiconductor memory elements located in and / or on the substrate may be arranged in two or three dimensions, such as in a two or three dimensional memory structure.

[0045] In a two-dimensional memory structure, semiconductor memory elements are arranged in a single plane or a single memory device level. Typically, in a two-dimensional memory structure, the memory elements are arranged in a plane (e.g., an xz-direction plane) that extends substantially parallel to a major surface of a substrate that supports the memory elements. The substrate may be a wafer on or in which a layer of memory elements is formed, or may be a carrier substrate to which the memory elements are attached after they are formed. As a non-limiting example, the substrate may include a semiconductor such as silicon.

[0046] The memory elements may be arranged in an ordered array, such as multiple rows and / or columns, in a single memory device level. However, the memory elements may be arranged in an irregular or non-orthogonal configuration. The memory elements may each have two or more electrodes or contact lines, such as bit lines and word lines.

[0047] A three-dimensional memory array is one in which memory elements are arranged to occupy multiple planes or multiple memory device levels, thereby forming a three-dimensional (i.e., x, y, and z directions, where the y direction is substantially perpendicular to the major surface of the substrate and the x and z directions are substantially parallel to the major surface of the substrate) structure.

[0048] As a non-limiting example, a three-dimensional memory structure can be arranged vertically as a stack of multiple two-dimensional memory device levels. As another non-limiting example, a three-dimensional memory array can be arranged as multiple vertical columns (e.g., columns extending substantially perpendicular to the major surface of the substrate, i.e., in the y-direction), with each column having multiple memory elements within each column. The columns can be arranged in a two-dimensional configuration, e.g., in the xz plane, resulting in a three-dimensional arrangement of memory elements with elements on multiple vertically stacked memory planes. Other configurations of three-dimensional memory elements can also make up a three-dimensional memory array.

[0049] As a non-limiting example, in a three-dimensional NAND memory array, memory elements can be coupled together to form NAND strings within a single horizontal (e.g., xz) memory device level. Alternatively, memory elements can be coupled together to form vertical NAND strings that traverse multiple horizontal memory device levels. Other three-dimensional configurations can be envisioned, in which some NAND strings contain memory elements within a single memory level and other strings contain memory elements that span multiple memory levels. Three-dimensional memory arrays can also be designed in NOR and ReRAM configurations.

[0050] Typically, in a monolithic three-dimensional memory array, one or more memory device levels are formed above a single substrate. Optionally, the monolithic three-dimensional memory array may also have one or more memory layers at least partially within the single substrate. As a non-limiting example, the substrate may include a semiconductor such as silicon. In a monolithic three-dimensional array, the layers making up each memory device level of the array are typically formed on layers of the memory device level below the array. However, layers of adjacent memory device levels of a monolithic three-dimensional memory array may be shared or may have intervening layers between the memory device levels.

[0051] Again, two-dimensional arrays can be formed separately and then packaged together to form a non-monolithic memory device having multiple memory layers. For example, a non-monolithic stacked memory can be constructed by forming memory levels on separate substrates and then stacking the memory levels on top of each other. The substrate may be thinned or removed from the memory device levels before stacking, but the resulting memory array is not a monolithic three-dimensional memory array because the memory device levels are first formed on separate substrates. Furthermore, multiple two-dimensional or three-dimensional memory arrays (monolithic or non-monolithic) can be formed on separate chips and then packaged together to form a stacked chip memory device.

[0052] Associated circuitry is typically required for operation of and communication with the memory elements. As a non-limiting example, a memory device may have circuitry used to control and drive the memory elements to accomplish functions such as programming and reading. This associated circuitry may be on the same substrate as the memory elements and / or on a separate substrate. For example, a controller for memory read-write operations may be located on a separate controller chip and / or on the same substrate as the memory elements.

[0053] Those skilled in the art will recognize that the present invention is not limited to the two-dimensional and three-dimensional structures described, but rather encompasses all relevant memory structures within the spirit and scope of the present invention as described herein and as understood by those skilled in the art.

[0054] The foregoing detailed description is intended to be understood as an illustration of selected forms that the invention can take, rather than as a definition of the invention. It is only the following claims, including all equivalents, that are intended to define the scope of the invention as claimed. Finally, it should be noted that any aspect of any of the embodiments described herein can be used alone or in combination with each other.

Claims

1. 1. A data storage device comprising: Memory and combining a plurality of different inference models, each inference model configured to use a different subset of the memory features; means for combining predictions of the plurality of different inference models to generate a final read threshold value.

2. The data storage device of claim 1 , wherein the memory characteristics include characteristics related to the physical address being read and / or characteristics related to the condition of the memory.

3. The data storage device of claim 1 , wherein the predictions of the first inference model are provided as part of the input features to the second inference model.

4. The data storage device of claim 3 , wherein the first inference model comprises a linear regression model.

5. The data storage device of claim 4 , wherein the second inference model comprises a tree-based model.

6. 1. A data storage device comprising: Memory and and one or more processors, said one or more processors individually or in combination: inputting a plurality of previously generated read thresholds into a linear regression model and a binary tree model; inputting a plurality of characteristics of the memory into the binary tree model; generating a recommended read threshold from the output of the linear regression model and the binary tree model; A data storage device configured to read the memory using the recommended read threshold.

7. The data storage device of claim 6 , wherein the binary tree model comprises a random forest with a symmetric tree model.

8. The data storage device of claim 6 , wherein the linear regression model includes a weighted sum of the plurality of features of the memory calculated for each of the previously generated read thresholds.

9. The data storage device of claim 6 , wherein the one or more processors are further configured, individually or in combination, to predict a correction to the previously generated read threshold.

10. 10. The data storage device of claim 9, wherein the one or more processors are further configured to, individually or in combination, input the predicted corrections to the previously generated read thresholds into the binary tree model.

11. The data storage device of claim 6 , wherein the plurality of characteristics of the memory includes a program temperature.

12. The data storage device of claim 6 , wherein the plurality of characteristics of the memory includes a read temperature.

13. 7. The data storage device of claim 6, wherein the plurality of characteristics of the memory comprises a difference between a program temperature of a representative word line and a current program temperature.

14. The data storage device of claim 6 , wherein the plurality of characteristics of the memory includes a cycling level of the memory.

15. The data storage device of claim 6 , wherein the plurality of characteristics of the memory includes a data retention level.

16. The data storage device of claim 6 , wherein the plurality of characteristics of the memory include a time tag / read audit input read threshold.

17. 7. The data storage device of claim 6, wherein the one or more processors are configured purely in hardware.

18. The data storage device of claim 6 , wherein the memory comprises a three-dimensional memory.

19. 1. A method, in a data storage device comprising a memory, comprising: inputting previously generated read threshold values ​​into a linear regression model, the linear regression model configured to output a predicted correction to the previously generated read threshold values; inputting a plurality of characteristics related to the memory into a binary symmetric tree model, the binary symmetric tree model configured to output a plurality of read thresholds; determining a recommended read threshold by combining the previously generated read threshold output from the linear regression model and the predicted corrections to the plurality of read thresholds output from the binary symmetric tree model; reading the memory using the recommended read threshold.

20. 20. The method of claim 19, further comprising inputting the predicted correction to the previously generated read threshold into the binary symmetric tree model.

21. 20. The method of claim 19, wherein the linear regression model comprises a weighted sum of the plurality of features of the memory calculated for each of the previously generated read thresholds.

22. 20. The method of claim 19, wherein the binary tree model comprises a random forest with a symmetric tree model.

23. 20. The method of claim 19, wherein the plurality of characteristics of the memory include one or more of a physical address, a program temperature, a read temperature, a difference between a program temperature of a representative word line and a current program temperature, a cycling level of the memory, a data retention level, and a time tag / read audit input read threshold.

24. 20. The method of claim 19, wherein the method is performed in a dedicated hardware module within the data storage device.

Images