Display device

Abstract

To suppress deviation in timing of potential change at each part of a scanning line provided in a display device.SOLUTION: When a signal input to a scan line is switched from a selection signal to a non-selection signal, the non-selection signal is input not only from one end of the scan line but also from both ends thereof. Specifically, the display device is provided with a scan line having one end to which a selection signal or a non-selection signal is input and a transistor having a gate to which a clock signal is input, a source to which the non-selection signal is input, and a drain connected to the scan line. The timing at which the signal input from the one end to the scan line is switched from a selection signal to a non-selection signal is the same or substantially the same as the timing at which the transistor is turned on from an off state. Thus, a non-selection signal is input not only from one end of the scan line but also from both ends thereof. For this reason, it is possible to suppress the deviation of the timing of the potential change at each place of the scanning line.SELECTED DRAWING: Figure 1

Description

[Technical Field]

[0001] The present invention relates to an article, a method, or a manufacturing method. The invention relates to the manufacture or composition of matter. One embodiment of the present invention is a semiconductor device, a display device, a light-emitting device, a driving method thereof, or In particular, one embodiment of the present invention relates to a method for manufacturing the same. Regarding placement. [Background technology]

[0002] In an active matrix display device, multiple pixels are arranged in a matrix. Then, by displaying a specific color according to the image signal for each pixel, the display device as a whole can display the desired color. The desired image is displayed.

[0003] Each pixel is provided with a transistor for rewriting the image signal. The gate of the transistor is connected to a scanning line to control the potential of the scanning line. The switching of the transistor is controlled by the matrix. The pixel data included in each of the plurality of pixels arranged in a specific row among the plurality of pixels arranged in a row is It is connected to the gate of the transistor that is included in the active matrix display. In a display device, image signals are rewritten for each specific row.

[0004] In an active matrix display device, a plurality of pixels arranged in a matrix are The same number of scanning lines as the number of pixel rows are provided. The scanning line driving circuit is arranged in a matrix. Although it is possible to provide them together on one side of the multiple pixels, it is also possible to provide them separately on both sides ( It is also possible to provide a first scanning line driving circuit and a second scanning line driving circuit (see Patent Document 1 and Patent Document 2). [Prior art documents] [Patent documents]

[0005] [Patent Document 1] U.S. Patent No. 8,462,098 [Patent Document 2] U.S. Patent Publication No. 2012 / 0062528 Summary of the Invention [Problem to be solved by the invention]

[0006] The effects of wiring resistance and parasitic capacitance tend to become apparent in the scanning lines. Therefore, the scanning line necessarily extends along a plurality of pixels arranged in a certain row. The length of the scanning line is long, and the wiring resistance is likely to increase. The wiring that serves as the input path for the image signal to the Therefore, the scanning lines have parasitic capacitance that occurs at the intersections with the signal lines, and The gate capacitance of the transistor connected to the Therefore, if the display device is made larger and the number of pixels is increased, these effects will become even greater. This is because the total length of the scanning lines becomes longer as the display device becomes larger. As the number of pixels in a device increases, the number of signal lines intersecting the scanning lines and the number of connected transistors also increase. Because it adds to the

[0007] Here, if the wiring resistance and parasitic capacitance become large, problems may occur in the display device. Specifically, when a signal is input to a scanning line, the potential at the input point of the signal changes first. Then, the potential at a point far from the input point changes. The timing at which the potential changes varies depending on the location. increases in proportion to the wiring resistance and parasitic capacitance. When the capacitance becomes large, the switching of the multiple transistors whose gates are connected to the scan line becomes difficult. This can cause a large difference in timing between the two signals, which can lead to problems with the display device. do.

[0008] There are two cases where the timing of transistor switching is shifted. Specifically, the timing at which the transistor changes from an off state to an on state is There are two cases: when the timing is off, and when the timing of switching from the on state to the off state is off. Therefore, in active matrix display devices, the latter case is particularly likely to cause problems. This is because if the timing at which the transistor changes from the on state to the off state is off, the desired This is because there is a high probability that an image signal different from the image signal in question will be input to the pixel.

[0009] In view of the above, one aspect of the present invention is to provide a method for controlling the timing of potential changes at each point of a scanning line. Another object of the present invention is to suppress the misalignment. The purpose is to suppress the timing discrepancy of the switching of multiple transistors. Another embodiment of the present invention is to suppress defects that occur in a display device. Another object of one embodiment of the present invention is to provide a novel display device. One aspect of the present invention aims to solve at least one of these problems. Furthermore, the description of these problems does not preclude the existence of other problems. The problem is self-evident from the description, drawings, claims, etc. It is possible to extract other issues from the descriptions in the drawings, claims, etc. [Means for solving the problem]

[0010] In one aspect of the present invention, when a signal input to a scanning line is switched from a selection signal to a non-selection signal, The gist is that a non-selection signal is input from both ends of the scanning line, not just one end. In this specification, a selection signal is a signal that turns on a transistor whose gate is connected to a scanning line. A select signal refers to a signal that sets the device in an ON state, and a non-select signal refers to a signal that sets the device in an OFF state. do.

[0011] For example, one embodiment of the present invention is a scanning line to which a selection signal or a non-selection signal is input from one end, a transistor to which a clock signal is input at its gate and a non-selection signal is input at its source; The other end of the scanning line and the drain of the transistor are electrically connected, and the input to the scanning line from one end The timing when the input signal switches from the select signal to the non-select signal is the timing when the transistor is turned off. The timing at which the display device changes from the ON state to the OFF state is the same or approximately the same as that of the display device. [Effects of the Invention]

[0012] In the display device according to one embodiment of the present invention, non-selection signals are applied not only to one end of the scanning line but also to both ends. Therefore, the timing difference of the potential change at each point of the scanning line is suppressed. Then, a plurality of transistors whose gates are connected to the scanning lines are As a result, it is possible to prevent the timing of switching of the display This makes it possible to suppress problems that occur in the display device. [Brief explanation of the drawings]

[0013] [Figure 1] 1A, 1B, and 1D are diagrams showing an example of the configuration of a display device, and 1C and 1E are diagrams showing signal waveforms. [Figure 2] FIG. 1A is a diagram showing an example of the configuration of a display device, and FIG. 1B is a diagram showing signal waveforms. [Figure 3] FIG. 1 illustrates an example of the configuration of a display device. [Figure 4] FIG. 1A is a diagram showing a specific example of a display device, and FIG. 1B is a diagram showing an example of the configuration of a pixel. [Figure 5] FIG. 2 is a diagram showing a configuration example of a scanning line driver circuit. [Figure 6] (A) A diagram showing the waveform of a clock signal, and (B) a diagram showing a pulse output circuit. [Figure 7] 1A is a diagram showing an example of the configuration of a pulse output circuit, and FIGS. 1B and 1C are diagrams showing signal waveforms and changes in node potentials. [Figure 8] 1A is a diagram showing an example of the configuration of a scanning line driving circuit, and FIG. 1B is a diagram showing signal waveforms. [Figure 9] FIG. 2 is a diagram showing a configuration example of a scanning line driver circuit. [Figure 10] FIG. 2 is a diagram showing an example of a display module. [Figure 11] FIG. 1A is a diagram showing an example of a mobile phone, and FIG. 1B is a diagram showing an example of a bangle-type display device. [Figure 12] (A) and (B) are diagrams showing an example of a portable product. DETAILED DESCRIPTION OF THE INVENTION

[0014] One embodiment of the present invention will be described in detail below. However, the present invention is not limited to the following description. The present invention is not limited to the above, and its form may be variously changed without departing from the spirit and scope of the present invention. Therefore, the present invention should not be construed as being limited to the following description.

[0015] In addition, when it is explicitly stated in this specification that X and Y are connected, is when X and Y are electrically connected and when X and Y are functionally connected. and the case where X and Y are directly connected are considered to be disclosed in this specification and the like. Therefore, the present invention is not limited to predetermined connection relationships, for example, connection relationships shown in drawings or text. Connections other than those shown in the drawings or text are also considered to be described in the drawings or text. do.

[0016] Here, X and Y are the object (for example, a device, an element, a circuit, a wiring, an electrode, a terminal, a conductive film, a layer, etc.). , etc.).

[0017] An example of a direct connection between X and Y is a circuit that allows electrical connection between X and Y. The elements to be considered (e.g., switches, transistors, capacitance elements, inductors, resistance elements, When no external device (such as a diode, display element, light-emitting element, or load) is connected between X and Y, The elements that allow electrical connection between X and Y (e.g., switches, transistors, capacitors) elements, inductors, resistors, diodes, display elements, light-emitting elements, loads, etc.) , X and Y are connected.

[0018] An example of an electrical connection between X and Y is The elements to be considered (e.g., switches, transistors, capacitance elements, inductors, resistance elements, One or more devices (such as diodes, display elements, light-emitting elements, and loads) can be connected between X and Y. It is possible. The switch has a function to control on / off. A switch can be in a conducting state (ON state) or a non-conducting state (OFF state), allowing current to flow. The switch has the function of controlling whether or not the current flows. When X and Y are electrically connected, This includes the case where Y is directly connected.

[0019] An example of a functional connection between X and Y is a function that allows the functional connection between X and Y. Circuits that perform the above functions (for example, logic circuits (inverters, NAND circuits, NOR circuits, etc.), signal conversion conversion circuits (DA conversion circuits, AD conversion circuits, gamma correction circuits, etc.), potential level conversion circuits (voltage power supply circuits (voltage boost circuits, voltage drop circuits, etc.), level shifter circuits that change the signal potential level, etc.) , voltage source, current source, switching circuit, amplifier circuit (which can increase the signal amplitude or current amount, etc.) circuits, operational amplifiers, differential amplifier circuits, source follower circuits, buffer circuits, etc.), signal generation One or more circuits (e.g., memory circuits, control circuits, etc.) can be connected between X and Y. For example, even if another circuit is inserted between X and Y, the signal output from X If X is transmitted to Y, then X and Y are considered to be functionally connected. When X and Y are functionally connected, there is a direct connection between X and Y and a direct connection between X and Y. This also includes the case where the and are electrically connected.

[0020] In addition, if it is explicitly stated that X and Y are electrically connected, are electrically connected (i.e., there is another element or circuit between X and Y) X and Y are functionally connected (i.e., X and Y are functionally connected) and (When there is a functional connection between them via another circuit) and when X and Y are directly connected (i.e., when X and Y are connected without any other element or circuit between them) is considered to be disclosed in the present specification. If it is explicitly stated that it is connected, The same content is considered to be disclosed in the present specification.

[0021] For example, if the source (or first terminal, etc.) of the transistor is connected via Z1 (or (not shown), electrically connected to X, and the drain (or second terminal, etc.) of the transistor is connected to Z 2 (or not), and is electrically connected to Y, or the source of the transistor (or the first terminal, etc.) is directly connected to a part of Z1, and another part of Z1 is directly connected to X. The drain (or second terminal, etc.) of the transistor is directly connected to a part of Z2. and another part of Z2 is directly connected to Y, It is possible to do so.

[0022] For example, "X and Y and the source (or first terminal, etc.) and drain (or second terminal, etc.) of a transistor" The terminals of the transistor (or the first terminal) are electrically connected to each other. 1 terminal, etc.), the drain of the transistor (or the second terminal, etc.), and Y. It can be expressed as "connected to the source (or the first The first terminal of the transistor is electrically connected to X, and the drain of the transistor is electrically connected to the second terminal of the transistor. The transistor source (or first terminal, etc.) is electrically connected to Y, and the transistor source (or first terminal, etc.) is electrically connected to X. The drain (or second terminal, etc.) of the transistor, Y, is electrically connected in this order. " Alternatively, "X is the source (or first terminal, etc.) of the transistor. and the drain (or second terminal, etc.) are electrically connected to Y, and X, the source (or first terminal, etc.) of a transistor, the drain (or second terminal, etc.) of a transistor ), Y is provided in this order of connection. By specifying the order of connections in the circuit configuration using a simple expression method, Distinguish between the source (or first terminal, etc.) and the drain (or second terminal, etc.) of a transistor. The technical scope can be determined by the above.

[0023] Alternatively, for example, "the source (or first terminal, etc.) of a transistor" is electrically connected to X through at least a first connection path, and the first connection path is , and the second connection path is a transistor through a transistor. The source (or first terminal, etc.) of the transistor and the drain (or second terminal, etc.) of the transistor The first connection path is a path via Z1, and the second connection path is a path between the first and second transistors. The drain (or second terminal, etc.) of the capacitor is electrically connected to Y through at least a third connection path. the third connection path does not have the second connection path, and the third connection path The connection path is the path via Z2. The source (or first terminal, etc.) of the resistor is connected to the resistor via at least the first connection path and Z1. and electrically connected to X, and the first connection path does not have a second connection path; The second connection path has a connection path through a transistor, and (or the second terminal, etc.) is connected to Y via at least a third connection path and Z2. The third connection path does not have the second connection path. Alternatively, the source (or first terminal, etc.) of the transistor may be at least Both are electrically connected to X via Z1 through a first electrical path, and the first electrical The primary path does not have a second electrical path, and the second electrical path is a From the source (or first terminal, etc.) to the drain (or second terminal, etc.) of the transistor The drain (or second terminal, etc.) of the transistor is connected to at least a third and electrically connected to Y through Z2 via the electrical path of , the fourth electrical path does not have the drain of the transistor. The electrical current from the in (or second terminal, etc.) to the source (or first terminal, etc.) of the transistor Using the same expression as these examples, we can express the circuit By defining the connection path in the structure, the source of the transistor (or the first Distinguish between the first terminal (or the first terminal, etc.) and the drain (or the second terminal, etc.) to determine the technical scope. It is possible.

[0024] These representation methods are merely examples, and the present invention is not limited to these representation methods. , Y, Z1, Z2 are objects (e.g., devices, elements, circuits, wiring, electrodes, terminals, conductive films, layer, etc.).

[0025] In addition, the circuit diagram shows independent components as if they are electrically connected to each other. Even if the components are different, one component may have the functions of multiple components. For example, when a part of the wiring also functions as an electrode, one conductive film functions as both the wiring and the electrode. Therefore, the electrode in this specification has the functions of both components. The term "electromagnetic connection" refers to a case where one conductive film has the functions of multiple components. This also falls within the scope of the above.

[0026] <1. Display device configuration example> A display device of one embodiment of the present invention will be described with reference to FIG. 1A is a diagram showing a part of the display device. In FIG. 1A, a selection signal (Sel) or a non-selection signal (NSEL) is applied to one end. The selection signal (n-Sel) is input to the scanning line 10, and the clock signal (CK) is input to the gate. The figure shows a transistor 11 whose source receives a non-selection signal (n-Sel). The other end of the scanning line 10 is connected to the drain of the transistor 11. In the scanning line 10 shown in FIG. 1A, a signal input from one end is different from a selection signal (Sel). The timing at which the selection signal (n-Sel) is switched to the ON state is the timing at which the transistor 11 is switched from the OFF state to the ON state. The signal is input so that it is the same or almost the same as the timing at which the device enters the ON state. In FIG. 1(A), an N-channel transistor is illustrated as the transistor 11. However, the transistor 11 may be replaced with a P-channel transistor.

[0027] In an actual display device, the scanning line 10 is a line of pixels arranged in a particular row. The gates of the transistors included in each transistor are connected to the gates of the transistors included in each transistor. The pixels 12_1 and 12_2 and the transistors 13 included in the pixels 12_1 and 12_2 are 13_1, 13_2 (hereinafter also referred to as pixel transistors) are added. As shown in FIG. 1(B), transistors 13_1 and 13_2 are N-channel transistors. In this case, the high power supply potential (VDD) is the select signal and the low power supply potential (VSS) is the non-select signal. FIG. 1C is a diagram showing an example of the waveform of the signal shown in FIG. 1B. As shown in FIG. 1B, in the scanning line 10 shown in FIG. 1B, a signal input from one end is a high power supply potential. The timing (TA) at which the power supply voltage (VDD) is switched to the low power supply voltage (VSS) is (CK) switches from the low power supply potential (VSS) to the high power supply potential (VDD). In FIG. 1(C), the clock signal (CK) is A signal with a duty ratio of 1 / 2 that alternates between high power supply potential (VDD) and low power supply potential (VSS) Although shown in the figure, at least one of the high power supply potential (VDD) and the low power supply potential (VSS) is connected to the other. Alternatively, a signal having a duty ratio other than 1 / 2 may be applied. .

[0028] Also, as shown in FIG. 1(C), during the period when a high power supply potential (VDD) is supplied to the scanning line 10, During this time, it is preferable that the transistor 11 is maintained in an off state. During this period, it is preferable that the clock signal (CK) maintains a low power supply potential (VSS). This prevents unnecessary current from flowing from one end of the scanning line 10 to the other end, This is because malfunctions and increases in power consumption can be suppressed.

[0029] FIG. 1D shows the transistors 11, 13_1, and 13_2 shown in FIG. 1B as P-channel transistors. 1 is a diagram showing a configuration in which high-speed transistors 14, 15_1, and 15_2 are replaced with The power supply potential (VDD) is the non-select signal, and the low power supply potential (VSS) is the select signal. FIG. 1(E) is a diagram showing an example of the waveform of the signal shown in FIG. 1(D). In the scanning line 10 shown in FIG. 1(D), a signal input from one end is set to a low power supply potential (VSS). The timing (TB) at which the power supply voltage is switched from low to high (VDD) is the timing at which the clock signal (CK) goes high. To match the timing of switching from the power supply potential (VDD) to the low power supply potential (VSS) A signal is input.

[0030] As shown in FIG. 1B, the drain of the transistor is connected to the other end of the scanning line 10. The transistor 11 and the transistors 13_1 and 13_2 whose gates are connected to the scanning line 10 have the same polarity. As shown in FIG. 1(D), the drain is preferably a swirl-type transistor. A transistor 14 connected to the other end of the scan line 10 and a transistor 15 whose gate is connected to the scan line 10 are connected to the other end of the scan line 10. It is preferable that the transistors 15_1 and 15_2 have the same polarity. In order to reduce the number of manufacturing processes compared to when both transistors have different polarities, In addition, it is preferable that the two transistors are of different polarities and the clock The clock signal (CK) is composed of a potential corresponding to a select signal and a potential corresponding to a non-select signal. In this case, the terminal to which the non-selection signal is input is the drain of the transistors 11 and 14, not the source. In this case, the gate of the transistor connected to the scanning line 10 is The transistors 11, 12 are driven from a potential corresponding to a non-selection signal, not a potential corresponding to a selection signal. A potential that has changed by the threshold voltage of 4 is input.

[0031] FIG. 2A is a diagram illustrating a part of a display device of one embodiment of the present invention. The scanning line 101 to which the signal (A1) is input from the left side of the paper, and the signal (A2) from the right side of the paper. The scan line 102 is input, the clock signal (CK2) is input to the gate, and the low voltage is input to the source. A transistor 111 to which a power supply potential (VSS) is input and a clock signal (CK1) is input to the gate. and a transistor 112 to whose source a low power supply potential (VSS) is input. The right end of the scanning line 101 on the paper surface is connected to the drain of the transistor 111. The left end of the scanning line 102 on the paper surface is connected to the drain of the transistor 112. In FIG. 2A, the pixels 121_1, 121_2, 122_1, 122_2 and the transistors The registers 131_1, 131_2, 132_1, and 132_2 are also shown. Registers 111, 112, 131_1, 131_2, 132_1, and 132_2 are N-channel It is a type transistor.

[0032] FIG. 2(B) is a diagram showing the waveform of the signal shown in FIG. 2(A). As shown in FIG. 2(B), In the scanning lines 101 and 102 shown in FIG. 2A, the input signal is at a high power supply potential (VDD). The timing (TA1, TA2) at which the power supply voltage changes from VSS to VSS is (CK1, CK2) switches from low power supply potential (VSS) to high power supply potential (VDD). The signals are input so that they match the timing of the clock signals (CK1, CK2). The duty ratio and the like can be changed as appropriate.

[0033] In the configuration shown in Figure 2(A), the input path for the clock signals (CK1, CK2) is The wiring is not arranged all together on one side of the display area, but is divided and arranged on both opposing sides. Therefore, it is possible to narrow the width of the frame of a display device in which the display area is located in the center (narrow It is possible to frame it.

[0034] In FIGS. 2A and 2B, the transistors included in the display device are N-channel transistors. The case of a P-channel transistor is shown. may be applied.

[0035] In FIG. 3, the configuration shown in FIG. 2(A) is provided with a shift register 141 on the left side of the paper. 1, a shift register 142 is additionally shown on the right side of the drawing. The clock signal (CK1) is input to the clock register 141, which outputs a signal to the scanning line 101. The shift register 142 is a circuit that receives a clock signal (CK2). This is a circuit that outputs a signal to the scanning line 102 .

[0036] In the configuration shown in FIG. 3, it is possible to narrow the frame in the same way as in the configuration shown in FIG. 2(A). In addition, in the configuration shown in FIG. 3, the clock signals (CK1, CK2) are applied to the transistors 111 , 112 as well as operating the shift registers 141, 142. Therefore, the configuration shown in Figure 3 is intended to efficiently narrow the frame. It is possible.

[0037] The configuration of the shift registers 141 and 142 is not limited to a specific configuration. For example, Complementary metal oxide transistors using both P-channel and N-channel transistors The shift registers 141 and 142 may be configured using a complementary metal-oxide semiconductor (CMOS) circuit. The shift registers 141 and 142 may be configured using only one of them. When the shift registers 141 and 142 are configured using CMOS circuits, This is preferable in that it is possible to reduce the power consumption in the shift register 42. 141 and 142 are transistors 111, 112, 131_1, 131_2, 132_1, When the transistors are composed of only transistors with the same polarity as 132_2, the number of manufacturing processes can be reduced. This is preferable in that it makes it possible to

[0038] <2. Specific examples of display devices> 4A is a diagram showing a specific example of a display device. The display device shown in FIG. 4A has m rows. m×n pixels 20 arranged in n columns (m, n is an even number) and m scanning lines 21 extending in the left-right direction of the pixel, and m scanning lines 21 extending in the up-down direction of the paper between the pixels. n signal lines 22, and scanning line driving circuits 22 each connected to the m scanning lines 21. 3, 24, and a signal line driving circuit 25 connected to the n signal lines 22.

[0039] <(1) Example of the configuration of the pixel 20> FIG. 4B is a diagram showing an example of a circuit diagram of the pixel 20 included in the display device shown in FIG. 4A. The pixel 20 shown in FIG. 4B has a gate connected to a scanning line 21 and a source or drain A transistor 201 has one electrode connected to a signal line 22, and a transistor 202 has one electrode connected to a transistor The other electrode is connected to the other of the source or drain of the capacitor 201, and the other electrode is a wiring that supplies a capacitance potential. a capacitor 202 connected to a capacitor line (also referred to as a capacitor line) and one electrode of the transistor 20 The other electrode of the capacitor 202 is connected to the other of the source and drain of the capacitor 202. The liquid crystal element 2 is electrically connected to a wiring (also called a common potential line) that supplies a common potential. 03. It is possible to make the capacitance potential and the common potential the same potential. 4B shows a configuration in which a liquid crystal element 203 is provided in the pixel 20. The pixels of the display device disclosed in this specification are not limited to this configuration. In the display device shown, the pixels may also be provided with light-emitting elements.

[0040] <(2) Configuration Example of Scanning Line Driving Circuits 23 and 24> FIG. 5 shows an example of the configuration of the scanning line driving circuits 23 and 24 included in the display device shown in FIG. 4(A). The scanning line driving circuit 23 shown in FIG. 5 is a diagram in which each of the clock signals (CKL1 to CKL4) is Four wirings supplying either one of the signals and a plurality of scanning lines 21 arranged in odd-numbered rows. Multiple pulse output circuits connected to one of _1, 21_3, 21_m-1 23_1, 23_3, 23_m-1, and each gate is connected to one of the four wires. The source is connected to the low power supply potential (VSS) line (hereinafter referred to as the low power supply potential line). ), and the drains of the plurality of scanning lines 21_2, 21_4, etc. are arranged in even-numbered rows. A plurality of transistors 23_2, 23_4 connected to any one of 21_m 5. The scanning line driving circuits 24 shown in FIG. 5 each have a clock signal ( CKR1 to CKR4), and each of the four wirings is arranged in an even-numbered row. A plurality of scanning lines 21_2, 21_4, . . . 21_m are connected to one of the plurality of scanning lines 21_2, 21_4, . . . 21_m. The pulse output circuits 24_2, 24_4, . . . 24_m and the gates of the four wirings are connected to each other. The source is connected to a low power supply potential line, and the drain is arranged in an odd-numbered row. The scanning line 21_1, 21_3, . . . 21_m-1 is connected to one of the scanning lines 21_1, 21_3, . . . 21_m-1. The transistors 24_1, 24_3, . . . , 24_m-1 are connected to the transistors 24_1, 24_3, . . . , 24_m-1. In the scanning line driving circuit 23 shown in FIG. m-1 constitute a shift register, and in the scanning line driving circuit 24 shown in FIG. The pulse output circuits 24_2, 24_4, . . . 24_m form a shift register. There are.

[0041] FIG. 6A shows one example of specific waveforms of the clock signals (CKL1 to CKL4, CKR1 to CKR4). 6A is a diagram showing an example of a clock signal (CKL1) that periodically goes high. The potential (high power supply potential (VDD)) and the low level potential (low power supply potential (VSS)) are repeatedly switched. The duty ratio of the clock signal (CKL2) is 3 / 8. The clock signal (CKL3) is a signal that is shifted in phase by 1 / 4 cycle from the clock signal (CKL1). , a signal whose phase is shifted by 1 / 2 cycle from the clock signal (CKL1), and KL4) is a signal that is shifted in phase by 3 / 4 cycle from the clock signal (CKL1). The clock signal (CKR1) is a signal whose phase is shifted by 1 / 8 cycle from the clock signal (CKL1). The clock signal (CKR2) is 3 / 8 cycle phase away from the clock signal (CKL1). The clock signal (CKR3) is 5 / 16 shy of the clock signal (CKL1). The clock signal (CKR4) is a signal that is eight cycles out of phase with the clock signal (CKL1 ) is a signal that is 7 / 8 cycle phase shifted from

[0042] In the above-described display device, each of the pulse output circuits 23_1, 23_3, . . . 23_m- 1, 24_2, 24_4, 24_m, and apply circuits with the same configuration. However, the electrical connection relationship between the multiple terminals of the pulse output circuit is The specific connection relationships will be explained with reference to Figures 5 and 6(B).

[0043] Each pulse output circuit, except for pulse output circuits 23_m-1 and 24_m, has terminals 31 to 3 Terminals 31 to 34 are input terminals, and terminals 35 and 36 are output terminals. Furthermore, the pulse output circuits 23_m-1 and 24_m have terminals 31 to 35.

[0044] First, the terminal 31 will be described. The terminal 31 of the pulse output circuit 23_1 is A pulse output circuit 23_2a-1 (a is 2 or more m) is connected to a wiring that supplies a signal (SP1). A terminal 31 of the pulse output circuit 23_2a-3 (a natural number equal to or less than 1 / 2) is connected to a terminal 36 of the pulse output circuit 23_2a-3. Furthermore, a terminal 31 of the pulse output circuit 24_2 supplies a start pulse (SP2). The terminal 31 of the pulse output circuit 24_2a is connected to the wiring a-2 is connected to terminal 36.

[0045] Next, the terminal 32 will be described. The pulse output circuit 23_8b-7 (b is m / 8 or less) The terminal 32 of the clock signal (CKL1) is connected to the wiring that supplies the clock signal (CKL2). The terminal 32 of the output circuit 23_8b-5 is connected to the wiring that supplies the clock signal (CKL2). The terminal 32 of the pulse output circuit 23_8b-3 supplies a clock signal (CKL3). The terminal 32 of the pulse output circuit 23_8b-1 is connected to a wiring that outputs a clock signal (CKL 4) is connected to the wiring. is connected to the wiring that supplies the clock signal (CKR1), and the pulse output circuit 24_8b- Terminal 32 of 4 is connected to the wiring that supplies the clock signal (CKR2), and the pulse output circuit Terminal 32 of 24_8b-2 is connected to the wiring that supplies the clock signal (CKR3), The terminal 32 of the pulse output circuit 24_8b is connected to a wiring that supplies a clock signal (CKR4). It has been done.

[0046] Next, the terminal 33 will be described. The terminal 33 of the pulse output circuit 23_8b-7 is The terminal of the pulse output circuit 23_8b-5 is connected to the wiring that supplies the clock signal (CKL2). 33 is connected to a wiring that supplies a clock signal (CKL3), and the pulse output circuit 23_8 Terminal 33 of b-3 is connected to the wiring that supplies the clock signal (CKL4), and the pulse output The terminal 33 of the circuit 23_8b-1 is connected to a wiring that supplies a clock signal (CKL1). Furthermore, the terminal 33 of the pulse output circuit 24_8b-6 receives a clock signal (CKR2). The terminal 33 of the pulse output circuit 24_8b-4 is connected to a wiring that supplies a clock signal (CKR3), and the terminal 33 of the pulse output circuit 24_8b-2 is A terminal of the pulse output circuit 24_8b connected to the wiring that supplies the clock signal (CKR4) 33 is connected to a wiring that supplies a clock signal (CKR1).

[0047] Next, the terminal 34 will be described. The terminal 34 of the pulse output circuit 23_8b-7 is The terminal of the pulse output circuit 23_8b-5 is connected to the wiring that supplies the clock signal (CKL3). 34 is connected to a wiring that supplies a clock signal (CKL4), and is connected to a pulse output circuit 23_8 Terminal 34 of b-3 is connected to the wiring that supplies the clock signal (CKL1), and is the pulse output The terminal 34 of the circuit 23_8b-1 is connected to a wiring that supplies a clock signal (CKL2). The terminal 34 of the pulse output circuit 24_8b-6 receives a clock signal (CKR3). The terminal 34 of the pulse output circuit 24_8b-4 is connected to a wiring that supplies a clock signal (CKR4), and the terminal 34 of the pulse output circuit 24_8b-2 is A terminal of the pulse output circuit 24_8b connected to a wiring that supplies a clock signal (CKR1) 34 is connected to a wiring that supplies a clock signal (CKR2).

[0048] Next, the terminal 35 will be described. The pulse output circuits 23_2x-1 and 24_2x (x is , a natural number equal to or less than m), the terminal 35 is connected to the scanning line 21_x arranged in the x-th row. .

[0049] Connection of terminal 36 of each pulse output circuit (excluding pulse output circuits 23_m-1 and 24_m) The relationship has already been mentioned, so the above explanation will be used here.

[0050] <(2-1) Example of pulse output circuit configuration> FIG. 7A is a diagram showing an example of the configuration of the pulse output circuit shown in FIGS. 5 and 6B. The pulse output circuit shown in (A) has transistors 41 to 49. The circuits 23_m-1 and 24_m do not need to be provided with the transistors 43 and 44.

[0051] The transistor 41 has a structure in which either the source or the drain supplies a high power supply potential (VDD). The transistor is connected to a line (hereinafter referred to as a high power supply potential line) and its gate is connected to a terminal 31.

[0052] The transistor 42 has one of its source and drain connected to a low power supply line. The other of the drains is connected to the other of the source or drain of the transistor 41.

[0053] The transistor 43 has one of its source and drain connected to the terminal 32. The other drain is connected to the terminal 36, and the gate is connected to the source or drain of the transistor 41. The other is connected to the other of the source or drain of the transistor 42 .

[0054] The transistor 44 has either a source or a drain connected to a low power supply potential line. The other drain of the transistor is connected to the terminal 36, and the gate is connected to the gate of the transistor 42. are.

[0055] The transistor 45 has either a source or a drain connected to a low power supply potential line. The other drain is connected to the gate of transistor 42 and the gate of transistor 44. , and the gate is electrically connected to terminal 31.

[0056] The transistor 46 has either a source or a drain connected to a high power supply potential line, and a gate It is connected to the terminal 33. Note that either the source or the drain of the transistor 46 is low. A voltage that is higher than the power supply potential (VSS) and lower than the high power supply potential (VDD). It may also be configured to be connected to a wiring that supplies a power supply potential (VCC).

[0057] The transistor 47 has either the source or the drain connected to the source or the drain of the transistor 46. The other of the source and drain is connected to the gate of transistor 42. The gate of the transistor 44 and the other of the source and drain of the transistor 45 are connected to the gate of the transistor 44 and the other of the source and drain of the transistor 45. The port is connected to terminal 34.

[0058] The transistor 48 has one of its source and drain connected to the terminal 32. The other drain is connected to the terminal 35, and the gate is connected to the source or drain of the transistor 41. On the other hand, the other of the source or drain of the transistor 42 and the gate of the transistor 43 is connected.

[0059] The transistor 49 has one of its source and drain connected to a low power supply potential line. The other drain is connected to the terminal 35, and the gate is the gate of the transistor 42. The gate of transistor 44, the other of the source or drain of transistor 45, and transistor 4 7 is connected to the other of the source or drain.

[0060] In the following, the other of the source and drain of the transistor 41 is referred to as the transistor The other of the source or drain of transistor 42, the gate of transistor 43, and the The node to which the gate is connected is referred to as node A. The gate of transistor 42, the gate of transistor 4 the gate of transistor 4, the other of the source or drain of transistor 45, and the source of transistor 47 The node to which the other of the drains and the gate of the transistor 49 are connected is defined as node B. I will explain.

[0061] <(2-2) Example of pulse output circuit operation> An example of the operation of the pulse output circuit described above will be explained with reference to FIGS. 7(B) and 7(C). FIG. 7B shows the waveforms of signals input to and output from the pulse output circuit 23_1, and the pulse output 7(C) is a diagram showing the potentials of nodes A and B in the pulse output circuit 23_1. Waveforms of signals input to and output from the pulse output circuit 24_2, and potentials of nodes A and B in the pulse output circuit 24_2 7B and 7C, Gout is the pulse output circuit. SRout represents the output signal for the scanning line, and SRout is provided at the rear stage of the pulse output circuit. 10 represents the output signal for the pulse output circuit.

[0062] First, the operation of the pulse output circuit 23_1 will be described with reference to FIG. 7(B).

[0063] At timing t1, a high-level potential (high power supply potential (VDD)) is input to terminal 31. This turns on the transistors 41 and 45. The potential of the transistor 41 is lower than the high-level potential (high power supply potential (VDD) At this point, the transistor 41 is turned off. The potential of the node B drops to the low power supply potential (VSS). 8 is turned on, and transistors 42, 44, and 49 are turned off. The signals output from terminals 35 and 36 are input to terminal 32. The signal input to 2 is at a low level potential (low power supply potential (VSS)). The pulse output circuit 23_1 is connected to the terminal 31 of the pulse output circuit 23_3 and the scanning line 21_1. It outputs a low-level potential (low power supply potential (VSS)).

[0064] At timing t2, a low-level potential (low power supply potential (VSS)) is input to the terminal 34. However, the signals output from terminals 35 and 36 do not change, and the pulse output circuit The line 23_1 supplies a low level to the terminal 31 of the pulse output circuit 23_3 and the scanning line 21_1. Outputs a voltage (low power supply voltage (VSS)).

[0065] At timing t3, a high-level potential (high power supply potential (VDD)) is input to terminal 32. At the timing t3, the potential of the node A (the source of the transistor 41) The potential of the other side of the drain (or the potential of the other side of the drain) is already at a high level (transferred from the high power supply potential (VDD) The potential of the transistor 41 is increased to a potential lower than the threshold voltage of the transistor 41. At this time, the terminal 32 is supplied with a high-level potential (high power supply potential (V DD)) is input, the capacitance coupling between the source and gate of transistors 43 and 48 As a result, the potential of the node A (potential of the gates of the transistors 43 and 48) further rises (block In addition, by performing this bootstrap operation, terminal 35 , the signal output from 36 is a high level potential (high power supply potential (VD Therefore, the pulse output circuit 23_1 does not fall from the pulse output circuit A high-level potential (high power supply potential (VDD)) is applied to the terminal 31 of 23_3 and the scanning line 21_1. Output.

[0066] At timing t4, a low-level potential (low power supply potential (VSS)) is input to terminal 31. At timing t5, a high-level potential (high power supply potential (VDD)) is applied to the terminal 33. However, the signals output from terminals 35 and 36 do not change, and pulses are output. The output circuit 23_1 outputs a high level signal to the terminal 31 of the pulse output circuit 23_3 and to the scanning line 21_1. The voltage of the input terminal (high power supply voltage (VDD)) is output.

[0067] At timing t6, a low-level potential (low power supply potential (VSS)) is input to terminal 32. At this time, due to the capacitive coupling between the source and gate of the transistors 43 and 48, The potential of node A (potential of the gates of transistors 43 and 48) drops (bootstrap operation). However, the potential of node A is still at a high level. Therefore, the signal input to the terminal 32 is , a signal output from the pulse output circuit 23_1. A low-level potential (low power supply potential (VSS)) is applied to the terminal 31 of the line 23_3 and the scanning line 21_1. ) is output.

[0068] At timing t7, a high-level potential (high power supply potential (VDD)) is input to terminal 34. At timing t7, the terminal 33 is also set to a high level potential (high power supply voltage). Therefore, both transistors 46 and 47 are in the ON state. As a result, the potential of node B becomes high level (high power supply potential (VDD) to The threshold voltage of transistor 46 or transistor 47 drops by the threshold voltage of the higher one. Therefore, the transistors 42, 44, and 49 are turned on. As a result, the potential of node A drops to a low level potential (low power supply potential (VSS)). As a result, the transistors 43 and 48 are turned off. At t7, the signals output from the terminals 35 and 36 are This signal is input to either the source or the drain. VSS). Therefore, the terminal 3 of the pulse output circuit 23_1 is 1 and the output signal to the scanning line 21_1 is at a low level potential (low power supply potential (VSS) ) will remain the same.

[0069] Next, the operation of the pulse output circuit 24_2 will be described. As shown in FIG. The pulse output circuit 24_2 operates in the same manner as the pulse output circuit 23_1. The output circuit 24_2 outputs clock signals (CKL1 to CKL4) in comparison with the pulse output circuit 23_1. , CKR1 to CKR4) operates with a delay of 1 / 8 cycle.

[0070] <(2-3) Operation of transistors 23_2···23_m and 24_1···24_m-1 Example> Example of operation of transistors 23_2···23_m and 24_1···24_m-1 This will be explained with reference to FIG. 8. FIG. 8(A) is a diagram excerpted from FIG. 5, and FIG. 8(B) 7B and 7C, the pulse output circuits 23_1 and 24_2 are connected to the scanning lines 21_1 and 21_2. The waveform of the signal output to 1_2 and the waveform of the signal input to the gates of the transistors 23_2 and 24_1 FIG. 10 is a diagram illustrating clock signals (CKR2, CKL3).

[0071] In the above-described display device, the pulse output circuit 23_1 scans as shown in FIG. The signal output to the line 21_1 changes from a high-level potential (high power supply potential (VDD)) to a low-level potential (VDD). The timing (ta) at which the voltage level changes to the low power supply voltage (VSS) is The signal (CKR2) changes from a low level potential (low power supply potential (VSS)) to a high level potential (high This coincides with the timing at which the power supply potential (VDD) is switched to the The timing (ta) coincides with the timing at which the transistor 24_1 changes from an off state to an on state. Similarly, when the signal output from the pulse output circuit 24_3 to the scanning line 21_2 is high, From high-level potential (high power supply potential (VDD)) to low-level potential (low power supply potential (VSS)) The timing (tb) at which the transistor 24_1 switches from the OFF state to the ON state is As a result, in the above-mentioned display device, the timing at which one end of the scanning line In addition, non-selection signals are input from both ends simultaneously. It is possible to suppress the difference in timing of the potential change at each point. The timing of switching of a plurality of transistors whose gates are connected to the scanning line is shifted. As a result, it is possible to suppress the occurrence of problems in the display device. This makes it possible to:

[0072] In the above-described display device, the transistors 23_2, 23_4, . . . 23_m , 24_1, 24_3, 24_m-1. The clock signals (CKL1 to CKR4) used to operate the That is, transistors 23_2, 23_4, 23_m, 24_1, 24_m, Wiring that supplies a new signal separately to control the switching of _3···24_m-1 Therefore, in the above-described display device, it is possible to efficiently narrow the frame. It is possible to do this.

[0073] <(3) Modifications of the Scanning Line Driving Circuits 23 and 24> The scanning line driving circuits 23 and 24 provided in the display device disclosed in this specification are the above-mentioned circuits. For example, the transistors 23_2, 23_m, 24_1, 24_2, and 24_3 are not limited to the above-mentioned circuits. The gate of _m-1 is connected to the wiring (CKL1 to CKL4, C KR1 to KR4), the pulse output circuit 23 1···23_m-1, 24_2···24_m-1. It is also possible to configure it as follows.

[0074] Specifically, if the pulse output circuit is as shown in FIG. 7(A), the configuration is as shown in FIG. 9. In the scanning line driving circuit 23 shown in FIG. The gates of the transistors (even numbers equal to or less than m-4) are connected to the terminal 35 of the pulse output circuit 23_c+3. The gate of the transistor 24_d (d is an odd number equal to or less than m-3) is connected to the end of the pulse output circuit 24_d+3. 9. Although not shown in FIG. 9, in FIG. 9, transistor 2 The gate of the transistor 3_m-2 is connected to the terminal 35 of the pulse output circuit 23_m-7. The gate of transistor 23_m is connected to terminal 35 of pulse output circuit 23_m-5. The gate of 4_m-1 is connected to a terminal 35 of a pulse output circuit 24_m-6.

[0075] Even when the scanning line driving circuits 23 and 24 shown in FIG. 9 are used, the scanning line driving circuits shown in FIG. The same effects as when the circuits 23 and 24 are used are achieved.

[0076] <3. Specific examples of transistors> What kind of transistors are used as the transistors included in the above-mentioned display device? For example, a transistor in which a channel is formed in a silicon film (a transistor in which a channel is formed in a silicon film) may be used. a transistor having a channel formation region or a transistor having a channel formed in an oxide semiconductor film a transistor (having a channel formation region in an oxide semiconductor film) in the display device described above; The present invention can be applied to a transistor included in the above.

[0077] The structure of the oxide semiconductor film will be described below.

[0078] Oxide semiconductor films are roughly classified into non-single-crystal oxide semiconductor films and single-crystal oxide semiconductor films. The non-single-crystal oxide semiconductor film is a CAAC-OS (C Axis Aligned Crystal Polycrystalline oxide semiconductor film The oxide semiconductor film includes a film, a microcrystalline oxide semiconductor film, an amorphous oxide semiconductor film, and the like.

[0079] First, the CAAC-OS film will be described.

[0080] The CAAC-OS film is one of the oxide semiconductor films that has multiple crystal parts aligned along the c-axis. .

[0081] The CAAC-OS film was observed under a transmission electron microscope (TEM). When observed under a tron ​​microscope, clear boundaries between the crystals are observed. It is not possible to confirm the grain boundary. It can be said that the AAC-OS film is less susceptible to the decrease in electron mobility caused by grain boundaries.

[0082] The CAAC-OS film was observed by TEM from a direction roughly parallel to the sample surface (cross-sectional TEM observation). When observed, it can be confirmed that metal atoms are arranged in layers in the crystalline part. Each layer of the CAAC-OS film is formed on a surface (also called a surface to be formed) or on a concave surface of the upper surface. The shape reflects the convexity and is aligned parallel to the surface on which the CAAC-OS film is formed or the upper surface.

[0083] In this specification, "parallel" means that two straight lines are at an angle of -10° or more and 10° or less. Therefore, it also includes the case where the angle is between -5° and 5°. "Perpendicular" refers to two straight lines that form an angle of 80° or more and 100° or less. Therefore, the angle may be between 85° and 95°.

[0084] On the other hand, the CAAC-OS film was observed by TEM from a direction approximately perpendicular to the sample surface (plane T EM observation reveals that metal atoms are arranged in triangular or hexagonal shapes in the crystalline region. However, no regularity was observed in the arrangement of metal atoms between different crystal regions. do not have.

[0085] Cross-sectional and planar TEM observations revealed that the crystals in the CAAC-OS film had an orientation. It can be seen that this is the case.

[0086] Most of the crystals in the CAAC-OS film are cubic crystals with sides of less than 100 nm. Therefore, the crystal part in the CAAC-OS film has a side length of 10 This also includes cases where the size fits within a cube of less than 5 nm, or less than 3 nm. However, multiple crystals in the CAAC-OS film are connected to form a single large crystal domain. For example, in a planar TEM image, 2 Over 5μm 2 or more than 1000μm 2 Crystal regions with more than this size may be observed.

[0087] X-ray diffraction (XRD) of the CAAC-OS film When structural analysis is performed using this device, for example, CAAC-OS with InGaZnO4 crystals can be seen. In the out-of-plane analysis of the film, the diffraction angle (2θ) peaks around 31°. This peak is attributed to the (009) plane of the InGaZnO4 crystal. Therefore, the crystals of the CAAC-OS film have a c-axis orientation, and the c-axis faces the surface on which the film is formed or the upper surface. It can be seen that the direction is roughly vertical.

[0088] On the other hand, the in-p X-rays incident on the CAAC-OS film are perpendicular to the c-axis. In the Lane analysis, a peak may appear around 2θ of 56°. The crystal structure of InGaZnO4 is composed of a single crystal of InGaZnO4. In the case of a nitride semiconductor film, 2θ is fixed at around 56°, and the normal vector of the sample surface is the axis (φ axis). When the sample is rotated and analyzed (φ scan), a crystal plane equivalent to the (110) plane is detected. In contrast, in the case of the CAAC-OS film, six peaks are observed, which are assigned to 2θ. Even when the φ is fixed at around 56° and scanned, no clear peak appears.

[0089] From the above, it can be concluded that the orientation of the a-axis and b-axis is uniform between different crystal regions in the CAAC-OS film. Although it is irregular, it has a c-axis orientation, and the c-axis is parallel to the normal vector of the surface on which it is formed or the upper surface. Therefore, the layered structure confirmed by the cross-sectional TEM observation mentioned above is consistent with the Each layer of arranged metal atoms is a plane parallel to the ab plane of the crystal.

[0090] The crystalline part is formed when the CAAC-OS film is formed or after a crystallization treatment such as a heat treatment. As described above, the c-axis of the crystal is aligned with the surface on which the CAAC-OS film is to be formed. Therefore, for example, in the CAAC-OS film, When the shape is changed by etching, the c-axis of the crystal is aligned with the CAAC-OS film. It may not be parallel to the normal vector of the face or top surface.

[0091] Furthermore, the distribution of c-axis oriented crystals in the CAAC-OS film does not need to be uniform. For example, the crystalline part of the CAAC-OS film is grown from the top surface of the CAAC-OS film. Therefore, when the crystal is formed, the region near the top surface has a crystal orientation that is more c-axis oriented than the region near the surface on which the crystal is formed. In addition, when impurities are added to the CAAC-OS film, the proportion of the impurity The region where the material was added is transformed, and regions with different proportions of c-axis oriented crystals are formed. It may also be possible.

[0092] In addition, the out-of-plane structure of the CAAC-OS film with InGaZnO4 crystals In the analysis by the method, in addition to the peak at 2θ near 31°, a peak also appeared at 2θ near 36°. The peak at 2θ around 36° is due to the presence of c-axis orientation in part of the CAAC-OS film. The CAAC-OS film contains crystals that do not have crystalline structure. It is preferable that the peak is exhibited at 2θ of about 36° and that the peak is not exhibited at 2θ of about 36°.

[0093] The CAAC-OS film is an oxide semiconductor film with a low concentration of impurities. The oxide semiconductor film is made of an element other than the main component, such as silicon or a transition metal element. The elements such as ZnO, which have stronger bonding strength with oxygen than the metal elements constituting the oxide semiconductor film, By removing oxygen from the oxide semiconductor film, the atomic arrangement of the oxide semiconductor film is disrupted, and the crystallinity is reduced. In addition, heavy metals such as iron and nickel, argon, and carbon dioxide are Because the diameter (or molecular radius) is large, when the molecule is contained inside the oxide semiconductor film, The impurities contained in the oxide semiconductor film are likely to disturb the atomic arrangement of the oxide semiconductor film, which may result in a decrease in crystallinity. The pure material may act as a carrier trap or a carrier generation source.

[0094] The CAAC-OS film is an oxide semiconductor film with a low density of defect states. Oxygen vacancies in semiconductor films can act as carrier traps and trap hydrogen. This can become a carrier generation source.

[0095] The low impurity concentration and low defect level density (low oxygen vacancies) are called high-purity intrinsic or The term "high-purity intrinsic" refers to a substantially high-purity intrinsic oxide semiconductor. Since the film has a small number of carrier generation sources, the carrier density can be reduced. The transistor using the oxide semiconductor film has electrical characteristics (noise) such that the threshold voltage is negative. It is also called "marine.") It is rare for it to become pure or substantially pure. An intrinsic oxide semiconductor film has few carrier traps. Transistors using this film have little fluctuation in electrical characteristics and are highly reliable. Note that it takes time for the charges trapped in the carrier traps in the oxide semiconductor film to be released. The time is long and the charge may behave as if it is fixed. Therefore, a transistor using an oxide semiconductor film with a high density of defect states has unstable electrical characteristics. This may be the case.

[0096] In addition, the electrical characteristics of transistors using CAAC-OS films are improved by irradiation with visible light or ultraviolet light. There is little gender variation.

[0097] Next, a microcrystalline oxide semiconductor film will be described.

[0098] In the microcrystalline oxide semiconductor film, crystal parts can be clearly seen in the TEM image. The crystal parts contained in the microcrystalline oxide semiconductor film may have a size of 1 nm or more and 100 nm or more. In particular, the size of the particles is between 1 nm and 10 nm. Nanocrystals (nc) are microcrystals with a diameter of 1 nm or less, or 1 nm to 3 nm. The oxide semiconductor film having nc-OS (nanocrystalline O The nc-OS film is called an oxide semiconductor film. In EM observation images, the grain boundaries may not be clearly visible.

[0099] The nc-OS film is a microscopic region (e.g., a region of 1 nm to 10 nm, especially a region of 1 nm or less). The nc-OS film has a periodic atomic arrangement in the region of 3 nm or less. There is no regularity in the crystal orientation between the crystal parts, and therefore no orientation is observed throughout the film. Therefore, the nc-OS film cannot be distinguished from an amorphous oxide semiconductor film depending on the analytical method. For example, XRD, which uses X-rays with a diameter larger than that of the crystal part, is used for nc-OS films. When structural analysis is performed using the device, the crystal plane is analyzed using the out-of-plane method. In addition, the peaks shown in the figure are not detected in the nc-OS film because the probe diameter is larger than that of the crystalline part. Electron beam diffraction (also called selected area electron beam diffraction) using an electron beam (for example, 50 nm or larger) When the diffraction pattern is changed to nc-OS film, a halo-like diffraction pattern is observed. The probe diameter is close to or smaller than the size of the crystal part (for example, 1 nm or more and 30 nm or less). When electron beam diffraction (also called nanobeam electron diffraction) is performed using the electron beam (bottom), Furthermore, when nanobeam electron diffraction is performed on the nc-OS film, a circular pattern is observed. In addition, a bright area (ring-shaped) may be observed for the nc-OS film. When performing nanobeam electron diffraction, multiple spots may be observed within a ring-shaped region. be.

[0100] The nc-OS film is an oxide semiconductor film with higher order than an amorphous oxide semiconductor film. Therefore, the nc-OS film has a lower density of defect states than the amorphous oxide semiconductor film. In the nc-OS film, there is no regularity in the crystal orientation between different crystal parts. The OS film has a higher density of defect states than the CAAC-OS film.

[0101] The oxide semiconductor film may be, for example, an amorphous oxide semiconductor film, a microcrystalline oxide semiconductor film, or a C The AAC-OS film may be a laminate film having two or more kinds of films.

[0102] <4. Examples of display modules> In the following, a display module having the above-described display device as one of its components will be described with reference to FIG. Please refer to the following for explanation.

[0103] The display module 8000 shown in FIG. 10 includes an upper cover 8001 and a lower cover 8002. Between them, touch panel 8004 connected to FPC8003 and A display panel 8006, a backlight unit 8007, a frame 8009, a printed circuit board The display module has a display board 8010 and a battery 8011. At least one of the components is not provided (for example, the backlight unit 8007, A configuration in which the battery 8011 or the touch panel 8004 is not provided may also be applied. It is Noh.

[0104] The above-mentioned display device corresponds to the display panel 8006 .

[0105] The upper cover 8001 and the lower cover 8002 are connected to the touch panel 8004 and the display panel The shape and dimensions can be changed as needed to fit the size of the 8006.

[0106] The touch panel 8004 is a resistive or capacitive touch panel. The display panel 8006 is overlapped with the opposing substrate (sealing substrate) of the display panel 8006. It is also possible to provide a touch panel function. It is also possible to provide an optical sensor in each pixel to create an optical touch panel. A touch sensor electrode is provided in each pixel of the display panel 8006, making it a capacitive touch panel. It is also possible to

[0107] The backlight unit 8007 includes a plurality of light sources 8008 arranged in a matrix. The backlight unit 8007 includes a linear light source and a light diffusion plate. In this case, the backlight unit 8007 may be configured to receive the light emitted by the linear light source. The linear light is diffused by a light diffusion plate and emitted as planar light.

[0108] The frame 8009 has a function of protecting the display panel 8006 and also a function of preventing the movement of the printed circuit board 8010. It also functions as an electromagnetic shield to block electromagnetic waves generated by the operation of the The frame 8009 may also function as a heat sink.

[0109] The printed circuit board 8010 includes a power supply circuit, a signal circuit for outputting a video signal and a clock signal. The power supply circuit is provided with a signal processing circuit. Alternatively, the power source may be a battery 8011 provided separately. 1 can be omitted if commercial power is used.

[0110] The display module 8000 also includes components such as a polarizing plate, a retardation plate, and a prism sheet. Additional ones may be provided.

[0111] <5. Examples of final products> An example of a final product manufactured using the above-described display device will be described below with reference to FIGS. 2 for further explanation.

[0112] The final product in question may be, for example, a television device (television or television receiver) (also known as computer monitors, digital cameras, digital video cameras, digital photo frames, mobile phones (also called mobile phones or mobile phone devices), portable game consoles , portable information terminals, audio playback devices, large game machines such as pachinko machines, etc. These final products have a curved display surface or can be arbitrarily folded. It is also possible to make it a possible product.

[0113] FIG. 11A is a diagram showing an example of a mobile phone. The mobile phone 7400 has a housing 74 In addition to the display unit 7402 incorporated in the 01, there are operation buttons 7403 and an external connection port 7404 , a speaker 7405, a microphone 7406, etc. The above-described display device is incorporated in the display portion 7402 .

[0114] In the mobile phone 7400 shown in FIG. 11A, when the surface of the display portion 7402 is touched with a finger or the like, By doing so, you can change the image displayed and perform other operations. The operation of inputting characters or the like can be performed by touching the surface of the display portion 7402 with a finger or the like. This can be done.

[0115] In addition, by operating the operation button 7403, the mobile phone 7400 can be started and stopped, and The above operations can be performed.

[0116] 11(B) is a diagram showing an example of a bangle-type display device. Bangle-type display device 7100 includes a housing 7101, a display unit 7102, operation buttons 7103, and a transmitting / receiving device 71 In the bangle-type display device 7100, the above-mentioned display device is provided as the display unit 7 It is incorporated into the 102.

[0117] The bangle-type display device 7100 can receive video signals through a transmitting / receiving device 7104. The received video can be displayed on the display unit 7102. In addition, the audio signal can be transmitted to other devices. It can also be sent to and received from the device.

[0118] In addition, the operation button 7103 can be used to start and stop the bangle-type display device 7100, It is possible to perform operations such as changing the image displayed, as well as adjusting the sound.

[0119] 12A is a diagram showing an example of a portable product. The portable product 7300 includes a housing 73 01, a display unit 7302, an operation button 7303, a drawer member 7304, and a control unit 7305. In the portable product 7300, the above-described display device is incorporated in the display portion 7302. It is being eaten.

[0120] The portable product 7300 is a rolled flexible surface in a cylindrical housing 7301. The display unit 7302 includes a first substrate on which a light-shielding layer or the like is formed, a The display portion 7302 is disposed in the housing 7301. The coil is wound so that the second substrate is always on the outside.

[0121] In addition, the portable product 7300 can receive a video signal through the control unit 7305. An image can be displayed on the display portion 7302. The control portion 7305 is also provided with a battery. In addition, the control unit 7305 is provided with a connector, and is configured to directly supply video signals and power. You may do so.

[0122] Also, operation buttons 7303 are used to start and stop the operation, change the displayed image, etc. The following operations can be performed.

[0123] FIG. 12B shows a state in which the display unit 7302 is pulled out by the pull-out member 7304. In this state, an image can be displayed on the display portion 7302. The operation button 7303 located on the front panel allows for easy operation with one hand.

[0124] In addition, the display unit 7302 is configured to bend when pulled out so that the display unit 7302 does not bend. A frame for reinforcement may be provided at the end of 02.

[0125] In addition to this configuration, a speaker is provided on the housing, and the audio signal received together with the video signal is output. The configuration may be such that sound is output. [Explanation of symbols]

[0126] 10 scan lines 101 scan lines 102 scan lines 11 Transistor 111 Transistor 112 transistors 12_1 pixels 12_2 pixels 121_1 pixels 121_2 pixels 122_1 pixels 122_2 pixels 13_1 Transistor 13_2 Transistor 131_1 Transistor 131_2 Transistor 132_1 Transistor 132_2 Transistor 14 Transistor 15_1 Transistor 15_2 Transistor 141 Shift Register 142 Shift Register 20 pixels 201 Transistor 202 Capacitor element 203 Liquid crystal element 21 scan lines 21_1~21_m scanning lines 22 Signal line 23 Scanning line driving circuit 24 Scanning line driving circuit 23_1 Pulse output circuit 23_3 Pulse output circuit 23_5 Pulse output circuit 23_m-1 Pulse output circuit 24_2 Pulse output circuit 24_4 Pulse output circuit 24_m Pulse output circuit 23_2 Transistor 23_4 Transistor 23_m Transistor 24_1 Transistor 24_3 Transistor 24_5 Transistor 24_m-1 Transistor 25 Signal line driver circuit Terminals 31 to 36 41~49 Transistors 7100 Bangle-type display device 7101 Housing 7102 Display section 7103 Operation button 7104 Transmitting and receiving equipment 7300 Portable Products 7301 Housing 7302 Display section 7303 Operation button 7304 Drawer parts 7305 Control Unit 7400 mobile phone 7401 Housing 7402 Display section 7403 Operation button 7404 External connection port 7405 Speaker 7406 Microphone 8000 Display Module 8001 Top cover 8002 Lower cover 8003 FPC 8004 Touch Panel 8005 FPC 8006 Display Panel 8007 Backlight Unit 8008 light source 8009 Frame 8010 Printed Circuit Board 8011 Battery

Claims

[Claim 1] a transistor having an oxide semiconductor film in a channel, the oxide semiconductor film has a plurality of crystal parts aligned along a c-axis, A scanning line is provided to one end of which a selection signal or a non-selection signal is input, a clock signal is input to the gate of the transistor, and the non-selection signal is input to the source of the transistor; The other end of the scanning line and the drain of the transistor are electrically connected, A display device in which the timing at which the signal input from one end to the scanning line switches from the selection signal to the non-selection signal is the same or approximately the same as the timing at which the transistor changes from an off state to an on state.

Images