Method of manufacturing fan-out packaging device and fan-out packaging device manufactured thereby

Abstract

To provide a method of manufacturing a fan-out packaging element which improves local flattening, expands a conduction path, and improves efficiency of an electrolytic plating process by constructing a metal sealing ring, and to provide the fan-out packaging element manufactured by the method.SOLUTION: Forming a first dielectric layer 100 in which a first via hole 120 is formed on a fan-out packaging substrate, forming a redistribution layer (RDL) 200 on the first dielectric layer and the first via hole, forming a second dielectric layer 300 in which a second via hole is formed on the redistribution layer, and forming a bump structure 400 connected to the redistribution layer on the second dielectric layer and the second via hole 320, wherein the redistribution layer includes a metal sealing ring 500, the plating process expands the conduction path.SELECTED DRAWING: Figure 5

Description

[Technical Field]

[0001] The present invention relates to a method for manufacturing a fan-out packaging device and a fan-out packaging device manufactured thereby, and more particularly to a method for manufacturing a fan-out packaging device in which a conductive path is expanded by forming a metal sealing ring, and a fan-out packaging device manufactured thereby. [Background technology]

[0002] Generally, the semiconductor packaging process includes the steps of wafer dicing, die attach, die interconnection, molding, and packaging test.

[0003] In the traditional semiconductor packaging process, after cutting the wafer, the packaging process is carried out on each cut wafer (substrate), but recently the "Wafer Level Packaging (WLP)" process is carried out while the die is maintained in the wafer state. This is a method in which the packaging process and test are carried out at once in the wafer state, and then cutting is carried out at the die terminal, which has the advantage of reducing package production costs compared to conventional methods.

[0004] In addition, research into the Panel Level Packaging (PLP) process, which goes beyond wafer level packaging, is also active. The PLP process has the advantage of being able to package a larger number of dies than the WLP process, further reducing production costs.

[0005] Meanwhile, as semiconductor devices become more highly integrated, perform better, and smaller, various packaging technologies are evolving based on the wafer level packaging or panel level packaging method, among which fan-in (wafer or panel level packaging) and fan-out (wafer or panel level packaging) technologies are being actively researched.

[0006] In particular, Fan-Out Wafer or Panel Level Packaging (hereinafter referred to as Fan-Out Wafer Level Packaging for convenience, and also referred to as "Fan Out WLP" or "FO-WLP" as needed) technology is a technology that uses a fan-out method to increase the number of I / O pins, and has the advantage of being able to secure a larger wiring formation surface compared to the die size by using a Re-Distribution Layer (RDL) process to expand the wiring formation range outside the die area.

[0007] In such a fan-out wafer level packaging process, the RDL process forms a dielectric layer on the surface of the die, then forms a wiring layer using copper plating, and if necessary, repeats these processes to extend the wiring formation area outside the die.

[0008] In the existing fan-out wafer-level packaging process, a thin Cu seed layer sputtered with an adhesion layer such as Ti or TiW is used to support the electroplating of the RDL (redistribution layer). That is, a thin Cu seed layer is formed using a sputtering process, and then an electroplating process is performed on top of it to form the RDL.

[0009] In this process, the thickness of the Cu seed layer is limited by the throughput of the sputtering equipment and the isotropic etching of the RDL lines that occurs during etching of the seed layer. In particular, for fine RDLs such as 2 μm L / S, the isotropic etching of the RDL lines must be limited due to the narrow line width, which requires a thinner seed layer.

[0010] The requirement for such a thinner seed layer limits plating speed and increases plating thickness non-uniformity, which reduces the efficiency of the electroplating process and results in increased production costs and reduced quality.

[0011] Additionally, local planarization must be improved to minimize the reduction in the thickness of the dielectric layer covering the edges of RDL lines and pads, which is critical to ensure electrical performance and structural integrity.

[0012] Also, as the thickness of the seed layer increases, the overall resistance increases if the conductive paths become insufficient. Therefore, although a faster plating speed can be achieved in the initial plating stage, the electrical performance may decrease as the thickness increases due to the lack of conductive paths.

[0013] In addition, improving the quality of the plating layer during the copper plating process is very important. Previously, attempts have been made to slow down the plating speed or improve the plating process conditions, but these have the problem of slowing down the process speed and making it difficult to ensure process reproducibility.

[0014] Furthermore, when multiple RDLs are formed, a dielectric layer is formed during the plating process, and if the plating quality is poor, the dielectric layer may become non-uniform, which leads to poor surface topology and defective wiring layers in the subsequent RDL process.

[0015] This can result in increased contact resistance and impedance, degrading electrical performance at low operating frequencies and thus reducing package performance. Summary of the Invention [Problem to be solved by the invention]

[0016] The present invention has been derived from the above-mentioned need, and its object is to provide a method for manufacturing a fan-out packaging device that improves local planarization, widens conductive paths, and increases the efficiency of an electroplating process by constructing a metal sealing ring, and a fan-out packaging device manufactured thereby. [Means for solving the problem]

[0017] To achieve the above object, the present invention provides a method for manufacturing a packaging device using a wafer level packaging process or a panel level packaging process, the method comprising the steps of: forming a first dielectric layer having a first via hole formed therein on a fan-out packaging substrate; forming a redistribution layer (RDL) on the first dielectric layer and the first via hole; forming a second dielectric layer having a second via hole formed therein on the redistribution layer; and forming a bump structure connected to the redistribution layer on the second dielectric layer and the second via hole, wherein the redistribution layer includes a metal sealing ring, and a conductive path is expanded by a plating process.

[0018] Another technical feature of the present invention is a packaging device using a wafer level packaging process or a panel level packaging process, comprising: a fan-out packaging substrate; a first dielectric layer formed on the fan-out packaging substrate and including first via holes that are formed and patterned to expose signal pads and ground pads of a die; a redistribution layer (RDL) formed on the first dielectric layer and the first via holes; a second dielectric layer formed on the redistribution layer and including second via holes that are formed and patterned to expose portions of the redistribution layer; and a bump structure formed on the second dielectric and the second via holes and connected to the redistribution layer, wherein the redistribution layer includes a metal sealing ring that extends a conductive path by a plating process.

[0019] Preferably, the metal sealing ring is formed along the outer periphery of the fan-out region of the fan-out packaging substrate.

[0020] In addition, it is preferable to form a first connection line that electrically connects the metal sealing rings formed on the outer peripheries of the adjacent fan-out regions to each other.

[0021] Also, a second connection line may be further formed to connect to the metal sealing ring so that a conduction path extends to an inactive region outside the fan-out region.

[0022] Preferably, the second connection line is formed along the periphery of the metal sealing ring and extends toward the edge of the non-active region.

[0023] Preferably, the second connection lines are discontinuously formed to face each other along the periphery of the metal sealing ring.

[0024] It is also preferable to form a third connection line for connecting the GND pad of the die to the metal sealing ring.

[0025] Also, it is preferable to form a fourth connection line for connecting the GND sealing ring of the die to the metal sealing ring.

[0026] Also, it is preferable to form a fifth connection line to connect a GND plane of the redistribution layer and the metal sealing ring.

[0027] In addition, it is preferable to form a third connection line for connecting the GND pad of the die to the metal sealing ring, a fourth connection line for connecting the GND sealing ring of the die to the metal sealing ring, and a fifth connection line for connecting the GND plane of the redistribution layer to the metal sealing ring, or to selectively form one or more of the third to fifth connection lines.

[0028] Also, a second connection line may be further formed to connect to the metal sealing ring so that a conduction path extends to an inactive region outside the fan-out region.

[0029] Also, it is preferable to repeat the first dielectric forming process to the redistribution layer forming process to form multiple redistribution layers / dielectric layers.

[0030] Preferably, the metal sealing rings formed on the multiple redistribution layers are electrically connected to each other by a first vertical connecting line.

[0031] Preferably, the metal sealing rings are formed on one or both sides of the redistribution layer, and when formed on both sides, they are electrically connected to each other by a second vertical connecting line. [Effects of the Invention]

[0032] The metal sealing ring of the present invention provides an additional conduction path, thereby distributing the current in the seed layer evenly over a wider area. In particular, when the seed layer is thin, there may not be enough conduction paths, but by adding a sealed metal sealing ring of the present invention, the conduction paths can be expanded.

[0033] In addition, the hermetic metal sealing ring according to the present invention provides an additional path for current to flow together with the seed layer, thereby expanding the conduction path, and therefore, when the thickness of the seed layer is increased, the overall resistance is reduced, which helps to improve the efficiency of the electrolytic plating process and accelerate the plating speed. As a result, if the current is uniformly distributed and the conduction path is sufficient, the uniformity of the plating thickness is also improved, allowing for the formation of a higher quality redistribution layer.

[0034] In particular, by additionally forming the hermetic metal sealing ring according to the present invention in a wafer level packaging process or a panel level packaging process, the process speed can be improved, production costs can be reduced, and overall package production costs can be reduced.

[0035] In addition, when multiple redistribution layers are formed, the hermetic metal sealing ring according to the present invention prevents unevenness of the dielectric layer formed between the redistribution layers, thereby reducing defects in the wiring layer during the subsequent redistribution layer formation process.

[0036] In addition, the hermetic metal sealing ring of the present invention improves the reproducibility of the electrolytic plating process, thereby maintaining consistent process conditions and providing a high-quality plating layer, while also enhancing the overall stability of the packaging structure and increasing resistance to mechanical and thermal stresses.

[0037] Furthermore, the redistribution layer structure of the present invention provides an initial short circuit path by connecting the GND plane of each layer to the hermetic metal sealing ring, thereby optimizing electrical performance and increasing the reliability of signal transmission. [Brief explanation of the drawings]

[0038] [Figure 1] 1A to 1C are side schematic views illustrating a method for manufacturing a fan-out packaging element according to an embodiment of the present invention. [Figure 2] 1 is a schematic diagram of a fan-out packaging device according to an embodiment of the present invention; [Figure 3] 2 is a schematic diagram showing a state in which a metal sealing ring is formed on a fan-out packaging substrate according to an embodiment of the present invention; [Figure 4] 2 is a schematic diagram showing a state in which a metal sealing ring and a connecting line are formed on a fan-out packaging substrate according to an embodiment of the present invention; [Figure 5] 1 is a schematic diagram of a fan-out packaging device according to another embodiment of the present invention; [Figure 6] 10 is a schematic diagram showing a state in which a metal sealing ring and a connection line are formed on a fan-out packaging substrate according to another embodiment of the present invention; [Figure 7] 10 is a schematic diagram showing a state in which a metal sealing ring and a connection line are formed on a fan-out packaging substrate according to another embodiment of the present invention; [Figure 8] 1 is a schematic diagram of a fan-out packaging device according to another embodiment of the present invention; DETAILED DESCRIPTION OF THE INVENTION

[0039] The present invention relates to a method for manufacturing a fan-out packaging device and a fan-out packaging device manufactured thereby, in which a metal sealing ring is formed to improve local planarization, widen conductive paths, and increase the efficiency of an electroplating process.

[0040] Therefore, the present invention has the advantage of improving electrical performance and structural stability in the fan-out packaging process, and increasing productivity.

[0041] Hereinafter, embodiments of the present invention will be described in detail with reference to the accompanying drawings. Fig. 1 is a side view showing a method for manufacturing a fan-out packaging device according to an embodiment of the present invention, Fig. 2 is a schematic view of a fan-out packaging device according to an embodiment of the present invention, Fig. 3 is a schematic view of a fan-out packaging substrate according to an embodiment of the present invention with a metal sealing ring formed on it, Fig. 4 is a schematic view of a fan-out packaging substrate according to an embodiment of the present invention with a metal sealing ring and a connecting line formed on it, Fig. 5 is a schematic view of a fan-out packaging device according to another embodiment of the present invention, Fig. 6 is a schematic view of a fan-out packaging substrate according to another embodiment of the present invention with a metal sealing ring and a connecting line formed on it, Fig. 7 is a schematic view of a fan-out packaging substrate according to another embodiment of the present invention with a metal sealing ring and a connecting line formed on it, and Fig. 8 is a schematic view of a fan-out packaging device according to another embodiment of the present invention.

[0042] As shown in the figure, a method for manufacturing a fan-out packaging device according to an embodiment of the present invention is a method for manufacturing a packaging device using a wafer level packaging process or a panel level packaging process, and includes the steps of forming a first dielectric layer 100 having a first via hole 120 formed therein on a fan-out packaging substrate 10, forming a redistribution layer (RDL) 200 on the first dielectric layer 100 and the first via hole 120, forming a second dielectric layer 300 having a second via hole 320 formed therein on the redistribution layer 200, and forming a bump structure 400 connected to the redistribution layer 200 on the second dielectric layer 300 and the second via hole 320, and is characterized in that the redistribution layer 200 includes a metal sealing ring 500, thereby expanding a conductive path during a plating process.

[0043] The fan-out packaging device according to an embodiment of the present invention manufactured in this manner is a packaging device using a wafer level packaging process or a panel level packaging process, and includes a fan-out packaging substrate, a first dielectric layer 100 formed on the fan-out packaging substrate 10 and including first via holes 120 that are formed and patterned to expose signal pads and ground pads of a die 11, a redistribution layer (RDL) 200 formed on the first dielectric layer 100 and the first via holes 120, a second dielectric layer 300 formed on the redistribution layer 200 and including second via holes 320 that are formed and patterned to expose portions of the redistribution layer 200, and a bump structure 400 formed on the second dielectric layer and the second via holes 320 and connected to the redistribution layer 200, and the redistribution layer 200 includes a metal sealing ring 500 that extends a conductive path through a plating process.

[0044] The present invention manufactures a packaging element using a wafer-level packaging process or a panel-level packaging process, and first forms a first dielectric layer 100 having a first via hole 120 formed on a fan-out packaging substrate 10 (FIGS. 1(a) and 1(b)).

[0045] The fan-out packaging substrate 10 according to an embodiment of the present invention is a wafer or substrate on which a single chip or a plurality of chip arrays are formed, or is provided by dicing such chips, reconstituting and arranging them on a wafer or panel, and then embedding the chips using EMC (Epoxy Molding Compound), etc. In the present invention, the terms "chip" and "die" 11 are used interchangeably.

[0046] In this way, by implementing the embedded die 11 on a wafer or panel, the input / output (I / O) signal pads 12 and GND pads 13 of the die 11 are exposed, and the areas other than the signal pads 12 and GND pads 13 are passivated and provided, and the outer area of ​​the die 11 is provided as a fan-out area F.

[0047] In one embodiment of the present invention, a first dielectric layer 100 is formed on a fan-out packaging substrate 10 including an embedded die 11 reassembled on a wafer or panel, and a first via hole 120 is formed in the first dielectric layer 100 to expose necessary areas, such as input / output (I / O) signal pads 12 and GND pads 13 of the die 11. In addition to the above locations, the first via hole 120 can also be formed in the die 11 area, the fan-out area F, and other areas.

[0048] The first dielectric layer 100 may be made of an organic or inorganic dielectric material, such as a polymer material such as polyimide, PBO (Polybenzoxazole), or BCB (Benzocyclobutene), or an inorganic material such as an oxide or nitride. Preferably, silicon nitride or silicon oxide may be used. In various embodiments, SiO2, SiO x , oxides such as Al2O3, ZrO2, Ta2O5, SiN x Nitrides such as SiN, ZrN, AlN, BN, TaN, and TaN can be used, and two or more materials can be mixed as needed. Also, the second dielectric layer 300 described below can be made of the same or different material.

[0049] Such a dielectric layer can be formed by a process such as spin coating, CVD (Chemical Vapor Deposition), sputtering, laminating, or a combination thereof, and can be formed by suitable physical and chemical vapor deposition processes. The first dielectric layer 100 is then patterned to form a via hole 120. The first via hole 120 is formed by an etching process during a patterning process, and is filled with metal to serve as an electrical connection path between upper and lower components.

[0050] A plurality of the first via holes 120 are formed in the first dielectric layer 100, thereby exposing a part of the die region and the fan-out region F or the active region A and the inactive region B. For example, by exposing the input / output (I / O) signal pads 12 and the GND pads 13 of the die 11, the redistribution layer 200 is connected to the signal pads 12 and the GND pads 13.

[0051] The via hole 120 can be filled with various metal materials such as aluminum (Al), tungsten (W), titanium (Ti), copper (Cu), etc., and can be filled by sputtering, atomic layer deposition (ALD), CVD, or electroplating processes.

[0052] According to an embodiment of the present invention, electrolytic plating is used, which has good step coverage and is excellent in cost and productivity, and copper is used as the metal material.

[0053] Then, a redistribution layer (RDL) 200 is formed on the first dielectric layer 100 and the first via hole 120 (FIG. 1(c)), and the redistribution layer 200 is electrically connected to the signal pad 12 and the GND pad 13 of the die 11. The redistribution layer 200 is realized by forming a metal layer on the first dielectric layer 100 and forming a metallization pattern thereof during or after the process of filling the first via hole 120 with a metal material.

[0054] The redistribution layer 200 according to one embodiment of the present invention is formed by electroplating a copper layer, which is then patterned and etched to form signal lines for redistribution of electrical connection wiring of the signal pads 12 or GND pads 13 exposed from the die 11.

[0055] The redistribution layer 200 can be realized as a single, multiple, or double-sided redistribution layer 200. That is, a multiple redistribution layer / dielectric layer is realized by repeatedly forming a dielectric layer and a metal layer (repeating the first dielectric forming process to the redistribution layer forming process), thereby forming a redistribution signal line in the fan-out region F.

[0056] In the present invention, particularly, during the process of forming the redistribution layer 200, a metal sealing ring 500 is formed in the redistribution layer 200.

[0057] The metal sealing ring 500 is formed simultaneously with or in a continuous process with the formation process of the redistribution layer 200, and is sealed in a specific area on the fan-out packaging substrate 10, i.e., it can be formed into a closed curved surface or closed shape that forms a closed circuit.

[0058] Preferably, it can be formed in a shape that surrounds the fan-out region F or the fan-out packaging substrate 10, and can be formed as a double or triple closed circuit if necessary, thereby providing a sealing ring that is hermetically sealed in a specific area without overlapping with the existing rerouted wiring circuit.

[0059] By forming such a metal sealing ring 500, a local planarization surface is provided by compensating for the reduction in thickness of the dielectric layer formed at the edges of the RDL line or pad, thereby providing an electrically and structurally planarized surface.

[0060] In addition, the metal sealing ring 500 provides an additional conductive path during the formation of the redistribution layer 200, and reduces the overall resistance by increasing the thickness of the seed layer, thereby helping to improve the efficiency of the electroplating process and accelerate the plating speed.

[0061] Generally, a seed layer provides a path for current to flow during an electrolytic plating process, and sufficient conductive paths are required for the current to flow uniformly during the electrolytic plating process. In other words, if the conductive paths are insufficient, the current cannot flow efficiently, resulting in a slower plating rate and increased non-uniformity in the plating thickness.

[0062] Therefore, the metal sealing ring 500 according to the present invention provides an additional conductive path, thereby helping to distribute the current in the seed layer more uniformly over a wider area. In particular, when the seed layer is thin, the conductive path may be insufficient, but adding the hermetic metal sealing ring 500 according to the present invention solves this problem.

[0063] Furthermore, as the thickness of the seed layer increases, if the conductive paths become insufficient, the overall resistance increases, thereby enabling a faster plating speed in the initial plating stage. However, as the thickness increases, the conductive paths become insufficient, which can lead to a decrease in electrical performance. However, in the present invention, by reducing the overall resistance through the metal sealing ring 500, current flows more efficiently during the electrolytic plating process, increasing the plating speed and improving the uniformity of the plating thickness.

[0064] That is, the hermetic metal sealing ring 500 according to the present invention provides an additional path for current to flow together with the seed layer, thereby expanding the conduction path, and therefore, when the thickness of the seed layer increases, the overall resistance is reduced, which helps to improve the efficiency of the electrolytic plating process and accelerate the plating speed. As a result, if the current is uniformly distributed and the conduction path is sufficient, the uniformity of the plating thickness is also improved, and a higher quality redistribution layer 200 can be formed.

[0065] In particular, by additionally forming the hermetic metal sealing ring 500 according to the present invention in the wafer level packaging process or panel level packaging process, the process speed can be improved, production costs can be reduced, and overall package production costs can be reduced.

[0066] In addition, when forming multiple redistribution layers 200, the hermetic metal sealing ring 500 according to the present invention prevents unevenness of the dielectric layer formed between the redistribution layers 200, thereby reducing defects in the wiring layer in the subsequent redistribution layer 200 formation process.

[0067] In addition, the hermetic metal sealing ring 500 according to the present invention improves the reproducibility of the electrolytic plating process, thereby maintaining consistent process conditions to provide a high-quality plating layer, and also enhances the overall stability of the packaging structure, increasing its resistance to mechanical and thermal stresses.

[0068] In addition, in this structure of multiple redistribution layers 200, the GND plane of each layer is connected to the hermetic metal sealing ring 500 to provide an initial short circuit path, thereby optimizing electrical performance and increasing the reliability of signal transmission.

[0069] Then, a second dielectric layer 300 having a second via hole 320 formed therein is formed on the redistribution layer 200 including the metal sealing ring 500, and a bump structure 400 connected to the redistribution layer 200 is formed on the second dielectric layer 300 and the second via hole 320 (FIGS. 1(d) and (e)).

[0070] The second dielectric layer 300 is formed using the same or similar material and process as the first dielectric layer 100 described above, and is patterned to form a second via hole 320, and a bump structure 400 connected to the redistribution layer 200 is formed on the second via hole 320.

[0071] When forming multiple redistribution layers 200, via holes are formed by patterning the second dielectric layer 300 in the same manner as the first dielectric layer 100, and the redistribution layers 200 are formed by a plating process, and then the redistribution layers 200 are connected to each other.

[0072] Here, when multiple redistribution layers 200 are formed, a metal sealing ring 500 is formed in each redistribution layer 200, and the metal sealing rings 500 formed in each redistribution layer 200 are electrically connected to each other via vertical connection lines (see FIG. 8).

[0073] In the embodiments of Figures 1(e) and 2, a first dielectric layer 100 is formed on a fan-out packaging substrate 10 including a single embedded die 11, a redistribution layer 200 is formed on the via hole and on top of the first dielectric layer 100, a second dielectric layer 300 and a second via hole 320 are formed on top of the first dielectric layer 100, and a bump structure 400 is formed on the second via hole 320 to connect to the redistribution layer 200.

[0074] The bump structure 400 according to the embodiment of the present invention is formed by forming an Under Bump Metallization (UBM) (depositing and patterning a Ti / Cu layer) on the second via hole 320 formed in the second dielectric layer 300, removing the solder plating and photoresist, removing unnecessary metal layers, and forming a solder bump by reflow. For the sake of convenience, the solder bump and UBM are referred to as the bump structure 400 in the present invention.

[0075] In this way, solder bumps can be formed at the wafer level or panel level, and additional or general packaging processes can be performed, after which the individual or modular fan-out packaging elements can be separated by a dicing process.

[0076] Specific embodiments of the present invention will be described below with reference to the accompanying drawings.

[0077] FIG. 3 is a schematic diagram showing a state in which a metal sealing ring 500 is formed on a fan-out packaging substrate 10 according to one embodiment of the present invention, and shows that the metal sealing ring 500 according to one embodiment of the present invention is formed along the periphery of the fan-out region F of the fan-out packaging substrate 10.

[0078] According to the embodiment of Figure 3, a first dielectric layer 100 and a first via hole 120 are formed on a fan-out packaging substrate 10 in which a single die 11 is embedded, and during the process of forming a redistribution layer 200 for forming a predetermined redistribution line, a metal sealing ring 500 is formed along the outer edge of the fan-out region F.

[0079] According to an embodiment of the present invention, the redistribution layer 200 is formed by an electrolytic plating process, and the metal sealing ring 500 is also formed by an electrolytic plating process, and copper is used as the metal material. In this figure, the description of the redistribution line is omitted.

[0080] The metal sealing ring 500 according to one embodiment of the present invention is formed at the outer periphery of the fan-out region F to compensate for the problem of reduced thickness of the dielectric layer at the edge and provide a locally planarized surface.

[0081] The metal sealing ring 500 serves to increase the efficiency of the electrolytic plating process and accelerate the plating speed by expanding additional conductive paths during the formation of the redistribution layer 200, thereby reducing the overall resistance when the thickness of the seed layer increases. As a result, if the current is uniformly distributed and the conductive paths are sufficient, the uniformity of the plating thickness is improved, and a higher quality redistribution layer 200 can be formed.

[0082] FIG. 4 is a schematic diagram showing a state in which a metal sealing ring 500 and a connecting line are formed on a fan-out packaging substrate 10 according to one embodiment of the present invention, in which the metal sealing ring 500 according to one embodiment of the present invention is formed along the outer periphery of the fan-out region F of the fan-out packaging substrate 10 and is formed so that the conductive path extends to the inactive region B outside the fan-out region F.

[0083] According to the embodiment of Figure 4, a first dielectric layer 100 and a first via hole 120 are formed on a fan-out packaging substrate 10 in which a single die 11 is embedded, and during the process of forming a redistribution layer 200 for forming a predetermined redistribution line, a metal sealing ring 500 is formed along the outer edge of the fan-out region F, and a second connecting line 620 is formed to extend the conductive path to the inactive region B outside the fan-out region F.

[0084] According to an embodiment of the present invention, the redistribution layer 200 is formed by an electrolytic plating process, and the metal sealing ring 500 is also formed by an electrolytic plating process, and copper is used as the metal material. In this figure, the description of the redistribution line is omitted.

[0085] The second connection line 620 is formed along the periphery of the metal sealing ring 500 and extends toward the edge of the non-active region B.

[0086] In addition, the second connection lines 620 are discontinuously formed along the periphery of the metal sealing ring 500 so as to face each other.

[0087] That is, the second connecting lines 620 are formed in the non-active region B outside the fan-out region F so as to extend along the periphery or are formed discontinuously so as to face each other along the periphery, thereby distributing the conductive paths uniformly throughout the fan-out region F and its outer regions, thereby improving the structural stability of the packaging structure and improving plating uniformity.

[0088] According to one embodiment of the present invention, the metal sealing ring 500 and the second connecting line 620 are formed on the outer edge of the fan-out region F and in the non-active region B outside the fan-out region F, thereby compensating for the problem of reduced thickness of the dielectric layer at the edge and providing a locally planarized surface.

[0089] The metal sealing ring 500 and the second connecting line 620 expand additional conductive paths during the formation of the redistribution layer 200. Therefore, when the thickness of the seed layer increases, the overall resistance is reduced, which helps to increase the efficiency of the electrolytic plating process and accelerate the plating speed. As a result, if the current is uniformly distributed and the conductive paths are sufficient, the uniformity of the plating thickness is improved, and a higher quality redistribution layer 200 can be formed.

[0090] Additionally, forming the second connecting lines 620 in the non-active area B outside the fan-out area F enhances the overall stability of the packaging structure and increases resistance to mechanical and thermal stresses.

[0091] FIG. 5 is a schematic diagram of a fan-out packaging device according to another embodiment of the present invention, and FIG. 6 is a schematic diagram of a fan-out packaging substrate 10 according to another embodiment of the present invention, on which a metal sealing ring 500 and a connecting line are formed.

[0092] According to the embodiment of Figures 5 and 6, two dies 11 are included, and metal sealing rings 500 are formed along the outer periphery of the fan-out region F of each die 11, and first connecting lines 610 are formed to electrically connect each adjacent metal sealing ring 500 to each other.

[0093] According to the embodiments of Figures 5 and 6, a first dielectric layer 100 and a first via hole 120 are formed on a fan-out packaging substrate 10 in which two dies 11 are embedded, and during the process of forming a redistribution layer 200 for forming predetermined redistribution lines, a metal sealing ring 500 is formed along the outer periphery of each fan-out region F, and a first connecting line 610 is formed to electrically connect these metal sealing rings 500 to each other.

[0094] According to an embodiment of the present invention, the redistribution layer 200 is formed by an electrolytic plating process, and the metal sealing ring 500 is also formed by an electrolytic plating process, and copper is used as the metal material. In this figure, the description of the redistribution line is omitted.

[0095] The first connection line 610 is formed along the periphery of the metal sealing ring 500 and is discontinuously formed to extend toward the edge of the non-active region B, thereby connecting the adjacent metal sealing rings 500 .

[0096] Here, the second connection lines 620 are formed along the periphery of the metal sealing ring 500, extending toward the edge of the non-active region B, and discontinuously formed to face each other along the periphery of the metal sealing ring 500.

[0097] In the non-active region B outside the fan-out region F, the first connecting line 610 and the second connecting line 620 are formed to extend along the periphery of the metal sealing ring 500 or are formed discontinuously so as to face each other along the periphery, thereby distributing the conductive paths uniformly throughout the fan-out region F and its surrounding regions, thereby ensuring the structural stability of the packaging structure and promoting plating uniformity.

[0098] That is, the first connection line 610 and the second connection line 620 are formed in the non-active region B, and the first connection line 610 connects the metal sealing rings 500 formed on the outer periphery of adjacent fan-out regions F to each other, and the second connection line 620 is formed in the non-active region B outside the remaining fan-out region F. Here, when the third and fourth embedded dies 11 are formed, the metal sealing rings 500 formed on the outer periphery of each fan-out region F can be connected to each other by the first connection line 610, and the second connection line 620 is formed in the non-active region B at the edge of the fan-out packaging substrate 10.

[0099] According to one embodiment of the present invention, the metal sealing ring 500, the first connecting line 610, and the second connecting line 620 are formed on the outer edge of the fan-out region F and in the non-active region B outside the fan-out region F, thereby compensating for the problem of a reduction in the thickness of the dielectric layer at the edge and providing a locally planarized surface.

[0100] The metal sealing ring 500, the first connecting line 610, and the second connecting line 620 extend additional conductive paths during the formation of the redistribution layer 200. Therefore, when the thickness of the seed layer increases, the overall resistance is reduced, which helps to increase the efficiency of the electrolytic plating process and accelerate the plating speed. As a result, if the current is uniformly distributed and the conductive paths are sufficient, the uniformity of the plating thickness is improved, and a higher quality redistribution layer 200 can be formed.

[0101] In addition, the first and second connection lines 610 and 620 are formed in the non-active area B outside the fan-out area F to enhance the overall stability of the packaging structure and increase resistance to mechanical and thermal stresses.

[0102] FIG. 7 is a schematic diagram showing a state in which a metal sealing ring 500 and connection lines are formed on a fan-out packaging substrate 10 according to another embodiment of the present invention.

[0103] The embodiment of Figure 7 is similar to the embodiment of Figure 6 in that a third connection line 630 is formed to connect the GND pad 13 of the die 11 to the metal sealing ring 500, a fourth connection line 640 is formed to connect the GND sealing ring 14 of the die 11 to the metal sealing ring 500, and a fifth connection line 650 is formed to connect the GND plane 15 of the redistribution layer 200 to the metal sealing ring 500.

[0104] The third connecting line 630 to the fifth connecting line 650 may all be formed or one or more may be selectively formed depending on the type of packaging or wiring environment.

[0105] Here, it is natural that a second connection line 620 can be formed that is connected to the metal sealing ring 500 so that the conductive path extends to the inactive area B outside the fan-out area F, and when multiple embedded dies 11 are formed, a first connection line 610 can also be formed that electrically connects the metal sealings formed on the outer edges of each fan-out area F to each other.

[0106] In addition, the redistribution layer 200 structure connects the GND plane 15 of each layer with the hermetic metal sealing ring 500 to provide an initial short circuit path, thereby optimizing electrical performance and increasing the reliability of signal transmission. According to one embodiment of the present invention, the metal sealing ring 500 and the first to fifth connecting lines 610 to 650 are formed to extend the conductive path and compensate for the problem of reduced thickness of the dielectric layer at the edges, thereby providing a locally planarized surface.

[0107] That is, the metal sealing ring 500 and the first connecting line 610 to the fifth connecting line 650 expand additional conductive paths during the formation of the redistribution layer 200. Therefore, when the thickness of the seed layer increases, the overall resistance is reduced, which helps to increase the efficiency of the electroplating process and accelerate the plating speed. As a result, if the current is uniformly distributed and the conductive paths are sufficient, the uniformity of the plating thickness is improved, and a higher quality redistribution layer 200 can be formed.

[0108] In addition, by forming the first connecting line 610 and the second connecting line 620 in the non-active area B outside the fan-out area F together with the metal sealing ring 500, the overall stability of the packaging structure is enhanced and resistance to mechanical stress and thermal stress is increased.

[0109] 8 is a schematic diagram of a fan-out packaging device according to another embodiment of the present invention. The embodiment of FIG. 8 embodies multiple redistribution layers 200 / dielectric layers by repeating the processes of forming the first dielectric layer 100 through the redistribution layer 200, and includes a fan-out packaging substrate / first dielectric layer / first redistribution layer 200 / second dielectric layer 300 / second redistribution layer 200 / third dielectric layer / bump structure 400. Metal sealing rings 500 formed on the multiple redistribution layers 200 can be electrically connected to each other by first vertical connecting lines 660.

[0110] In addition, the metal sealing ring 500 may be formed on one side or both sides of the redistribution layer 200, and when formed on both sides, they may be electrically connected to each other by a second vertical connection line (not shown).

[0111] In addition, in this structure of multiple redistribution layers 200, the GND plane 15 of each layer is connected to the hermetic metal sealing ring 500 to provide an initial short circuit path, thereby optimizing electrical performance and increasing the reliability of signal transmission.

[0112] In this way, the metal sealing ring of the present invention provides an additional conduction path, allowing the current in the seed layer to be distributed evenly over a wider area.In particular, when the seed layer is thin, there may not be enough conduction paths, but by adding a hermetic metal sealing ring of the present invention, the conduction paths can be expanded.

[0113] In addition, the hermetic metal sealing ring according to the present invention provides an additional path for current to flow together with the seed layer, thereby expanding the conduction path, and thus, when the thickness of the seed layer increases, the overall resistance is reduced, which helps to improve the efficiency of the electrolytic plating process and accelerate the plating speed. As a result, if the current is uniformly distributed and the conduction path is sufficient, the uniformity of the plating thickness is also improved, and a higher quality redistribution layer can be formed.

[0114] In particular, by additionally forming the hermetic metal sealing ring according to the present invention in a wafer level packaging process or a panel level packaging process, the process speed can be improved, production costs can be reduced, and overall package production costs can be reduced.

[0115] In addition, when forming multiple redistribution layers, the hermetic metal sealing ring according to the present invention prevents unevenness of the dielectric layer formed between the redistribution layers, thereby reducing defects in the wiring layer during the subsequent redistribution layer formation process.

[0116] Additionally, the hermetic metal sealing ring according to the present invention improves the reproducibility of the electrolytic plating process, thereby maintaining consistent process conditions and providing a high-quality plating layer, while also enhancing the overall stability of the packaging structure and increasing resistance to mechanical and thermal stresses.

[0117] Furthermore, the redistribution layer structure of the present invention provides an initial short circuit path by connecting the GND plane of each layer to the hermetic metal sealing ring, thereby optimizing electrical performance and increasing the reliability of signal transmission. [Explanation of symbols]

[0118] 10 Fan-out packaging substrate 11 Die 12 Signal Pads 13 GND pad 14 GND sealing ring 15 GND plane 100 First dielectric layer 120 Beer Hall No. 1 200 redistribution layer 300 Second dielectric layer 320 Second Beer Hall 400 bump structure 500 Metal Sealing Ring 610 First Connecting Line 620 Second Connecting Line 630 Third Connecting Line 640 4th Connecting Line 650 5th Connecting Line 660 First Vertical Connecting Line F fan-out region A active area B Inactive area

Claims

1. A method for manufacturing a packaging device using a wafer level packaging process or a panel level packaging process, forming a first dielectric layer having a first via hole formed therein on the fan-out packaging substrate; forming a redistribution layer (RDL) on the first dielectric layer and the first via hole; forming a second dielectric layer having a second via hole formed therein on the redistribution layer; forming a bump structure connected to the redistribution layer on the second dielectric layer and the second via hole; The redistribution layer includes a metal sealing ring, and a conductive path is expanded by a plating process.

2. 2. The method of claim 1, wherein the metal sealing ring is formed along an outer periphery of the fan-out region of the fan-out packaging substrate.

3. 3. The method of claim 2, further comprising forming a first connection line electrically connecting the metal sealing rings formed on the outer peripheries of the adjacent fan-out regions to each other.

4. 4. The method of claim 3, further comprising forming a second connection line connected to the metal sealing ring so that a conduction path extends to an inactive region outside the fan-out region.

5. 5. The method of claim 4, wherein the second connection line is formed to extend along the periphery of the metal sealing ring toward an edge of the non-active region.

6. 5. The method of claim 4, wherein the second connection lines are discontinuously formed to face each other along the periphery of the metal sealing ring.

7. 4. The fan-out packaging device of claim 3, further comprising forming a third connection line for connecting the GND pad of the die to the metal sealing ring.

8. 4. The method of claim 3, further comprising forming a fourth connection line for connecting a GND sealing ring of a die to the metal sealing ring.

9. 4. The method of claim 3, further comprising forming a fifth connection line to connect a GND plane of the redistribution layer and the metal sealing ring.

10. forming a third connection line for connecting a GND pad of the die to the metal sealing ring, a fourth connection line for connecting the GND sealing ring of the die to the metal sealing ring, and a fifth connection line for connecting a GND plane of the redistribution layer to the metal sealing ring; or 4. The method of claim 3, wherein one or more of the third to fifth connecting lines are selectively formed.

11. 11. The method of claim 10, further comprising forming a second connection line connected to the metal sealing ring so that a conduction path extends to an inactive region outside the fan-out region.

12. 2. The method of claim 1, wherein the first dielectric forming process to the redistribution layer forming process are repeated to form multiple redistribution layers / dielectric layers.

13. 13. The method of claim 12, wherein the metal sealing rings formed in the multiple redistribution layers are electrically connected to each other by a first vertical connecting line.

14. 2. The method of claim 1, wherein the metal sealing rings are formed on one or both sides of the redistribution layer, and when formed on both sides, are electrically connected to each other by second vertical connecting lines.

15. A packaging device using a wafer level packaging process or a panel level packaging process, a fan-out packaging substrate; a first dielectric layer formed on the fan-out packaging substrate and patterned to include first via holes exposing signal and ground pads of a die; a redistribution layer (RDL) formed on the first dielectric layer and the first via hole; a second dielectric layer formed on the redistribution layer and patterned to include a second via hole exposing a portion of the redistribution layer; a bump structure formed on the second dielectric and the second via hole and connected to the redistribution layer; The fan-out packaging device, wherein the redistribution layer includes a metal sealing ring and extends a conductor path through a plating process.

16. The fan-out packaging device of claim 15, wherein the metal sealing ring is formed along an outer periphery of the fan-out region of the fan-out packaging substrate.

17. 17. The fan-out packaging device of claim 16, further comprising a first connection line electrically connecting the metal sealing rings formed on the outer peripheries of the adjacent fan-out regions to each other.

18. 18. The fan-out packaging device of claim 17, further comprising a second connection line connected to the metal sealing ring so that a conductive path extends to an inactive region outside the fan-out region.

19. 20. The fan-out packaging device of claim 18, wherein the second connection line is formed along the periphery of the metal sealing ring and extends toward an edge of the non-active region.

20. 20. The fan-out packaging device of claim 18, wherein the second connection lines are discontinuously formed to face each other along the periphery of the metal sealing ring.

21. 18. The fan-out packaging device of claim 17, further comprising a third connection line for connecting a GND pad of a die to the metal sealing ring.

22. 18. The fan-out packaging device of claim 17, further comprising a fourth connection line for connecting a GND sealing ring of a die to the metal sealing ring.

23. The fan-out packaging device of claim 17, wherein a fifth connection line is formed to connect a GND plane of the redistribution layer and the metal sealing ring.

24. a third connection line for connecting a GND pad of the die to the metal sealing ring, a fourth connection line for connecting the GND sealing ring of the die to the metal sealing ring, and a fifth connection line for connecting a GND plane of the redistribution layer to the metal sealing ring are formed; or 18. The fan-out packaging device of claim 17, wherein one or more of the third to fifth connecting lines are selectively formed.

25. 25. The fan-out packaging device of claim 24, wherein a second connection line is formed connected to the metal sealing ring so that a conductive path extends to an inactive region outside the fan-out region.

26. 16. The fan-out packaging device of claim 15, wherein multiple redistribution layers / dielectric layers are formed by repeating the first dielectric forming process to the redistribution layer forming process.

27. 27. The fan-out packaging device of claim 26, wherein the metal sealing rings formed in the multiple redistribution layers are electrically connected to each other by a first vertical interconnection line.

28. 16. The fan-out packaging device of claim 15, wherein the metal sealing rings are formed on one or both sides of the redistribution layer, and when formed on both sides, are electrically connected to each other by second vertical connecting lines.

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