Method of manufacturing fan-out packaging device and fan-out packaging device manufactured thereby

Abstract

To provide a method of manufacturing a fan-out packaging element which reduces wiring density of a rewiring layer and improves electrical and mechanical reliability by forming an additional GND layer, and to provide the fan-out packaging element.SOLUTION: A method of manufacturing a packaging device using a wafer level packaging process or a panel level packaging process includes forming an additional GND layer 100 on a partial region of a fan-out packaging substrate 10, forming a first dielectric layer 200 having a first via hole 220 formed therein on the additional GND layer, forming a redistribution layer 300 on the first dielectric layer and the first via hole, forming a second dielectric layer 400 having a second via hole 420 formed therein on the redistribution layer, and forming a bump structure 500 connected to the redistribution layer on the second dielectric layer and the second via hole. The additional GND layer is formed on four sides or at least two opposite sides of the die 11.SELECTED DRAWING: Figure 3

Description

[Technical Field]

[0001] The present invention relates to a method for manufacturing a fan-out packaging device and a fan-out packaging device manufactured thereby, and more particularly to a method for manufacturing a fan-out packaging device that provides a high-performance, high-reliability fan-out packaging device by forming an additional GND layer, and a fan-out packaging device manufactured thereby. [Background technology]

[0002] The eight major processes in semiconductor manufacturing are the wafer process, oxidation process, photo process, etching process, thin film process, wiring process, test process and packaging process, which are carried out in this order.

[0003] The present invention relates to a packaging process in a semiconductor manufacturing process, and generally, the semiconductor packaging process includes the steps of wafer dicing, die attach, die interconnection, molding, and packaging test.

[0004] While the traditional semiconductor packaging process involves cutting wafers and then carrying out the packaging process, the recent trend is to carry out the "Wafer Level Packaging (WLP)" process while maintaining the die in wafer form. This process involves carrying out the packaging process and testing at once in wafer form, and then cutting the die (chips), which has the advantage of reducing package production costs compared to conventional methods.

[0005] In addition, research into the Panel Level Packaging (PLP) process, which goes beyond wafer level packaging, is also active. This has the advantage of being able to package a larger number of dies than the WLP process, further reducing production costs.

[0006] Meanwhile, as semiconductor devices become more highly integrated, perform better, and smaller, various packaging technologies are evolving based on the wafer level packaging or panel level packaging method, and fan-in (wafer or panel level packaging) and fan-out (wafer or panel level packaging) technologies are being actively researched.

[0007] In particular, Fan-Out Wafer or Panel Level Packaging (hereinafter referred to as Fan-Out Wafer Level Packaging for convenience, and also referred to as "Fan Out WLP" or "FO-WLP" as needed) technology is a fan-out technology that increases the number of I / O pins. It uses a Re-Distribution Layer (RDL) process to expand the wiring formation area outside the die area, thereby securing a wiring formation surface that is larger than the die size.

[0008] In such fan-out wafer level packaging, the RDL process forms a dielectric layer on the surface of the die, then forms a wiring layer using copper plating, and if necessary, repeats these processes to extend the wiring formation area outside the die.

[0009] In other words, the RDL optimizes the connections inside the package by rearranging the chip's input / output (I / O) signal pads. However, in a high-density wiring environment, the RDL layout becomes very complicated, which can cause many problems during the manufacturing process. In particular, as the number of connections between chips increases, the wiring density of the RDL layer increases, which can lead to reduced electrical performance and increased manufacturing costs.

[0010] In addition, in order to improve the yield and contact resistance of the wiring layer in the RDL process, it is very important to improve the quality of the plating layer in the copper plating process.

[0011] In order to improve the quality of such plating layers, attempts have been made to slow down the plating speed or improve the plating process conditions, but this slows down the process speed and does not ensure process reproducibility.

[0012] Furthermore, when forming such RDL wiring layers in multiple layers, a dielectric layer is formed during the plating process, which can lead to problems such as unevenness of the dielectric layer and deterioration of surface topology due to deterioration of the quality of the plating layer, ultimately resulting in defects in the wiring layer during the subsequent RDL process, which in turn leads to increased contact resistance and impedance and a low operating frequency. Summary of the Invention [Problem to be solved by the invention]

[0013] The present invention has been devised to solve the above problems, and its object is to provide a method for manufacturing a fan-out packaging device that reduces the wiring density of a redistribution layer by forming an additional GND layer, improves electrical and mechanical reliability, improves plating speed and plating quality, and increases the efficiency of the manufacturing process, and a fan-out packaging device manufactured thereby. [Means for solving the problem]

[0014] To achieve the above object, the present invention provides a method for manufacturing a packaging device using a wafer-level packaging process or a panel-level packaging process, the method comprising the steps of: forming an additional ground plane (GND) layer on a portion of a fan-out packaging substrate; forming a first dielectric layer having a first via hole formed therein on the additional ground plane; forming a re-distribution layer (RDL) on the first dielectric layer and the first via hole; forming a second dielectric layer having a second via hole formed therein on the re-distribution layer; and forming a bump structure connected to the re-distribution layer on the second dielectric layer and the second via hole, wherein the additional GND layer is formed in the direction of four sides or at least two opposing sides of the die.

[0015] In order to achieve the above object, the present invention provides a packaging device using a wafer level packaging process or a panel level packaging process, comprising: a fan-out packaging substrate; an additional GND layer formed on a portion of the fan-out packaging substrate; a first dielectric layer formed on the additional GND layer and including a first via hole; a redistribution layer (RDL) formed on the first dielectric layer and the first via hole; a second dielectric layer formed on the redistribution layer and including a second via hole that is patterned to expose a portion of the redistribution layer; and a bump structure formed on the second dielectric and the second via hole and connected to the redistribution layer, wherein the additional GND layer is formed in the direction of four surfaces or at least two opposing surfaces of the die.

[0016] In addition, it is preferable that the additional GND layer according to the embodiment of the present invention is electrically connected to a GND seal ring or a GND pad to provide a rebuilt GND seal ring or a rebuilt pad.

[0017] In addition, the additional GND layer may include a wiring line for die-to-die connection.

[0018] Preferably, an insulating layer having an additional via hole formed therein is formed between the fan-out packaging substrate and the additional GND layer.

[0019] Preferably, the additional via hole is connected to a GND pad and a signal pad by filling the additional GND layer, thereby forming a reconstructed pad by the additional GND layer at the position of the additional via hole.

[0020] Preferably, the additional via hole is formed by applying a laser direct imaging method.

[0021] The insulating layer is preferably formed to have a thickness of 2 μm or less.

[0022] Also, it is preferable that the first dielectric forming process to the redistribution layer forming process be repeated to implement multiple redistribution layers / dielectric layers.

[0023] Also, the additional GND layer is preferably connected to all or some of the GND planes formed in the subsequent redistribution layer.

[0024] In addition, during the process of forming the redistribution layer, it is preferable to form a sealed metal sealing ring on the outer periphery of the fan-out packaging substrate to provide an additional conduction path.

[0025] In addition, it is preferable that the hermetic metal sealing ring is connected to an additional GND layer by a vertical connection part, or when formed in a multiple redistribution layer / dielectric layer structure, it is connected to a lower layer hermetic metal sealing ring by a vertical connection part and to an additional GND layer by a vertical connection part. [Effects of the Invention]

[0026] According to an embodiment of the present invention, by forming an additional GND layer in a fan-out packaging device, an additional conduction path is provided during the process of forming a redistribution layer, which improves the plating speed and ensures uniformity of the plating layer (redistribution layer), thereby ensuring uniformity of the dielectric layer and redistribution layer formed later and reducing defects in the redistribution layer, which is particularly useful when forming multiple redistribution layers.

[0027] Furthermore, the additional GND layer according to the present invention ensures the reproducibility and process safety of the electrolytic plating process, thereby allowing the process conditions to be maintained constant, thereby providing a plating layer (redistribution layer) of high reproducibility and quality.

[0028] In addition, the additional GND layer according to the present invention is formed as a large plane on four sides or at least two opposing sides of the die, thereby enhancing the overall stability of the packaging structure and increasing resistance to mechanical and thermal stresses.

[0029] Furthermore, the additional GND layer according to the present invention efficiently dissipates heat, thereby improving the thermal management performance of the semiconductor device and ensuring stable operation of the high performance fan-out packaging device.

[0030] Additionally, embodiments of the present invention may provide improved local planarization, wider conductive paths, and more efficient electroplating processes by forming a metal sealing ring on the fan-out packaging device.

[0031] Furthermore, according to an embodiment of the present invention, an insulating layer is formed between the fan-out packaging substrate and the additional GND layer, thereby providing electrical insulation between the fan-out packaging substrate and the additional GND layer and alleviating the difference in physical properties between the surface of the fan-out packaging substrate and the thin additional GND layer, i.e., the stress that occurs when the additional GND layer is formed directly on the fan-out packaging substrate, i.e., the mechanical stress, thereby improving the structural safety of the fan-out packaging device and ensuring its long-term reliability.

[0032] In addition, the additional via holes in the insulating layer formed according to an embodiment of the present invention are formed on the signal pads and GND pads of the die, and are filled on the via holes in the insulating layer to form reconstructed pads using the additional GND layer, thereby compensating for die position errors. Furthermore, they can also serve as a reference when forming via holes in the dielectric layer and redistribution layer formed thereon, thereby improving the overall precision of via formation. This improves the accuracy of electrical connections and ensures the reproducibility of the manufacturing process.

[0033] In addition, the thin insulating layer formed on the fan-out substrate and the additional GND layer according to the embodiment of the present invention allows small via holes to be formed and a planarized surface to be maintained after the via holes are filled, and also facilitates lamination of the subsequent metal layer (additional GND layer), thereby improving the efficiency and reliability of the entire process. [Brief explanation of the drawings]

[0034] [Figure 1] 1 is a schematic front view of a fan-out packaging device according to an embodiment of the present invention; [Figure 2] 1 is a schematic front view of a fan-out packaging device according to an embodiment of the present invention; [Figure 3] 1A and 1B are schematic side views of fan-out packaging devices according to various embodiments of the present invention; [Figure 4]1A and 1B are schematic side views of fan-out packaging devices according to various embodiments of the present invention; [Figure 5] 1A and 1B are schematic side views of fan-out packaging devices according to various embodiments of the present invention; [Figure 6] 1A and 1B are schematic side views of fan-out packaging devices according to various embodiments of the present invention; [Figure 7] 1A and 1B are schematic side views of fan-out packaging devices according to various embodiments of the present invention; [Figure 8] 1A and 1B are schematic side views of fan-out packaging devices according to various embodiments of the present invention; [Figure 9] 2 is a schematic diagram of a hermetic metal sealing ring formed according to an embodiment of the present invention; DETAILED DESCRIPTION OF THE INVENTION

[0035] The present invention relates to a method for manufacturing a fan-out packaging device and a fan-out packaging device manufactured thereby, and by forming an additional GND layer, it is possible to reduce the wiring density of a redistribution layer, improve electrical and mechanical reliability, improve plating speed and plating quality, and improve the efficiency of the manufacturing process.

[0036] Therefore, the present invention provides a high performance and highly reliable fan-out packaging device in the fan-out packaging process.

[0037] Hereinafter, embodiments of the present invention will be described in detail with reference to the accompanying drawings, in which Figures 1 and 2 are schematic front views of fan-out packaging devices according to embodiments of the present invention, Figures 3 to 8 are schematic side views of fan-out packaging devices according to various embodiments of the present invention, and Figure 9 is a schematic view of a state in which a hermetic metal sealing ring is formed according to an embodiment of the present invention.

[0038] As shown in the figures, a method for manufacturing a fan-out packaging device according to an embodiment of the present invention is a method for manufacturing a packaging device using a wafer-level packaging process or a panel-level packaging process, and includes the steps of forming an additional ground plane (GND) layer 100 on a portion of a fan-out packaging substrate 10, forming a first dielectric layer 200 having a first via hole 220 formed therein on the additional GND layer 100, forming a re-distribution layer (RDL) 300 on the first dielectric layer 200 and the first via hole 220, forming a second dielectric layer 400 having a second via hole 420 formed therein on the re-distribution layer 300, and forming a bump structure 500 connected to the re-distribution layer 300 on the second dielectric layer 400 and the second via hole 420, wherein the additional GND layer 100 is formed in the direction of four sides or at least two opposing sides of the die 11.

[0039] The fan-out packaging device according to an embodiment of the present invention manufactured as described above is a packaging device using a wafer level packaging process or a panel level packaging process, and includes: a fan-out packaging substrate; an additional GND layer 100 formed on a portion of the fan-out packaging substrate 10; a first dielectric layer 200 formed on the additional GND layer 100 and including a first via hole 220; a redistribution layer (RDL) 300 formed on the first dielectric layer 200 and the first via hole 220; a second dielectric layer 400 formed on the redistribution layer 300 and patterned to include a second via hole 420 exposing a portion of the redistribution layer 300; and a bump structure 500 formed on the second dielectric and the second via hole 420 and connected to the redistribution layer 300, wherein the additional GND layer 100 is formed in the direction of four sides or at least two opposing sides of the die 11.

[0040] The present invention manufactures a packaging device using a wafer level packaging process or a panel level packaging process, and first forms an additional GND layer 100 on a partial region of a fan-out packaging substrate 10 .

[0041] The fan-out packaging substrate 10 according to an embodiment of the present invention is a wafer or substrate on which a single chip or a plurality of chip arrays are formed, or is provided by dicing such chips, re-constituting and arranging them on a wafer or panel, and then embedding the chips using EMC (Epoxy Molding Compound), etc. In the present invention, the terms "chip" and "die" 11 are used interchangeably.

[0042] In this way, by implementing the embedded die 11 on a wafer or panel, the input / output (I / O) signal pads 12 of the die 11 are exposed, and the area other than the signal pads 12 is passivated and provided, and the outer area of ​​the die 11 is provided as a fan-out area F.

[0043] In one embodiment of the present invention, an additional GND layer 100 is formed on a partial area of ​​the fan-out packaging substrate 10 that is reconstructed on a wafer or panel and includes an embedded die 11 .

[0044] The additional GND layer 100 may be formed in a partial region of the fan-out packaging substrate 10 in the direction of four sides of the die 11 or at least two opposing sides thereof.

[0045] That is, when forming the additional GND layer 100 on the fan-out packaging substrate 10 in which the die 11 is embedded and the signal input / output (I / O) pads and GND input / output (I / O) pads (GND pads) 13 of the die 11 are exposed on the upper side, the additional GND layer 100 is formed in the directions of the four sides centered on the die 11, or formed so as to face the directions of at least the two opposing sides.

[0046] For example, when a single die 11 is embedded, the additional GND layer 100 can be formed in the direction of the four sides of the die 11 or in the direction of the two opposing sides, and when multiple dies 11 are embedded, the additional GND layer 100 can be formed in the direction of the three sides of the die 11 and between the dies 11 (the remaining side).

[0047] FIG. 1 shows a case where two dies 11 are embedded, with GND layers formed along three sides of the dies 11 and between the dies 11 (on the remaining side), while FIG. 2 shows a case where additional GND layers 100 are formed along the two opposing sides, and the GND layer is formed between the dies 11 in the form of a wiring line 110 for die-to-die connection.

[0048] That is, the additional GND layer 100 according to the present invention may be formed in a planar shape around the periphery of the die 11, and may be formed in the form of a wiring line 110 for connecting the input / output signal pads 12 between the dies 11 in a specific region.

[0049] Generally, in fan-out packaging technology, as the electrical connections between chips increase in the process of integrating multiple dies 11 into a single package, the wiring density of the redistribution layer 300 increases rapidly, which can cause problems such as signal interference and power loss.

[0050] By connecting the dies 11 to each other by the additional GND layer 100 in the form of the wiring line 110 according to one embodiment of the present invention, the wiring density of the next redistribution layer 300 can be reduced, wiring space can be secured, and electrical performance can be improved.

[0051] 1 and 2, an additional GND layer 100 is electrically connected to a GND seal ring 14 or a GND pad 13 to provide a rebuilt GND seal ring 120 or a rebuilt pad 130. That is, the additional GND layer 100 is formed on the GND seal ring 14 or the GND pad 13 to provide the rebuilt GND seal ring 120 or the rebuilt pad 130, which is then connected to a wiring line of the next redistribution layer 300 to provide a reconstituted GND seal ring 14 or a reconstituted pad by the redistribution layer 300.

[0052] In this way, by forming the additional GND layer 100, the present invention provides more conductive paths to support the electrolytic plating process during the process of forming the redistribution layer 300, thereby increasing the plating speed and improving the quality of the plating layer (redistribution layer 300).

[0053] In addition, the additional GND layer 100 according to the present invention ensures the uniformity of the plating layer (redistribution layer 300), thereby ensuring the uniformity of the dielectric layer and redistribution layer 300 to be formed later, and reducing defects in the redistribution layer, which is a more noticeable effect when multiple redistribution layers are formed.

[0054] Furthermore, the additional GND layer 100 according to the present invention ensures the reproducibility and process safety of the electrolytic plating process, thereby allowing the process conditions to be maintained constant, thereby providing a high-quality plating layer with high reproducibility.

[0055] In addition, the additional GND layer 100 according to the present invention is formed as a large plane on four sides or at least two opposing sides of the die 11, thereby enhancing the overall stability of the packaging structure and increasing resistance to mechanical and thermal stresses.

[0056] Furthermore, the heat is efficiently dispersed through the additional GND layer 100 according to the present invention, thereby improving the thermal management performance of the semiconductor device and ensuring stable operation of the high performance fan-out packaging device.

[0057] Then, a first dielectric layer 200 having a first via hole 220 formed therein is formed on the additional GND layer 100 .

[0058] The first dielectric layer 200 according to the embodiment of the present invention is formed of an organic or inorganic dielectric material, and may be formed of a polymer material such as polyimide, PBO (Polybenzoxazole), BCB (Benzocyclobutene), etc., or an inorganic material such as oxide or nitride. Preferably, silicon nitride or silicon oxide may be used. In various embodiments, SiO2, SiO x , oxides such as Al2O3, ZrO2, Ta2O5, SiN x Nitrides such as SiN, ZrN, AlN, BN, TaN, and TaN can be used, and two or more materials can be mixed and used as needed. Also, the second dielectric layer 400 described below can be made of the same or different material.

[0059] Such a dielectric layer can be formed by a process such as spin coating, CVD (Chemical Vapor Deposition), sputtering, laminating, or a combination thereof, and can be formed by suitable physical and chemical vapor deposition processes. The first dielectric layer 200 is then patterned to form a first via hole 220. The first via hole 220 is formed by an etching process during a patterning process, and is filled with metal to form an electrical connection path between upper and lower components.

[0060] A plurality of first via holes 220 are formed in the first dielectric layer 200, thereby exposing a portion of the die 11 region and the fan-out region F or the active region A and the inactive region B. For example, by exposing the input / output (I / O) signal pads 12 and the GND pads 13 of the die 11, the redistribution layer 300 is connected to the signal pads 12 and the GND pads 13.

[0061] The first via hole 220 may be filled with various metal materials such as aluminum (Al), tungsten (W), titanium (Ti), copper (Cu), etc., and may be filled by sputtering, atomic layer deposition (ALD), CVD, or electroplating processes.

[0062] According to an embodiment of the present invention, electrolytic plating is used, which has good step coverage and is excellent in cost and productivity, and copper is used as the metal material.

[0063] Then, a redistribution layer (RDL) 300 is formed on the first dielectric layer 200 and the first via hole 220, so that the redistribution layer 300 is electrically connected to the signal pad 12 and the GND pad 13 of the die 11. The redistribution layer 300 is realized by forming a metal layer on the first dielectric layer 200 and forming a metallization pattern thereof during or after the process of filling the first via hole 220 with a metal material.

[0064] The redistribution layer 300 according to one embodiment of the present invention is formed by electroplating a copper layer, and then patterning and etching the copper layer to form signal lines for redistribution of electrical connection wiring of the signal pads 12 or GND pads 13 exposed from the die 11.

[0065] The redistribution layer 300 can be realized as a single, multiple, or double-sided redistribution layer 300. That is, a multiple redistribution layer / dielectric layer is realized by repeatedly forming a dielectric layer and a metal layer (the processes from forming the first dielectric layer 200 to forming the redistribution layer 300 are repeated) to form a redistribution signal line in the fan-out region F.

[0066] The redistribution layer 300 can be realized as a single, multiple, or double-sided redistribution layer 300. That is, a multiple redistribution layer / dielectric layer is realized by repeatedly forming a dielectric layer and a metal layer (the processes from forming the first dielectric layer 200 to forming the redistribution layer 300 are repeated) to form a redistribution signal line in the fan-out region F.

[0067] According to an embodiment of the present invention, when formed as multiple redistribution layers / dielectric layers, the additional GND layer 100 is connected to each or all of the GND planes 15 formed in the subsequent redistribution layer 300, providing an initial short circuit path, thereby optimizing electrical performance and increasing the reliability of signal transmission.

[0068] In the present invention, particularly, during the process of forming the redistribution layer 300, a metal sealing ring 700 may be formed in the redistribution layer 300.

[0069] The metal sealing ring 700 is formed simultaneously with or in a continuous process with the formation process of the redistribution layer 300, and is sealed in a specific area on the fan-out packaging substrate 10, i.e., it can be formed into a closed curved surface or closed shape that forms a closed circuit.

[0070] Preferably, it can be formed in a shape that surrounds the fan-out region F or the fan-out packaging substrate 10, i.e., in the active region A or the non-active region B, and can be formed as a double or triple closed circuit as needed. Thus, a metal sealing ring 700 is provided that does not overlap with the existing rerouted wiring circuit but seals in a specific area.

[0071] By forming such a metal sealing ring 700, a local planarization surface is provided by compensating for the reduction in the thickness of the dielectric layer formed at the edges of the wiring lines and pads of the redistribution layer, thereby providing an electrically and structurally planarized surface.

[0072] In addition, the hermetic metal sealing ring 700 according to the embodiment of the present invention provides an additional path for current to flow together with the seed layer, thereby expanding the conductive path, and thus reducing the overall resistance as the thickness of the seed layer increases, thereby helping to improve the efficiency of the electrolytic plating process and accelerate the plating speed. As a result, if the current is distributed uniformly and the conductive path is sufficient, the uniformity of the plating thickness is improved, allowing for the formation of a higher quality redistribution layer.

[0073] In particular, by additionally forming the hermetic metal sealing ring 700 according to the present invention in the wafer level packaging process or panel level packaging process, the process speed can be improved, production costs can be reduced, and overall package production costs can be reduced.

[0074] In addition, when forming multiple redistribution layers 300, the hermetic metal sealing ring 700 according to the present invention can prevent unevenness of the dielectric layer formed between the redistribution layers 300, thereby reducing defects in the wiring layer in the subsequent redistribution layer 300 formation process.

[0075] In addition, since the hermetic metal sealing ring 700 according to the present invention is formed along the edge of the fan-out region F or the edge of the non-active region B, it enhances the overall stability of the packaging structure and increases resistance to mechanical and thermal stress.

[0076] In addition, in this structure of multiple redistribution layers 300, the GND plane of each layer is connected to the hermetic metal sealing ring 700 to provide an initial short circuit path, thereby optimizing electrical performance and increasing the reliability of signal transmission.

[0077] Then, a second dielectric layer 400 having a second via hole 420 formed therein is formed on the redistribution layer 300, and a bump structure 500 connected to the redistribution layer 300 is formed on the second dielectric layer 400 and the second via hole 420.

[0078] The second dielectric layer 400 is formed using the same or similar material and process as the first dielectric layer 200 described above, and is patterned to form a second via hole 420, and a bump structure 500 connected to the redistribution layer 300 is formed on the second via hole 420.

[0079] Furthermore, according to an embodiment of the present invention, the processes of forming the first dielectric layer 200 to the redistribution layer 300 may be repeated to implement multiple redistribution layers / dielectric layers.

[0080] That is, the redistribution layer 300 according to the embodiment of the present invention may be implemented as a single, multiple, or double-sided redistribution layer 300. That is, multiple redistribution layers / dielectric layers are implemented by repeatedly forming dielectric layers and metal layers (repeating the process of forming the first dielectric layer 200 to the process of forming the redistribution layer 300), thereby forming redistribution signal lines in the fan-out region F.

[0081] When formed as multiple redistribution layers / dielectric layers according to an embodiment of the present invention, the additional GND layer 100 is connected to each or all of the GND planes 15 formed in the subsequent redistribution layer 300 to provide an initial short-circuit path, thereby optimizing electrical performance and increasing the reliability of signal transmission.

[0082] Furthermore, when multiple redistribution layers 300 are formed, the hermetic metal sealing ring 700 is formed in each redistribution layer 300, and the hermetic metal sealing rings 700 formed in each redistribution layer 300 are electrically connected to each other by vertical connectors 720 and to the additional GND layer 100 according to the present invention through the vertical connectors 720. Thus, an initial short circuit path is provided, optimizing electrical performance and improving reliability of signal transmission. Of course, even when a single redistribution layer 300 is formed, the hermetic metal sealing ring 700 is connected to the additional GND layer 100 through the vertical connectors 720.

[0083] 1 to 3, a first dielectric layer 200 is formed on a fan-out packaging substrate 10 including two embedded dies 11, a redistribution layer 300 is formed on the via holes and the first dielectric layer 200, a second dielectric layer 400 and a second via hole 420 are formed thereon, and a bump structure 500 is formed on the second via hole 420 to connect to the redistribution layer 300. In the embodiment of FIG. 2, the two embedded dies 11 are connected by an additional GND layer 100 in the form of a wiring line 110. In the embodiments of FIGS. 4 to 8, the above structure is formed on a fan-out packaging substrate 10 including a single embedded die 11.

[0084] The bump structure 500 according to the embodiment of the present invention is formed by forming an Under Bump Metallization (UBM) (depositing and patterning a Ti / Cu layer) on the second via hole 420 formed in the second dielectric layer 400, removing the solder plating and photoresist, removing unnecessary metal layers, and forming a solder bump by reflow. For the sake of convenience, the solder bump and UBM are referred to as the bump structure 500 in the present invention.

[0085] In this way, solder bumps can be formed at the wafer level or panel level, and additional or general packaging processes can be performed, after which the fan-out packaging elements of the units or modules can be separated by a dicing process.

[0086] Meanwhile, according to the embodiment of the present invention, it is preferable to form an insulating layer 600 having an additional via hole 620 formed between the fan-out packaging substrate 10 and the additional GND layer 100 .

[0087] The insulating layer 600 is thinly formed on the entire surface of the fan-out packaging substrate 10, and an additional via hole 620 is formed to expose a portion of the die 11, and the signal pad 12, GND pad 13, or GND seal ring 14 of the die 11 is electrically connected to the upper redistribution layer 300 through the additional via hole 620.

[0088] The insulating layer 600 according to the embodiment of the present invention is formed of an organic or inorganic insulating material, and may be formed of a polymer material such as polyimide, PBO (Polybenzoxazole), BCB (Benzocyclobutene), etc., or an inorganic material such as oxide or nitride. Preferably, silicon nitride or silicon oxide may be used. In addition, in various embodiments, SiO2, SiO x , oxides such as Al2O3, ZrO2, Ta2O5, SiN x Nitrides such as Si3N4, ZrN, AlN, BN, TaN, and TaN can be used, and two or more materials can be mixed as needed.

[0089] The insulating layer 600 can be formed by a process such as spin coating, chemical vapor deposition (CVD), sputtering, laminating, or a combination thereof, and can be formed by a suitable physical or chemical vapor deposition process.

[0090] The insulating layer 600 is formed between the fan-out packaging substrate 10 and the additional GND layer 100 to provide electrical insulation between the fan-out packaging substrate 10 and the additional GND layer 100 and to relieve the difference in physical properties between the surface of the fan-out packaging substrate 10 and the thin additional GND layer 100, i.e., the stress, i.e., mechanical stress, that occurs when the additional GND layer 100 is formed directly on the fan-out packaging substrate 10. This improves the structural stability of the fan-out packaging device and ensures its long-term reliability.

[0091] In addition, the insulating layer 600 is formed thinly to have a thickness of 2 μm or less, thereby reducing the size of the vias and maintaining flatness in subsequent processes.

[0092] The insulating layer 600 is then patterned to form an additional via hole 620. The additional via hole 620 can be formed by a basic photolithography patterning process, and the additional via hole 620 is filled with metal by a separate metal filling process (such as a plating process) or simultaneously with the formation of the additional GND layer 100 to form a via. This serves as an electrical connection path connecting the pad elements of the die 11 and the redistribution layer 300.

[0093] According to an embodiment of the present invention, the additional via hole 620 is connected to the GND pad 13 and the signal pad 12 by metal filling when forming the additional GND layer 100, and a reconstructed pad 130 is formed by the additional GND layer 100 at the position of the additional via hole 620.

[0094] The insulating layer 600 can be formed thin, having a thickness of 2 μm or less, and smaller via holes can be formed in the insulating layer 600. The smaller via holes are filled during the formation process of the next metal layer (additional GND layer 100) to form a flatter surface, which makes it easier to stack vias on the next dielectric layer.

[0095] The additional via hole 620 and the reconstructed GND seal ring 120 or the reconstructed pad 130 may be formed by applying a laser direct imaging method. This involves directly exposing a desired via pattern to the insulating layer 600 with a laser, selectively hardening or removing the portion where the via pattern is to be formed. Then, the insulating layer 600 is chemically or physically etched along the exposed pattern to form the via hole.

[0096] Here, the additional via hole 620 formed by etching is formed to precisely mate with the signal pad 12 or the GND pad 13 of the die 11, allowing for very accurate control of the via position and size. That is, the additional via hole 620 of the insulating layer 600 is formed on the signal pad 12 or the GND pad 13 of the die 11 and is filled on the via hole of the insulating layer 600 to form a reconstructed pad 130 by the additional GND layer 100, thereby compensating for positional errors of the die 11. Furthermore, it can also serve as a reference when forming via holes in the dielectric layer and redistribution layer 300 formed thereon, thereby improving the overall precision of via formation. This improves the accuracy of electrical connection and ensures reproducibility of the manufacturing process.

[0097] In addition, the thin insulating layer 600 formed on the fan-out substrate and the additional GND layer 100 according to the embodiment of the present invention allows small via holes to be formed, thereby maintaining a planarized surface after filling the via holes. In addition, stacking of the subsequent metal layer (additional GND layer 100) is facilitated, thereby improving the efficiency and reliability of the entire process.

[0098] Specific embodiments of the present invention will be described below with reference to the accompanying drawings.

[0099] Fig. 1 is a diagram showing a case where two dies 11 are embedded and GND layers are formed along three sides of the dies 11 and between the dies 11 (on the remaining side), and Fig. 2 is a diagram showing a case where additional GND layers 100 are formed along two opposing sides, and the GND layer is formed between the dies 11 in the form of wiring lines 110 for die-to-die connection. Fig. 3 is a side view schematic diagram of a fan-out packaging device when two dies 11 are embedded according to an embodiment of the present invention.

[0100] That is, the additional GND layer 100 according to the present invention can be formed in a planar shape around the periphery of the die 11, or in a specific region, can be formed in the form of a wiring line 110 for connecting the input / output signal pads 12 between the dies 11.

[0101] Generally, in fan-out packaging technology, in the process of integrating many dies 11 into a single package, the electrical connections between the chips increase, and the wiring density of the redistribution layer 300 increases rapidly, which can cause problems such as signal interference and power loss.

[0102] By connecting the dies 11 to each other with an additional GND layer 100 in the form of a wiring line 110 according to one embodiment of the present invention, the wiring density of the next redistribution layer 300 can be reduced, thereby securing wiring space and improving electrical performance.

[0103] 1 to 3, the additional GND layer 100 is electrically connected to the GND seal ring 14 or the GND pad 13 to provide a rebuilt GND seal ring 120 or a rebuilt pad 130. That is, the additional GND layer 100 is formed on the GND seal ring 14 or the GND pad 13 to provide the rebuilt GND seal ring 120 or the rebuilt pad 130, and is connected to the wiring line of the next redistribution layer 300.

[0104] In this way, by forming the additional GND layer 100, the present invention provides more conductive paths to support the electrolytic plating process during the process of forming the redistribution layer 300, thereby increasing the plating speed and improving the quality of the plating layer (redistribution layer 300).

[0105] Furthermore, the additional GND layer 100 according to the present invention ensures the uniformity of the plating layer (redistribution layer 300), thereby ensuring the uniformity of the dielectric layer and redistribution layer 300 to be formed later and reducing defects in the redistribution layer 300. This effect is more noticeable when multiple redistribution layers 300 are formed.

[0106] Furthermore, the additional GND layer 100 according to the present invention ensures the reproducibility and process safety of the electrolytic plating process, thereby allowing the process conditions to be maintained constant, thereby providing a high-quality plating layer with high reproducibility.

[0107] In addition, the additional GND layer 100 according to the present invention is formed as a large plane on four sides or at least two opposing sides of the die 11, thereby enhancing the overall stability of the packaging structure and increasing resistance to mechanical and thermal stresses.

[0108] 4 to 8 are schematic side views of fan-out packaging devices according to various embodiments of the present invention, and FIG. 9 is a schematic view of a state in which a hermetic metal sealing ring 700 is formed according to an embodiment of the present invention.

[0109] In Figures 4 and 5, according to an embodiment of the present invention, an insulating layer 600 is formed on a fan-out packaging substrate 10, and an additional GND layer 100 is formed while filling an additional via hole 620 in the insulating layer 600, thereby providing a reconstructed GND seal ring 120 and a reconstructed GND pad 130 by the additional GND layer 100 at the positions of the GND seal ring 14 and GND pad 13 of the die 11, respectively.

[0110] In FIG. 6, according to an embodiment of the present invention, an insulating layer 600 is formed on a fan-out packaging substrate 10, and an additional GND layer 100 is formed while filling an additional via hole 620 in the insulating layer 600, thereby providing a reconstructed GND seal ring 120 and a reconstructed GND pad 130 by the additional GND layer 100 at the positions of the GND seal ring 14 and GND pad 13 of the die 11.

[0111] 7, according to an embodiment of the present invention, an insulating layer 600 is formed on a fan-out packaging substrate 10, and an additional GND layer 100 is formed while filling additional via holes 620 in the insulating layer 600, thereby providing a reconstructed GND seal ring 120 and a reconstructed pad 130 by the additional GND layer 100 at the positions of the GND seal ring 14 and the GND pad 13 of the die 11. Here, a multiple redistribution layer 300 is formed.

[0112] In FIG. 7, the additional GND layer 100 is connected to each or all of the GND planes 15 formed in the subsequent redistribution layer 300 to provide an initial short circuit path, thereby optimizing electrical performance and increasing the reliability of signal transmission.

[0113] 8, according to an embodiment of the present invention, an insulating layer 600 is formed on a fan-out packaging substrate 10, and an additional GND layer 100 is formed while filling an additional via hole 620 in the insulating layer 600, thereby providing a reconstructed GND seal ring 120 and a reconstructed pad 130 by the additional GND layer 100 at the positions of the GND seal ring 14 and GND pad 13 of the die 11. Here, a multiple redistribution layer 300 is formed. In particular, during the formation of the redistribution layer 300, a metal sealing ring 700 is formed within the redistribution layer 300.

[0114] The metal sealing ring 700 is formed simultaneously with or in a continuous process with the formation of the redistribution layer 300, and is formed as a sealing ring in a specific area on the fan-out packaging substrate 10, i.e., as a closed surface or closed figure that forms a closed circuit.

[0115] Preferably, the metal sealing ring is formed in a shape that surrounds the fan-out region F or the fan-out packaging substrate 10, i.e., in the active region A or the non-active region B, and can be formed as a double or triple closed circuit as needed. This provides a metal sealing ring 700 that seals a specific area while not overlapping with the existing rerouted wiring circuit. Figures 8 and 9 are diagrams showing a metal sealing ring 700 formed in the non-active region B to surround the fan-out packaging substrate 10.

[0116] By forming such a metal sealing ring 700, a local planarized surface is provided by compensating for the reduction in thickness of the dielectric layer formed at the edges of the wiring lines and pads of the redistribution layer 300, thereby providing an electrically and structurally planarized surface.

[0117] In addition, the hermetic metal sealing ring 700 according to the embodiment of the present invention provides an additional path for current to flow together with the seed layer, thereby expanding the conductive path, and thus reducing the overall resistance as the thickness of the seed layer increases, thereby helping to improve the efficiency of the electrolytic plating process and accelerate the plating speed. As a result, if the current is uniformly distributed and the conductive path is sufficient, the uniformity of the plating thickness is also improved, allowing the formation of a higher quality redistribution layer 300.

[0118] In particular, by additionally forming the hermetic metal sealing ring according to the present invention in a wafer level packaging process or a panel level packaging process, the process speed can be improved, production costs can be reduced, and overall package production costs can be reduced.

[0119] In addition, when forming multiple redistribution layers, the hermetic metal sealing ring according to the present invention can prevent unevenness of the dielectric layer formed between the redistribution layers, thereby reducing defects in the wiring layer during the formation process of the subsequent redistribution layers.

[0120] Furthermore, the hermetic metal sealing ring according to the present invention is formed along the periphery of the fan-out area and non-active area, thereby enhancing the overall stability of the packaging structure and increasing resistance to mechanical and thermal stresses.

[0121] In addition, this multi-redistribution layer structure provides an initial short circuit path by connecting the GND plane of each layer with a sealed metal sealing ring, optimizing electrical performance and increasing the reliability of signal transmission.

[0122] In this way, by forming an additional GND layer in a fan-out packaging device according to an embodiment of the present invention, an additional conduction path is provided during the process of forming the redistribution layer, thereby improving the plating speed and ensuring uniformity of the plating layer (redistribution layer), thereby ensuring uniformity of the dielectric layer and redistribution layer formed later and reducing defects in the redistribution layer, which is particularly useful when forming multiple redistribution layers.

[0123] Furthermore, the additional GND layer according to the present invention ensures the reproducibility and process safety of the electrolytic plating process, thereby allowing the process conditions to be maintained constant, thereby providing a plating layer (redistribution layer) of high reproducibility and quality.

[0124] Furthermore, the additional GND layer according to the present invention is formed as a large plane on four sides or at least two opposing sides of the die, thereby enhancing the overall stability of the packaging structure and increasing resistance to mechanical and thermal stresses.

[0125] Furthermore, the additional GND layer according to the present invention efficiently dissipates heat, improving the thermal management performance of the semiconductor device, thereby ensuring stable operation of the high-performance fan-out packaging device.

[0126] Furthermore, by forming a metal sealing ring on the fan-out packaging device according to embodiments of the present invention, it is possible to improve local planarization, widen the conductive path, and increase the efficiency of the electroplating process.

[0127] Furthermore, according to an embodiment of the present invention, an insulating layer is formed between the fan-out packaging substrate and the additional GND layer, thereby providing electrical insulation between the fan-out packaging substrate and the additional GND layer and alleviating the difference in physical properties between the surface of the fan-out packaging substrate and the thin additional GND layer, i.e., the stress that occurs when the additional GND layer is formed directly on the fan-out packaging substrate, i.e., the mechanical stress, thereby improving the structural stability of the fan-out packaging device and ensuring its long-term reliability.

[0128] In addition, the additional via holes in the insulating layer formed according to an embodiment of the present invention are formed on the signal pads and GND pads of the die, and are filled on the via holes in the insulating layer to form reconstructed pads using the additional GND layer, thereby compensating for die position errors. Furthermore, they can also serve as a reference when forming via holes in the dielectric layer and redistribution layer formed thereon, thereby improving the overall precision of via formation. This improves the accuracy of electrical connections and ensures the reproducibility of the manufacturing process.

[0129] In addition, the thin insulating layer formed on the fan-out substrate and the additional GND layer according to the embodiment of the present invention allows for the formation of small via holes, and maintains a planarized surface after the via holes are filled. Also, it facilitates the stacking of subsequent metal layers (additional GND layers), thereby improving the efficiency and reliability of the overall process. [Explanation of symbols]

[0130] 10 Fan-out packaging substrate 11 Die 12 Signal Pads 13 GND pad 14 GND seal ring 15 GND plane 100 Additional GND layer 110 Wiring line for die-to-die connection 120 Rebuilt GND seal ring 130 Rebuilt Pads 200 First dielectric layer 220 Beer Hall No. 1 300 redistribution layer 400 Second dielectric layer 420 Second Beer Hall 500 bump structure 600 insulating layer 620 Additional Beer Hole 700 Metal Sealing Ring 720 Vertical connection F fan-out region A active area B Inactive area

Claims

1. A method for manufacturing a packaging device using a wafer level packaging process or a panel level packaging process, forming an additional ground plane on a portion of the fan-out packaging substrate; forming a first dielectric layer having a first via hole formed therein on the additional GND layer; forming a re-distribution layer (RDL) on the first dielectric layer and the first via hole; forming a second dielectric layer having a second via hole formed therein on the redistribution layer; forming a bump structure connected to the redistribution layer on the second dielectric layer and the second via hole; The method for manufacturing a fan-out packaging element is characterized in that the additional GND layer is formed in the direction of four faces or at least two opposite faces of the die.

2. 2. The method of claim 1, wherein the additional GND layer is electrically connected to a GND seal ring or a GND pad to provide a rebuilt GND seal ring or a rebuilt pad.

3. 2. The method of claim 1, wherein the additional GND layer includes a wiring line for die-to-die connection.

4. 2. The method of claim 1, further comprising forming an insulating layer having an additional via hole between the fan-out packaging substrate and the additional GND layer.

5. 5. The method for manufacturing a fan-out packaging element according to claim 4, wherein the additional via hole is connected to a GND pad and a signal pad by filling the additional GND layer, thereby forming a reconstructed pad by the additional GND layer at the position of the additional via hole.

6. 6. The method of claim 5, wherein the additional via holes are formed by applying a laser direct imaging method.

7. 5. The method of claim 4, wherein the insulating layer is formed to have a thickness of 2 [mu]m or less.

8. 2. The method of claim 1, wherein the first dielectric forming process to the redistribution layer forming process are repeated to form multiple redistribution layers / dielectric layers.

9. 9. The method of claim 8, wherein the additional GND layer is connected to all or some of the GND planes formed in the subsequent redistribution layer.

10. 2. The method of claim 1, further comprising forming a hermetic metal sealing ring on an outer periphery of the fan-out packaging substrate during the redistribution layer formation process to provide an additional conductive path.

11. The hermetic metal sealing ring is connected to an additional GND layer by a vertical connection; or 11. The method for manufacturing a fan-out packaging device according to claim 10, wherein when formed in a structure of multiple redistribution layers / dielectric layers, the vertical connection portion is connected to a lower layer hermetic metal sealing ring and the vertical connection portion is connected to an additional GND layer.

12. A packaging device using a wafer level packaging process or a panel level packaging process, a fan-out packaging substrate; an additional GND layer formed on a partial region of the fan-out packaging substrate; a first dielectric layer formed on the additional GND layer and including a first via hole; a redistribution layer (RDL) formed on the first dielectric layer and the first via hole; a second dielectric layer formed on the redistribution layer and patterned to include a second via hole exposing a portion of the redistribution layer; a bump structure formed on the second dielectric and the second via hole and connected to the redistribution layer; A fan-out packaging element, wherein the additional GND layer is formed in the direction of four faces or at least two opposing faces of the die.

13. 13. The fan-out packaging element according to claim 12, wherein the additional GND layer is electrically connected to a GND seal ring or a GND pad to provide a reconstructed GND seal ring or a reconstructed pad.

14. 13. The fan-out packaging device of claim 12, wherein the additional GND layer includes a wiring line for die-to-die connection.

15. The fan-out packaging device of claim 12, wherein an insulating layer including an additional via hole is formed between the fan-out packaging substrate and the additional GND layer.

16. 16. The fan-out packaging device of claim 15, wherein the additional via holes are connected to GND pads and signal pads by filling the additional GND layer, thereby forming reconstructed pads by the additional GND layer at the positions of the additional via holes.

17. The fan-out packaging device of claim 16, wherein the additional via holes are formed by applying a laser direct imaging method.

18. 16. The fan-out packaging device of claim 15, wherein the insulating layer is formed to have a thickness of 2 [mu]m or less.

19. 13. The fan-out packaging device of claim 12, wherein the first dielectric forming process to the redistribution layer forming process are repeated to form multiple redistribution layers / dielectric layers.

20. 20. The fan-out packaging device of claim 19, wherein the additional GND layer is connected to all or some of the GND planes formed in the subsequent redistribution layer.

21. 13. The fan-out packaging device of claim 12, wherein a hermetic metal sealing ring is formed on an outer periphery of the fan-out packaging substrate during the redistribution layer formation process to provide an additional conduction path.

22. The hermetic metal sealing ring is connected to an additional GND layer by a vertical connection; or 22. The fan-out packaging device of claim 21, wherein when formed in a multiple redistribution layer / dielectric layer structure, the fan-out packaging device is connected to a lower layer hermetic metal sealing ring by a vertical connection portion and to an additional GND layer by a vertical connection portion.

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