Semiconductor device

Abstract

To provide a storage device for storing a large amount of data.SOLUTION: The memory device includes a first transistor, a second transistor, a third transistor, a first capacitor, a second capacitor, and first to third wirings. The first transistor includes an oxide semiconductor in a channel formation region, the second transistor includes silicon in a channel formation region, and the third transistor includes silicon in a channel formation region. The first capacitor is provided in the same layer as the first transistor, and the second capacitor and the first capacitor overlap with each other in a region. The thickness of the dielectric of the second capacitor is preferably larger than that of the dielectric of the first capacitor.SELECTED DRAWING: Figure 6

Description

[Technical Field]

[0001] TECHNICAL FIELD One aspect of the present invention relates to a storage device.

[0002] Another embodiment of the present invention relates to a semiconductor device. Another aspect of the present invention relates to an object, a method, or a manufacturing method thereof. Alternatively, one aspect of the present invention relates to a process, machine, manufacture, or or composition of matter.

[0003] In this specification and the like, a semiconductor device is a device that can function by utilizing semiconductor characteristics. This refers to the general term. Storage devices, display devices, electro-optical devices, power storage devices, semiconductor circuits, and electronic devices , may have semiconductor devices. [Background technology]

[0004] A transistor (thin film transistor) is made using a semiconductor thin film formed on a substrate with an insulating surface. The technology of constructing thin-film transistors (also called TFTs) is attracting attention. It is widely used in electronic devices such as ICs and image display devices. Semiconductor materials, such as silicon, are widely known as semiconductor thin films that can be used in transistors. However, oxide semiconductors are attracting attention as other materials. For example, zinc oxide or I A technique for fabricating a transistor using an n-Ga-Zn oxide semiconductor has been disclosed (Patent (See Patent Document 1).

[0005] In addition, transistors using oxide semiconductors (Oxide Semiconductor The off-state current of an OS transistor is very small. Patent Documents 2 and 3 disclose an OS transistor, a Si transistor, and a capacitor element. These nonvolatile memories are rewritable and have There is no limit to the number of units, and they consume very little power.

[0006] In Patent Document 2, a nonvolatile memory in which an OS transistor and a capacitance element are formed in the same layer is disclosed. In addition, Patent Document 3 discloses a method in which an OS transistor and a capacitor element are formed in different layers. A non-volatile memory is disclosed that is formed. [Prior art documents] [Patent documents]

[0007] [Patent Document 1] Japanese Patent Application Laid-Open No. 2007-123861 [Patent Document 2] Japanese Patent Application Laid-Open No. 2011-151383 [Patent Document 3] Japanese Patent Application Laid-Open No. 2015-195074 Summary of the Invention [Problem to be solved by the invention]

[0008] When the capacitance element of the nonvolatile memory is formed in the same layer as the OS transistor, the memory The OS transistor occupies a certain area of ​​the cell, so the capacitance element It is not possible to allocate sufficient area to

[0009] When the capacitor is formed above the OS transistor, the capacitor is However, as memory cell integration progresses, When the size of the capacitor becomes smaller, it becomes impossible to allocate a sufficient area to the capacitor element.

[0010] An object of one embodiment of the present invention is to provide a highly integrated memory cell. An object of one embodiment of the present invention is to provide a storage device that can store a large amount of data. Another object of one embodiment of the present invention is to provide a memory device with low power consumption. Another object of one embodiment of the present invention is to provide a novel semiconductor device.

[0011] It should be noted that the description of multiple problems does not preclude the existence of each problem. The embodiment does not necessarily solve all of these problems. These problems are also clearly evident from the description of the present invention, such as drawings and claims. This could be a form of challenge for Ming. [Means for solving the problem]

[0012] One aspect of the present invention is a semiconductor device including a first transistor, a second transistor, a first capacitance element, and a second capacitance element. The memory device has a capacitor, a conductor, and a wiring. The conductor is a first transistor. The conductor functions as either a source or a drain. The second electrode of the first capacitor is electrically connected to the wiring. The first electrode of the capacitor is electrically connected to the conductor. The second electrode of the second capacitor is electrically connected to the wiring. The gate of the second transistor is electrically connected to the conductor. The second transistor has an oxide semiconductor in a channel formation region. The second capacitance element and the first capacitance element have an overlapping region. do.

[0013] In the above embodiment, the thickness of the dielectric of the second capacitance element is thicker than the thickness of the dielectric of the first capacitance element. Larger is preferable.

[0014] One aspect of the present invention is a semiconductor device including a first transistor, a second transistor, a third transistor, and a third transistor. A memory device having a first capacitance element, a second capacitance element, a conductor, and first to third wirings. The conductor functions as either the source or the drain of the first transistor. The conductor functions as a first electrode of the first capacitor. The second electrode of the first capacitor is The first electrode of the second capacitance element is electrically connected to the first wiring. The second electrode of the second capacitor is electrically connected to the first wiring. The gate is electrically connected to the conductor. The second transistor is electrically connected to the second wiring via the third transistor. The other of the source and drain is electrically connected to a third wiring. The second transistor has an oxide semiconductor in a channel formation region. The third transistor has silicon in a channel formation region. One capacitance element has an overlapping area.

[0015] In the above embodiment, the thickness of the dielectric of the second capacitance element is thicker than the thickness of the dielectric of the first capacitance element. Larger is preferable.

[0016] One aspect of the present invention is a semiconductor wafer having a plurality of the memory devices according to the above aspects and having an isolation region. It's Ha.

[0017] One embodiment of the present invention is an electronic device including the storage device according to any one of the above embodiments and a battery. . [Effects of the Invention]

[0018] According to one embodiment of the present invention, a highly integrated memory cell can be provided. According to one embodiment of the present invention, a storage device that stores a large amount of data can be provided. According to one embodiment of the present invention, a memory device with low power consumption can be provided. According to one embodiment of the present invention, a novel semiconductor device can be provided.

[0019] The description of these effects does not preclude the existence of other effects. The embodiment does not necessarily have all of these effects. Effects other than these may be included in the description, This becomes clear from the description, drawings, claims, etc. From any description, it is possible to extract effects other than these. [Brief explanation of the drawings]

[0020] [Figure 1] FIG. 1 is a circuit diagram showing a configuration example of a memory cell. [Figure 2] 10 is a timing chart showing an example of the operation of a memory cell. [Figure 3] FIG. 1 is a top view showing a configuration example of a memory cell. [Figure 4] FIG. 1 is a top view showing a configuration example of a memory cell. [Figure 5] FIG. 1 is a top view showing a configuration example of a memory cell. [Figure 6] FIG. 1 is a cross-sectional view showing a configuration example of a memory cell. [Figure 7] 3A and 3B are a top view and a cross-sectional view showing a configuration example of transistors Tr1 and Tr2. [Figure 8] 1A and 1B are a top view and a cross-sectional view illustrating a configuration example of a transistor OS1. [Figure 9] A diagram explaining the InMZnO4 crystal. [Figure 10] FIG. 1 is a block diagram showing an example of the configuration of a storage device. [Figure 11] FIG. 1 is a circuit diagram showing a configuration example of a memory cell. [Figure 12] FIG. 1 is a circuit diagram showing a configuration example of a memory cell. [Figure 13] 3A and 3B are a top view and a cross-sectional view showing a configuration example of transistors Tr1 and Tr2. [Figure 14] 1A and 1B are a top view and a cross-sectional view illustrating a configuration example of a transistor OS1. [Figure 15] 1A and 1B are a top view and a cross-sectional view illustrating a configuration example of a transistor OS1. [Figure 16] FIG. 2 is a block diagram showing an example of the configuration of a CPU. [Figure 17] Block diagram showing an example of an RFIC configuration. [Figure 18] Top view of a semiconductor wafer. [Figure 19] 1A and 1B are a flowchart and a perspective view illustrating a manufacturing process of a semiconductor device. [Figure 20] FIG. 1 is a perspective view showing an example of an electronic device. [Figure 21] FIG. 1 is a cross-sectional view showing a configuration example of a memory cell. [Figure 22] FIG. 1 is a cross-sectional view showing a configuration example of a memory cell. [Figure 23] 10 is a graph showing the dependency of memory capacity on the area of ​​a memory cell. [Figure 24] 10 is a graph showing the dependency of retention time on the area of ​​a memory cell. DETAILED DESCRIPTION OF THE INVENTION

[0021] Hereinafter, embodiments will be described with reference to the drawings. The present invention may be implemented in any form without departing from the spirit and scope of the present invention. It will be readily apparent to those skilled in the art that various modifications may be made to the design and details of the present invention. The present invention should not be construed as being limited to the following description of the embodiments.

[0022] Also, in the drawings, the size, layer thickness, or area may be exaggerated for clarity. Therefore, the scale is not necessarily limited to that shown. The drawings are merely schematic illustrations and are not limited to the shapes or values ​​shown in the drawings.

[0023] In this specification, the high power supply voltage is referred to as the H level (or V DD ), low power supply voltage is L level This is sometimes called the ground (or GND).

[0024] In addition, in this specification, the following embodiment modes and examples can be combined as appropriate. In addition, when a plurality of configuration examples are shown in one embodiment, the configuration examples may be combined with each other as appropriate. It is possible to match.

[0025] (Embodiment 1)

[0026] In this embodiment, a memory cell according to one embodiment of the present invention and a memory device using the memory cell will be described. We will explain the location.

[0027] <<Example of memory cell configuration>> <Memory cell 10a> FIG. 1A is a circuit diagram showing an example of the configuration of a memory cell 10a. A transistor OS1, a transistor Tr1, a transistor Tr2, a capacitance element Cs1, , and a capacitor Cs2. The memory cell 10a also includes a wiring BL, a wiring SL, and a wiring It is electrically connected to the wiring WWL, the wiring RWL, the wiring WCL and the wiring BG.

[0028] The transistor OS1 has a first gate and a second gate. The first gate and the second gate have overlapping regions with a channel forming region therebetween. The first gate is sometimes called the main gate or front gate, and the second gate is sometimes called the back gate.

[0029] The first gate of the transistor OS1 is electrically connected to the wiring WWL. The second gate of the transistor OS1 is electrically connected to the wiring BG. One of the drains is electrically connected to the gate of the transistor Tr1. The other of the source and the drain of the transistor 1 is electrically connected to a wiring BL.

[0030] Either the source or the drain of the transistor Tr1 is connected to the transistor Tr2. The other of the source and drain of the transistor Tr1 is electrically connected to the line SL. It is electrically connected to BL.

[0031] A first electrode of the capacitance element Cs1 is electrically connected to the gate of the transistor Tr1. The second electrode of Cs1 is electrically connected to the wiring WCL. The first electrode of the capacitance element Cs2 is The second electrode of the capacitance element Cs2 is electrically connected to the wiring WCL. The capacitance elements Cs1 and Cs2 are electrically connected. It can be considered as follows.

[0032] One of the source or drain of the transistor OS1 and the gate of the transistor Tr1 The node of this is called node FN.

[0033] The wiring BL is a bit line, to which data to be stored in the memory cell 10a is applied.

[0034] The wiring SL is a power supply line, to which a constant potential is applied.

[0035] The wiring WWL is a word line, and when writing data to the memory cell 10a, a high-level voltage is applied. The rank is given.

[0036] The wiring RWL is a word line, and when reading data written in the memory cell 10a, An L level potential is applied.

[0037] A constant potential (GND) is applied to the wiring WCL.

[0038] Transistor Tr1 and transistor Tr2 should be p-channel transistors. It is also preferable that the transistors Tr1 and Tr2 have a large on-state current. It is preferable to use a transistor having a large on-state current. A transistor (Si transistor) using silicon (Si) in the channel forming region is preferred. stomach.

[0039] When the transistor OS1 is in a non-conducting state, a current (off) flows between the source and drain. It is preferable to use a transistor with a low off-state current. The voltage between the source and drain is 1.8V, and the standard is The calculated off-state current is 1×10 at room temperature. -20 A or less, 1 x 10 at 85°C -1 8 A or less, or 1 x 10 at 125°C -16 A and below. An example of a transistor with low off-state current is an OS transistor.

[0040] In the memory cell 10a, the node FN is connected to the line BL and the transistor OS1. After the charge is written to the node FN, the transistor OS By turning off 1, the memory cell 10a can retain charge at node FN.

[0041] Since the off-current of the transistor OS1 is extremely small, the memory cell 10a can store data for a long time. In addition, the memory cell 10a can hold the data by simply turning on the transistor OS1. Since data can be written, it is possible to write data to a memory card that is not compatible with flash memory, which requires a high voltage for writing data. In other words, data can be written with less power than when using the memory cell 10a. The storage device can reduce power consumption.

[0042] <Memory cell 10b> The memory cell 10a connects the transistor Tr2 to the source or drain of the transistor Tr1. The other of the two wirings can be provided between the wiring BL and the other of the two wirings BL. A circuit diagram in this case is shown in FIG. For details of each component of the memory cell 10b shown in FIG. 1B, please refer to the description of the memory cell 10a. Just check it out.

[0043] <<Memory Cell Operation Example>> Next, the write and read operations of the memory cell 10a will be explained with reference to FIG. The following explanation will be given for the case where node FN holds 1 bit of data. The following explanation can be applied to the memory cell 10b as well.

[0044] 2 is a timing chart showing an example of the operation of the memory cell 10a. WWL, wiring RWL, wiring WCL, wiring BL, wiring SL, node FN, and wiring BG are given The timing chart of FIG. 2 shows the potentials in the periods P1 to P5. It is divided into:

[0045] Periods P1, P3, and P5 represent standby periods of the memory cell 10a. Period P2 represents a write period for the memory cell 10a, and period P3 represents a read period for the memory cell 10a.

[0046] During the periods P1 to P5, the wiring WCL is always supplied with GND. is preferably at a low power supply potential or ground potential.

[0047] In addition, in the periods P1 to P5, the potential V3 is always applied to the wiring SL, and the potential V4 is always applied to the wiring BG. Potential V BG is given. The potential V BG is preferably a negative potential. BG to By applying a negative potential, the transistor OS1 can be made normally off. Normally off means that when GND is applied to the wiring WWL, the transistor OS The current per 1 μm of channel width flowing through the -20 Below A, 85℃ Place 1×10 -18 A or less, or 1 x 10 at 125°C -16 A or below say.

[0048] The operation of each period will be explained below in order.

[0049] <Period P1> First, in the period P1, the wiring WWL and the wiring BL are given GND, and the wiring RWL is At this time, the transistor Tr2 is turned off, and the wiring BL and the wiring No current flows between the line SL. To turn off the transistor Tr2, the potential V2 and the The difference (V2-V3) between the voltages V2 and V3 is preferably greater than the threshold voltage of the transistor Tr2. Desirable.

[0050] <Period P2> Next, in a period P2, a potential V1 is applied to the wiring WWL, and a potential V2 (data The potential V1 is connected to the transistor V2. It is preferable that the threshold voltage of the transistor OS1 is larger than the sum of the threshold voltages of the transistor OS2 and the transistor OS3. Transistor OS1 turns on, and the data given to wire BL is written to node FN. .

[0051] <Period P3> Next, in a period P3, GND is applied to the wiring WWL and the wiring BL. Register OS1 is turned off and the data written to node FN is retained.

[0052] <Period P4> Next, during period P4, the wiring BL is set in an electrically floating state, and GND is applied to the wiring RWL. At this time, the transistor Tr2 turns on.

[0053] If "1" is written to node FN, transistor Tr1 is off. Therefore, no current flows between the wiring SL and the wiring BL, and the wiring BL is maintained at GND. To turn off the transistor Tr1, the difference between the potential V2 and the potential V3 (V2-V3) is It is preferable that the threshold voltage is larger than the threshold voltage of the transistor Tr1.

[0054] If "0" is written to node FN, transistor Tr1 is on. Therefore, the wiring SL and the wiring BL are in a conductive state, and the wiring BL is at a potential V3 ( The line SL is charged until the potential of the line SL is equal to that of the line SL. Therefore, the difference between GND and potential V3 (-V3) is smaller than the threshold voltage of transistor Tr1. In order to turn on the transistor Tr2, it is preferable to set the potential V3 to VGND. The difference (-V3) is preferably smaller than the threshold voltage of transistor Tr2.

[0055] In the period P4, the potential of the wiring BL is read, and the data written to the node FN is It becomes possible to determine the following.

[0056] <Period P5> Next, in a period P5, a potential V2 is applied to the wiring RWL, a GND is applied to the wiring BL, and Holds the data of the FN.

[0057] As described above, the operations shown in periods P1 to P5 allow data to be read and written from the memory cell 10a. It becomes possible to write.

[0058] <<Top view of memory cell>> Next, a top view of the memory cell 10a will be described with reference to FIGS.

[0059] The top view of the memory cell 10a will be explained in order from the bottom up. The top view of the transistor Tr1 and the transistor Tr2 formed on the plate is shown in Figure 3( In A), the semiconductor SEM1 is an active layer region of the transistors Tr1 and Tr2. The conductor G11 functions as the gate electrode of the transistor Tr1. The body G12 functions as the gate electrode of the transistor Tr2.

[0060] In FIG. 3A, lx represents the length of the memory cell 10a in the x direction (horizontal direction), and ly represents The product of lx and ly represents the length of the memory cell 10a in the y direction (vertical direction). This represents the area of ​​Rule 10a.

[0061] FIG. 3(B) shows the top view of FIG. 3(A) with conductors M11, M12, M13, and This is a top view when a conductor M14 is added. The conductor M11 functions as a wiring BL. The conductor M12 functions as a wiring SL.

[0062] In Figures 3(A) and 3(B), conductors G11 and M13 are electrically connected via plug V11. The semiconductor SEM1 and the conductor M11 are electrically connected via the plug V12. The semiconductor SEM1 and the conductor M12 are electrically connected via the plug V13. Conductor G12 and conductor M14 are electrically connected via plug V14. .

[0063] FIG. 3(C) shows the top view of FIG. 3(B) with conductors M21, M22, M23 and The conductor M24 functions as a wiring RWL. It has.

[0064] In Figures 3(B) and (C), the conductors M11 and M21 are electrically connected via the plug V21. Conductor M13 and conductor M23 are electrically connected via plug V22. Conductor M14 and conductor M24 are electrically connected via plug V23. There are.

[0065] FIG. 3D is a top view in which a semiconductor SEM 2 is added to the top view of FIG. 3C. The semiconductor SEM2 functions as the semiconductor region of the transistor OS1.

[0066] FIG. 4(A) shows the top view of FIG. 3(D) with conductors S21 and S22 added. The conductor S22 is used as either the source or the drain of the transistor OS1. The conductor S21 functions as the other of the source and drain of the transistor OS1. It has all the functions.

[0067] Figure 4(B) shows the top view of Figure 4(A) with conductors G21 and G22 added. The conductor G21 functions as the gate of the transistor OS1.

[0068] FIG. 4C shows the positions of the transistor OS1 and the capacitor Cs1 in the top view of FIG. 4B. is shown by a thick dashed line.

[0069] FIG. 4(D) shows the top view of FIG. 4(B) with conductors M31, M32, M33 and M41. The conductor M32 functions as the wiring WWL. The conductor M34 functions as the wiring WCL.

[0070] In Figures 4(B) and (D), conductors M21 and M31 are electrically connected via plug V41. Conductor S21 and conductor M31 are electrically connected via plug V42. Conductor G21 and conductor M32 are electrically connected via plug V43. The conductor S22 and the conductor M33 are electrically connected via the plug V44. Conductor M23 and conductor M33 are electrically connected via plug V45. and conductor M34 are electrically connected via plug V46.

[0071] Figure 5(A) shows the top view of Figure 4(D) with conductors CE1 and CE2 added. The conductor CE1 functions as a first electrode of the capacitance element Cs2, and the conductor CE 2 functions as the second electrode of the capacitance element Cs2.

[0072] In FIG. 5B, the position of the capacitance element Cs2 in FIG. 5A is indicated by a thick dashed line. It is preferable that the element Cs2 has an area overlapping with the capacitive element Cs1 described above. By doing so, the area of ​​the memory cell 10a can be reduced while maintaining the storage capacity of the memory cell 10a. It can be made easier.

[0073] FIG. 5(C) shows the top view of FIG. 5(A) with conductors M41 and M42 added. FIG.

[0074] In Figures 5(A) and (C), conductors M33 and M41 are electrically connected via plug V51. Conductor CE1 and conductor M41 are electrically connected via plug V52. Conductor CE2 and conductor M42 are electrically connected via plug V53. The conductor M34 and the conductor M42 are electrically connected via a plug V54.

[0075] <<Cross-section of memory cell>> Next, a cross-sectional view of the memory cell 10a will be described with reference to FIG. 6. FIG. 6 is a cross-sectional view of the memory cell 10a shown in FIG. 5(C). ) is a cross-sectional view taken along the dashed dotted line Y1-Y2.

[0076] The memory cell 10a shown in FIG. 6 includes, in order from the bottom, a layer L1, a layer L2, a layer L3, and a layer L4. , has layer L5.

[0077] The layer L1 includes a substrate 11, an element isolation layer 12, a semiconductor SEM1, an insulator 34a, and a conductor G11, a sidewall insulating layer 14, a sidewall insulating layer 15, and a plug V11.

[0078] In the figure, the part corresponding to the transistor Tr1 is shown by a dashed line. Details will be provided below.

[0079] The layer L2 includes an insulator 13, an insulator 24, a conductor M13, and a plug V22.

[0080] The layer L3 includes an insulator 16, an insulator 25, a conductor M22, a conductor M23, and a conductor M2. 4, an insulator 17, an insulator 18, an insulator 19, an oxide semiconductor 41, and an oxide semiconductor 42, an oxide semiconductor 43, an insulator 20, an insulator 21, a conductor S21, and a conductor S 22, a conductor G21, a conductor G22, a plug V42, and an insulator 22. The conductor M24 functions as the wiring RWL.

[0081] In the figure, the parts corresponding to the transistor OS1 and the capacitance element Cs1 are indicated by dashed lines. Conductor G21 functions as the gate of transistor OS1. The conductor S21 functions as either the source or drain of the transistor OS1. The conductor S22 functions as the other of the source and drain of the conductor OS1. The conductor G22 functions as the first electrode of the capacitor Cs1. The insulator 20 functions as a dielectric of the capacitance element Cs1. The insulator 20 also functions as a gate insulator for the transistor OS1. The transistor OS1 will be described in detail later.

[0082] The layer L4 includes a conductor M31, a conductor M32, and a conductor M34. has a function as the wiring WWL, and the conductor M34 has a function as the wiring WCL.

[0083] The layer L5 includes a conductor CE1, an insulator 23, a conductor CE2, a plug V53, and a conductor M. The conductor CE1 functions as a first electrode of the capacitance element Cs2, and the conductor The insulator 23 functions as the second electrode of the capacitance element Cs2. In the figure, the area corresponding to the capacitance element Cs2 is indicated by a dashed line. be.

[0084] In the memory cell 10a, the capacitance element Cs1 is provided in the same layer as the transistor OS1. Therefore, in the manufacturing process of the memory cell 10a, the source and The drain and the first electrode of the capacitor Cs1 are formed at the same time. The gate insulator of OS1 and the dielectric of the capacitor Cs1 are formed simultaneously. The gate of the transistor OS1 and the second electrode of the capacitor Cs1 are formed at the same time.

[0085] In the memory cell 10a, the capacitive element Cs2 is formed above the capacitive element Cs1. Furthermore, the capacitive element Cs1 and the capacitive element Cs2 have an overlapping region.

[0086] For example, if the capacitance element of the memory cell 10a is composed of only the capacitance element Cs1, If the transistor OS1 occupies a certain area of ​​the resonator 10a, A sufficient area cannot be allocated to the capacitance element Cs1.

[0087] For example, when the capacitive element of the memory cell 10a is composed of only the capacitive element Cs2, The element Cs2 can have a large area without being affected by the transistor OS1, but As the integration of the memory cell 10a progresses and the size of the memory cell 10a becomes smaller, the capacitance element Cs It will no longer be possible to allocate sufficient area to 2.

[0088] The configuration shown in FIG. 6 prevents the shortage of the capacitance element Cs2 even if the size of the memory cell 10a is reduced. This is preferable because the capacitance element Cs1 can compensate for this loss.

[0089] The thickness of the dielectric (insulator 20) of the capacitance element Cs1 is The insulator 20 is preferably thinner than the gate electrode 23 of the transistor OS1. Since the insulator 20 also serves as a gate insulator, if the insulator 20 is made too thick, the transistor OS1 will not operate. Furthermore, since the capacitance element Cs2 has a large area, if the insulator 23 is made too thin, the capacitance element Cs2 The leakage current flowing through 3 increases, and the capacitance element Cs2 becomes unable to hold charge.

[0090] The substrate 11 may be a single crystal semiconductor substrate made of silicon or silicon carbide, or a polycrystalline semiconductor substrate. substrates, compound semiconductor substrates made of silicon germanium, and SOI (Silicon On Insulator) In addition, as the substrate 11, for example, , glass substrate, quartz substrate, plastic substrate, metal substrate, laminated film, fibrous Paper containing the material, a base film, etc. may be used. The device may be formed and then the semiconductor device may be transferred to another substrate.

[0091] A flexible substrate may also be used as the substrate 11. For example, metal, alloy, resin, glass, or fibers thereof may be used. Examples of resins include polyester, polyolefin, polyamide (nylon), Polyimide, polycarbonate, acrylic, polytetrafluoroethylene There are also methods for mounting transistors on flexible substrates, such as PTFE. In this case, a transistor is fabricated on a non-flexible substrate, and then the transistor is peeled off and placed on a flexible substrate. There is also a method of transferring the transistor to a flexible substrate 11. In this case, the substrate and the transistor It is advisable to provide a release layer between the stamper and the substrate.

[0092] FIG. 6 shows an example in which a single crystal silicon wafer is used as the substrate 11.

[0093] The transistor Tr1 is provided on a substrate 11, and is isolated from other adjacent transistors by an element isolation layer 12. The element isolation layer 12 is made of silicon oxide, silicon oxynitride, Silicon nitride oxide, silicon nitride, etc. can be used. Nitrides are compounds that contain more oxygen than nitrogen, and oxynitrides are compounds that contain more oxygen than nitrogen. Also refers to compounds with a high nitrogen content.

[0094] Conductors M13, M31, M32, M34, CE1, CE2, M42 and plug V1 1, V42, V53, copper, tungsten, molybdenum, gold, aluminum, manganese Titanium, Tantalum, Nickel, Chromium, Lead, Tin, Iron, Cobalt, Ruthenium, Platinum, Low-resistivity materials such as iridium and strontium, alloys, or those containing these as the main components It is preferable to use a single layer or a multilayer of a conductor containing a compound having heat resistance and conductivity. It is preferable to use a high melting point material such as tungsten or molybdenum, which satisfies both of the above requirements. It is preferable to use a low resistance material such as aluminum or copper.

[0095] When copper is used for the conductor or the plug, the insulators 13 and 24 serve to suppress the diffusion of copper. For example, an insulator that suppresses copper diffusion is nitrogen. Silicon oxide can also be used. Metal oxides such as aluminum oxide can also be used. good.

[0096] For details about conductors M23 and M24 and plug V22, see the description of conductor M22 below. Please refer to the following.

[0097] Hydrogen generated from the substrate 11, the transistor Tr1, or the capacitance element Cs2 When the OS1 penetrates into the oxide semiconductor, the characteristics of the transistor OS1 are degraded. Therefore, the insulators 16, 25 and 22 have a barrier property against hydrogen. It is preferable to use an insulator having the following characteristics. An example of the insulator is a material formed by a CVD method. Silicon nitride is an example.

[0098] Examples of insulators having barrier properties against hydrogen include aluminum oxide and oxide Examples of metal oxides include hafnium oxide and tantalum oxide. In particular, aluminum oxide is Aluminum oxide also has a high blocking effect against oxygen. Therefore, it is possible to suppress the release of oxygen from the oxide semiconductor forming the transistor OS1. can.

[0099] The sides and bottom of the conductors M22, M23, M24 and the plug V22 are barriers to hydrogen. It is preferable that a conductor having barrier properties against hydrogen is provided. As mentioned above, tantalum nitride has a barrier property against hydrogen. By providing a conductor that penetrates the transistor OS1 through the conductor or plug, This can prevent hydrogen from being released.

[0100] For example, the insulator 16 is formed by atomic layer deposition (ALD). It is preferable to form the insulator 16 by the ion method. This also makes it possible to suppress the formation of cracks, pinholes, etc. It is preferable to form the insulator 25 by sputtering. The film can be formed at a faster film formation rate and can be made thicker with better productivity than the insulator 16 . By laminating the insulators 16 and 25 in this way, the barrier against impurities such as hydrogen is reduced. The insulator 25 is configured to be provided under the insulator 16. In addition, if the insulator 16 has sufficient barrier properties against impurities, the insulator 25 may be It may not be provided.

[0101] In FIG. 6, the areas without symbols and hatching patterns are made of insulating material. The insulators include aluminum oxide, aluminum oxide nitride, and magnesium oxide. Silicon oxide, silicon oxynitride, silicon nitride oxide, silicon nitride, gallium oxide , germanium oxide, yttrium oxide, zirconium oxide, lanthanum oxide, neodymium oxide The insulating material contains one or more materials selected from the group consisting of tantalum oxide, hafnium oxide, and the like. In addition, the region may be made of a polyimide resin, a polyamide resin, an acrylic resin, or the like. Organic resins such as siloxane resin, epoxy resin, and phenol resin can also be used.

[0102] <<Transistor Tr1, Transistor Tr2>> Next, the details of the transistors Tr1 and Tr2 will be described with reference to FIGS. 7(A) to 7(C). Details will be explained.

[0103] FIG. 7A is a top view of the transistor Tr1 and the transistor Tr2 (the top view of FIG. 3A). FIG. 7(B) is a cross section taken along the dashed line X1-X2 in FIG. 7(A). 7(C) shows a cross-sectional view taken along the dashed line Y1-Y2 in FIG. 7(A). The dashed line X1-X2 indicates the channel length direction of the transistors Tr1 and Tr2, and the dashed line Y 1-Y2 may be referred to as the channel width direction of the transistor Tr1.

[0104] In FIG. 7B, the transistors Tr1 and Tr2 are formed by low-concentration impurity regions 32a to 32b. d, high-concentration impurity regions 31a to 31c, and conductive layers provided in contact with the high-concentration impurity regions. The insulating regions 33a to 33c function as the gate insulator of the transistor Tr1. an insulator 34a and an insulator 34b that functions as a gate insulator for the transistor Tr2; A conductor G11 that functions as the gate electrode of the transistor Tr1, and a transistor T The conductor G12 has a function as a gate electrode of r2, and the conductor G11 is provided on the side wall of the conductor G11. The sidewall insulating layers 14a and 15a are formed on the sidewalls of the conductor G12, and the sidewall insulating layers 14b and 15b are formed on the sidewalls of the conductor G12. The conductive regions 33a to 33c are formed using metal silicide or the like. Good too.

[0105] For details of plug V12 and plug V13, please refer to the description of plug V11 above. .

[0106] <<Transistor OS1>> Next, the transistor OS1 will be described in detail with reference to FIGS.

[0107] FIG. 8A is a top view of the memory cell 10a shown in FIG. 4C, showing the transistor OS1 FIG. 8(B) is a cross-sectional view taken along the dashed line Y1-Y2 in FIG. 8(A). 8(C) shows a cross-sectional view taken along the dashed line X1-X2 in FIG. The dashed line Y1-Y2 indicates the channel length direction of the transistor OS1, and the dashed line X1-X2 indicates This may be referred to as the channel width direction of the transistor OS1.

[0108] The transistor OS1 has a conductor G21 that functions as a gate (first gate) and a gate insulator G22. The insulator 20 functions as an insulator (first gate insulator) and the conductive layer 21 functions as a second gate. The conductor M22 (conductor M22a, conductor M22b) and the insulating layer that functions as the second gate insulator. The oxide semiconductor 40 (oxide semiconductor 41, oxide semiconductors42 and oxide semiconductors43) and a conductive layer that functions as either the source or the drain. Conductor S22, conductor S21 functioning as the other of the source and drain, and conductor G2 1 and an insulator 21 that protects the electrode 1 and has excess oxygen (containing oxygen in excess of the stoichiometric composition). ) insulator 26.

[0109] The conductor G21 and the conductor M22 are connected via an opening 44 (FIG. 8(C)).

[0110] The oxide semiconductor 40 includes an oxide semiconductor 41 and an oxide semiconductor 42 on the oxide semiconductor 41. 2 and an oxide semiconductor 43 on the oxide semiconductor 42. When the gate is turned on, a current flows mainly through the oxide semiconductor 42. On the other hand, the oxide semiconductor 41 and the oxide semiconductor 43 is a region where a current flows near the interface with the oxide semiconductor 42 (which may be a mixed region). Some regions may act as insulators, while others may act as insulators.

[0111] The oxide semiconductors 41 and 42 correspond to the semiconductor SEM2 in the top view of FIG.

[0112] Oxide semiconductors Next, oxide semiconductors that can be used for the oxide semiconductor 40 will be described.

[0113] The oxide semiconductor preferably contains at least indium or zinc. In addition to these, aluminum, gallium, It is preferable that yttrium or tin is contained. Also, boron, silicon, Titanium, iron, nickel, germanium, zirconium, molybdenum, lanthanum, cerium , neodymium, hafnium, tantalum, tungsten, magnesium, etc. One or more of these may be included.

[0114] Here, the oxide semiconductor is InMZnO having indium, element M, and zinc. The element M can be aluminum, gallium, yttrium, tin, etc. Other elements that can be used for element M include boron, silicon, titanium, iron, Nickel, germanium, zirconium, molybdenum, lanthanum, cerium, neodymium, Hafnium, tantalum, tungsten, magnesium, etc. However, as the element M In some cases, a combination of the above elements may be used.

[0115] Oxide semiconductors are divided into single-crystal oxide semiconductors and other non-single-crystal oxide semiconductors. As a non-single-crystal oxide semiconductor, for example, CAAC-OS (c-axis alignable oxide semiconductor) gned crystalline oxide semiconductor), polycrystalline nc-OS (nanocrystalline oxide semiconductor) conductor), pseudo-amorphous oxide semiconductor (a-like OS) amorphous oxide semiconductors) and amorphous oxide semiconductors etc.

[0116] CAAC-OS has a c-axis orientation and multiple nanocrystals are connected in the ab-plane direction. The crystal structure has distortion. The distortion is the area where multiple nanocrystals are connected. In the region, the lattice arrangement is changed between a region with a uniform lattice arrangement and another region with a uniform lattice arrangement. Indicates the point where the direction is changing.

[0117] Nanocrystals are basically hexagonal, but they are not limited to regular hexagonal shapes and may be non-regular hexagonal. The distortion may also have lattice arrangements such as pentagons and heptagons. In CAAC-OS, clear grain boundaries (grain boundaries) are observed even near the strain. It is not possible to confirm the grain boundary (also called grain boundary distortion) due to the distortion of the lattice arrangement. This is because the CAAC-OS has a high SiO2 content in the ab-plane direction. The oxygen atoms are not densely packed, and the bond distance between atoms changes due to the substitution of metal elements. This is thought to be because distortion can be tolerated by, for example, increasing the thickness.

[0118] In addition, the CAAC-OS has a layer containing indium and oxygen (hereinafter referred to as an In layer) and an element A layered crystal structure in which layers containing M, zinc, and oxygen (hereinafter referred to as (M, Zn) layers) are stacked. It is noted that indium and element M tend to have a layered structure. It is possible, and when the element M in the (M,Zn) layer is replaced with indium, (In,M,Zn) Also, when indium in the In layer is replaced with element M, (In,M ) layer.

[0119] nc-OS is a material that can be used in microscopic areas (e.g., areas between 1 nm and 10 nm, especially areas between 1 nm and 3 nm). The nc-OS has periodic atomic arrangement in the nanometer range (nm or less). There is no regularity in the crystal orientation between the crystals. Therefore, no orientation is observed throughout the film. Therefore, depending on the analysis method, nc-OS may be distinguished from a-like OS or amorphous oxide semiconductor. It may be difficult to distinguish between the two.

[0120] The a-like OS is an oxide semiconductor with a structure between the nc-OS and amorphous oxide semiconductor. Conductive. A-like OS has voids or low density regions. The OS has lower crystallinity than the nc-OS and CAAC-OS.

[0121] Next, referring to FIGS. 9A, 9B, and 9C, the insulating film of the oxide semiconductor will be described. The preferred range of the atomic ratio of the elements M, M, and zinc will be described below. 9(B) and 9(C), the atomic ratio of oxygen is not shown. The atomic ratios of indium, element M, and zinc in the oxide semiconductor are expressed as [I [n], [M], and [Zn].

[0122] In Figures 9(A), 9(B), and 9(C), the dashed lines indicate the [In]:[M]:[Z n] = (1 + α):(1 - α):1, where the atomic ratio (-1 ≦ α ≦ 1) is [In] :[M]:[Zn]=(1+α):(1-α):2 atomic ratio line, [In]: The line where the atomic ratio of [M]:[Zn]=(1+α):(1-α):3, [In]:[ The line where the atomic ratio of [M]:[Zn]=(1+α):(1-α):4, and [In] : Represents the line where the atomic ratio of [M]:[Zn]=(1+α):(1-α):5.

[0123] The dashed line indicates the line where the atomic ratio of [In]:[M]:[Zn]=5:1:β (β≧0). The line where the atomic ratio of [In]:[M]:[Zn]=2:1:β is ]:[Zn]=1:1:β, where the atomic ratio is [In]:[M]:[Zn]=1: The line where the atomic ratio is 2:β, [In]:[M]:[Zn]=1:3:β and and the line where the atomic ratio is [In]:[M]:[Zn]=1:4:β. represent.

[0124] The dashed two-dot line indicates the atomic ratio (- 1≦γ≦1). Also, in Figures 9(A), 9(B), and 9(C), The atomic ratio of [In]:[M]:[Zn]=0:2:1 and oxides with values ​​close to that ratio are shown. Semiconductors tend to have a spinel-type crystal structure.

[0125] In some oxide semiconductors, multiple phases coexist (two-phase coexistence, three-phase coexistence, etc.). For example, When the atomic ratio is close to [In]:[M]:[Zn]=0:2:1, the spinel type The two phases of crystalline structure and layered crystalline structure tend to coexist. Also, the atomic ratio [In]:[M] When the value of [Zn] is close to 1:0:0, the bixbyite-type crystal structure and the layered crystal structure When multiple phases coexist in an oxide semiconductor, different crystal structures are likely to coexist. During the construction, grain boundaries may be formed.

[0126] A region A shown in FIG. 9A is a region containing indium, the element M, and zinc in the oxide semiconductor. An example of a preferred range of the atomic ratio is shown.

[0127] By increasing the indium content of an oxide semiconductor, the carrier mobility of the oxide semiconductor can be improved. This is because the indium, element M, and zinc In oxide semiconductors, the s orbitals of heavy metals mainly contribute to carrier conduction, while indium This is because the area where the s orbitals overlap becomes larger by increasing the content of s orbitals. Therefore, oxide semiconductors with a high indium content are The carrier mobility is higher compared to

[0128] On the other hand, when the content of indium and zinc in the oxide semiconductor is low, the carrier mobility Therefore, the atomic ratio [In]:[M]:[Zn]=0:1:0 and its vicinity In the case of a near value (for example, region C shown in FIG. 9C), the insulating property is high.

[0129] Therefore, the oxide semiconductor according to one embodiment of the present invention has high carrier mobility and few crystal grain boundaries. It is preferable that the atomic ratio be that shown in region A in FIG. 9(A), which tends to form a layered structure without any problem. It's nice.

[0130] In particular, in region B shown in FIG. 9(B), CAAC-OS is more likely to occur than in region A. An excellent oxide semiconductor with high carrier mobility can be obtained.

[0131] CAAC-OS is an oxide semiconductor with high crystallinity. Since it is not possible to confirm the grain boundaries, the decrease in electron mobility due to the grain boundaries is unlikely to occur. In addition, the crystallinity of oxide semiconductors can be degraded by the inclusion of impurities and the generation of defects. Therefore, CAAC-OS is an oxide with few impurities and defects (such as oxygen vacancies). Therefore, oxide semiconductors with CAAC-OS have stable physical properties. Therefore, an oxide semiconductor having a CAAC-OS is heat-resistant and highly reliable.

[0132] Region B is the region where [In]:[M]:[Zn]=4:2:3 to 4.1 and its vicinity. Nearby values ​​include, for example, [In]:[M]:[Zn]=5:3:4. Region B is [In]:[M]:[Zn]=5:1:6 and its neighboring values, [In]:[M]:[Zn]=5:1:7 and its neighboring values.

[0133] Note that the properties of an oxide semiconductor are not uniquely determined by the atomic ratio. Even if the ratio is the same, the properties of the oxide semiconductor may differ depending on the formation conditions. When forming a film of semiconductor material using a sputtering device, the atomic ratio of the target may deviate. Also, depending on the substrate temperature during film formation, the film thickness is higher than the target [Zn]. Therefore, the region shown in the figure is a region where the oxide semiconductor is particularly The boundary between Region A and Region C is a region showing the atomic ratio that tends to have certain characteristics. isn't it.

[0134] Let us return to the transistor OS1 shown in FIGS.

[0135] The oxide semiconductors 41 and 43 have a lower energy level at the conduction band edge than the oxide semiconductor 42. The energy level is close to the vacuum level, and is typically the energy level at the bottom of the conduction band of the oxide semiconductor 42. The difference between the energy level at the bottom of the conduction band of oxide semiconductor 41 and oxide semiconductor 43 is 0. 15 eV or more, or 0.5 eV or more and 2 eV or less, or 1 eV or less That is, the electron affinities of the oxide semiconductors 41 and 43 and the oxide semiconductors The difference between the electron affinity of the molecule 42 and the electron affinity of the molecule 42 is 0.15 eV or more, or 0.5 eV or more and 2 eV or more. It is preferably 1 eV or less.

[0136] The oxide semiconductor 42 preferably has an energy gap of 2 eV or more, and more preferably has an energy gap of 2.5 eV or more. More preferably, the upper limit is 3.0 eV or less. In this case, the energy gap is preferably 2 eV or more, more preferably 2.5 eV or more, and The oxide semiconductor 41 and the oxide semiconductor The energy gap of the conductor 43 is larger than the energy gap of the oxide semiconductor 42. For example, the energy gap between the oxide semiconductor 41 and the oxide semiconductor 43 is preferably The energy gap of the oxide semiconductor42 is 0.15 eV or more, or 0. It is preferably 5 eV or more, or 1.0 eV or more and 2 eV or less, or 1 eV or less. Desirable.

[0137] By reducing the carrier density of the oxide semiconductor, the threshold voltage of the transistor can be reduced. This is preferable because the shift can be suppressed or the off-state current of the transistor can be reduced.

[0138] Factors that affect the carrier density in oxide semiconductors include oxygen vacancies in the oxide semiconductor ( Vo) or impurities in the oxide semiconductor. When the oxygen vacancy is increased, hydrogen bonds to the oxygen vacancy (this state is also called VoH), and the defect level Alternatively, when the amount of impurities in the oxide semiconductor increases, defects due to the impurities increase. Therefore, by controlling the defect state density in the oxide semiconductor, The carrier density of the compound semiconductor can be controlled.

[0139] For example, the carrier density of the oxide semiconductor 41 and the oxide semiconductor 43 is 8×10 15 cm -3 Less than 1 x 10 11 cm -3 less than 1×10 10 cm - 3 Less than 1 x 10 -9 cm -3 That's all there is to it.

[0140] On the other hand, the improvement of the on-state current of the transistor or the field-effect mobility of the transistor In this case, it is preferable to increase the carrier density of the oxide semiconductor. When increasing the carrier density of an oxide semiconductor, the impurity concentration of the oxide semiconductor is slightly increased. Alternatively, the defect state density of the oxide semiconductor may be increased slightly. It is preferable to make the band gap of the compound semiconductor smaller.

[0141] The carrier density of the oxide semiconductor 42 is higher than that of the oxide semiconductor 41 and the oxide semiconductor 43. The carrier density of the oxide semiconductor 42 is preferably as high as 1×10 5 cm -3 1 more x10 18 cm -3 Less than 1 x 10 is preferable. 7 cm -3 More than 1×10 17 cm -3 below is more preferable, and 1×10 9 cm -3 5x10 or more 16 cm -3 More preferably, 1×10 10 cm -3 More than 1×10 16 cm -3 Even better: 1 x 10 11 c m -3 More than 1×10 15 cm -3 The following is even more preferred:

[0142] The interface between the oxide semiconductor 41 and the oxide semiconductor 42, or the interface between the oxide semiconductor 42 and the oxide semiconductor It is preferable to reduce the defect level density of the mixed layer formed at the interface with 43.

[0143] Specifically, the oxide semiconductor 41 and the oxide semiconductor 42, the oxide semiconductor 42 and the oxide semiconductor 4 3) has a common element other than oxygen (as the main component), resulting in a mixture with a low defect level density. For example, the oxide semiconductor 42 may be an In—Ga—Zn oxide semiconductor. In this case, the oxide semiconductor 41 and the oxide semiconductor 43 are In-Ga-Zn oxide semiconductors, It is preferable to use a Ga-Zn oxide semiconductor, gallium oxide, or the like.

[0144] At this time, the main path of the carriers is the oxide semiconductor 42. Defects at the interface with the semiconductor 42 and at the interface between the oxide semiconductor 42 and the oxide semiconductor 43 Since the level density can be reduced, the effect of interface scattering on carrier conduction is small. A high on-current can be obtained.

[0145] When electrons are captured in the trap level, the captured electrons behave like fixed charges. Therefore, the V th is shifted to the positive direction. By providing the semiconductor 43, the trap states can be placed farther away from the oxide semiconductor 42. By using this configuration, the V th prevents the value from shifting in the positive direction. It can be stopped.

[0146] The oxide semiconductors 41 and 43 have sufficient electrical conductivity compared to the oxide semiconductor 42. At this time, the oxide semiconductor 42, the oxide semiconductor 42 and the oxide semiconductor 41 are used. The interface between the oxide semiconductor 41 and the oxide semiconductor 42 and the oxide semiconductor 43 are mainly the channel region. For example, the oxide semiconductor 41 and the oxide semiconductor 43 have the following functions: In this case, an oxide semiconductor having an atomic ratio shown in region C where the insulating property is high may be used. Region C shown in C) is where [In]:[M]:[Zn]=0:1:0 or its nearby values. The atomic ratio is shown.

[0147] In particular, the oxide semiconductor 42 is formed by adding an oxide semiconductor having an atomic ratio shown in region A in FIG. 9(A). When used, the oxide semiconductor 41 and the oxide semiconductor 43 have an [M] / [In] ratio of 1 or more. It is preferable to use an oxide semiconductor having a conductivity of 2 or more. 3, [M] / ([Zn]+[In]) is 1 or more to obtain sufficiently high insulation. It is preferable to use an oxide semiconductor having the above-mentioned properties.

[0148] The oxide semiconductor 42 preferably has the above-described CAAC-OS.

[0149] The oxide semiconductor 43 preferably has lower crystallinity than the oxide semiconductor 42. By lowering the crystallinity of the oxide semiconductor 43, the oxygen permeability of the oxide semiconductor 43 increases. Oxygen is more easily supplied to the oxide semiconductor 42 from the insulator located above the semiconductor 43 . Similarly, the oxide semiconductor 41 preferably has lower crystallinity than the oxide semiconductor 42. By lowering the crystallinity of the oxide semiconductor 41, the oxygen permeability of the oxide semiconductor 41 is increased. Therefore, oxygen is easily supplied to the oxide semiconductor 42 from the insulator located below the oxide semiconductor 41. For example, the oxide semiconductors 41 and 43 are the above-mentioned nc-OS or a-like An OS may also be used.

[0150] <Other components> Next, other components of the transistor OS1 will be described.

[0151] Conductor M22 is made of molybdenum, titanium, tantalum, tungsten, aluminum, copper, A metal film containing an element selected from the group consisting of chromium, neodymium, and scandium, or a metal film containing the above elements. metal nitride films (titanium nitride film, molybdenum nitride film, tungsten nitride film) Or, indium tin oxide, indium oxide containing tungsten oxide, tungsten oxide Indium zinc oxide containing stainless steel, indium oxide containing titanium oxide, titanium oxide Indium tin oxide, indium zinc oxide, indium stannate with silicon oxide Conductive materials such as carbides can also be applied.

[0152] For example, titanium nitride is used as the conductor M22a, which has a barrier property against hydrogen. It is preferable to use tungsten or the like as the conductor M22b, and to laminate tungsten, which has high conductivity. By using this combination, the conductivity of the wiring can be maintained while the oxide semiconductor 40 is This can suppress the diffusion of hydrogen.

[0153] The insulators 17 and 19 are insulators containing oxygen, such as silicon oxide films or silicon oxynitride films. It is particularly preferable to use an insulator containing excess oxygen as the insulator 19. The insulator containing such excess oxygen is preferably an oxide semiconductor that constitutes the transistor OS1. By providing the oxide semiconductor layer in contact with the oxide semiconductor layer, oxygen vacancies in the oxide semiconductor layer can be compensated for. The insulators 17 and 19 do not necessarily have to be made of the same material.

[0154] The insulator 18 may be, for example, silicon nitride, silicon oxynitride, aluminum oxide, or hafnium oxide. Titanium, tantalum oxide, zirconium oxide, lead zirconate titanate (PZT), titanate Insulators containing strontium (SrTiO3) or (Ba,Sr)TiO3 (BST) It is preferable to use a single layer or a laminate of insulating materials. nium, bismuth oxide, germanium oxide, niobium oxide, silicon oxide, titanium oxide, Tungsten oxide, yttrium oxide, or zirconium oxide may also be added. The insulator may be nitrided.

[0155] The insulator 18 may have a laminated structure of two or more layers. The present invention is not limited to a laminated structure in which the first and second layers are laminated together, but may be a laminated structure made of different materials.

[0156] In addition, by appropriately adjusting the film thickness of the insulators 17 to 19, V th can be controlled Alternatively, a transistor with a small leakage current when not conducting can be provided. By thinning the film thickness of each of 17 to 19, V th Easier to control For example, the thickness of each of the insulators 17 to 19 is preferably 50 nm or less, more preferably 50 nm or less. Preferably, each is 30 nm or less, more preferably, each is 10 nm or less, and even more preferably, should be set to 5 nm or less.

[0157] The insulator 20 may be, for example, silicon oxide, silicon oxynitride, silicon nitride oxide, or aluminum oxide. aluminum, hafnium oxide, tantalum oxide, zirconium oxide, lead zirconate titanate ( PZT), strontium titanate (SrTiO3) or (Ba,Sr)TiO3(B Insulators such as PTFE (Titanium Dioxide) can be used in single or multilayer configurations. For example, aluminum oxide, bismuth oxide, germanium oxide, niobium oxide, silicon oxide, Titanium oxide, tungsten oxide, yttrium oxide, and zirconium oxide may be added. Alternatively, these insulators may be nitrided. Silicon or silicon nitride may also be used in a laminated form.

[0158] As the insulator 20, like the insulator 19, more oxygen than that which satisfies the stoichiometric composition is used. It is preferable to use an oxide insulator containing excess oxygen. By providing the oxide semiconductor 40 in contact with the oxide semiconductor 40, oxygen vacancies in the oxide semiconductor 40 are reduced. It is possible.

[0159] The insulator 20 may be aluminum oxide, aluminum oxynitride, hafnium oxide, or oxide. Uses insulators such as hafnium nitride and silicon nitride that have barrier properties against oxygen and hydrogen. When such a material is used, oxygen from the oxide semiconductor 40 can be removed. It functions as a layer that prevents the release of hydrogen and other impurities from entering from the outside.

[0160] Conductors S21 and S22 are aluminum, titanium, chromium, nickel, copper, and yttrium. metals such as zirconium, molybdenum, silver, tantalum, or tungsten, or Although the figure shows a single-layer structure, it is possible to use an alloy with two or more layers. The above laminated structure may also be used.

[0161] For example, the conductors S21 and S22 may be made of a laminate of titanium and aluminum. Two-layer structure with aluminum laminated on tungsten, copper-magnesium-aluminum alloy Two-layer structure with copper layered on gold, two-layer structure with copper layered on titanium, copper layered on tungsten A two-layer structure may also be used.

[0162] For example, the conductors S21 and S22 may be titanium or titanium nitride with aluminum or titanium nitride on top. A three-layer structure in which titanium or titanium nitride is laminated on top of copper or molybdenum. Molybdenum or molybdenum nitride is layered on top of that, and aluminum or copper is layered on top of that. There are three-layer structures in which indium oxide or molybdenum nitride are laminated. Transparent conductive materials including tin oxide or zinc oxide may also be used.

[0163] The conductor G21 may be made of, for example, aluminum, chromium, copper, tantalum, titanium, molybdenum, or titanium. or an alloy containing the above metals, or It can be formed by using a combination of alloys, etc. Also, manganese, zirconium, etc. One or more metals selected from the above may be used. Semiconductors such as doped polycrystalline silicon, silicides such as nickel silicide, It may be used.

[0164] For example, the conductor G21 may have a two-layer structure in which titanium is laminated on aluminum. In addition, there are two-layer structures in which titanium is laminated on titanium nitride, and tungsten is laminated on titanium nitride. a two-layer structure in which tungsten is laminated on tantalum nitride or tungsten nitride; It may also be possible to use the following.

[0165] The conductor G21 is made of indium tin oxide, indium oxide containing tungsten oxide, etc. , indium zinc oxide containing tungsten oxide, indium oxide containing titanium oxide, Indium tin oxide containing titanium oxide, indium zinc oxide, silicon oxide added A light-transmitting conductive material such as indium tin oxide can also be used.

[0166] By using a conductive material with a high work function as the conductor G21, V th The work function of the conductor G21 is preferably Preferably, it is 4.8 eV or more, more preferably 5.0 eV or more, and even more preferably 5.2 eV or more. eV or more, more preferably 5.4 eV or more, and even more preferably 5.6 eV or more Conductive materials with a large work function include, for example, molybdenum and molybdenum oxide. Indium, Pt, Pt silicide, Ni silicide, Indium tin oxide, Nitrogen doped Examples include In-Ga-Zn oxide.

[0167] An insulator 21 is provided to cover the conductor G21. The insulator 21 is made of aluminum oxide, Aluminum nitride, hafnium oxide, hafnium oxynitride, silicon nitride, etc. An insulator with a barrier property against hydrogen can be used. In this case, the conductor G21 can be prevented from being oxidized during the heat treatment process. The insulator 21 can be omitted by using a material that is difficult to oxidize for the conductor G21. .

[0168] An insulator 26 is provided above the transistor OS1. The insulator 26 contains excess oxygen. In particular, it is preferable that an insulator having excess oxygen is provided in an interlayer film near the transistor OS1. By providing the above, the oxygen vacancies in the transistor OS1 are reduced, thereby improving reliability. It is possible.

[0169] As an insulator having excess oxygen, specifically, an oxide material from which some oxygen is released by heating is used. It is preferable to use an oxide material that releases oxygen when heated. , the amount of oxygen released in terms of oxygen atoms is 1.0 × 10 18 atoms / cm 3 Above, I like Or 3.0 x 10 20 atoms / cm3 The oxide film is as described above. The surface temperature of the membrane during analysis is 100°C or higher and 700°C or lower, or 100°C or higher. A range of 500°C or less is preferred.

[0170] For example, a material containing silicon oxide or silicon oxynitride is used as such a material. In this specification, silicon oxynitride refers to a material having a composition of nitrogen. Silicon nitride oxide refers to a material that contains more oxygen than silicon. indicates a material with a higher nitrogen content than

[0171] <<Storage device configuration example>> FIG. 10 shows an example of the configuration of a memory device 100 having a memory cell 10a or a memory cell 10b. In the following description, the memory cell 10a or the memory cell 10b will be referred to as They are collectively referred to as memory cells 10.

[0172] The memory device 100 shown in FIG. 10 includes a memory cell array 10 having a plurality of memory cells 10. 1, row selection driver 102, and column selection driver 103. A memory matrix with n rows (m is a natural number greater than or equal to 2) and n columns (n ​​is a natural number greater than or equal to 2). It has 10 resellers.

[0173] In FIG. 10, the wiring WWL[m-1] connected to the memory cell 10 in the (m-1)th row, the wiring RWL[m-1], the wiring WWL[m] connected to the memory cell 10 in the m-th row, the wiring RWL[m], and connects the memory cell 10 in the (m-1)th row and the memory cell 10 in the mth row. The memory cell 10 in the (m-1)th row and the memory cell 11 in the mth row are connected to the wiring WCL. 0.

[0174] In addition, in FIG. 10, the wiring BL[n-1] connected to the memory cell 10 in the (n-1)th column, The wiring BL[n] connected to the memory cell 10 in the nth column is shown, and the wiring BL[n] connected to the memory cell 10 in the (n-1)th column is shown. 10 and a wiring SL connected to the memory cells 10 in the n-th column.

[0175] In the memory cell array 101 shown in FIG. 10, the wirings SL and WC By adopting this configuration, the occupied area of ​​each wiring is Therefore, in a storage device employing this configuration, the memory area per unit area is reduced. This allows for an improvement in storage capacity.

[0176] The row selection driver 102 selects the transistors OS1 and Tr1 in each row of the memory cells 10. The row selection driver 102 is a circuit having a function of selectively bringing the row selection driver 102 into a conductive state. The memory device 100 selects writing and reading of data to the memory cells 10 on a row-by-row basis. This can be done as follows.

[0177] The column select driver 103 selectively applies data to the node FN in each column of the memory cells 10. A function for writing, a function for initializing the potential of the wiring BL, and a function for electrically floating the wiring BL. Specifically, a circuit that applies a potential corresponding to data to a wiring BL By providing the column selection driver 103, the memory device 100 can select the column selection driver 103 for the memory cells 10. Data can be written and read by selecting each column.

[0178] As described above, by using the memory cell shown in this embodiment mode, a highly integrated memory cell can be provided. It is also possible to provide a storage device that stores a large amount of data. In addition, a memory device with low power consumption can be provided.

[0179] (Embodiment 2) In this embodiment, another structural example of the memory cell shown in Embodiment 1 will be described with reference to FIG. The explanation will be given with reference to FIG.

[0180] The memory cells 10a and 10b shown in FIG. 1 have the wiring BL as the wiring BL1 for writing data. , and data read wiring BL2. In this case, the configuration example is shown in FIG. B).

[0181] FIG. 11A shows that the wiring BL of the memory cell 10a is divided into two wirings, BL1 and BL2. 10 is a circuit diagram of a memory cell 10c when the source or drain of a transistor OS1 is The other end is electrically connected to the wiring BL1, and the other end is connected to the source or drain of the transistor Tr1. The other end is electrically connected to the wiring BL2.

[0182] FIG. 11B shows that the wiring BL of the memory cell 10b is divided into two wirings, BL1 and BL2. 10 is a circuit diagram of a memory cell 10d when the source or drain of a transistor OS1 is The other end is electrically connected to the wiring BL1, and the other end is connected to the source or drain of the transistor Tr1. The other end is electrically connected to a wiring BL2 via a transistor Tr2.

[0183] As in the memory cell 10c and the memory cell 10d, the wiring BL is used as the wiring for data writing. By dividing the wiring into two for data writing and reading, data writing and reading can be performed independently. This allows for increased freedom in the operation of the memory cells.

[0184] The memory cells 10a and 10b shown in FIG. 1 are shown with the transistor Tr2 and the wiring RWL omitted. The circuit diagram for this case is shown in Figures 12(A) and 12(B).

[0185] FIG. 12A shows the transistor Tr2 of the memory cell 10a or the memory cell 10b. 1 is a circuit diagram of a memory cell 10e when the wiring RWL is omitted. By applying an L-level potential, data can be read from the memory cell 10. Since memory cell e has fewer transistors and wirings than memory cells 10a and 10b, The size of the memory cells can be reduced, and the memory cells can be highly integrated.

[0186] FIG. 12B shows a wiring BL of the memory cell 10e, which is connected to a wiring BL1 for writing data and a wiring BL2 for writing data. 1 is a circuit diagram of a memory cell 10f when it is divided into a data read wiring BL2. The other of the source and drain of the transistor OS1 is electrically connected to the wiring BL1. The other of the source and drain of Tr1 is electrically connected to the wiring BL2. This allows data to be written and read independently, and the operation of the memory cell It can increase the degree of freedom.

[0187] (Embodiment 3) In this embodiment, the transistor Tr1 and the transistor Tr2 shown in the first embodiment are Another configuration example will be described with reference to FIG.

[0188] FIG. 13A is a top view of the transistor Tr1 and the transistor Tr2 (FIG. 3A). FIG. 13(B) shows the cross section of the dashed line X1-X2 in FIG. 13(A). 13(C) shows a cross-sectional view taken along the dashed line Y1-Y2 in FIG. 13(A). The dashed dotted line X1-X2 indicates the channel length direction of the transistors Tr1 and Tr2. The dashed dotted line Y1-Y2 may be referred to as the channel width direction of the transistor Tr1.

[0189] In the transistors Tr1 and Tr2 shown in FIG. 13, the semiconductor SEM3 has a convex shape. Insulators 34a and 34b and conductors G11 and G12 are provided along the upper surface. A transistor having such a shape is called a FIN transistor. Although the case where a part of the plate 11 is processed to form a convex portion has been shown, it is also possible to process the SOI substrate to form a convex shape. It may be formed.

[0190] In a FIN transistor, the channel formation region is surrounded by gate electrodes on the top, left and right sides. Therefore, the gate electric field can be effectively applied to the channel forming region. The on-current of the transistor can be improved and the short channel effect can be suppressed.

[0191] For details regarding the other components shown in FIG. 13, please refer to the description of FIG.

[0192] (Fourth embodiment) In this embodiment, other configuration examples of the transistor OS1 described in Embodiment 1 will be described. The following description will be given with reference to FIGS. 14 and 15.

[0193] <<Configuration Example 1>> FIG. 14A is a top view of the memory cell 10a, showing the transistor OS1 and the capacitance element C 14(B) shows the area around s1 and its surroundings along the dashed line Y1-Y2 in FIG. 14(A) shows a cross-sectional view taken along the dashed line X1-X2 in FIG. 14(A), and FIG. 14(C) shows a cross-sectional view taken along the dashed line X1-X2 in FIG. The dashed line Y1-Y2 indicates the channel length direction of the transistor OS1, and the dashed line X1-X2 may be referred to as the channel width direction of the transistor OS1.

[0194] 14B, the oxide semiconductor 43 is omitted from the cross-sectional view of FIG. 6. An oxide semiconductor 45 is provided in place of the conductive layer 41 and the oxide semiconductor 42. The conductor S21 and the conductor S22 are provided so as to be in contact with the side surfaces of the oxide semiconductor 45. The insulator 21 is provided to cover the transistor OS1 and the capacitance element Cs1. This simplifies the manufacturing process of the memory cell 10a.

[0195] In FIGS. 14A to 14C, the insulator 20 is the gate insulator of the transistor OS1. The conductor S22 functions as a dielectric of the capacitance element Cs1. It functions as either the source or drain of the transistor OS1, and It also functions as a first electrode.

[0196] As in FIG. 6, the dielectric (insulator 20) of the capacitance element Cs1 in FIGS. 14(B) and 14(C) The film thickness is preferably thinner than the film thickness of the dielectric of the capacitive element Cs2.

[0197] The oxide semiconductor 45 may be any of the oxide semiconductors 41 to 43. can be applied.

[0198] For details regarding the other components shown in FIGS. 14(A) to 14(C), see FIGS. 6 and 8(A). Please refer to the descriptions in (C) and (D).

[0199] <<Configuration Example 2>> FIG. 15A is a top view of the memory cell 10a, showing the transistor OS1 and the capacitance element C 15(B) shows the area around s1 and its surroundings along the dashed line Y1-Y2 in FIG. 15(C) shows a cross-sectional view taken along the dashed line X1-X2 in FIG. 15(A). The dashed line Y1-Y2 indicates the channel length direction of the transistor OS1, and the dashed line X1-X2 may be referred to as the channel width direction of the transistor OS1.

[0200] In FIGS. 15A to 15C, the insulator 20 is the gate insulator of the transistor OS1. The conductor S22 functions as a dielectric of the capacitance element Cs1. It functions as either the source or drain of the transistor OS1, and It also functions as a first electrode.

[0201] As in FIG. 6, the dielectric (insulator 20) of the capacitance element Cs1 in FIGS. 15(B) and (C) The film thickness is preferably thinner than the film thickness of the dielectric of the capacitive element Cs2.

[0202] The transistor OS1 shown in FIGS. 15A to 15C is formed in an opening in the insulator 26. , an oxide semiconductor 43, an insulator 20, and a conductor G21 are formed.

[0203] The transistor OS1 is connected to the conductor G21 and the conductor S21 (or the conductor G21 and the conductor S2 2) has a structure where the conductors G21 and S21 do not overlap, By reducing the parasitic capacitance (or the parasitic capacitance formed between conductor G21 and conductor S22), That is, a transistor with a high operating frequency can be provided.

[0204] For details of the other components shown in FIG. 15, please refer to the descriptions of FIGS. 6 and 8. .

[0205] (Embodiment 5) In this embodiment, a semiconductor device including the memory device described in Embodiment 1 will be described. .

[0206] For example, the storage device may be incorporated into a processor (also called a "processing unit"). The processor stores data (including instructions) necessary for processing. PU, GPU (Graphics Processing Unit), PLD (Pro grammable Logic Device), DSP(Digital Sign al Processor), MCU (Microcontroller Unit), These include custom LSI and RFIC.

[0207] < <cpu>> 16 is a block diagram showing an example of the configuration of a CPU. U-core 1330, power management unit (PMU) 1331 and peripheral circuits 13 It has 32.

[0208] The CPU core 1330 includes a control unit 1307, a program counter (PC) 1308, and a processor. A pipeline register 1309, a pipeline register 1310, an arithmetic logic unit (ALU) rithmetic logic unit) 1311, and register file 131 2, and a data bus 1333. Data transfer occurs via a data bus 1333 .

[0209] The PMU 1331 includes a power controller 1302 and a power switch 1303. The peripheral circuit 1332 includes a cache memory 1304, a bus interface (BUS I / F) 1305 and Debug I / F 1306. do.

[0210] The storage device of the first embodiment can be applied to the cache memory 1304. This makes it possible to suppress increases in area and power consumption and increase the capacity of the cache memory 1304. In addition, the standby power consumption of the cache memory 1304 can be reduced, resulting in a compact This makes it possible to provide a CPU 1300 with low power consumption.

[0211] The control unit 1307 includes a program counter 1308, a pipeline register 1309, and a program counter 1309a. Pipeline register 1310, ALU 1311, register file 1312, cache memory 1304, bus interface 1305, debug interface 1306, and the operation of the power controller 1302 are controlled in an integrated manner, It has the function of decoding and executing instructions contained in programs such as applications.

[0212] The ALU 1311 has the function of performing various arithmetic operations such as arithmetic operations and logical operations. The flash memory 1304 has a function of temporarily storing frequently used data. The program counter 1308 is a register that stores the address of the next instruction to be executed. Although not shown in FIG. 16, the cache memory 1304 contains A control circuit is provided to control the operation of the flash memory 1304 .

[0213] The pipeline register 1309 has the function of temporarily storing instruction data. The data file 1312 has a plurality of registers including general-purpose registers, and is connected to the main memory. It stores data read from the ALU1311 or data obtained as a result of ALU1311 arithmetic processing. The pipeline register 1310 is used for the arithmetic processing of the ALU 1311. It temporarily stores data to be used or data obtained as a result of ALU1311 calculations. It has the function of storing information.

[0214] The bus interface 1305 is a communication interface between the CPU 1300 and various devices external to the CPU 1300. The debug interface 130 functions as a data path between the device and the 6 is a signal path for inputting instructions for controlling debugging to the CPU 1300; It has the function of

[0215] The power switch 1303 is a power supply that the CPU 1300 has other than the power controller 1302. It has the function of controlling the supply of power supply voltage to various circuits. The power-gated circuit is one of the CPUs 1300. The circuits that belong to the same power domain are connected by a power switch. The power supply voltage is controlled by the power controller 1303. The power supply management system has a function of controlling the operation of the power switch 1303. This allows the CPU 1300 to perform power gating.

[0216] < <rfic>> As an example of a processor, we will explain RFIC. RFIC is a processor that is used for RF tags, wireless chips, etc. RFICs are also called RFID chips, wireless ID chips, etc. RFICs have internal memory circuits. The necessary information is stored in the device, and information is exchanged with the outside world using a non-contact means, such as wireless communication. Due to these characteristics, RFIC can read individual information of items, etc. It can be used in an individual authentication system for identifying items.

[0217] 17 is a block diagram showing an example of the configuration of an RFIC. 404, rectifier circuit 1405, constant voltage circuit 1406, demodulation circuit 1407, modulation circuit 1408 , logic circuit 1409, RAM 1410, ROM (read-only memory) 1411, battery These circuits can be omitted as needed. For example, The RFIC 1400 is an active type, but it is a passive type without a battery 1412. Here, the RFIC 1400 may be configured as a A semiconductor device that does not include an antenna 1404 is called an RFIC 1400. It is also possible.

[0218] The storage device of the first embodiment can be applied to the RAM 1410. Since memory devices have a high affinity with CMOS circuits, the RFIC1400 is manufactured It is possible to incorporate circuits other than the antenna 1404 into one chip without increasing the complexity of the system. The chip is equipped with an antenna 1404 with performance according to the communication band. The transmission method is an electromagnetic coupling method in which a pair of coils are placed opposite each other and communicate through mutual induction. There are various methods, such as the electromagnetic induction method, which uses electromagnetic fields to communicate, and the radio wave method, which uses radio waves to communicate. The RFIC 1400 shown in the embodiment can be used in either system.

[0219] The antenna 1404 transmits a radio signal to an antenna 1421 connected to a communication device 1420. The rectifier circuit 1405 is for transmitting and receiving the antenna 1404. The input AC signal generated by receiving a radio signal is rectified, for example, by half-wave double voltage rectification. The input voltage is then smoothed by the capacitive element installed in the subsequent stage. The rectifier circuit 1405 is a circuit for generating a limiting voltage. A limiter circuit is a circuit that limits the amplitude of the input AC signal to the internally generated voltage. When the power consumption is large, the power consumption is controlled so that it does not exceed a certain level. It is a road.

[0220] The constant voltage circuit 1406 generates a stable power supply voltage from the input voltage and supplies it to each circuit. The constant voltage circuit 1406 has a reset signal generating circuit inside. The reset signal generation circuit may utilize the rising edge of the stable power supply voltage to reset the logic circuit. This is a circuit for generating a reset signal for 1409.

[0221] The demodulation circuit 1407 demodulates the input AC signal by detecting its envelope and generates a demodulated signal. The modulation circuit 1408 is a circuit for modulating the data output from the antenna 1404. This is a circuit for performing modulation according to the data.

[0222] The logic circuit 1409 is a circuit for decoding and processing the demodulated signal. , a circuit that holds input information, row decoder, column decoder, driver, memory area The ROM 1411 stores a unique number (ID) and other information, and This is a circuit for outputting.

[0223] (Embodiment 6) In this embodiment mode, a semiconductor wafer including the memory device or the semiconductor device described in the above embodiment mode is Examples of wafers, IC chips, and electronic components will be described with reference to FIGS.

[0224] [Semiconductor wafers, chips] FIG. 18(A) shows a top view of the substrate 611 before the dicing process is performed. The plate 611 may be, for example, a semiconductor substrate (also called a "semiconductor wafer"). A plurality of circuit regions 612 are provided on the substrate 611. The semiconductor device or the like described in the above embodiment mode can be provided.

[0225] The plurality of circuit regions 612 are each surrounded by an isolation region 613. A separation line (also called a "dicing line") 614 is set at the overlapping position. By cutting the substrate 611 along the 14, chips 615 including circuit regions 612 are separated from the substrate 6 The chip 615 can be cut out from the substrate 11. An enlarged view of the chip 615 is shown in FIG.

[0226] A conductive layer or a semiconductor layer may be provided in the separation region 613. By providing a conductive layer, ESD that may occur during the dicing process is mitigated, and This prevents a decrease in yield. In addition, the dicing process generally requires cooling the substrate, grinding, and Pure water that has been treated with carbon dioxide gas to reduce its resistivity for the purposes of removing dust and preventing static electricity. By providing a conductive layer or a semiconductor layer in the separation region 613, The amount of pure water used can be reduced, thereby reducing the production cost of semiconductor devices. Furthermore, the productivity of semiconductor devices can be improved.

[0227] The semiconductor layer provided in the separation region 613 has a band gap of 2.5 eV or more and 4.2 eV or less. It is preferable to use a material with a specific energy of 2.7 eV or more and 3.5 eV or less. Such materials are more resistant to ESD because they allow the accumulated charge to slowly discharge. This suppresses the sudden movement of charges due to static electricity, making it less likely that electrostatic breakdown will occur.

[0228] [Electronic Components] An example of applying the chip 615 to an electronic component will be described with reference to FIG. The product is also called a semiconductor package or IC package. There are multiple standards and names depending on the direction and terminal shape.

[0229] The electronic component is a semiconductor device according to the above embodiment that is used in an assembly process (post-process). The device is completed by combining components other than the semiconductor device.

[0230] The post-process will be explained using the flowchart shown in Figure 19(A). After the element substrate having the semiconductor device shown in the above embodiment is completed, the back surface ( The back surface (the surface on which semiconductor devices are not formed) is ground (step S1). By thinning the element substrate through grinding, warping of the element substrate can be reduced, and electronic components can be It is possible to reduce the size of the device.

[0231] Next, a "dicing step" is carried out to separate the element substrate into a plurality of chips (step S2). Then, the separated chips are individually picked up and bonded onto the lead frame. The die bonding process is then carried out (step S3). The joining to the frame is done by resin joining, tape joining, etc., depending on the product. In addition, instead of a lead frame, the chip is bonded to an interposer substrate. You may do so.

[0232] Next, the leads of the lead frame and the electrodes on the chip are electrically connected with thin metal wires. The wire bonding process is then carried out to connect the wires to the substrate (step S4). Silver wire or gold wire can be used. Wire bonding is also called ball bonding. Alternatively, wedge bonding can be used.

[0233] The wire-bonded chip is sealed with epoxy resin in the "sealing process (module)". The electronic components are then sealed in a resin (step S5). The circuitry built into the chip and the wires connecting the chip and the leads are mechanically It can protect from external forces and reduce deterioration of characteristics (reduced reliability) due to moisture and dust. It is possible.

[0234] Next, a "lead plating process" is carried out to plate the leads of the lead frame (step The plating process prevents the leads from rusting and prevents soldering when later attached to the printed circuit board. Next, the leads are cut and shaped. The "process" is carried out (step S7).

[0235] Next, a "marking process" is carried out, in which printing (marking) is applied to the surface of the package. (Step S8) Then, the "inspection process" ( After step S9), the electronic component is completed.

[0236] A perspective view of the completed electronic component is shown in FIG. 19(B). As an example of a product, a perspective view of a QFP (Quad Flat Package) is shown below. The electronic component 650 shown in FIG. 19(B) includes leads 655 and a semiconductor device 653. The semiconductor device 653 may be the memory device or semiconductor device shown in the above embodiment modes. Placement etc. can be used.

[0237] The electronic component 650 shown in FIG. 19(B) is provided on, for example, a printed circuit board 652. A plurality of such electronic components 650 are combined and each is electrically connected on a printed circuit board 652. By connecting the components together, a substrate 654 is completed. Used in electronic devices, etc.

[0238] (Embodiment 7) The memory device or the semiconductor device described in the above embodiment is used in an electronic device having a built-in battery. It is preferable that the storage device or the like described in the above embodiment is used in an electronic device having a built-in battery. By using the semiconductor device, the power consumption of the electronic device can be reduced and the battery power can be saved. A specific example is shown in Figure 20.

[0239] FIG. 20A shows a wristwatch-type terminal 700. The wristwatch-type terminal 700 includes a housing 701, a crown, a The housing 701 includes a lens 702, a display unit 703, a belt 704, a detection unit 705, and the like. The display unit 703 has a battery, a memory device, or a semiconductor device. The user can input information by using a finger that touches the touch panel as a pointer. can.

[0240] The detection unit 705 has a function of detecting the surrounding conditions and acquiring information. For example, Acceleration sensor, direction sensor, pressure sensor, temperature sensor, humidity sensor, illuminance sensor or G Detects PS (Global Positioning System) signal receiving circuits, etc. It can be used in part 705.

[0241] For example, the ambient brightness detected by the illuminance sensor of the detection unit 705 is input to the calculation unit inside the housing 701. However, when it is determined that the illuminance is sufficiently bright compared with a predetermined illuminance, the luminance of the display unit 703 is reduced. Alternatively, if it is determined that the light is dim, the luminance of the display unit 703 is increased. Reduced electronics can be provided.

[0242] FIG. 20B shows a mobile phone 710. The mobile phone 710 includes a housing 711, a display unit 7 16, operation buttons 714, external connection port 713, speaker 717, microphone 712, etc. The housing 711 has a battery, a memory device, or a semiconductor device therein. 710 allows information to be input by touching the display unit 716 with a finger or the like. Any operation such as making a call or entering text can be performed by touching the display unit 716 with a finger or the like. Also, by operating the operation button 714, the power can be turned on, It is possible to switch the OFF operation and the type of image displayed on the display unit 716. For example, You can switch from the email creation screen to the main menu screen.

[0243] FIG. 20C shows a notebook personal computer 720, which includes a housing 721, a display unit 72, and a 2, a keyboard 723, a pointing device 724, etc. The housing 721 has It has a battery, a memory device or a semiconductor device.

[0244] Figure 20(D) shows a goggle-type display 730. The goggle-type display 730 is , a mounting portion 731, a housing 732, a cable 735, a battery 736, and a display portion 737. The battery 736 is housed in the mounting portion 731. The display portion 737 is provided in the housing 732. The housing 732 houses various electronic components such as a semiconductor device, a wireless communication device, and a memory device. A display unit 737 and a display unit 738 are connected to a battery 736 via a cable 735. Power is supplied to the electronic components. The display unit 737 displays various images, such as images transmitted wirelessly. The information is displayed.

[0245] The goggle-type display 730 may have a camera in the housing 732. By detecting the movement of the eyeballs and eyelids, the user can operate the goggle-type display 730. The goggle-type display 730 can also include a temperature sensor in the mounting section 731. Various sensors such as a pressure sensor, an acceleration sensor, and a biosensor may be provided. The display 730 acquires biometric information of the user by a biometric sensor, and displays the biometric information on the housing 732. The goggle-type display 730 also stores the information in a storage device within the goggle-type display 730 by wireless signals. The acquired biometric information may be transmitted to another information terminal.

[0246] 20(E) shows a video camera 740. The video camera 740 is made up of a first housing 741, a second housing 742, a 2. The device has a housing 742, a display unit 743, operation keys 744, a lens 745, a connection unit 746, etc. The operation keys 744 and the lens 745 are provided on the first housing 741, and the display unit 743 The first housing 741 is provided with a battery, a storage device, and The battery may be provided outside the first housing 741. The housing 741 and the second housing 742 are connected by a connection part 746. The angle between the display unit 743 and the second housing 742 can be changed by the connector 746. The image at the first housing 741 is projected in accordance with the angle between the first housing 741 and the second housing 742 at the connection portion 746. It may be configured to switch between them.

[0247] FIG. 20(F) shows an automobile 750. The automobile 750 comprises a body 751, wheels 752, a dash The vehicle body 751 has a battery, a storage device, and a has a semiconductor device.

[0248] In this specification, the ordinal numbers "first," "second," and "third" are used to avoid confusion of the constituent elements. Therefore, it does not limit the number of components. The order of the components is not limited. In this case, a component referred to as "first" may be used in other embodiments or in the claims. In addition, for example, in the implementation of this specification, The elements referred to as "first" in one embodiment may be used in other embodiments or in the claims. It may be omitted within the scope of the request.

[0249] In this specification, unless otherwise specified, the on-current is the current when a transistor is in the on-state. The on-state refers to the drain current when the transistor is in the on-state, unless otherwise specified. In a transistor, the voltage between the gate and source (V G ) is the threshold voltage (V th ) or more states, p In a channel transistor, V G V th For example, the following state is shown: The on-current of a transistor is V G V th This refers to the drain current when The on-state current of a transistor is determined by the voltage between the drain and source (V D ) may depend on

[0250] In this specification, unless otherwise specified, the off-state current refers to the current when a transistor is in an off state. The off state refers to the drain current when the transistor is in the off state unless otherwise specified. At the stadium, V G V th For p-channel transistors, V G V th For example, the off-state current of an n-channel transistor is higher than V G V th The off-state current of a transistor is the drain current when the voltage is lower than V G Depends on Therefore, the off-state current of the transistor may be -21 Less than A means that The off-state current of the transistor is 10 -21 V less than A G It may be said that there exists a value of

[0251] The off-state current of the transistor is V D In this specification, Currents are V unless otherwise specified. D The absolute value of is 0.1V, 0.8V, 1V, 1.2V, 1 0.8V, 2.5V, 3V, 3.3V, 10V, 12V, 16V, or 20V Alternatively, it may refer to a semiconductor device that includes the transistor. Used V D The term may refer to the off-state current at

[0252] In this specification and the like, when describing the connection relationship of a transistor, one of the source and the drain is referred to as "one of the source and drain" (or the first electrode or the first terminal), and the source The other of the source and drain is called the "other of the source or drain" (or second electrode, or second terminal). This means that the source and drain of a transistor are This is because it changes depending on the operating conditions, etc. Regarding the names of the source and drain of a transistor, In this case, the term source (drain) terminal, source (drain) electrode, etc. may be used appropriately depending on the situation. It can be replaced.

[0253] In this specification, the terms "electrode" and "wiring" are used to define these components functionally. For example, an "electrode" may be used as part of a "wiring" and vice versa. Furthermore, the terms "electrode" and "wiring" are used to refer to a plurality of "electrodes" and "wirings." This also includes cases where they are formed integrally.

[0254] In this specification and the like, the terms voltage and potential can be interchanged as appropriate. For example, the reference potential is the ground potential (earth potential). If we use the term "ground potential" (potential), we can translate voltage into potential. Note that the potential is relative, and the distribution may differ depending on the reference potential. The potential applied to the wires may be changed.

[0255] In this specification, a switch refers to a device that is in a conducting state (ON) or a non-conducting state (OFF). It is a device that has the function of controlling whether or not current flows. refers to a device that has the function of selecting and switching the path through which current flows. The switch may be a static or mechanical switch. Anything that can control the above is acceptable, and is not limited to a specific one.

[0256] An example of an electrical switch is a transistor (e.g., a bipolar transistor, M OS transistors, etc.), diodes (e.g., PN diodes, PIN diodes, Schottky diode, MIM (Metal Insulator Metal) diode MIS (Metal Insulator Semiconductor) diodes diode-connected transistors), or logic circuits that combine these. be.

[0257] When a transistor is used as a switch, the "conduction state" of the transistor is This refers to a state in which the source and drain of a transistor can be considered to be electrically short-circuited. The "non-conducting state" of a transistor means that the source and drain of the transistor are electrically isolated. In addition, when a transistor is operated simply as a switch, In this case, the polarity (conductivity type) of the transistor is not particularly limited.

[0258] An example of a mechanical switch is a digital micromirror device (DMD). There are switches that use MEMS (microelectromechanical systems) technology. The switch has a mechanically movable electrode, and the movement of the electrode Thus, the device operates by controlling conduction and non-conduction.

[0259] For example, in this specification, when it is explicitly stated that X and Y are connected, In this case, X and Y are electrically connected, and X and Y are functionally connected. The case where X and Y are directly connected is also considered to be disclosed in this specification. Therefore, the present invention is not limited to the predetermined connection relationships, for example, the connection relationships shown in the drawings or text. Connections other than those shown in the drawings or text are also treated as if they were described in the drawings or text. do.

[0260] Here, X and Y are the object (for example, a device, an element, a circuit, a wiring, an electrode, a terminal, a conductive film, a layer, etc.). , etc.).

[0261] An example of a direct connection between X and Y is a circuit that allows electrical connection between X and Y. The elements to be considered (e.g., switches, transistors, capacitance elements, inductors, resistance elements, When no external device (such as a diode, display element, light-emitting element, or load) is connected between X and Y, The elements that allow electrical connection between X and Y (e.g., switches, transistors, capacitors) elements, inductors, resistors, diodes, display elements, light-emitting elements, loads, etc.) , X and Y are connected.

[0262] An example of an electrical connection between X and Y is The elements to be considered (e.g., switches, transistors, capacitance elements, inductors, resistance elements, One or more devices (such as diodes, display elements, light-emitting elements, and loads) can be connected between X and Y. It is possible.

[0263] An example of a functional connection between X and Y is a function that allows the functional connection between X and Y. Circuits that perform the above functions (for example, logic circuits (inverters, NAND circuits, NOR circuits, etc.), signal conversion conversion circuits (DA conversion circuits, AD conversion circuits, gamma correction circuits, etc.), potential level conversion circuits (voltage power supply circuits (voltage boost circuits, voltage drop circuits, etc.), level shifter circuits that change the signal potential level, etc.) , voltage source, current source, switching circuit, amplifier circuit (which can increase the signal amplitude or current amount, etc.) circuits, operational amplifiers, differential amplifier circuits, source follower circuits, buffer circuits, etc.), signal generation One or more circuits (e.g., memory circuits, control circuits, etc.) can be connected between X and Y. For example, even if another circuit is inserted between X and Y, the signal output from X If X is transmitted to Y, then X and Y are considered to be functionally connected. When X and Y are functionally connected, there is a direct connection between X and Y and a direct connection between X and Y. This also includes the case where the and are electrically connected.

[0264] In addition, if it is explicitly stated that X and Y are electrically connected, are electrically connected (i.e., there is another element or circuit between X and Y) X and Y are functionally connected (i.e., X and Y are functionally connected) and (When there is a functional connection between them via another circuit) and when X and Y are directly connected (i.e., when X and Y are connected without any other element or circuit between them) is considered to be disclosed in the present specification. If it is explicitly stated that it is connected, The same content is considered to be disclosed in the present specification.

[0265] For example, if the source (or first terminal, etc.) of the transistor is connected via Z1 (or (not shown), electrically connected to X, and the drain (or second terminal, etc.) of the transistor is connected to Z 2 (or not), and is electrically connected to Y, or the source of the transistor (or the first terminal, etc.) is directly connected to a part of Z1, and another part of Z1 is directly connected to X. The drain (or second terminal, etc.) of the transistor is directly connected to a part of Z2. and another part of Z2 is directly connected to Y, It is possible to do so.

[0266] For example, "X and Y and the source (or first terminal, etc.) and drain (or second terminal, etc.) of a transistor" The terminals of the transistor (or the first terminal) are electrically connected to each other. 1 terminal, etc.), the drain of the transistor (or the second terminal, etc.), and Y. It can be expressed as "connected to the source (or the first The first terminal of the transistor is electrically connected to X, and the drain of the transistor is electrically connected to the second terminal of the transistor. The transistor source (or first terminal, etc.) is electrically connected to Y, and the transistor source (or first terminal, etc.) is electrically connected to X. The drain (or second terminal, etc.) of the transistor, Y, is electrically connected in this order. " Alternatively, "X is the source (or first terminal, etc.) of the transistor. and the drain (or second terminal, etc.) are electrically connected to Y, and X, the source (or first terminal, etc.) of a transistor, the drain (or second terminal, etc.) of a transistor ), Y is provided in this order of connection. By specifying the order of connections in the circuit configuration using a simple expression method, Distinguish between the source (or first terminal, etc.) and the drain (or second terminal, etc.) of a transistor. The technical scope can be determined by the above.

[0267] Alternatively, for example, "the source (or first terminal, etc.) of a transistor" is electrically connected to X through at least a first connection path, and the first connection path is , and the second connection path is a transistor through a transistor. The source (or first terminal, etc.) of the transistor and the drain (or second terminal, etc.) of the transistor The first connection path is a path via Z1, and the second connection path is a path between the first and second transistors. The drain (or second terminal, etc.) of the capacitor is electrically connected to Y through at least a third connection path. the third connection path does not have the second connection path, and the third connection path The connection path is the path via Z2. The source (or first terminal, etc.) of the resistor is connected to the resistor via Z1 by at least the first connection path. and electrically connected to X, and the first connection path does not have a second connection path; The second connection path has a connection path through a transistor, and (or the second terminal, etc.) is connected to Y via Z2 by at least a third connection path. The third connection path does not have the second connection path. Alternatively, the source (or first terminal, etc.) of the transistor may be at least The first electrical path is electrically connected to X through Z1. The primary path does not have a second electrical path, and the second electrical path is a From the source (or first terminal, etc.) to the drain (or second terminal, etc.) of the transistor The drain (or second terminal, etc.) of the transistor is connected to at least a third The third electrical path is electrically connected to Y through Z2. , does not have a fourth electrical path, and the fourth electrical path is (or second terminal, etc.) to the source (or first terminal, etc.) of the transistor. Using the same expression as these examples, the circuit configuration By defining the connection path in Distinguishing between the first terminal (or the second terminal, etc.) and the drain (or the second terminal, etc.) to determine the technical scope. can be done.

[0268] These representation methods are merely examples, and the present invention is not limited to these representation methods. , Y, Z1, Z2 are objects (e.g., devices, elements, circuits, wiring, electrodes, terminals, conductive films, layer, etc.).

[0269] In addition, the circuit diagram shows independent components as if they are electrically connected to each other. Even if the components are different, one component may have the functions of multiple components. For example, when a part of the wiring also functions as an electrode, one conductive film functions as both the wiring and the electrode. Therefore, the electrode in this specification has the functions of both components. The term "electromagnetic connection" refers to a case where one conductive film has the functions of multiple components. This also falls within the scope of the above. [Example]

[0270] In this embodiment, the memory capacity and retention time of the memory cell are measured when the area of ​​the memory cell is changed. Calculations were performed on the following.

[0271] Regarding the memory cell 10a shown in the first embodiment and the memory cells shown in FIGS. 21 and 22, A comparison was made.

[0272] The memory cell shown in FIG. 21 is a layer L including the memory cell 10a shown in FIG. 6 and the capacitance element Cs2. 5 is omitted. The memory cell 10a has a storage capacity of Cs1+Cs2. However, the memory cell shown in FIG. 21 has only Cs1 as its storage capacity.

[0273] The memory cell shown in FIG. 22 is the same as the memory cell 10a shown in FIG. 6 except that the conductor G22 is omitted. The memory cell 10a has a storage capacity of Cs1+Cs2. In contrast, the memory cell shown in FIG. 22 has only Cs2 as its storage capacity.

[0274] Figure 23 shows the relationship between the area of ​​a memory cell (cell size) and the memory capacity (Cap capacity) of the memory cell. The data indicated by A represents the memory cell 10a in FIG. 6, and the data indicated by B represents the memory cell 10b in FIG. The data indicated by C represents the memory cell in FIG. 22. The film thickness of the dielectric (insulator 20) of the capacitance element Cs2 is 10 nm, and the film thickness of the dielectric (insulator 23) of the capacitance element Cs3 is 10 nm. The thickness is assumed to be 46 nm. The dielectric constant of the capacitor elements Cs1 and Cs2 is A silicon oxide of 3.9 was assumed.

[0275] The cell size in FIG. 23 corresponds to the product of lx and ly in FIG. 3(A). The thickness and area of ​​each plug are always constant.

[0276] From the calculation results in Figure 23, the storage capacity of A (Cs1 / Cs2) is It was confirmed that the memory capacity of A and B is larger than that of s2). The difference between C and C tends to be smaller, but still, when the cell size is 3.5 μm 2 More than that Therefore, the storage capacity of A (Cs1 / Cs2) is larger than that of B (Cs1) or C (Cs2). It was confirmed that the difference was larger than that.

[0277] Next, the retention time was calculated from the storage capacity in Figure 23. The calculation results are shown in Figure 24.

[0278] The retention times shown in FIG. 24 were calculated according to the following formulas (1) and (2).

[0279] Retention time=ΔQ / (I OFF ·W) (1)

[0280] ΔQ=C·V (2)

[0281] In equation (1), W represents the channel width of the transistor OS1, which is assumed to be 0.15 μm. .I OFF is the ON resistance of transistor OS1 when the channel width is 1 μm and the measurement temperature is 85°C. represents the current, 93 x 10 -24 In equation (2), C is the value shown in Figure 23. The calculated Cap capacitance was substituted, and V was assumed to be an applied voltage of 0.5V.

[0282] From the calculation results in Figure 24, the cell size is 3.5 μm 2 In the above, A(Cs1 / Cs2) It was confirmed that the retention time of Cs1 was longer than that of B (Cs1) or C (Cs2). It was.

[0283] As described above, by using the memory cell 10a shown in the first embodiment in a memory device, the memory device can It was confirmed that data can be retained for a long time. [Explanation of symbols]

[0284] BG wiring, BL wiring, BL1 wiring, BL2 wiring, CE1 conductor, C E2 conductor, Cs1 capacitance element, Cs2 capacitance element, G11 conductor, G12 Conductor, G21 conductor, G22 conductor, L1 layer, L2 layer, L3 layer, L4 layer, L5 layer, M11 conductor, M12 conductor, M13 conductor , M14 conductor, M21 conductor, M22 conductor, M22a conductor, M2 2b conductor, M23 conductor, M24 conductor, M31 conductor, M32 Conductor, M33 Conductor, M34 Conductor, M41 Conductor, M42 Conductor, OS1 transistor, P1 period, P2 period, P3 period, P4 period, P5 period, RWL wiring, S21 conductor, S22 conductor, SEM1 semi-conductor Conductor, SEM2 semiconductor, SEM3 semiconductor, SL wiring, Tr1 transistor Transistor Tr2, V11 plug, V12 plug, V13 plug , V14 plug, V21 plug, V22 plug, V23 plug, V41 Plug, V42 Plug, V43 Plug, V44 Plug, V45 Plug Plug, V46 Plug, V51 Plug, V52 Plug, V53 Plug, V5 4 plugs, WCL wiring, WWL wiring, 10 memory cells, 10a memory Resell, 10b memory cell, 10c memory cell, 10d memory cell, 10e memory cell, 10f memory cell, 11 substrate, 12 element isolation layer, 13 Insulator, 14 Sidewall insulating layer, 14a Sidewall insulating layer, 14b Sidewall insulating layer, 15 Sidewall insulating layer, 15a Sidewall insulating layer, 15b Sidewall insulating layer, 16 Insulator, 17 Insulators, 18 Insulators, 19 Insulators, 20 Insulators, 21 Insulators, 22 Insulators, 23 Insulators, 24 Insulators, 25 Insulators, 26 Insulators, 31a High concentration impurity region, 31c High concentration impurity region, 32a Low concentration impurity region, 32 d lightly doped region, 33a conductive region, 33c conductive region, 34a isolated Insulators, 34b Insulators, 40 Oxide semiconductors, 41 Oxide semiconductors, 42 Oxides Compound semiconductors, 43 Oxide semiconductors, 44 Openings, 45 Oxide semiconductors, 100 Memory device, 101 memory cell array, 102 row selection driver, 103 column selection Driver, 611 substrate, 612 circuit area, 613 isolation area, 614 isolation Wires, 615 Chips, 650 Electronic Components, 652 Printed Circuit Boards, 653 Semiconductors Body device, 654 substrate, 655 lead, 700 watch-type terminal, 701 housing , 702 Crown, 703 Display, 704 Belt, 705 Detection, 71 0 Mobile phone, 711 Housing, 712 Microphone, 713 External connection port, 7 14 Operation buttons, 716 Display, 717 Speaker, 720 Notebook PC Personal computer, 721, housing, 722, display, 723, keyboard, 72 4 Pointing device, 730 Goggle-type display, 731 Wearing part , 732 Housing, 735 Cable, 736 Battery, 737 Display, 74 0 Video camera, 741 Housing, 742 Housing, 743 Display, 744 Operation key, 745 lens, 746 connection part, 750 automobile, 751 body, 752 wheels, 753 dashboard, 754 lights, 1300 CPU, 1302 power controller, 1303 power switch, 1304 cache memory, 1305 bus interface, 1306 debug interface , 1307 control unit, 1308 program counter, 1309 pipeline Registers, 1310 Pipeline Registers, 1311 ALU, 1312 Registers Stafile, 1330 CPU core, 1331 PMU, 1332 peripheral circuit, 1333 Data bus, 1400 RFIC, 1404 Antenna, 1405 Rectifier circuit, 1406 constant voltage circuit, 1407 demodulation circuit, 1408 modulation circuit, 1 409 Logic circuit, 1410 RAM, 1411 ROM, 1412 Battery , 1420 communication device, 1421 antenna, 1422 radio signal< / rfic> < / cpu>

Claims

1. The first transistor and The second transistor, The third transistor, A first capacitive element and A second capacitive element, A first conductor and A second conductor and A third conductor and A fourth conductor, The first wiring and, The second wiring and The third wiring and The fourth wiring and It has a fifth wiring, The first conductor has the function of being either the source or the drain of the first transistor, and the function of being the first electrode of the first capacitive element. The second conductor functions as either the source or the drain of the first transistor, and is always electrically connected to the third wiring through a first opening provided on the second conductor. The fourth wiring functions as the first gate of the first transistor. The fifth wiring has the function of a second gate of the first transistor. The second electrode of the first capacitive element is always electrically connected to the first wiring. The first electrode of the second capacitive element is always in electrical contact with the first conductor through a second opening provided on the first conductor. The second electrode of the second capacitive element is always electrically connected to the first wiring. The third conductor functions as the gate of the second transistor and is always electrically connected to the first conductor through a third opening provided on the third conductor and the second opening. The fourth conductor functions as the gate of the third transistor. The fourth conductor is arranged in the same layer as the third conductor. Either the source or drain of the second transistor is always in electrical contact with either the source or drain of the third transistor. The source or drain of the second transistor is always in electrical contact with the third wiring. The source or drain of the third transistor, the other of which is always in electrical contact with the second wiring, The first transistor has an oxide semiconductor in the channel formation region, The second transistor has silicon in the channel formation region, The third transistor has silicon in the channel formation region, The fourth wiring is provided on the fifth wiring via the oxide semiconductor, In a top view, the second wiring has a region that intersects with the first wiring. In a top view, the fourth conductor has a region that overlaps with the first conductor. In a top view, the second electrode of the first capacitive element has a region that overlaps with the fourth conductor. In a top view, the first electrode of the second capacitive element has a region that overlaps with the first conductor. In a top view, the second electrode of the second capacitive element has a region that overlaps with the first conductor. In a top view, the first electrode of the second capacitive element has a region that overlaps with the third conductor. In a top view, the second electrode of the second capacitive element has a region that overlaps with the third conductor. In a top view, the first electrode of the second capacitive element has a region that overlaps with the fourth conductor. A semiconductor device in which, in a top view, the second electrode of the second capacitive element has a region that overlaps with the fourth conductor.

2. In claim 1, A semiconductor device wherein the channel formation region of the second transistor has a region in which carriers flow in a direction different from the channel length direction of the first transistor.

3. In claim 1 or 2, The second wiring has a region extending in the first direction, The third wiring has a region extending in the first direction, The first wiring has a region that extends in a direction different from the first direction, The fourth wiring has a region that extends in a direction different from the first direction, The semiconductor device has a fifth wiring having a region that extends in a direction different from the first direction.

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