Semiconductor device

Abstract

To provide a transistor in which a short channel effect does not substantially occur and switching characteristics can be obtained even when a channel length is small. A highly integrated semiconductor device including the transistor is provided.SOLUTION: The channel length is greater than or equal to 5nm and less than 60nm, and the channel length is greater than or equal to 5nm and less than 200nm. At this time, the channel width is greater than or equal to 0.5 times and less than or equal to 10 times the channel length.SELECTED DRAWING: Figure 1

Description

[Technical Field]

[0001] The present invention relates to a semiconductor device and a manufacturing method thereof.

[0002] In this specification, a semiconductor device is a device that can function by utilizing semiconductor characteristics. Generally speaking, electro-optical devices, semiconductor circuits, electronic devices, etc. are all semiconductor devices. [Background technology]

[0003] Silicon semiconductor devices are miniaturized according to the scaling rules of transistors and the like. This has led to increased integration, reduced power consumption, and improved performance.

[0004] However, in recent years, the limits of the scaling law have become a problem. By reducing the channel length, the so-called short channel effect such as punch-through phenomenon becomes apparent. came.

[0005] It is also known that a narrow channel effect occurs when the channel width is reduced.

[0006] Miniaturized transistors have threshold voltages that are affected by short channel effects and narrow channel effects. This makes it difficult to control the voltage, and the characteristics tend to vary. A design rule has been proposed that takes into account the variation in threshold voltage due to the narrow channel effect. (See Patent Document 1.)

[0007] In addition, in order to reduce the short channel effect that occurs when transistors are miniaturized, Various methods have been investigated (see Patent Document 2). [Prior art documents] [Patent documents]

[0008] [Patent Document 1] Japanese Patent Application Publication No. 4-134832 [Patent Document 2] Japanese Patent Application Laid-Open No. 2006-100842 Summary of the Invention [Problem to be solved by the invention]

[0009] However, conventional technology is a major factor in the deterioration of the electrical characteristics of transistors as they are miniaturized. The main aim is to reduce the influence of certain short channel effects, and No transistor without this has been proposed.

[0010] Therefore, one aspect of the present invention is to provide a semiconductor device that does not substantially cause a short channel effect even if the channel length is short. Another object of the present invention is to provide a transistor which has high switching characteristics.

[0011] Another object is to provide a highly integrated semiconductor device using the transistor. do. [Means for solving the problem]

[0012] A transistor including an oxide semiconductor film, the channel length of which is 5 nm or more and less than 60 nm, The channel width is set to 5 nm or more and less than 200 nm.

[0013] In this case, the channel width is set to be 0.5 to 10 times the channel length.

[0014] Note that the oxide semiconductor film preferably contains at least In.

[0015] Alternatively, the oxide semiconductor film preferably contains at least In, Ga, and Zn.

[0016] The inventors have found that the short channel effect occurring in a transistor using silicon is reduced by using an oxide semiconductor film. This is quite surprising. Therefore, this is completely different from the miniaturization of transistors according to conventional scaling rules. It can be said that the need has arisen to establish different rules for miniaturization.

[0017] The punch-through phenomenon, which is one of the short channel effects that occurs in silicon transistors, One of the reasons for this is the Drain Induced Barrier Lowering (DIBL) ing) is known.

[0018] In the following, we will discuss the bands that occur near the junctions between the oxide semiconductor film and the source and drain electrodes. Focusing on the bending width of the oxidized layer, we found that the DIBL seen in silicon transistors This indicates that this phenomenon is unlikely to occur in transistors using compound semiconductor films.

[0019] FIG. 21 shows the band structure between the source and drain of a transistor using n-type silicon. Figure 21(A) shows a schematic diagram of the band structure for a long channel, and Figure 21(B) shows a schematic diagram for a short channel. The band structure diagrams for each gate voltage (V g ) is zero The case where there is one (off state) will be explained.

[0020] From Figure 21, the drain voltage (V d Even when ) is zero, the band is bent near the pn junction interface. This is because n + The Fermi levels of the p-region and p-region are equal. As a result of the exchange of carriers, a depletion layer with donor ions and acceptor ions is formed. This is because an electric field is generated.

[0021] Here, V d When the drain side n + The band of the region is eV d As the The depletion layer spreads from the drain side (dashed line). In this case, in the case of a long channel, V d Is Thor On the other hand, in the case of a short channel, V d spreads from the drain side The depletion layer extends to the source side, causing a decrease in the potential of the p-region (the bank lowers). As a result, current flows more easily and the threshold voltage shifts in the negative direction.

[0022] Therefore, if the channel length of a transistor using n-type silicon is reduced, the The width of the depletion layer that spreads from the d It can be seen that it increases by The source of a transistor using silicon and a transistor using an oxide semiconductor film is The width of the band bending near the junction between the source and drain and the channel (pn junction interface) is Each is derived analytically.

[0023] Figure 22 shows the band structure on the source side of a transistor using n-type silicon. For reference, the band curve on the source side of the p region of a transistor using n-type silicon is Width L s Si L s Si is equal to the width of the depletion layer containing the acceptor ions. (y) is the potential at a distance y from the pn junction interface, and the origin is the intrinsic level E i pL Si eφ F Si is E ipL Siand the Fermi level E F Si The difference between this and eφ F Si =E ipL Si -E F Si Here, e is the elementary charge. The width reflects the spatial variation of φ(y). Equation (1) is the Poisson equation.

[0024]

number

[0025] ε Si is the dielectric constant, and ρ is the charge density. When focusing on the depletion layer in the p region, ρ is a negative charge. Only the acceptor ions need to be considered, resulting in equation (2).

[0026]

number

[0027] where N A Si is the acceptor density. Substituting equation (2) into equation (1), we obtain equation ( By solving under the boundary conditions shown in 3), equation (4) is obtained.

[0028]

number

[0029]

number

[0030] Here, from the boundary condition shown in equation (5), L s Si is calculated as shown in equation (6).

[0031]

number

[0032]

number

[0033] On the other hand, V d Band bending width L on the drain side when voltage is applied d Si L s Si Similar calculations as in the case of By calculation, we obtain formula (7).

[0034]

number

[0035] From equation (7), for a silicon transistor, V d By L d Si increases, That is, V d This shows that the depletion layer spreads from the drain side. This is DIBL in transistors.

[0036] Next, FIG. 23 shows a barrier between the source and drain of a transistor using an oxide semiconductor film. The oxide semiconductor structure of a transistor using an oxide semiconductor film is shown in FIG. The source-side band bending width L in the region s OS and the drain-side band bending width L d OS Calculate the work function φ of the metal used for the source and drain. m and electrons in oxide semiconductors affinity χ OS and is equal to (φ m =χ OS ) and the metal-oxide semiconductor is assumed to be ohmic. φ(y) is the distance y from the metal-oxide semiconductor junction interface on the source side. The origin is the intrinsic potential E iL OS eφ F OS is E iL OS and the Fermi level E on the source side F OS The difference between eφ F OS =E iL OS -E F OS In this case, the band bending width of the oxide semiconductor region is the majority carrier. The electron density n OS Since it is thought to arise from (y), the charge density ρ is expressed as equation (8).

[0037]

number

[0038] where k is the Boltzmann constant and T is the absolute temperature. OS is the bulk region of the oxide semiconductor. The electron density in the region is the intrinsic carrier density n i OS Using this, it is expressed as formula (9).

[0039]

number

[0040] Therefore, φ(y) can be determined from the Poisson equation shown in equation (10).

[0041]

number

[0042] When this is solved under the boundary conditions shown in equation (11), equation (12) is obtained.

[0043]

number

[0044]

number

[0045] Therefore, the boundary condition shown in formula (13) gives formula (14).

[0046]

number

[0047]

number

[0048] where E g OS / 2+eφ F OS >>Since it is 2kT, equation (14) becomes equation (15) It can be approximated as follows.

[0049]

number

[0050] On the other hand, V d L when applied d OS is eφ in Equation (13). F OS eφ F OS +eV d Place it In this case too, E g OS / 2+eφ F OS +eV d>>2kT, so the number This is expressed as equation (16).

[0051]

number

[0052] As a result, in the case of a transistor using an oxide semiconductor film, L d OS is V d does not depend on Therefore, it can be said that DIBL does not occur in a transistor including an oxide semiconductor film. can.

[0053] In addition, punch-through phenomenon that occurs in silicon transistors is caused by the electric field at the gate. This can also occur because the depletion layer does not extend deep enough into the channel region. The minority carrier density in silicon is 1×10 11 pieces / cm 3 This is because the degree is high. In other words, the accumulation of minority carriers makes the penetration of the electric field at the gate shallower, and the transistor is completely The transistor cannot be completely turned off, and the off-current increases.

[0054] Meanwhile, the inventors' extensive research has revealed that the density of minority carriers contained in an oxide semiconductor film is 1×10 -9 pieces / cm 3 It has been found that the oxide semiconductor In transistors using conductive films, accumulation of minority carriers hardly occurs, and the gate voltage The penetration of the field is deep, making it easy to completely turn off the transistor, which reduces the off-current. As shown in the figure, in a transistor using an oxide semiconductor film, the depletion layer expands due to the electric field at the gate. The impact will be extremely large.

[0055] As mentioned above, the short channel effect commonly known in silicon-based transistors is It can be said that there is substantially no transistor including an oxide semiconductor film.

[0056] Therefore, a transistor including an oxide semiconductor film can be switched even when the channel length is short. It can be said that it is easy to obtain matching characteristics.

[0057] In addition, when miniaturizing silicon transistors, the channel length is reduced and the channel size is also reduced. It was common for panel widths to also decrease.

[0058] However, in a transistor using an oxide semiconductor film, the channel length is reduced and the When the channel width is reduced, the threshold voltage may shift in the negative direction. This is also one of the things that the inventors have discovered through their intensive research.

[0059] Therefore, in order to obtain switching characteristics in a transistor including an oxide semiconductor film, When the channel length is small, it is important to make the channel width large enough. It is important to miniaturize the channel while maintaining a constant ratio of channel width to channel length. .

[0060] Here, it should be noted that the oxide semiconductor film generates electrons as carriers due to oxygen vacancies. It should be.

[0061] When electrons are generated in the oxide semiconductor film, the transistor is turned on even when the gate voltage is zero. Therefore, the oxide semiconductor film is likely to have a normally-on electrical characteristic. It is preferable to reduce the element deficiency.

[0062] For example, in order to reduce oxygen vacancies in the oxide semiconductor film, oxygen is supplied from the outside of the oxide semiconductor film. As a method for supplying oxygen from the outside, specifically, ion doping The oxidation treatment such as ping treatment, ion implantation treatment, or plasma treatment may be performed. An excess oxygen-containing layer may be provided to supply oxygen to the oxide semiconductor film.

[0063] Even if such a method is used, transistors using oxide semiconductor films cannot be miniaturized. By using oxygen from the outside, the proportion of oxygen vacancies generated in the oxide semiconductor film is higher than that of oxygen supplied from the outside. One of the reasons for this is that with miniaturization, the surface area of ​​the oxide semiconductor film relative to its volume has decreased. From this viewpoint, when the channel length is reduced, the area of ​​the channel increases. It can be said that it is important to increase the channel width.

[0064] However, if the channel width is made too large, it will be difficult to miniaturize the transistor. Therefore, the ratio of the channel length to the channel width is From this perspective, it is possible to make the channel length as small as possible without any constraints. This was not practical because the channel width could not be increased beyond a certain level. There is a possibility.

[0065] Therefore, it is important to effectively utilize oxygen supplied from the outside of the oxide semiconductor film. For example, by providing a layer with low oxygen permeability over a transistor including an oxide semiconductor film, This suppresses outward diffusion of elements, allowing oxygen to be used effectively. Even when the channel width is below a certain size, switching characteristics can be obtained. This can be done.

[0066] Furthermore, as transistors using oxide semiconductor films are miniaturized, the side surfaces of the oxide semiconductor films This issue has also been thoroughly investigated by the inventors. This is one of the things I have learned.

[0067] The effect of the parasitic channel can be significant in short-channel transistors, It is often mistaken for the short channel effect, but strictly speaking it is different.

[0068] The parasitic channel often has a lower threshold voltage than the transistor's native channel. Therefore, when the influence of the parasitic channel becomes large, it is as if the threshold voltage of the transistor This is because the side of the oxide semiconductor film is Therefore, the side surface of the oxide semiconductor film is easily formed with a large amount of oxygen compared to other surfaces. It is therefore important to provide more oxygen from the outside than from the inside.

[0069] For example, a structure in which a layer with low oxygen permeability is provided on the side surface of an oxide semiconductor film, and oxygen vacancies are less likely to occur. Furthermore, the excess oxygen-containing layer may be formed by stacking a layer with low oxygen permeability on an oxide semiconductor film. In this case, the excess oxygen-containing layer is provided in contact with the side surface of the oxide semiconductor film. It is preferable to do so.

[0070] In addition to oxygen vacancies, the oxide semiconductor film generates electrons as carriers by hydrogen. Therefore, it is preferable to reduce hydrogen in the oxide semiconductor film.

[0071] The minority carrier density is extremely low, and carrier generation sources such as oxygen vacancies and hydrogen are reduced. In addition, a transistor including an oxide semiconductor film can have an extremely small off-state current.

[0072] In addition, a transistor using an oxide semiconductor film has a high resistance to heat and is superior to conventional transistors using silicon or the like. For example, silicon-based transistors and compound Transistors using semiconductors have a higher on-state current than transistors using oxide semiconductor films. Therefore, for transistors that require good on-state characteristics, silicon is used. Low off-state current is required using transistors and transistors using compound semiconductors. A transistor including an oxide semiconductor film may be used as the transistor. The semiconductor film can be formed by a thin film forming method such as sputtering, so it is Another feature is that there are few restrictions when combining it with conductive materials.

[0073] In addition, transistors using silicon have good electrical conductivity when the silicon surface is hydrogen-terminated. Therefore, it can be used as a hydrogen source for silicon-based transistors. However, as mentioned above, when an oxide semiconductor film is used, it is preferable to provide a hydrogen-containing layer. For transistors, hydrogen is a carrier generation source and a factor that deteriorates electrical characteristics. be.

[0074] Therefore, a transistor using silicon and a transistor using an oxide semiconductor film are combined. When used together, the hydrogen-containing layer is provided on the silicon-based transistor side, and hydrogen permeability is improved. It is preferable that the layer with a low conductivity be provided on the transistor including an oxide semiconductor film side. [Effects of the Invention]

[0075] By using an oxide semiconductor film, the short channel effect is substantially eliminated even if the channel length is short. Therefore, a transistor can be provided that does not generate a problem and has a switching characteristic.

[0076] Furthermore, a highly integrated semiconductor device using the transistor can be provided. [Brief explanation of the drawings]

[0077] [Figure 1] 1A and 1B are a top view and a cross-sectional view illustrating an example of a semiconductor device according to one embodiment of the present invention. [Figure 2] 1A and 1B are a top view and a cross-sectional view illustrating an example of a semiconductor device according to one embodiment of the present invention. [Figure 3] 1A and 1B are a top view and a cross-sectional view illustrating an example of a semiconductor device according to one embodiment of the present invention. [Figure 4] 1A and 1B are a top view and a cross-sectional view illustrating an example of a semiconductor device according to one embodiment of the present invention. [Figure 5] 1A to 1C are cross-sectional views illustrating an example of a method for manufacturing a semiconductor device according to one embodiment of the present invention. [Figure 6] 1A to 1C are cross-sectional views illustrating an example of a method for manufacturing a semiconductor device according to one embodiment of the present invention. [Figure 7] 1A and 1B are a top view and a cross-sectional view illustrating an example of a semiconductor device according to one embodiment of the present invention. [Figure 8] 1A to 1C are cross-sectional views illustrating an example of a method for manufacturing a semiconductor device according to one embodiment of the present invention. [Figure 9] 1A and 1B are a top view and a cross-sectional view illustrating an example of a semiconductor device according to one embodiment of the present invention. [Figure 10] 1A to 1C are cross-sectional views illustrating an example of a method for manufacturing a semiconductor device according to one embodiment of the present invention. [Figure 11] 1A to 1C are cross-sectional views illustrating an example of a method for manufacturing a semiconductor device according to one embodiment of the present invention. [Figure 12] 1A to 1C are cross-sectional views illustrating an example of a method for manufacturing a semiconductor device according to one embodiment of the present invention. [Figure 13] 1A and 1B are a top view and a cross-sectional view illustrating an example of a semiconductor device according to one embodiment of the present invention. [Figure 14] 1A to 1C are cross-sectional views illustrating an example of a method for manufacturing a semiconductor device according to one embodiment of the present invention. [Figure 15]1A and 1B are a top view and a cross-sectional view illustrating an example of a semiconductor device according to one embodiment of the present invention. [Figure 16] 1A to 1C are cross-sectional views illustrating an example of a method for manufacturing a semiconductor device according to one embodiment of the present invention. [Figure 17] 1A to 1C are a circuit diagram, a diagram showing electrical characteristics, and a cross-sectional view illustrating an example of a semiconductor memory device according to one embodiment of the present invention. [Figure 18] 1A to 1C are a circuit diagram, a diagram showing electrical characteristics, and a cross-sectional view illustrating an example of a semiconductor memory device according to one embodiment of the present invention. [Figure 19] 1A and 1B are a block diagram and a circuit diagram of a portion thereof showing a specific example of a CPU according to one embodiment of the present invention; [Figure 20] FIG. 10 is a perspective view illustrating an example of an electronic device according to one embodiment of the present invention. [Figure 21] Band diagram between the source and drain of a transistor using n-type silicon. [Figure 22] Band diagram of the source side of a transistor using n-type silicon. [Figure 23] FIG. 10 is a band diagram between a source and a drain of a transistor including an oxide semiconductor film. DETAILED DESCRIPTION OF THE INVENTION

[0078] The embodiments of the present invention will be described in detail with reference to the drawings. The present invention is not limited to the above, and various modifications in form and details can be easily made by those skilled in the art. It is understood that the present invention should not be construed as being limited to the description of the following embodiments. In explaining the configuration of the invention using the drawings, the same symbols are used in different The hatch pattern is used in common between drawings. However, there are cases where no particular symbol is attached.

[0079] The present invention will be explained below, but the terms used in this specification will be briefly explained. In this specification, one of the source and drain of a transistor is referred to as the drain. In other words, they are not distinguished by the level of potential. In the specification, the part referred to as a source can also be read as a drain.

[0080] Also, voltage is a voltage between a certain potential and a reference potential (for example, ground potential (GND) or source potential). Therefore, voltage can be replaced with potential. .

[0081] In this specification, even when the expression "electrically connect" is used, it does not mean that the actual circuit In some cases, there may be no physical connection and only wires running.

[0082] The ordinal numbers such as 1st and 2nd are used for convenience and do not indicate the order of the processes or the order of stacking. Furthermore, in this specification, the specific name is not used as a matter for identifying the invention. It does not indicate a title.

[0083] The channel length refers to the distance between the source and drain of a transistor. The shorter the length, the smaller the on-resistance, making it possible for the transistor to operate at high speed. The channel width is the length between the source and drain of a transistor. The smaller the gate insulating film, the smaller the on-resistance, and the higher the speed of the transistor.

[0084] (Embodiment 1) In this embodiment, a transistor according to one embodiment of the present invention will be described.

[0085] 1A is a top view of a transistor according to one embodiment of the present invention. A cross-sectional view corresponding to the dashed line A1-A2 is shown in FIG. 1(B). A cross-sectional view corresponding to A3-A4 is shown in FIG. 1(C). In A), the underlying insulating film 102 and the like are omitted.

[0086] FIG. 1A shows the channel length (L) and channel width (W) of a transistor. The channel region of the transistor overlaps with the gate electrode 104 in the oxide semiconductor film 106. At least part of the two side surfaces of the oxide semiconductor film 106 is a region where the gate electrode Overlaps with 104.

[0087] The transistor shown in FIG. 1A has a channel length of 5 nm or more and less than 60 nm. The width is 5 nm or more and less than 200 nm.

[0088] In addition, the transistor shown in FIG. 1A has a channel width of 0.5 or more times the channel length. The upper limit is 10 times less.

[0089] FIG. 1B shows a base insulating film 102 provided on the substrate 100 and a film 103 provided on the base insulating film 102. The oxide semiconductor film 106 is covered with a gate insulating film 108. 12, a gate insulating film 112 that is provided over the oxide semiconductor film 106 and overlaps with the oxide semiconductor film 106, 1 shows a cross-sectional structure of a transistor having a gate electrode 104.

[0090] 1B shows the oxide semiconductor film 106 and the oxide semiconductor film 108 formed over the gate electrode 104. an interlayer insulating film 118 having an opening reaching the compound semiconductor film 106; 10A and 10B, a wiring 136 provided in contact with the oxide semiconductor film 106 with a portion interposed therebetween.

[0091] The oxide semiconductor film 106 may be made of, for example, an In-M-Zn-O-based material. Here, the metal element M is an element whose bond energy with oxygen is higher than that of In and Zn. Or, it is an element that has the function of suppressing the desorption of oxygen from In-M-Zn-O based materials. The metal element M acts to suppress the generation of oxygen vacancies in the oxide semiconductor film to some extent. Therefore, it is possible to reduce the fluctuation in the electrical characteristics of the transistor caused by oxygen vacancies. As a result, a highly reliable transistor can be obtained.

[0092] The metal element M is specifically Al, Sc, Ti, V, Cr, Mn, Fe, Co, Ni, Ga , Y, Zr, Nb, Mo, Sn, La, Ce, Pr, Nd, Sm, Eu, Gd, Tb, D Y, Ho, Er, Tm, Yb, Lu, Hf, Ta or W, and preferably Al , Ti, Ga, Y, Zr, Ce or Hf. The metal element M is one or more of the above elements. Alternatively, Si or Ge may be used in place of the metal element M. No.

[0093] However, the oxide semiconductor film 106 cannot be formed by the action of the metal element M alone. Therefore, the formation of oxygen vacancies in the base insulating film 102 and the It is important to supply oxygen from at least one of the gate insulating film 111 and the gate insulating film 112.

[0094] The hydrogen concentration in the oxide semiconductor film 106 is set to 2×10 20 atoms / cm 3 Below is good Preferably 5 x 10 19 atoms / cm 3 or less, more preferably 1 × 10 19 atom s / cm 3This is because hydrogen contained in the oxide semiconductor film 106 is an unintended carrier. The generated carriers can affect the electrical properties of the transistor. This is a factor that causes fluctuations.

[0095] The oxide semiconductor film 106 may be single-crystalline, polycrystalline (also referred to as polycrystalline), or amorphous. Which state to take?

[0096] The oxide semiconductor film 106 is preferably a CAAC-OS (C Axis Aligned Oxide Semiconductor) film. Crystalline Oxide Semiconductor) film.

[0097] The CAAC-OS film is neither completely single crystalline nor completely amorphous. The oxide semiconductor film has a crystalline-amorphous mixed phase structure in which a crystalline portion is included in an amorphous phase. The crystal portion is often sized to fit within a cube with one side less than 100 nm. Transmission Electron Microscope (TEM) In the observation image using a microscope, the boundary between the amorphous and crystalline parts in the CAAC-OS film was The grain boundaries in the CAAC-OS film were not clearly observed by TEM. Therefore, the CAAC-OS film is not affected by the carriers originating from the grain boundaries. The decrease in carrier mobility is suppressed.

[0098] The crystal parts included in the CAAC-OS film have their c-axes aligned on the surface on which the CAAC-OS film is formed or on the top surface. Atomic arrangement aligned perpendicularly and triangular or hexagonal when viewed perpendicular to the ab plane When viewed from the direction perpendicular to the c-axis, the metal atoms are layered or the metal atoms and oxygen atoms are layered. The orientation of the a-axis and b-axis differs between different crystal parts. In this specification, when simply referring to vertical, it also includes the range of 85° to 95°. It will be included.

[0099] In the CAAC-OS film, the distribution of the crystal parts may not be uniform. In the process of forming the C-OS film, when crystal growth is performed from the top surface side of the oxide semiconductor film 106, The proportion of crystalline portions may be higher on the upper surface side than on the surface on which the CAA is formed. By adding impurities to the C-OS film, the crystalline part in the impurity-doped region becomes amorphous. It can also become

[0100] The c-axis of the crystalline part in the CAAC-OS film is the normal vector of the surface on which the CAAC-OS film is formed. The CAAC-OS film shape (on the surface where the film is formed) is Depending on the cross-sectional shape of the front surface or the cross-sectional shape of the top surface, the directions may be different from each other. The direction of the c-axis of the crystal is the normal vector of the surface on which the CAAC-OS film is formed. The direction of the crystal is parallel to the normal vector of the top surface or the film. is formed by carrying out a crystallization treatment such as a heat treatment after the film formation.

[0101] The electrical characteristics of a transistor using a CAAC-OS film change when irradiated with visible or ultraviolet light. Therefore, the transistor has high reliability.

[0102] The oxide semiconductor film 106 includes a region 106a and a region 106b. The region 106a functions as a channel region, and the region 106b functions as a source region and a drain region. Therefore, the region 106b may be called a conductor rather than a semiconductor. For convenience, even when the oxide semiconductor film 106 is referred to, the region 106 is omitted. Sometimes it refers only to a.

[0103] The region 106b has a lower resistance than the region 106a. This is a region containing impurities that act to reduce the resistance of the conductive film. Impurities that have a detrimental effect include, for example, helium, boron, nitrogen, fluorine, neon, and aluminum. Mu, Phosphorus, Argon, Arsenic, Krypton, Indium, Tin, Antimony and Xenon Examples include:

[0104] The region 106a in the oxide semiconductor film 106 has a band gap of 2.8 eV to 3.2 e V, and the minority carrier density is 10 -9 pieces / cm 3 Very few, many careers The only power comes from the source of the transistor.

[0105] The oxide semiconductor film 106 has a band gap that is larger than that of silicon by about 1 to 2 eV. Therefore, the transistor including the oxide semiconductor film 106 is less likely to undergo impact ionization. Avalanche breakdown is unlikely to occur. It can be said that deterioration is less likely to occur.

[0106] Furthermore, the region 106a has a low impurity concentration and a small oxygen deficiency. When the oxide semiconductor film 106 is thick (for example, 15 nm or more and less than 100 nm), ) the region 106a can be completely depleted by the electric field of the gate electrode 104. Therefore, the transistor does not experience a negative shift in threshold voltage due to the punch-through phenomenon. For example, when the channel length is 3 μm, the off-state current per 1 μm of the channel width is The flow rate was 10 -21 Less than A or 10 -24 It can be less than A.

[0107] The oxide semiconductor film with few oxygen vacancies exhibits electron spin resonance (ESR) In Resonance), oxide semiconductors that do not have signals due to oxygen vacancies Specifically, the spin density due to oxygen vacancies is 5×10 16 spins / c m 3 When the oxide semiconductor film has oxygen vacancies, the ESR A signal with symmetry appears at a g value of around 1.93.

[0108] It is preferable that the base insulating film 102 has sufficient flatness. Specifically, the average surface roughness (R a) is 1 nm or less, preferably 0.3 nm or less, and more preferably 0.1 nm or less By setting Ra to the above value or less, the oxide semiconductor film 106 with high crystallinity can be provided. In addition, the roughness of the interface between the base insulating film 102 and the oxide semiconductor film 106 can be reduced. By doing so, the influence of interface scattering can be reduced. The arithmetic mean roughness defined in ISO 4287:1997 is applied to curved surfaces. It is a three-dimensional extension of the method, which calculates the average absolute value of the deviation from the reference surface to the specified surface. This can be expressed as the "value obtained by dividing the

[0109]

number

[0110] Here, the specified surface is the surface to be measured for roughness, and has coordinates (x1, y1, f(x1, y 1)),(x1,y2,f(x1,y2)),(x2,y1,f(x2,y1)),(x 2, y2, f(x2, y2)) and the specified surface is the xy plane. The area of ​​the projected rectangle is S0, and the height of the reference plane (average height of the specified plane) is Z0. was evaluated using an atomic force microscope (AFM). It is possible to price it.

[0111] The base insulating film 102 is preferably an insulating film containing excess oxygen.

[0112] An insulating film containing excess oxygen is a material that has a high TDS (Thermal Desorption Spectroscopy) The oxygen released in the thermal desorption spectroscopy (TDS) analysis is converted to oxygen atoms. 1×10 18 atoms / cm 3 That's it, 1 x 10 19 atoms / cm 3 or more or 1× 10 20 atoms / cm 3 The insulating film is defined as above.

[0113] Here, a method for measuring the amount of released oxygen using TDS analysis will be described below.

[0114] The total amount of released gas during TDS analysis is proportional to the integral value of the ion intensity of the released gas. The total amount of released gas can then be calculated by comparing this integral value with that of a standard sample.

[0115] For example, the TDS analysis results of a silicon wafer containing a specified density of hydrogen as a standard sample, and From the results of TDS analysis of the insulating film, the amount of oxygen molecules released from the insulating film (NO2 ) is expressed by Equation (18) Here, the total mass of the gas detected at mass number 32 obtained by TDS analysis can be calculated as follows: We assume that the mass number of the molecule is 32. There is another molecule with mass number 32, CH3OH, but it does not exist. It is unlikely that this will occur, so it will not be considered here. The oxygen molecule containing the oxygen atom with mass number 17 and the oxygen atom with mass number 18 also exists in nature. Not considered because its abundance is extremely small.

[0116]

number

[0117] N H2 is the density converted value of hydrogen molecules desorbed from the standard sample. H2 is a standard test The integral value of the ion intensity when the sample is subjected to TDS analysis. H2 / S H2 Let's say S O2 is the integral value of the ion intensity when the insulating film is analyzed by TDS. α is a coefficient that affects the ion intensity in TDS analysis. For details, see Japanese Patent Application Laid-Open No. 6-275697. The standard sample was measured using a thermal desorption analyzer EMD-WA1000S / W manufactured by Electronic Science Corporation. as 1×10 16 atoms / cm 2 The measurement was carried out using a silicon wafer containing hydrogen atoms. Ta.

[0118] In addition, some of the oxygen is detected as oxygen atoms in TDS analysis. The ratio of the oxygen molecules can be calculated from the ionization rate of the oxygen molecules. Since the ionization rate of oxygen atoms is included in the calculation, the amount of oxygen atoms released can be estimated by evaluating the amount of oxygen molecules released. It can also be estimated.

[0119] In addition, N O2 is the amount of released oxygen molecules. The amount of released oxygen atoms is This is twice the amount released.

[0120] Alternatively, the insulating film containing excess oxygen may be an insulating film containing peroxide radicals. The spin density due to the peroxide radical is 5×10 17 spins / cm 3 The above It is an insulating film. Note that insulating films containing peroxide radicals have an ESR g value of around 2.01. It is an insulating film having an asymmetric signal.

[0121] Alternatively, the insulating film containing excess oxygen may be formed by converting silicon oxide (SiO X (X>2) Silicon oxide (SiO X (X>2)) is the number of silicon atoms It contains more than twice as many oxygen atoms per unit volume as silicon atoms per unit volume. The number of electrons and the number of oxygen atoms are values ​​measured by Rutherford backscattering spectroscopy.

[0122] The base insulating film 102 is made of aluminum oxide, aluminum nitride, magnesium oxide, silicon oxide, or the like. Silicon, silicon oxide nitride, germanium oxide, yttrium oxide, zirconium oxide, One or more materials including lanthanum oxide, neodymium oxide, hafnium oxide, and tantalum oxide In addition to the above-mentioned single layer or laminated layer, , silicon nitride oxide, and silicon nitride may be stacked.

[0123] Silicon oxynitride is a material whose composition contains more oxygen than nitrogen. Silicon nitride oxide refers to a material whose composition contains more nitrogen than oxygen. .

[0124] The gate insulating film 112 is preferably an insulating film containing excess oxygen.

[0125] The gate insulating film 112 is made of aluminum oxide, magnesium oxide, silicon oxide, silicon oxynitride, or the like. Silicon, silicon oxide nitride, silicon nitride, germanium oxide, yttrium oxide, oxide Contains zirconium oxide, lanthanum oxide, neodymium oxide, hafnium oxide and tantalum oxide One or more materials may be selected and used in a single layer or in a laminated form.

[0126] The excess oxygen contained in at least one of the base insulating film 102 and the gate insulating film 112 The excess oxygen is oxygen contained in excess of the stoichiometric composition of the material. When energy is applied, excess oxygen is released. Since it is contained in the membrane, even if it is lost by release, it will not deteriorate the membrane quality. do not have.

[0127] For example, oxygen vacancies in the oxide semiconductor film 106 are filled by the insulating base film 102 and the gate insulating film 11. The oxide semiconductor film 2 can be used to reduce the amount of oxygen supplied. The reduction of oxygen vacancies in 106 shifts the threshold voltage of the transistor in the negative direction. To achieve this, it is possible to suppress the formation of at least some of the insulating film undercoat and the gate insulating film. An insulating film containing excess oxygen may be used for either of them.

[0128] The oxide semiconductor film 106 is sandwiched between the base insulating film 102 and the gate insulating film 112 and heated. By this treatment, oxygen released from the base insulating film 102 is efficiently transferred to the oxide semiconductor film 1 06. The heat treatment can be performed at a temperature of 250°C or higher and 550°C or lower. When the oxide semiconductor film 106 is heated, oxygen is supplied to the oxide semiconductor film 106 and the The hydrogen concentrations in the base insulating film 102 and the gate insulating film 112 can be reduced.

[0129] However, the heat treatment may cause damage to either the base insulating film 102 or the gate insulating film 112. The excess oxygen contained in the film may be lost. From the viewpoint of the above, either the base insulating film 102 or the gate insulating film 112 remains unchanged even after the heat treatment. Preferably, contains excess oxygen.

[0130] There are no particular limitations on the substrate 100, but it should at least have heat resistance to the extent that it can withstand subsequent heat treatment. For example, glass substrate, ceramic substrate, quartz substrate, sapphire substrate Alternatively, a single crystal semiconductor such as silicon or silicon carbide may be used as the substrate 100. Conductor substrates, polycrystalline semiconductor substrates, compound semiconductor substrates such as silicon germanium, SOI ( It is also possible to apply a silicon-on-insulator (SIO) substrate. Any of these substrates on which semiconductor elements are provided may be used as the substrate 100.

[0131] The substrate 100 is a fifth generation (1000mm x 1200mm or 1300mm x 1500mm), 6th generation (1500mm x 1800mm), 7th generation (1870mm x 2200mm), 8th generation (2200mm x 2500mm), 9th generation (2400mm x Using large glass substrates such as 10th generation (2800mm x 3130mm) and 11th generation (2880mm x 3130mm) In this case, shrinkage of the substrate 100 due to heat treatment or the like in the manufacturing process of the semiconductor device may occur. Therefore, it is sometimes difficult to perform fine processing on a large glass substrate as described above. When using 100, it is preferable to use one that shrinks little when heated. For example, the substrate 100 is heated to 400°C, preferably 450°C, and more preferably 500°C. The shrinkage amount after heat treatment at temperature for 1 hour is 10 ppm or less, preferably 5 ppm or less, More preferably, a large glass substrate with a density of 3 ppm or less may be used.

[0132] A flexible substrate may also be used as the substrate 100. The method of providing a transistor is to fabricate a transistor on a non-flexible substrate and then Alternatively, the resistor may be peeled off and transferred to the flexible substrate 100. A release layer may be provided between the non-flexible substrate and the transistor.

[0133] The gate electrode 104 is made of Al, Ti, Cr, Co, Ni, Cu, Y, Zr, Mo, Ag, T A single layer or multilayer of a and W, which contains one or more of the element, nitride, oxide or alloy. Just use it.

[0134] The interlayer insulating film 118 is made of aluminum oxide, aluminum nitride, magnesium oxide, silicon oxide, or the like. Silicon, silicon oxynitride, silicon nitride oxide, silicon nitride, germanium oxide, oxide Yttrium oxide, zirconium oxide, lanthanum oxide, neodymium oxide, hafnium oxide and One or more materials containing tantalum oxide may be selected and used in a single layer or a multilayer.

[0135] It is preferable that the interlayer insulating film 118 has a low relative dielectric constant and a sufficient thickness. For example, a silicon oxide film with a relative dielectric constant of about 3.8 is used, and the thickness is 200 nm to 1000 nm. The upper surface of the interlayer insulating film 118 is slightly fixed due to the influence of atmospheric components, etc. The charge can cause the threshold voltage of the transistor to fluctuate. Therefore, the interlayer insulating film 118 is formed in a ratio range that sufficiently reduces the influence of charges generated on the upper surface. For the same reason, it is preferable to form a polyimide film on the interlayer insulating film 118. By forming a resin film such as polyethylene resin, acrylic resin, epoxy resin, or silicone resin, The influence of charges generated on the upper surface of the interlayer insulating film 118 may be reduced.

[0136] Wiring 136 includes Al, Ti, Cr, Co, Ni, Cu, Y, Zr, Mo, Ag, Ta and and W, and the element, nitride, oxide or alloy containing one or more of them is used in a single layer or a laminated layer. That's fine.

[0137] In addition, transistors with structures different from those shown in Figure 1 will be described using Figure 2. explain.

[0138] 2A is a top view of a transistor according to one embodiment of the present invention. A cross-sectional view corresponding to the chain line B1-B2 is shown in FIG. 2(B). A cross-sectional view corresponding to B3-B4 is shown in FIG. 2(C). In A), the underlying insulating film 102 and the like are omitted.

[0139] FIG. 2(A) shows the channel length (L) and channel width (W) of the transistor. The channel region of the transistor overlaps with the gate electrode 104 in the oxide semiconductor film 106. At least part of the two side surfaces of the oxide semiconductor film 106 is a region where the gate electrode Overlaps with 104.

[0140] The transistor shown in FIG. 2A has a channel length of 5 nm or more and less than 60 nm. The width is 5 nm or more and less than 200 nm.

[0141] In addition, the transistor shown in FIG. 2A has a channel width of 0.5 times or more relative to the channel length. The upper limit is 10 times less.

[0142] FIG. 2B shows a base insulating film 102 provided on the substrate 100 and a film 103 provided on the base insulating film 102. The oxide semiconductor film 106 is covered with a gate insulating film 108. 12, a gate insulating film 112 that is provided over the oxide semiconductor film 106 and overlaps with the oxide semiconductor film 106, the gate electrode 104, and the insulating base film 102, the oxide semiconductor film 106, and the gate electrode 104. a barrier film 108 having an opening reaching the oxide semiconductor film 106, 1 is a cross-sectional view of a transistor.

[0143] 2B shows the oxide semiconductor film 106 and the oxide semiconductor film 108 formed over the gate electrode 104. an interlayer insulating film 118 having an opening reaching the compound semiconductor film 106; 10A and 10B, a wiring 136 provided in contact with the oxide semiconductor film 106 with a portion interposed therebetween.

[0144] The transistor shown in FIG. 2 includes a base insulating film 102, an oxide semiconductor film 106, and a gate electrode. A barrier film 108 having an opening reaching the oxide semiconductor film 106 is formed on the oxide semiconductor film 104. The only difference from the transistor shown in FIG. Reference may be made to the description of FIG.

[0145] The barrier film 108 is an insulating film with low oxygen permeability. Specifically, it is heated at 350° C. for 1 hour. It is an insulating film that has the property of being oxygen impermeable when subjected to heat treatment.

[0146] The barrier film 108 is made of aluminum oxide, aluminum nitride, magnesium oxide, or oxide gel. Al, yttrium oxide, zirconium oxide, lanthanum oxide, neodymium oxide, halide oxide One or more materials containing fluorine and tantalum oxide are selected and used in a single layer or laminated layer. Preferably, an aluminum oxide film is used.

[0147] The transistor shown in FIG. 2 includes a base insulating film 102, an oxide semiconductor film 106, and a gate electrode. A barrier film 108 having an opening reaching the oxide semiconductor film 106 is formed on the oxide semiconductor film 104. Therefore, excess oxygen contained in either the base insulating film 102 or the gate insulating film 112 Therefore, the outward diffusion of the insulating film 102 and the gate insulating film 11 can be suppressed. 2 can be efficiently supplied to the oxide semiconductor film 106. That is, the threshold voltage of the transistor can be further decreased in the negative direction than that of the transistor shown in FIG. This can suppress the shift in the direction of

[0148] In addition, transistors having structures different from those shown in FIGS. 1 and 2 are shown in FIG. 3 will be used to explain.

[0149] 3A is a top view of a transistor according to one embodiment of the present invention. A cross-sectional view corresponding to the chain line C1-C2 is shown in FIG. A cross-sectional view corresponding to C3-C4 is shown in FIG. 3(C). In A), the underlying insulating film 102 and the like are omitted.

[0150] FIG. 3A shows the channel length (L) and channel width (W) of the transistor. The channel region of the transistor overlaps with the gate electrode 104 in the oxide semiconductor film 106. At least part of the two side surfaces of the oxide semiconductor film 106 is a region where the gate electrode Overlaps with 104.

[0151] The transistor shown in FIG. 3A has a channel length of 5 nm or more and less than 60 nm. The width is 5 nm or more and less than 200 nm.

[0152] In addition, the transistor shown in FIG. 3A has a channel width of 0.5 times or more relative to the channel length. The upper limit is 10 times less.

[0153] FIG. 3B shows a base insulating film 102 provided on the substrate 100 and a film 103 provided on the base insulating film 102. The oxide semiconductor film 106 is covered with the first layer 132. a gate insulating film 132 including a first layer 132a and a second layer 132b; and a gate insulating film 132 on the gate insulating film 132, a transistor having a gate electrode 104 overlapping with an oxide semiconductor film 106; The first layer 132a is thicker than the second layer 132b. It is located on the 106 side.

[0154] 3B shows the oxide semiconductor film 106 and the oxide semiconductor film 108 formed over the gate electrode 104. an interlayer insulating film 118 having an opening reaching the compound semiconductor film 106; 10A and 10B, a wiring 136 provided in contact with the oxide semiconductor film 106 with a portion interposed therebetween.

[0155] The transistor shown in FIG. 3 has a first layer 132a and a second layer 132b instead of the gate insulating film 112. 1 only in that it has a gate insulating film 132 including a layer 132b. Therefore, for other configurations, the description of FIG. 1 can be referred to.

[0156] Here, the first layer 132a is an insulating film containing excess oxygen.

[0157] The first layer 132a is made of aluminum oxide, aluminum nitride, magnesium oxide, silicon oxide, or the like. Silicon, silicon oxynitride, silicon nitride oxide, silicon nitride, germanium oxide, oxide Yttrium oxide, zirconium oxide, lanthanum oxide, neodymium oxide, hafnium oxide and One or more materials containing tantalum oxide may be selected and used in a single layer or a multilayer.

[0158] The second layer 132b is an insulating film with low oxygen permeability. It is an insulating film that has the property of being oxygen impermeable when subjected to heat treatment for a long period of time.

[0159] The second layer 132b is made of aluminum oxide, aluminum nitride, magnesium oxide, or gallium oxide. Rumanium oxide, yttrium oxide, zirconium oxide, lanthanum oxide, neodymium oxide, oxide One or more materials including hafnium and tantalum oxide are selected and used in a single layer or a laminated layer. Preferably, an aluminum oxide film is used.

[0160] As shown in FIG. 3C, the oxide semiconductor film 10 The first layer 132a is provided in contact with the side surface of the gate electrode 104. In the region, oxygen is supplied from the first layer 132a to the side surface of the oxide semiconductor film 106. In addition, the second layer 132b may be provided so as to cover the first layer 132a. Therefore, oxygen can be efficiently supplied from the first layer 132a.

[0161] A parasitic channel is formed on the side surface of the oxide semiconductor film due to the properties of the side surface of the oxide semiconductor film. The parasitic channel is formed at a lower threshold voltage than the natural channel of the transistor. Therefore, if the influence of the parasitic channel becomes large, it is as if the This appears to be due to the negative shift of the threshold voltage of the oxide semiconductor film. This is because carriers are easily generated on the side surface of the oxide semiconductor film. It is important to provide more oxygen from the outside than to other surfaces.

[0162] The effect of the parasitic channel can be significant in short-channel transistors, For miniaturized transistors, it is effective to adopt the structure shown in Figure 3. do.

[0163] The transistor shown in FIG. 3 has an oxide semiconductor film 1 A parasitic channel is less likely to form on the side of the transistor 06. Furthermore, the negative shift of the threshold voltage of the transistor can be suppressed.

[0164] 4 for transistors having structures different from those shown in FIGS. 1 to 3. This will be explained using:

[0165] 4A is a top view of a transistor according to one embodiment of the present invention. A cross-sectional view corresponding to the chain line D1-D2 is shown in FIG. A cross-sectional view corresponding to D3-D4 is shown in FIG. 4(C). In A), the underlying insulating film 102 and the like are omitted.

[0166] FIG. 4A shows the channel length (L) and channel width (W) of the transistor. The channel region of the transistor overlaps with the gate electrode 104 in the oxide semiconductor film 106. At least part of the two side surfaces of the oxide semiconductor film 106 is a region where the gate electrode Overlaps with 104.

[0167] The transistor shown in FIG. 4A has a channel length of 5 nm or more and less than 60 nm. The width is 5 nm or more and less than 200 nm.

[0168] In addition, the transistor shown in FIG. 4A has a channel width of 0.5 times or more relative to the channel length. The upper limit is 10 times less.

[0169] FIG. 4B shows a base insulating film 102 provided on the substrate 100 and a film 103 provided on the base insulating film 102. The oxide semiconductor film 106 is covered with the first layer 132. a gate insulating film 132 including a first layer 132a and a second layer 132b; and a gate insulating film 132 on the gate insulating film 132, The gate electrode 104 overlapping with the oxide semiconductor film 106, the base insulating film 102, and the oxide semiconductor film 106 are The oxide semiconductor film 106 is formed on the oxide semiconductor film 106 and the gate electrode 104. 1 shows a cross-sectional structure of a transistor having a barrier film 108 having an opening for the transistor. The first layer 132a is provided closer to the oxide semiconductor film 106 than the second layer 132b.

[0170] 4B shows the oxide semiconductor film 106 and the oxide semiconductor film 108 formed over the gate electrode 104. an interlayer insulating film 118 having an opening reaching the compound semiconductor film 106; 10A and 10B, a wiring 136 provided in contact with the oxide semiconductor film 106 with a portion interposed therebetween.

[0171] The transistor shown in FIG. 4 includes a base insulating film 102, an oxide semiconductor film 106, and a gate electrode. A barrier film 108 having an opening reaching the oxide semiconductor film 106 is formed on the oxide semiconductor film 104. 4 is similar to the transistor shown in FIG. 2 in that it has a gate Instead of the gate insulating film 112, a gate insulating film including a first layer 132a and a second layer 132b is used. 3 in that it has a film 132. Therefore, the transistor shown in FIG. For the configuration of the register, please refer to the explanations of FIGS.

[0172] The transistor shown in FIG. 4 includes a base insulating film 102, an oxide semiconductor film 106, and a gate electrode. A barrier film 108 having an opening reaching the oxide semiconductor film 106 is formed on the oxide semiconductor film 104. Therefore, the excess oxygen contained in either the base insulating film 102 or the first layer 132a is Therefore, the outward diffusion of the insulating base film 102 and the first layer 132a can be suppressed. Excess oxygen contained in either of them can be efficiently supplied to the oxide semiconductor film 106. That is, the negative shift of the threshold voltage of the transistor can be suppressed.

[0173] As shown in FIG. 4C, the oxide semiconductor The first layer 132a is provided in contact with the side surface of the film 106. In the overlapping region, oxygen is supplied from the first layer 132a to the side surface of the oxide semiconductor film 106. In addition, a second layer 132b is provided to cover the first layer 132a. This allows oxygen to be efficiently supplied from the first layer 132a.

[0174] Therefore, in the transistor shown in FIG. 4, the oxide film is formed in the region overlapping with the gate electrode 104. A parasitic channel is unlikely to be formed on the side surface of the semiconductor film 106. That is, the threshold voltage of the transistor The voltage shift in the negative direction can be suppressed.

[0175] As shown above, even when the channel length is small (5 nm or more and less than 60 nm), the As a transistor in which the channel effect does not occur, a transistor with a large channel width (5 nm or more, 200 nm or less) A transistor using an oxide semiconductor film (less than m) is proposed.

[0176] In addition, a transistor using an oxide semiconductor film with a constant ratio of the channel width to the channel length was developed. I suggest Transista.

[0177] In addition, the threshold voltage shifts in the negative direction due to oxygen vacancies in the oxide semiconductor film 106, and parasitic We propose a transistor in which the negative shift of the threshold voltage due to the channel is suppressed.

[0178] As a result, it is possible to provide a transistor that can obtain switching characteristics even when miniaturized. Cut.

[0179] A method for manufacturing the transistor shown in FIG. 4 will be described below with reference to FIGS. 5 and 6. Regarding the manufacturing method of the transistors shown in FIGS. 1 to 3, the manufacturing method of the transistor shown in FIGS. For ease of explanation, a cross-sectional view corresponding to FIG. Only shown.

[0180] First, a substrate 100 is prepared.

[0181] Next, a base insulating film 102 is formed on the substrate 100 (see FIG. 5(A)). 02 is selected from the materials shown as the base insulating film 102 and is formed by sputtering or chemical vapor deposition. Chemical Vapor Deposition (CVD), molecular beam epitaxy MBE (Molecular Beam Epitaxy) method, atomic layer deposition (A LD (Atomic Layer Deposition) method or pulsed laser deposition ( The film can be formed using the PLD (Pulsed Laser Deposition) method. .

[0182] At this stage, the base insulating film 102 may be subjected to dehydration and dehydrogenation treatment. The treatment can be carried out, for example, by heat treatment. The temperature of the heat treatment is 250°C or higher. The heat treatment may be carried out at 50°C or less, preferably 300°C or more and 500°C or less. Inert gas atmosphere, atmosphere containing oxidizing gas at 10 ppm or more, 1% or more, or 10% or more The heat treatment is carried out in an inert gas atmosphere or under reduced pressure. After that, to compensate for the oxygen that has been released, oxidizing gas is added at 10 ppm or more, 1% or more, or Alternatively, the heat treatment may be carried out in an atmosphere containing 0% or more of SiO 2 . Alternatively, the dehydration and dehydrogenation treatment may be carried out in the following manner: Plasma treatment, UV treatment or chemical treatment may also be performed.

[0183] Next, oxygen may be added to the base insulating film 102 from the upper surface side. This can be done by ion implantation or ion doping. In this case, the acceleration voltage should be 5 kV or more. The voltage must be 100 kV or less. The amount of oxygen added must be 1 x 10 14 ions / cm 2 1x or more 10 16 ions / cm 2 Furthermore, the base insulating film 102 is provided with a different layer from the upper surface side. Oxygen may be added under the following conditions:

[0184] Alternatively, oxygen can be added by applying a bias voltage to the substrate side in a plasma containing oxygen. In this case, the bias voltage should be 10 V or more and less than 1 kV. The voltage application time is 10 seconds or more and 1000 seconds or less, preferably 10 seconds or more and 200 seconds or less, more preferably 10 seconds or more and 200 seconds or less. More preferably, the bias voltage is set to 10 seconds or more and 60 seconds or less. The longer the voltage is applied, the more oxygen can be added, but the simultaneous etching of the film You will no longer be able to ignore the

[0185] By adding oxygen, the base insulating film 102 can be an insulating film containing excess oxygen. However, the method for forming the insulating film containing excess oxygen is not limited to the above method. The process is performed in an atmosphere with a high ratio of SiO2 and at a substrate temperature between room temperature (approximately 25°C) and 150°C. An insulating film containing excess oxygen can also be formed by sputtering. The ratio of oxidizing gas such as oxygen in the film forming gas is set to 20% or more, preferably 50% or more, more preferably 10% or more. More preferably, the content is 80% or more. The method for forming an insulating film containing excess oxygen is as follows. It can be adjusted.

[0186] In this manner, the base insulating film 102 containing excess oxygen may be formed. The embodiment is not limited to the case where the base insulating film 102 contains excess oxygen.

[0187] It is preferable that the base insulating film 102 has sufficient flatness. As the planarization process, chemical mechanical polishing (CMP) may be performed. Mechanical Polishing) or dry etching method. Specifically, the average surface roughness (Ra) is 1 nm or less, preferably 0.3 nm or less. The base insulating film 102 is provided so that the thickness is more preferably 0.1 nm or less.

[0188] Next, an oxide semiconductor film is formed. The oxide semiconductor film is shown as an oxide semiconductor film 106. Select from the materials and deposit them using sputtering, CVD, MBE, ALD or PLD methods. The oxide semiconductor film is preferably formed by a sputtering method. In this case, the oxidizing gas such as oxygen is 5% or more, preferably 10% or more, and more preferably A film-forming gas containing 20% ​​or more, more preferably 50% or more of the following is used. A gas with a low impurity concentration, such as hydrogen, is used.

[0189] After the oxide semiconductor film is formed, first heat treatment may be performed. The first heating may be carried out at a temperature of 50°C or higher and 650°C or lower, preferably 300°C or higher and 500°C or lower. The heat treatment atmosphere is an inert gas atmosphere, oxidizing gas is 10 ppm or more, 1% or more or The first heat treatment is carried out in an atmosphere containing 10% or more of fluorine or in a reduced pressure state. After heat treatment in an active gas atmosphere, oxidizing gas is added at 10 ppm to compensate for the oxygen that has been removed. The heat treatment may be performed in an atmosphere containing 1% or more or 10% or more of the above. By this, impurities such as hydrogen and water can be removed from the oxide semiconductor film.

[0190] Next, the oxide semiconductor film is processed into an island shape to form the oxide semiconductor film 107 (FIG. 5B )reference.).

[0191] Next, a first layer 133a is formed. The first layer 133a is shown as a first layer 132a. Select from the materials and deposit them using sputtering, CVD, MBE, ALD or PLD methods. The film may be formed using the same.

[0192] At this stage, the first layer 133a may be subjected to dehydration and dehydrogenation treatment. The treatment can be carried out, for example, by heat treatment. The temperature of the heat treatment is 250°C or higher. The heat treatment may be carried out at 50°C or less, preferably 300°C or more and 500°C or less. Inert gas atmosphere, atmosphere containing oxidizing gas at 10 ppm or more, 1% or more, or 10% or more The heat treatment is carried out in an inert gas atmosphere or under reduced pressure. After that, to compensate for the oxygen that has been released, oxidizing gas is added at 10 ppm or more, 1% or more, or Alternatively, the heat treatment may be carried out in an atmosphere containing 0% or more of SiO 2 . Alternatively, the dehydration and dehydrogenation treatment may be carried out in the following manner: Plasma treatment, UV treatment or chemical treatment may also be performed.

[0193] Next, oxygen may be added to the first layer 133a from the upper surface side. This can be done by ion implantation or ion doping. In this case, the acceleration voltage should be 5 kV or more. The voltage must be 100 kV or less. The amount of oxygen added must be 1 x 10 14 ions / cm 2 1x or more 10 16 ions / cm 2 Furthermore, the first layer 133a is provided with a different layer from the upper surface side. Oxygen may be added under the following conditions:

[0194] Alternatively, oxygen can be added by applying a bias voltage to the substrate side in a plasma containing oxygen. In this case, the bias voltage should be 10 V or more and less than 1 kV. The voltage application time is 10 seconds or more and 1000 seconds or less, preferably 10 seconds or more and 200 seconds or less, more preferably 10 seconds or more and 200 seconds or less. More preferably, the time is set to 10 seconds or more and 60 seconds or less.

[0195] By adding oxygen, the first layer 133a can be an insulating film containing excess oxygen. However, the method for forming an insulating film containing excess oxygen is not limited to the above method. Sputtering is performed in an atmosphere with a high ratio of and at a substrate temperature between room temperature and 150°C. An insulating film containing excess oxygen can also be formed by the method. The ratio may be set to 20% or more, preferably 50% or more, and more preferably 80% or more. The methods for forming the insulating film containing excess oxygen can be combined as appropriate.

[0196] In this manner, the first layer 133a containing excess oxygen can be formed. The embodiment is not limited to the case where the first layer 133a contains excess oxygen.

[0197] Next, the second layer 133b is formed. The second layer 133b is shown as the second layer 132b. Select from the materials and deposit them using sputtering, CVD, MBE, ALD or PLD methods. The film may be formed using the same.

[0198] Next, a conductive film 105 is formed (see FIG. 5(C)). 4 and process it by sputtering, CVD, MBE, ALD or The film can be formed by using the PLD method.

[0199] Next, the conductive film 105 is processed to form the gate electrode 104 .

[0200] Next, the gate electrode 104 is used as a mask, or a mask is used for processing the gate electrode 104. The second layer 133b and the first layer 133a are processed to form the second layer 132b and the A gate insulating film 132 including a first layer 132a is formed (see FIG. 6(A)).

[0201] Next, impurities are added to the oxide semiconductor film 107 using the gate electrode 104 as a mask. Impurities include helium, boron, nitrogen, fluorine, neon, aluminum, phosphorus, and selected from the group consisting of argon, arsenic, krypton, indium, tin, antimony and xenon One or more impurities may be added. The method of adding impurities is ion implantation or ion doping. In this case, the acceleration voltage is set to 5 kV or more and 100 kV or less. The amount added is 1×10 14 ions / cm 2 More than 1×10 16 ions / cm 2 The following applies. After that, a heat treatment may be carried out.

[0202] The oxide semiconductor film 107 is partially formed by adding the impurities (and performing heat treatment). Here, the region where the resistance is reduced is referred to as region 106b, and the region where the resistance is not reduced is referred to as region 106c. The region 106a and the oxide semiconductor film 106 are collectively referred to as the oxide semiconductor film 106.

[0203] Note that in this embodiment, after the gate insulating film 132 is formed, Although the method of adding a pure substance is described above, it is not limited to this. For example, the gate electrode After forming the oxide semiconductor 104, the oxide semiconductor 104 is formed on the second layer 133b and the first layer 133a. Impurities may be added to the film 107. This makes it possible to make the oxide semiconductor film 107 less susceptible to damage.

[0204] Next, the barrier film 108 is formed (see FIG. 6(B)). Select from the materials shown as 08 and use sputtering, CVD, MBE, ALD or other methods. Alternatively, the film may be formed using a PLD method.

[0205] After the barrier film 108 is formed, a second heat treatment is performed. Oxygen can be released from the insulating film 102 and / or the gate insulating film 132. The released oxygen is supplied to the oxide semiconductor film 106, thereby reducing oxygen vacancies. Furthermore, the influence of the parasitic channel can be reduced. This may be carried out under the same conditions as above.

[0206] The second heat treatment may be performed at any time after the barrier film 108 is formed. The second heat treatment may not be performed.

[0207] In the above manner, the transistor shown in FIG. 4 can be manufactured.

[0208] The transistor shown in FIG. 4 has few oxygen vacancies in the oxide semiconductor film 106 and a parasitic channel. The effect is small, and switching characteristics can be obtained even with miniaturization.

[0209] Next, an interlayer insulating film 118 is formed on the barrier film 108. The interlayer insulating film 118 is an interlayer insulating film. The film 118 is formed by a method such as sputtering, CVD, MBE, or ALD. The film may be formed by the PLD method or the PLD method.

[0210] Next, an opening is formed in the interlayer insulating film 118 and the barrier film 108, and the oxide semiconductor film 106 is To be exposed.

[0211] Next, a conductive film that will become the wiring 136 is formed. Select from the materials shown below and deposit them by sputtering, CVD, MBE, ALD or PL The film can be formed using Method D.

[0212] Next, the conductive film that will become the wiring 136 is processed to form the wiring 136 (see FIG. 6(C)). .

[0213] This embodiment provides a transistor that can obtain switching characteristics even when miniaturized. Furthermore, a highly integrated semiconductor device using the transistor can be provided. can be done.

[0214] Note that this embodiment mode can be used in combination with other embodiment modes as appropriate.

[0215] (Embodiment 2) In this embodiment, a transistor having a structure different from that in Embodiment 1 will be described.

[0216] 7A is a top view of a transistor according to one embodiment of the present invention. A cross-sectional view corresponding to the chain line E1-E2 is shown in Fig. 7(B). A cross-sectional view corresponding to E3-E4 is shown in FIG. 7(C). In A), the underlying insulating film 202 and the like are omitted.

[0217] FIG. 7A shows the channel length (L) and channel width (W) of the transistor. The channel region of the transistor overlaps with the gate electrode 204 in the oxide semiconductor film 206. At least two side surfaces of the oxide semiconductor film 206 are covered with the gate electrode 204. and superimpose.

[0218] The transistor shown in FIG. 7A has a channel length of 5 nm or more and less than 60 nm. The width is 5 nm or more and less than 200 nm.

[0219] In addition, the transistor shown in FIG. 7A has a channel width of 0.5 times or more relative to the channel length. The upper limit is 10 times less.

[0220] FIG. 7B shows a base insulating film 202 provided on the substrate 200 and a film 203 provided on the base insulating film 202. The oxide semiconductor film 206 is formed on the same plane as the oxide semiconductor film 206. the electrode 216, the gate insulating film 212 provided on the oxide semiconductor film 206, and the gate insulating film a gate electrode 204 provided over the insulating film 212 and overlapping with the oxide semiconductor film 206; 1 is a cross-sectional view of a transistor having the structure shown in FIG.

[0221] 7B shows the oxide semiconductor film 206, the pair of electrodes 216, and the gate electrode 204. an interlayer insulating film 218 having openings reaching the pair of electrodes 216, Wiring 236 is shown in contact with the pair of electrodes 216 through the openings in the film 218.

[0222] The material of the substrate 200 may be selected from the same materials as those of the substrate 100.

[0223] Note that the base insulating film 202 may be formed using a material selected from the same materials as those of the base insulating film 102 .

[0224] The gate electrode 204 may be made of the same material as the gate electrode 104 .

[0225] The gate insulating film 212 may be made of the same material as the gate insulating film 112. The gate insulating film 212 may be provided in the same layer structure as the gate insulating film 132 .

[0226] The oxide semiconductor film 206 may be formed using a material selected from the same materials as those of the oxide semiconductor film 106. .

[0227] The interlayer insulating film 218 may be made of the same material as the interlayer insulating film 118 .

[0228] The wiring 236 may be made of a material similar to that of the wiring 136 .

[0229] The pair of electrodes 216 may be made of Al, Ti, Cr, Co, Ni, Cu, Y, Zr, Mo, Ag, T A single layer or multilayer of a and W, which contains one or more of the element, nitride, oxide or alloy. Just use it.

[0230] Although not shown, the base insulating film 202, the pair of electrodes 216, the oxide semiconductor film 206, and the gate electrode 216 are A barrier film may be provided on the barrier electrode 204. The barrier film may be made of the same material as the barrier film 108. The barrier film 108 has the same function as the barrier film 108.

[0231] Therefore, the transistor shown in FIG. 7 is different from the transistors shown in FIGS. 1 to 4 in that it is an oxide semiconductor. The only difference is the shape of the membrane 206 and the presence of a pair of electrodes 216. For this configuration, reference can be made to the explanations given in connection with FIGS.

[0232] The transistor illustrated in FIG. 7 differs from the transistor illustrated in FIG. 1 in that the oxide semiconductor film 106 The structure has a pair of electrodes 216 instead of the region 106b. Compared to the transistor shown in Fig. 1, the source and drain resistances can be reduced. Therefore, even when miniaturized, a transistor with excellent on-state characteristics can be provided.

[0233] A method for manufacturing the transistor shown in FIG. 7 will be described below with reference to FIG. Therefore, only the cross-sectional view corresponding to FIG. 7(B) is shown here.

[0234] First, a substrate 200 is prepared.

[0235] Next, a base insulating film 202 is formed on the substrate 200. The base insulating film 202 is It may be formed using the same materials and methods as in 02.

[0236] Next, a conductive film that will become the pair of electrodes 216 is formed. The counter electrode 216 is formed by a method such as sputtering, CVD, MBE, or the like. The film may be formed using the ALD method or the PLD method.

[0237] Next, the conductive film that will become the pair of electrodes 216 is processed to have openings that expose the base insulating film 202. A conductive film 217 is formed.

[0238] Next, an oxide semiconductor film 207 is formed (see FIG. 8A). The oxide semiconductor film 106 may be formed using the materials and the method described above for the oxide semiconductor film 106.

[0239] After the oxide semiconductor film 207 is formed, first heat treatment may be performed. Please refer to embodiment 1.

[0240] Next, planarization treatment is performed on the oxide semiconductor film 207 and the conductive film 217. The planarization process may be performed by CMP or the like. An oxide semiconductor film is provided only on the insulating film.

[0241] Next, the oxide semiconductor film provided only in the openings of the conductive film 217 and the conductive film 217 are heated. The oxide semiconductor film 206 and the pair of electrodes 216 are formed in an island shape (FIG. 8(B)). )reference.).

[0242] Next, a gate insulating film 212 and a gate electrode 204 on the gate insulating film 212 are formed. (See FIG. 8C.) The gate insulating film 212 is the same as the gate insulating film 112 or the gate insulating film 112. The gate electrode 204 may be formed using the same material and method as the gate electrode 132. It may be formed using the same material and method as the pole 104 .

[0243] Next, a barrier film may be formed using the same material and method as the barrier film 108. The film may be formed using the following.

[0244] In the above manner, the transistor shown in FIG. 7 can be manufactured.

[0245] The transistor shown in FIG. 7 has few oxygen vacancies in the oxide semiconductor film 206 and a parasitic channel. The effect is small, and switching characteristics can be obtained even when the electrodes are miniaturized. By having 16, it is possible to make a transistor with excellent on-state characteristics even when miniaturized. Cut.

[0246] Next, an interlayer insulating film 218 is formed. The interlayer insulating film 218 is made of the same material as the interlayer insulating film 118. The film may be formed using any suitable material and method.

[0247] Next, openings are formed in the interlayer insulating film 218 to expose the pair of electrodes 216 .

[0248] Next, the wiring 236 is formed. The wiring 236 is formed using the same material and method as the wiring 136. (See FIG. 8(D)).

[0249] According to this embodiment, switching characteristics can be obtained even when miniaturized, and transistors with excellent on-state characteristics can be obtained. Furthermore, a highly integrated semiconductor device using the transistor can be provided. A body device can be provided.

[0250] Note that this embodiment mode can be used in combination with other embodiment modes as appropriate.

[0251] (Embodiment 3) In this embodiment, a transistor having a structure different from that of the first and second embodiments will be described. and explain.

[0252] 9A is a top view of a transistor according to one embodiment of the present invention. A cross-sectional view corresponding to the dashed line F1-F2 is shown in Fig. 9(B). A cross-sectional view corresponding to F3-F4 is shown in FIG. 9(C). In A), the underlying insulating film 302 and the like are omitted.

[0253] FIG. 9A shows the channel length (L) and channel width (W) of the transistor. The channel region of the transistor overlaps with the gate electrode 304 in the oxide semiconductor film 306. At least two side surfaces of the oxide semiconductor film 306 are covered with the gate electrode 304. and superimpose.

[0254] The transistor shown in FIG. 9A has a channel length of 5 nm or more and less than 60 nm. The width is 5 nm or more and less than 200 nm.

[0255] In addition, the transistor shown in FIG. 9A has a channel width of 0.5 times or more relative to the channel length. The upper limit is 10 times less.

[0256] FIG. 9B shows a base insulating film 302 provided on the substrate 300 and a film 303 provided on the base insulating film 302. an oxide semiconductor film 306 having a first region 306a and a second region 306b; a gate insulating film 312 provided over the oxide semiconductor film 306; The gate electrode 304 is provided to overlap with the oxide semiconductor film 306, and the gate electrode 30 4, and the insulating film 320 is in contact with the side surfaces of the gate electrode 304 and the insulating film 320. The sidewall insulating film 310 is formed on the oxide semiconductor film 306. A pair of electrodes 316 are provided in contact with the second region 306b of the first insulating film 306 and the sidewall insulating film 310. An interlayer insulating film 31 is provided on the pair of electrodes 316 and has an upper surface flush with the insulating film 320. 8 and a cross-sectional view of a transistor having the same.

[0257] 9B, the interlayer insulating film 318 and the interlayer insulating film 320 are formed on the insulating film 320. 328, and the interlayer insulating film 318 and the pair of electrodes 316 provided on the interlayer insulating film 328. 3 shows a wiring 336 provided in contact with the pair of electrodes 316 through the opening.

[0258] In FIG. 9B, the gate electrode 304 and the insulating film 320 have the same top surface shape. The gate insulating film 312 has the same top surface shape as the gate electrode 304 and the sidewall insulating film 310. do.

[0259] Note that the first region 306a of the oxide semiconductor film 306 serves as a channel region of a transistor. The second region 306b of the oxide semiconductor film 306 functions as a source region of the transistor. It functions as a source region and a drain region.

[0260] In the transistor shown in FIG. 9, a pair of electrodes 316 sandwich a sidewall insulating film 310 between which a gate electrode 3 Therefore, the resistance of the source and drain can be reduced. This makes it possible to improve the on-state characteristics of the transistor.

[0261] The material of the substrate 300 may be selected from the same materials as those of the substrate 100.

[0262] The base insulating film 302 may be formed using a material selected from the same materials as those of the base insulating film 102 .

[0263] The gate electrode 304 may be made of the same material as the gate electrode 104 .

[0264] The gate insulating film 312 may be made of the same material as the gate insulating film 112. The gate insulating film 312 may be provided in the same layer structure as the gate insulating film 132 .

[0265] The oxide semiconductor film 306 may be formed using a material selected from the same materials as those of the oxide semiconductor film 106. .

[0266] The sidewall insulating film 310 is made of aluminum oxide, aluminum nitride, magnesium oxide, silicon oxide, or the like. Silicon, silicon oxynitride, silicon nitride oxide, silicon nitride, germanium oxide, oxide Yttrium oxide, zirconium oxide, lanthanum oxide, neodymium oxide, hafnium oxide and One or more materials containing tantalum oxide may be selected and used.

[0267] The insulating film 320 is made of aluminum oxide, aluminum nitride, magnesium oxide, silicon oxide, or the like. silicon oxynitride, silicon nitride oxide, silicon nitride, germanium oxide, germanium oxide Thorium oxide, zirconium oxide, lanthanum oxide, neodymium oxide, hafnium oxide and oxide One or more materials containing tantalum may be selected and used.

[0268] The pair of electrodes 316 may be made of the same materials as the pair of electrodes 216 .

[0269] The interlayer insulating film 318 may be made of the same material as the interlayer insulating film 218 .

[0270] The interlayer insulating film 328 may be made of the same material as the interlayer insulating film 218 .

[0271] The wiring 336 may be made of a material similar to that of the wiring 136 .

[0272] Although not shown, the insulating film 302, the pair of electrodes 316, the oxide semiconductor film 306, the insulating film 3 A barrier film may be provided on the gate electrode 304 and the barrier film 108. The barrier film 108 may be made of a material similar to that of the barrier film 108, and has the same function as the barrier film 108.

[0273] A method for manufacturing the transistor shown in FIG. 9 will be described below with reference to FIGS. For simplicity, only the cross-sectional view corresponding to FIG. 9(B) is shown here.

[0274] First, a substrate 300 is prepared.

[0275] Next, a base insulating film 302 is formed. The base insulating film 302 is made of the same material as the base insulating film 102. The film may be formed using any suitable material and method.

[0276] Next, an oxide semiconductor film 307 is formed. 7 may be formed using the same materials and methods.

[0277] Next, the gate insulating film 313 is formed. The gate insulating film 313 is formed on the gate insulating film 112 or The insulating film 132 may be formed using the same material and method as the gate insulating film 132 .

[0278] Next, a conductive film 305 is formed. The conductive film 305 is a material that will become the gate electrode 304. Select from the materials listed above and process them by sputtering, CVD, MBE, ALD or PLD methods. The film may be formed using the following.

[0279] Next, an insulating film 321 is formed (see FIG. 10(A)). and forming the material by sputtering, CVD, MBE, ALD or The film may be formed using the PLD method.

[0280] Next, the insulating film 321 and the conductive film 305 are processed, and the insulating film 322 and the gate electrode 304 are formed. (See FIG. 10(B)). The insulating film 322 and the gate electrode 304 have the same upper surface. The shape.

[0281] Next, the oxide semiconductor film 307 was treated with an impurity-containing solution using the insulating film 322 and the gate electrode 304 as a mask. Specifically, impurities such as helium, boron, nitrogen, fluorine, neon, Aluminum, phosphorus, argon, arsenic, krypton, indium, tin, antimony and and xenon. The method for adding the ions is an ion implantation method, This can be done by ion doping, preferably by ion implantation. The voltage is set to 5 kV or more and 100 kV or less. The amount of impurities added is 1 × 10 14 ions / cm 2 More than 1×10 16 ions / cm 2 The following may be followed by a heat treatment. .

[0282] The region to which the impurity is added has a low resistance and becomes the second region 306b. The area that is not added becomes the first area 306a. and the oxide semiconductor film 306 having the second region 306b is formed (see FIG. 10C). .).

[0283] Next, an insulating film that will become the sidewall insulating film 310 is formed. The wall insulating film 310 is formed by selecting from the materials shown and depositing the insulating film 310 by a method such as sputtering, CVD, MBE, or the like. The film may be formed by ALD or PLD. By performing highly anisotropic etching on the insulating film 322 and the gate electrode 3 A sidewall insulating film 310 can be formed in contact with the side surface of the gate insulating film 04.

[0284] The sidewall insulating film 310 is formed, and the gate insulating film 313 is formed on the sidewall insulating film 310 and the gate insulating film 313. The gate electrode 304 is processed as a mask to form a gate insulating film 312 (see FIG. 11(A)). Light. ).

[0285] Next, a conductive film 317 is formed (see FIG. 11B). The materials are selected from those shown as 16 and deposited by sputtering, CVD, MBE, ALD or other methods. Alternatively, the film may be formed using a PLD method.

[0286] After the conductive film 317 is formed, a second heat treatment is performed. Oxygen can be released from the insulating film 302 and / or the gate insulating film 312. The oxygen thus supplied is supplied to the oxide semiconductor film 306, thereby reducing oxygen vacancies. The second heat treatment may be performed under the same conditions as those of the second heat treatment described in Embodiment Mode 1.

[0287] The second heat treatment is not limited to the time immediately after the formation of the conductive film 317. It may be performed at any step after the above.

[0288] Next, an interlayer insulating film 319 is formed (see FIG. 11(C)). The insulating film 318 is selected from the materials shown and deposited by sputtering, CVD, MBE, or A. The film may be formed using the LD method or the PLD method.

[0289] Next, a planarization process (CMP process, dry etching process, etc.) is performed on the interlayer insulating film 319. A pair of electrodes 316, an interlayer insulating film 318, a sidewall insulating film 310, and an insulating film 320 are formed. (See FIG. 12(A)).

[0290] By performing a planarization process on the interlayer insulating film 319, the insulating film 322 (gate Only the area overlapping with the electrode 304 can be removed. The insulating film 320 is also subjected to a planarization process, resulting in a thinner insulating film 320.

[0291] By forming the pair of electrodes 316 using such a method, the pair of electrodes 316 The sidewall insulating film 310 can be provided so as to be close to the gate electrode 304 .

[0292] In the above manner, the transistor shown in FIGS. 9A and 9B can be manufactured.

[0293] The transistor illustrated in FIG. 9 has few oxygen vacancies in the oxide semiconductor film 306 and a parasitic channel. The effect is small, and switching characteristics can be obtained even when the electrodes are miniaturized. By having 16, it is possible to make a transistor with excellent on-state characteristics even when miniaturized. Cut.

[0294] Next, an interlayer insulating film 328 is formed (see FIG. 12(B)). The insulating film 328 is selected from the materials shown and deposited by sputtering, CVD, MBE, or A. The film may be formed using the LD method or the PLD method.

[0295] Next, the interlayer insulating film 328 and the interlayer insulating film 318 are processed to expose the pair of electrodes 316. An opening is formed.

[0296] Next, a wiring 336 is formed (see FIG. 12C). The wiring 336 is formed in the same manner as the wiring 136. The material and method may be used to form the insulating film.

[0297] According to this embodiment, switching characteristics can be obtained even when miniaturized, and transistors with excellent on-state characteristics can be obtained. Furthermore, a highly integrated semiconductor device using the transistor can be provided. A body device can be provided.

[0298] Note that this embodiment mode can be used in combination with other embodiment modes as appropriate.

[0299] (Fourth embodiment) In this embodiment, a transistor having a structure different from that of Embodiments 1 to 3 will be described. I will explain.

[0300] FIG. 13A is a top view of a transistor according to one embodiment of the present invention. A cross-sectional view corresponding to the dashed line G1-G2 is shown in FIG. 13(B). A cross-sectional view corresponding to the dashed line G3-G4 is shown in FIG. Therefore, the base insulating film 402 and the like are omitted in FIG. 13(A).

[0301] FIG. 13A shows the channel length (L) and channel width (W) of the transistor. The channel region of the transistor is formed by overlapping the gate electrode 404 in the oxide semiconductor film 406. At least two side surfaces of the oxide semiconductor film 406 are overlapped by the gate electrode 40. Overlap with 4.

[0302] The transistor shown in FIG. 13(A) has a channel length of 5 nm or more and less than 60 nm. The width of the hole is 5 nm or more and less than 200 nm.

[0303] In addition, the transistor shown in FIG. 13A has a channel width that is 0.5 times larger than the channel length. It is 10 times or less.

[0304] FIG. 13B shows a base insulating film 402 provided on a substrate 400 and a an oxide semiconductor film 406 having a thickness of 1 to 5 times the width of a channel; a gate insulating film 412 provided on the compound semiconductor film 406; a transistor including a gate electrode 404 overlapping with an oxide semiconductor film 406; This is the cross-sectional structure.

[0305] Note that in FIG. 13B, an oxide semiconductor film 406 and an oxide semiconductor film 408 are formed over the gate electrode 404. an interlayer insulating film 418 having an opening reaching the nitride semiconductor film 406; A wiring 436 provided in contact with the oxide semiconductor film 406 through the opening is also shown.

[0306] Figure 13 shows a so-called fin-type transistor. The thicker the channel region, the larger the carrier conduction path, allowing for A transistor with excellent on-state characteristics can be obtained.

[0307] In the case of a silicon fin-type transistor, the channel region is thick, As a result, the depletion layer caused by the electric field at the gate does not fully expand, making it difficult to completely turn off the transistor. On the other hand, in a fin transistor using an oxide semiconductor film, Even if the channel region is thick, the depletion layer due to the electric field of the gate is sufficiently expanded to turn the transistor on. You can do this.

[0308] The material of the substrate 400 may be selected from the same materials as those of the substrate 100 .

[0309] Note that the base insulating film 402 may be formed using a material selected from the same materials as those of the base insulating film 102 .

[0310] The gate electrode 404 may be made of a material selected from the same materials as those of the gate electrode 104 .

[0311] The gate insulating film 412 may be made of the same material as the gate insulating film 112. The gate insulating film 412 may have the same layer structure as the gate insulating film 132 .

[0312] The oxide semiconductor film 406 may be formed using a material selected from the same materials as those of the oxide semiconductor film 106. The thickness of the oxide semiconductor film 406 is greater than or equal to 100 nm and less than 2 μm.

[0313] The interlayer insulating film 418 may be made of the same material as the interlayer insulating film 118 .

[0314] The wiring 436 may be made of a material similar to that of the wiring 136 .

[0315] Although not shown, a barrier layer is formed on the base insulating film 402, the oxide semiconductor film 406, and the gate electrode 404. The barrier film may be made of the same material as the barrier film 108. It often has the same function as the barrier film 108 .

[0316] A method for manufacturing the transistor shown in FIG. 13 will be described below with reference to FIG. Therefore, only the cross-sectional view corresponding to FIG. 13(B) is shown here.

[0317] First, a substrate 400 is prepared.

[0318] Next, a base insulating film 402 is formed on the substrate 400. The base insulating film 402 is It may be formed using the same materials and methods as in 02.

[0319] Next, an oxide semiconductor film is formed (see FIG. 14A). The conductive film 107 may be formed using the same material and method as those for the conductive film 107 .

[0320] Next, a gate insulating film 412 and a gate electrode 404 on the gate insulating film 412 are formed ( (See FIG. 14B.) The gate insulating film 412 is the same as the gate insulating film 112 or the gate insulating film The gate electrode 404 may be formed using the same material and method as the gate electrode 132. It may be formed using the same material and method as the pole 104 .

[0321] Next, impurities are added to the oxide semiconductor film 407 using the gate electrode 404 as a mask. In general, impurities include helium, boron, nitrogen, fluorine, neon, aluminum, and phosphorus. , argon, arsenic, krypton, indium, tin, antimony and xenon The method for adding one or more of the above-mentioned elements may be an ion implantation method, an ion doping method, or the like. Preferably, ion implantation is used. At this time, the acceleration voltage is set to 5 kV or more and 10 0 kV or less. The amount of impurities added is 1 × 10 14 ions / cm 2 More than 1×10 16 ions / cm 2 The following applies: After that, a heat treatment may be carried out.

[0322] Next, a barrier film may be formed using the same material and method as the barrier film 108. The film may be formed using the following.

[0323] In the above manner, the transistor shown in FIG. 13 can be manufactured.

[0324] The transistor illustrated in FIG. 13 has few oxygen vacancies in the oxide semiconductor film 406 and a parasitic channel The influence of the oxide semiconductor is small, and switching characteristics can be obtained even when the device is miniaturized. By making the thickness of the membrane 406 1 to 5 times the channel width, A transistor with excellent on-state characteristics can be obtained.

[0325] Next, an interlayer insulating film 418 is formed. The interlayer insulating film 418 is made of the same material as the interlayer insulating film 118. The material and method may be used.

[0326] Next, an opening is formed in the interlayer insulating film 418 to expose the oxide semiconductor film 406 .

[0327] Next, the wiring 436 is formed. The wiring 436 is formed using the same material and method as the wiring 136. (See FIG. 14(C)).

[0328] According to this embodiment, switching characteristics can be obtained even when miniaturized, and transistors with excellent on-state characteristics can be obtained. Furthermore, a highly integrated semiconductor device using the transistor can be provided. A body device can be provided.

[0329] Note that this embodiment mode can be used in combination with other embodiment modes as appropriate.

[0330] (Embodiment 5) In this embodiment, a transistor having a structure different from that of the first to fourth embodiments will be described. I will explain.

[0331] FIG. 15A is a top view of a transistor according to one embodiment of the present invention. A cross-sectional view corresponding to the dashed line H1-H2 is shown in FIG. A cross-sectional view corresponding to the dashed line H3-H4 is shown in FIG. Therefore, the base insulating film 502 and the like are omitted in FIG. 15(A).

[0332] FIG. 15(A) shows the channel length (L) and channel width (W) of the transistor. The channel region of the transistor is sandwiched between a pair of electrodes 516 in the oxide semiconductor film 506. At least two side surfaces of the oxide semiconductor film 506 are covered with the gate electrode 50. Overlap with 4.

[0333] The transistor shown in FIG. 15(A) has a channel length of 5 nm or more and less than 60 nm. The width of the hole is 5 nm or more and less than 200 nm.

[0334] In addition, the transistor shown in FIG. 15A has a channel width that is 0.5 times the channel length. It is 10 times or less.

[0335] FIG. 15B shows a base insulating film 502 provided on a substrate 500 and a A gate electrode 504 is provided, and a gate insulating film 512 is provided on the gate electrode 504. , an oxide semiconductor film 512 is provided to overlap with the gate electrode 504 with a gate insulating film 512 interposed therebetween. 506, a pair of electrodes 516 provided over the oxide semiconductor film 506, and 5 is a cross-sectional view of a transistor having an interlayer insulating film 518 provided thereon.

[0336] The material of the substrate 500 may be selected from the same materials as those of the substrate 100 .

[0337] The base insulating film 502 is formed so that impurities originating from the substrate 500 do not affect the oxide semiconductor film 506. However, if the substrate 500 does not contain impurities, the base insulating film The gate insulating film 512 may be omitted. If this can be controlled, the base insulating film 502 may not be provided.

[0338] The base insulating film 502 is made of aluminum oxide, aluminum nitride, magnesium oxide, silicon oxide, or the like. Silicon, silicon oxide nitride, germanium oxide, yttrium oxide, zirconium oxide, One or more materials including lanthanum oxide, neodymium oxide, hafnium oxide, and tantalum oxide In addition to the above-mentioned single layer or laminated layer, , silicon nitride oxide, and silicon nitride may be stacked.

[0339] The gate electrode 504 may be made of a material selected from the same materials as those of the gate electrode 104 .

[0340] The gate insulating film 512 is made of the same material as the gate insulating film 112 or the gate insulating film 132. You can just select and use it.

[0341] The oxide semiconductor film 506 may be formed using a material selected from the same materials as those of the oxide semiconductor film 106. .

[0342] The pair of electrodes 516 may be made of the same material as the pair of electrodes 216 .

[0343] The interlayer insulating film 518 is made of aluminum oxide, aluminum nitride, magnesium oxide, silicon oxide, or the like. Silicon, silicon oxide nitride, germanium oxide, yttrium oxide, zirconium oxide, One or more materials including lanthanum oxide, neodymium oxide, hafnium oxide, and tantalum oxide In addition to the above-mentioned single layer or laminated layer, , silicon nitride oxide, and silicon nitride may be stacked.

[0344] It is preferable that the interlayer insulating film 518 has a low relative dielectric constant and a sufficient thickness. For example, a silicon oxide film with a relative dielectric constant of about 3.8 is used, and the thickness is 200 nm to 1000 nm. The upper surface of the interlayer insulating film 518 is slightly fixed due to the influence of atmospheric components, etc. The charge can cause the threshold voltage of the transistor to fluctuate. Therefore, the interlayer insulating film 518 is formed in a ratio range that sufficiently reduces the influence of the electric charge generated on the upper surface. For the same reason, it is preferable to form a polyimide film on the interlayer insulating film 518. By forming a resin film such as polyethylene resin, acrylic resin, epoxy resin, or silicone resin, The influence of charges generated on the upper surface of the interlayer insulating film 518 may be reduced.

[0345] A method for manufacturing the transistor shown in FIG. 15 will be described below with reference to FIG. For clarity, only the cross-sectional view corresponding to FIG. 15(B) is shown here.

[0346] First, a substrate 500 is prepared.

[0347] Next, a base insulating film 502 is formed on the substrate 500. Select from the materials shown as 02 and use sputtering, CVD, MBE, ALD or other methods. Alternatively, the film may be formed using a PLD method.

[0348] Next, a gate electrode 504 is formed. The gate electrode 504 is made of the same material as the gate electrode 104. The material and method may be used.

[0349] Next, a gate insulating film 512 is formed (see FIG. 16(A)). The gate insulating film 512 is If it is formed using the same material and method as the gate insulating film 112 or the gate insulating film 132, That's fine.

[0350] Next, an oxide semiconductor film 506 is formed (see FIG. 16B). The oxide semiconductor film 106 may be formed using a material and a method similar to those of the oxide semiconductor film 107.

[0351] Next, a conductive film that will become the pair of electrodes 516 is formed. The counter electrode 516 is formed by selecting a material from the materials shown in the table and depositing it by a sputtering method, a CVD method, an MBE method, or the like. The film may be formed using the ALD method or the PLD method.

[0352] Next, the conductive film that will become the pair of electrodes 516 is processed to form the pair of electrodes 516. The conductive film that becomes the pair of electrodes 516 is processed in part by an electron beam lithography system (EB). It is preferable to use an EB exposure machine. Since it can be processed, it is suitable for manufacturing miniaturized transistors.

[0353] Next, an interlayer insulating film 518 is formed (see FIG. 16(C)). The insulating film 518 is selected from the materials shown and deposited by sputtering, CVD, MBE, or A. The film may be formed using the LD method or the PLD method.

[0354] In the above manner, the transistor shown in FIG. 15 can be manufactured.

[0355] The transistor illustrated in FIG. 15 has few oxygen vacancies in the oxide semiconductor film 506 and a parasitic channel The effect of the difference is small, and switching characteristics can be obtained even when the device is miniaturized. By having 516, it is possible to make a transistor with excellent on-state characteristics even when miniaturized. can.

[0356] According to this embodiment, switching characteristics can be obtained even when miniaturized, and transistors with excellent on-state characteristics can be obtained. Furthermore, a highly integrated semiconductor device using the transistor can be provided. A body device can be provided.

[0357] Note that this embodiment mode can be used in combination with other embodiment modes as appropriate.

[0358] (Sixth embodiment) In this embodiment, the transistor described in any of Embodiments 1 to 5 is used. An example of manufacturing a semiconductor memory device will be described below.

[0359] A typical example of a volatile semiconductor memory device is a memory element that is made up of a transistor. By storing charge in the capacitor, information is stored in the DRAM (Dynamic Random Access Memory). Random Access Memory (RANDOM), which uses circuits such as flip-flops to store data. SRAM (Static Random Access Memory) holds the data. be.

[0360] A typical example of a nonvolatile semiconductor memory device is a transistor having a gate and a channel region. The floating gate is located in the memory cell, and the memory cell stores electric charge in the floating gate. There is a flash memory that does this.

[0361] Some of the transistors included in the semiconductor memory device described above are A transistor shown in any one of the following can be applied.

[0362] First, a semiconductor device to which the transistor described in any of Embodiments 1 to 5 is applied FIG. 17 shows a specific example of a memory cell that constitutes a memory device.

[0363] The memory cell is composed of a bit line BL, a word line WL, a sense amplifier SAmp, and a transistor. The transistor Tr and the capacitor C are included (see FIG. 17(A)).

[0364] The time change in the voltage held in capacitor C is caused by the off-current of transistor Tr, as shown in Figure 1. It is known that the voltage gradually decreases as shown in Figure 7(B). Over time, the applied voltage will decrease to VA, which is the limit at which data1 can be read. This period is called the retention period T_1. In other words, in the case of a binary memory cell, during the retention period T_1 You need to refresh it.

[0365] Here, the transistor Tr may be any of the transistors shown in the first to fifth embodiments. By applying a capacitor, the off-state current of the transistor can be made extremely small. The period T_1 can be lengthened. In other words, the frequency of refresh can be reduced. Therefore, power consumption can be reduced. For example, when the off-state current is 1×10 -21 A or ra1×10 -25 When a memory cell is configured with a transistor Tr, which is A, no power is supplied. It is possible to store data for periods ranging from a few days to several decades.

[0366] In addition, the transistor Tr may be a transistor shown in any one of the first to fifth embodiments. When this is applied, the area of ​​the memory cell can be reduced because the transistor is miniaturized. Therefore, the degree of integration of the semiconductor memory device can be increased.

[0367] FIG. 17C shows an example of a cross-sectional structure of a memory cell. The transistor shown in Figure 4 is used for the transistor Tr. For each configuration that is not described below, please refer to the description in the first embodiment and the like.

[0368] Here, the capacitor C is on the base insulating film 102, and the region 106b of the transistor Tr The electrode 116 provided in contact with the gate insulating film 132 is formed in the same layer and made of the same material. The insulating layer and the electrode (capacitor electrode) are formed in the same layer and made of the same material as the gate electrode 104. In FIG. 17C, the electrode 116 is embedded in the base insulating film 102. The electrode 116 is located on the base insulating film 102, but is not limited to this. Any shape may be used as long as it is in contact with the region 106b of the transistor Tr. No.

[0369] The electrode 116 is made of Al, Ti, Cr, Co, Ni, Cu, Y, Zr, Mo, Ag, Ta and and W, and the element, nitride, oxide or alloy containing one or more of them is used in a single layer or a laminated layer. That's fine.

[0370] The word line WL is electrically connected to the gate electrode 104. The bit line BL is , and is electrically connected to the wiring 136.

[0371] In the memory cell shown in FIG. 17C, the transistor Tr and the capacitor C are in the same layer and Since the electrodes and insulating film are made of the same material, the number of processes can be reduced and However, if the transistor Tr and the capacitor C are in the same layer and The electrodes and insulating film do not have to be made of the same material. By overlapping the transistor Tr and the capacitor C, the area of ​​the memory cell can be further reduced. It's okay to make it smaller.

[0372] As described above, according to one embodiment of the present invention, a semiconductor memory device with high integration and low power consumption can be provided. You can get a position.

[0373] Next, a semiconductor memory device to which the transistor described in any of Embodiments 1 to 5 is applied will be described. An example of memory cells constituting a storage device, which is different from that shown in FIG. 17, will be described with reference to FIG.

[0374] 18A is a circuit diagram of a memory cell. The memory cell includes a transistor Tr_1 and A word line WL_1 electrically connected to the gate of the transistor Tr_1, and a a source line SL_1 electrically connected to the source of the transistor r_1; a transistor Tr_2; a source line SL_2 electrically connected to the source of the transistor Tr_2; a drain line DL_2 electrically connected to the drain of the capacitor C; The capacitance line CL is electrically connected to one end of the capacitor C, the other end of the transistor Tr_1. a node N electrically connected to the drain and the gate of the transistor Tr_2; .

[0375] In the semiconductor memory device described in this embodiment, the transistor T This utilizes the fact that the apparent threshold voltage of r_2 fluctuates. For example, in Figure 18 (B) is the voltage V of the capacitance line CL CL and the drain current I flowing through transistor Tr_2 d _ 2.

[0376] The potential of the node N can be adjusted via the transistor Tr_1. For example, The potential of the source line SL_1 is set to VDD. At this time, the potential of the word line WL_1 is set to the transistor By setting the potential at or above the sum of the threshold voltage Vth of transistor Tr_1 and VDD, The potential of the word line WL_1 can be set to HIGH. By setting the threshold voltage Vth of node N_1 or less, the potential of node N can be set to LOW. do.

[0377] Therefore, V shown with N=LOW CL -Id _2 curve and V shown with N=HIGH CL -I d _2 curves can be obtained. That is, when N=LOW, V CL =0V At I d Since _2 is small, the data is 0. Also, when N=HIGH, V CL =0V TE I d Since _2 is larger, it becomes data 1. In this way, the data can be stored. Cut.

[0378] Here, the transistor Tr_1 is a transistor shown in any one of the first to fifth embodiments. When a transistor is used, the off-state current of the transistor can be made extremely small. The charge stored at node N is unintentionally transferred between the source and drain of transistor Tr_1. This prevents data from leaking to the server. Therefore, data can be stored for a long period of time. In addition, since high voltage is not required when writing, it consumes less power than flash memory. It consumes less power and can operate at a faster speed.

[0379] In addition, the transistor Tr_1 may be a transistor shown in any one of the first to fifth embodiments. When a transistor is applied, the area of ​​the memory cell is reduced because the transistor is miniaturized. Therefore, the degree of integration of the semiconductor memory device can be increased.

[0380] FIG. 18C shows an example of a cross-sectional structure of a memory cell. The transistor shown in Figure 4 is applied to the transistor Tr_1. For each configuration of r_1 that is not described below, please refer to the description of the first embodiment. Illuminate.

[0381] In this embodiment, the transistor Tr_2 is a silicon transistor. However, the case where the transistor Tr_2 is applied with the first embodiment to the second embodiment will be described. Any of the transistors described in Embodiment 5 may be used.

[0382] The transistor using silicon is the same as the transistor described in any of Embodiments 1 to 5. Therefore, it is suitable for transistors that require a low off-current. This is more suitable for transistor Tr_2, which requires higher on-state characteristics than transistor Tr_1. .

[0383] Here, the transistor Tr_2 is formed by a base insulating film 152 provided on a substrate 150 and a base insulating film A silicon film 156 including a region 156a and a region 156b is provided on the insulating film 152. a gate insulating film 162 provided on the silicon film 156; The gate electrode 154 is provided so as to overlap the silicon film 156, and the gate insulating film 162 and and a sidewall insulating film 160 provided in contact with the sidewall of the gate electrode 154 .

[0384] An interlayer insulating film 158 is provided on the transistor Tr_2. A hydrogen-containing layer 168 is provided.

[0385] The material of the substrate 150 may be selected from the same materials as those of the substrate 100 .

[0386] The base insulating film 152 may be formed using a material selected from the same materials as those of the base insulating film 102 .

[0387] The silicon film 156 may be a single crystal silicon film, a polycrystalline silicon film, or the like. good.

[0388] The region 156a functions as a channel region, and the region 156b functions as a source region and a and serves as the drain region.

[0389] In this embodiment, silicon films are used for the channel region, source region, and drain region. However, when the substrate 150 is a semiconductor substrate such as a silicon wafer, A channel region, a source region and a drain region may be provided.

[0390] The gate insulating film 162 may be formed using a material selected from the same materials as those of the gate insulating film 112 .

[0391] The gate electrode 154 may be made of a material selected from the same materials as those of the gate electrode 104 .

[0392] The sidewall insulating film 160 may be made of the same material as the sidewall insulating film 310 .

[0393] The interlayer insulating film 158 may be made of the same material as the interlayer insulating film 118. On the interlayer insulating film 158, a resin such as polyimide resin, acrylic resin, epoxy resin, or silicone resin is formed. Any resin film may be formed.

[0394] The hydrogen-containing layer 168 is analyzed by secondary ion mass spectrometry (SIMS). Ass Spectrometry) to measure hydrogen at 1×10 21 atoms / cm 3 Including It is an insulating film.

[0395] The hydrogen-containing layer 168 may be, for example, a silicon nitride oxide film or a silicon nitride film.

[0396] Since the transistor Tr_2 is a transistor using silicon, the silicon film 156 The electrical properties can be improved by hydrogen-terminating the surface of the It is preferable that hydrogen is supplied from the layer 168. However, in this embodiment, the hydrogen-containing layer 168 For example, the transistor may be formed without using the hydrogen-containing layer 168. Hydrogen may be supplied to Tr_2.

[0397] Although not shown, a layer with low hydrogen permeability is provided between the hydrogen-containing layer 168 and the underlying insulating film 102. The transistor Tr_1 is a transistor including an oxide semiconductor film. In the oxide semiconductor film, hydrogen can be a source of carrier generation. Therefore, when the hydrogen-containing layer 168 is provided, the hydrogen permeation It is preferable to use a layer with low conductivity to suppress the diffusion of hydrogen into the transistor Tr_1.

[0398] Specifically, the layer with low hydrogen permeability is formed by heating at 350°C for 1 hour. It is an insulating film that has the property of not transmitting light.

[0399] The capacitor C is located on the insulating base film 102 and is located in the region 106 of the transistor Tr_1. b, an electrode 166 provided in contact with the gate insulating film 132, and formed in the same layer and made of the same material as the gate insulating film 132. The insulating layer and the electrode (capacitor electrode) are formed in the same layer and made of the same material as the gate electrode 104. The electrode 166 is formed by the insulating base film 102, the hydrogen-containing layer 168, and the interlayer insulating film. The film 158 is in contact with the gate electrode 154 of the transistor Tr_2 through an opening provided in the film 158. In FIG. 18(C), the electrode 166 is embedded in the base insulating film 102. The electrode 166 is on the base insulating film 102, and the transistor The gate electrode 154 of the transistor Tr_2 is provided in contact with the region 106b of the transistor Tr_1. The shape of the wire may be any shape as long as it fits snugly into the wire.

[0400] Electrodes 166 include Al, Ti, Cr, Co, Ni, Cu, Y, Zr, Mo, Ag, Ta and and W, and the element, nitride, oxide or alloy containing one or more of them is used in a single layer or a laminated layer. That's fine.

[0401] The word line WL_1 is electrically connected to the gate electrode 104. L_1 is electrically connected to the wiring 136. The capacitance line CL is electrically connected to the capacitance electrode. Connected.

[0402] In the memory cell shown in FIG. 18C, the transistor Tr_1 and the capacitor C are formed in the same layer. In addition, the number of processes can be reduced because the electrodes and insulating film are made of the same material. However, the transistor Tr_1 and the capacitor C are The electrode and insulating film do not have to be formed in one layer from the same material. For example, by providing a transistor Tr and a capacitor C in an overlapping manner, the area of ​​the memory cell can be reduced. It may be made even smaller.

[0403] As described above, according to one embodiment of the present invention, a semiconductor memory device with high integration and low power consumption can be provided. You can get a position.

[0404] This embodiment mode can be implemented in appropriate combination with other embodiment modes.

[0405] (Embodiment 7) The transistor described in any of Embodiments 1 to 5 or the transistor described in Embodiment 6 A CPU (Central Processing Unit) is implemented by using at least a part of the semiconductor memory device. ng Unit).

[0406] FIG. 19(A) is a block diagram showing a specific configuration of the CPU. The PU is provided with an arithmetic logic unit (ALU) on a board 1190. unit) 1191, ALU controller 1192, instruction decoder 11 93, interrupt controller 1194, timing controller 1195, register 1196, register controller 1197, bus interface (Bus I / F) 1 198, rewritable ROM 1199, and ROM interface (ROM I / The substrate 1190 may be a semiconductor substrate, an SOI substrate, a glass substrate, or the like. The ROM 1199 and the ROM interface 1189 are provided on separate chips. Of course, the CPU shown in FIG. 19(A) is an example in which the configuration is simplified. However, actual CPUs have a wide variety of configurations depending on their use.

[0407] The instructions input to the CPU via the bus interface 1198 are After being input to the decoder 1193 and decoded, the ALU controller 1192 Rupture controller 1194, register controller 1197, timing controller It is entered into 1195.

[0408] ALU controller 1192, interrupt controller 1194, register controller The timing controller 1197 and the timing controller 1195 control various Specifically, the ALU controller 1192 controls the operation of the ALU 1191. The interrupt controller 1194 also generates a signal for the CPU program. During execution, interrupt requests from external I / O devices and peripheral circuits are handled according to their priority and mask status. The register controller 1197 determines the address of the register 1196 and processes it. It generates a process and reads and writes register 1196 depending on the CPU state.

[0409] The timing controller 1195 controls the ALU 1191 and the ALU controller 119 2, an instruction decoder 1193, an interrupt controller 1194, and It generates a signal to control the timing of the operation of the register controller 1197. The timing controller 1195 generates an internal clock signal CLK1 based on the reference clock signal CLK1. The internal clock generator generates the clock signal CLK2. Supply to the circuit.

[0410] In the CPU shown in FIG. 19A, a register 1196 is provided with a storage element. The memory element of the starter 1196 can be the semiconductor memory device shown in the sixth embodiment. .

[0411] In the CPU shown in FIG. 19A, the register controller 1197 controls the ALU 1191 In accordance with the instruction from the register 1196, the register 1196 performs the holding operation. In the memory element, data is held by a flip-flop or a capacitor. If the data is held by a flip-flop, The power supply voltage is supplied to the storage element in the register 1196. If the data is held, the data is rewritten to the capacitor and the register 1196 The supply of power supply voltage to the memory elements in the memory cell can be stopped.

[0412] Regarding the power supply shutdown, as shown in FIG. 19(B) or 19(C), the memory element group and the power supply A switching element is installed between nodes to which the power supply potential VDD or VSS is applied. The circuits in Figures 19(B) and 19(C) are explained below. Do the following.

[0413] In FIG. 19B and FIG. 19C, a switch for controlling the supply of a power supply potential to a memory element is shown. In the case where the transistor described in any of Embodiments 1 to 5 is used as the switching element, Here is an example.

[0414] The memory device shown in FIG. 19B includes a switching element 1141 and a memory element 1142. Specifically, each of the memory elements 1142 has The semiconductor memory device described in Embodiment 6 can be used. Each of the storage elements 1142 is connected to a high level through a switching element 1141. The power supply potential VDD is supplied to the memory element group 1143. The element 1142 is supplied with the potential of the signal IN and the potential of the low-level power supply potential VSS. There are.

[0415] In FIG. 19B, a transistor with an extremely small off-state current is used as the switching element 1141. The transistor is switched by a signal SigA applied to its gate. The switching is controlled.

[0416] In FIG. 19B, the switching element 1141 has only one transistor. However, the present invention is not limited to this configuration, and a plurality of transistors may be included. In the case where the switching element 1141 has a plurality of transistors that function as switching elements, In this case, the plurality of transistors may be connected in parallel or in series. Alternatively, a combination of series and parallel connections may be used.

[0417] In addition, in FIG. 19C, each memory element 1142 included in the memory element group 1143 is A low-level power supply potential VSS is supplied via the switching element 1141. 11 shows an example of a memory device. The switching element 1141 controls the memory elements of a memory element group 1143. The supply of the low-level power supply potential VSS to each of the storage elements 1142 can be controlled. Cut.

[0418] A switch is provided between the memory element group and a node to which the power supply potential VDD or VSS is applied. When a switching element is provided and the CPU operation is temporarily stopped and the supply of power voltage is stopped, It is possible to retain data even in this state, and power consumption can be reduced. For example, a user of a personal computer may input information into an input device such as a keyboard. Even during a shutdown, the CPU can be stopped, thereby reducing power consumption. It is possible.

[0419] Here, we have taken the CPU as an example, but the same can be said for DSP (Digital Signal Processor) processor), custom LSI, FPGA (Field Programmable Gate Array) It can also be applied to LSIs such as MOS gate arrays.

[0420] This embodiment mode can be implemented in appropriate combination with any of the above embodiment modes.

[0421] (Embodiment 8) In this embodiment, an electronic device to which at least one of the first to seventh embodiments is applied An example of the device will be described.

[0422] 20(A) shows a portable information terminal. The portable information terminal shown in FIG. 20(A) has a housing 93 00, a button 9301, a microphone 9302, a display unit 9303, and a speaker 9 304 and a camera 9305, and has the function of a mobile phone. One embodiment can be applied to a computing device, a wireless circuit, or a memory circuit inside the main body.

[0423] 20B shows a display. The display shown in FIG. 20B is mounted on a housing 931. 0 and a display unit 9311. It can be applied to line circuits or memory circuits.

[0424] Fig. 20(C) shows a digital still camera. The device includes a housing 9320, a button 9321, a microphone 9322, and a display unit 9323. According to one embodiment of the present invention, a computing device, a wireless circuit, or a memory circuit is provided inside the main body. can be applied to.

[0425] FIG. 20(D) shows a foldable mobile information terminal. The portable information terminal includes a housing 9630, a display unit 9631a, a display unit 9631b, a fastener 9633, and a , and an operation switch 9638. In one embodiment of the present invention, a computing device, a wireless It can be applied to circuits or memory circuits.

[0426] Note that the display portion 9631a and / or the display portion 9631b may be partially or entirely touch panel-type. The display can be used as a panel, and data can be entered by touching the displayed operation keys. can.

[0427] By using a semiconductor device according to one embodiment of the present invention, the performance of an electronic device can be improved and power consumption can be reduced. It can be done easily.

[0428] This embodiment mode can be implemented in appropriate combination with other embodiment modes. [Explanation of symbols]

[0429] 100 boards 102 Undercoat insulating film 104 gate electrode 105 Conductive film 106 Oxide semiconductor film 106a area 106b area 107 Oxide semiconductor film 108 Barrier Film 112 Gate insulating film 116 Electrode 118 Interlayer insulating film 132 Gate insulating film 136 Wiring 150 boards 152 Undercoat insulating film 154 gate electrode 156 Silicone membrane 156a area 156b area 158 Interlayer insulating film 160 Sidewall insulating film 162 Gate insulating film 166 Electrode 168 Hydrogen-containing layer 200 boards 202 Undercoat insulating film 204 gate electrode 206 Oxide semiconductor film 207 Oxide semiconductor film 212 Gate insulating film 216 Pair of Electrodes 217 Conductive Film 218 Interlayer insulating film 236 Wiring 300 boards 302 Undercoat insulating film 304 Gate electrode 305 Conductive Film 306 Oxide semiconductor film 306a area 306b area 307 Oxide semiconductor film 310 Sidewall insulating film 312 Gate insulating film 313 Gate insulating film 316 Pair of electrodes 317 Conductive Film 318 Interlayer insulating film 319 Interlayer insulating film 320 insulating film 321 Insulating Film 322 insulating film 328 Interlayer insulating film 336 Wiring 400 boards 402 Undercoat insulating film 404 gate electrode 406 Oxide semiconductor film 407 Oxide semiconductor film 412 Gate insulating film 418 Interlayer insulating film 436 Wiring 500 boards 502 Undercoat insulating film 504 gate electrode 506 Oxide semiconductor film 512 Gate insulating film 516 Pair of electrodes 518 Interlayer insulating film 1141 Switching element 1142 Memory element 1143 Memory Element Group 1189 ROM interface 1190 PCB 1191 ALU 1192 ALU controller 1193 Instruction Decoder 1194 Interrupt Controller 1195 Timing Controller 1196 registers 1197 Register Controller 1198 Bus Interface 1199 ROM 9300 chassis 9301 Button 9302 Microphone 9303 Display section 9304 Speaker 9305 Camera 9310 chassis 9311 Display section 9320 chassis 9321 Button 9322 Microphone 9323 Display section 9630 chassis 9631a Display section 9631b Display section 9633 Fasteners 9638 Operation switch

Claims

[Claim 1] an oxide semiconductor film; a gate electrode overlapping the oxide semiconductor film; a gate insulating film provided between the gate electrode and the oxide semiconductor film, A semiconductor device having a channel length of 5 nm or more and less than 60 nm, and a channel width of 5 nm or more and less than 200 nm.

Images