Semiconductor device

Abstract

To provide a semiconductor device having a novel structure.SOLUTION: The semiconductor device includes an oxide semiconductor layer including a crystal region over an insulating surface, a source electrode layer and a drain electrode layer in contact with the oxide semiconductor layer, a gate insulating layer covering the oxide semiconductor layer, the source electrode layer, and the drain electrode layer, and a gate electrode layer over the gate insulating layer and in a region overlapping with the crystal region.SELECTED DRAWING: Figure 1

Description

[Technical Field]

[0001] The technical field of the disclosed invention relates to a semiconductor device using an oxide semiconductor and a manufacturing method thereof. Here, the semiconductor device is an element or device that functions by utilizing the semiconductor characteristics. This refers to all equipment and devices. [Background technology]

[0002] Field-effect transistors are one of the most widely used semiconductor devices. The materials used for the transistors vary depending on the application. Semiconductor materials containing ZnO are often used.

[0003] Silicon field-effect transistors meet the characteristics required for many applications. For example, single crystal silicon is used for integrated circuits that require high speed operation. This satisfies the demand. In addition, amorphous silicon is used for large area applications such as display devices. By using it, you can meet that requirement.

[0004] As such, silicon is highly versatile and can be used for a variety of purposes. There is a trend toward semiconductor materials that are more versatile and offer greater performance. From the viewpoint of improving the performance of display devices, large-scale switching elements are required to achieve high-speed operation. There is a need for semiconductor materials that can be easily scaled up and have performance that exceeds that of amorphous silicon. .

[0005] In this situation, field-effect transistors (also called FETs) using oxide semiconductors have been developed. For example, Patent Document 1 describes a technique for producing a homologous compound InM O3(ZnO)m (M=In, Fe, Ga, or Al, m=an integer of 1 or more and less than 50) A transparent thin film field effect transistor using the same is disclosed.

[0006] Patent Document 2 also describes an amorphous oxide semiconductor containing In, Ga, and Zn, which is an electron carrier. density is 10 18 / cm 3 A field effect transistor using less than In this document, the atomic ratio of the amorphous oxide semiconductor is In:Ga:Zn. =1:1:m(m<6).

[0007] Furthermore, Patent Document 3 discloses a field-effect transistor having an active layer made of an amorphous oxide semiconductor containing microcrystals. A transistor is disclosed. [Prior art documents] [Patent documents]

[0008] [Patent Document 1] Japanese Patent Application Laid-Open No. 2004-103957 [Patent Document 2] International Publication No. 05 / 088726 [Patent Document 3] Japanese Patent Application Laid-Open No. 2006-165529 Summary of the Invention [Problem to be solved by the invention]

[0009] In Patent Document 3, the composition in the crystalline state is InGaO3(ZnO) m (m=less than 6 In addition, in Example 1 of Patent Document 3, it is disclosed that InGaO3 However, the case of (ZnO)4 is disclosed. Even when they are used, the reality is that sufficient properties are not obtained.

[0010] In view of the above problems, a semiconductor device with a new structure using an oxide semiconductor layer with a new structure is provided. One of the objectives is to [Means for solving the problem]

[0011] In the disclosed invention, a semiconductor is formed using an oxide semiconductor layer that is highly purified and has a crystalline region. The crystalline region is, for example, a region that has electrical anisotropy. This is an area that prevents the intrusion of impurities.

[0012] For example, the following configuration can be adopted.

[0013] One embodiment of the disclosed invention is a semiconductor device including an oxide semiconductor layer having a crystalline region on an insulating surface and an oxide semiconductor layer. a source electrode layer and a drain electrode layer in contact with the oxide semiconductor layer; a gate insulating layer covering the gate electrode layer and the drain electrode layer, and a region on the gate insulating layer that overlaps with the crystalline region; and a gate electrode layer having a c-axis oriented in a direction substantially perpendicular to a surface of the oxide semiconductor layer. In this specification, the term "substantially perpendicular" refers to a semiconductor device having a region having oriented crystals. " refers to a state within ±10° from the vertical direction.

[0014] Another aspect of the disclosed invention is a first gate electrode layer on an insulating surface; a first gate insulating layer covering the first gate insulating layer; and an oxide semiconductor layer having a crystalline region on the first gate insulating layer. a source electrode layer and a drain electrode layer in contact with the oxide semiconductor layer; a second gate insulating layer covering the source electrode layer and the drain electrode layer; and a second gate electrode layer in a region overlapping the crystalline region, the crystalline region being an oxide semiconductor. The semiconductor device is a region having crystals whose c-axes are oriented in a direction substantially perpendicular to the surface of the semiconductor layer.

[0015] Further, a source electrode layer and a drain electrode layer are formed on the source electrode layer and the drain electrode layer. The insulating layers may have substantially the same shape. , which is used in the sense that they do not need to be strictly identical, and can be considered to be identical. For example, differences in the case of a single etching process are acceptable. Also, the thickness does not need to be the same.

[0016] In addition, a source electrode layer and a gate electrode layer using a material with low affinity for oxygen are formed in a portion in contact with the oxide semiconductor layer. The gate electrode layer may also have a drain electrode layer.

[0017] In addition, in a region other than the crystalline region of the oxide semiconductor layer (for example, a region other than the channel formation region), ) may have an amorphous structure.

[0018] The difference in height of the surface of the oxide semiconductor layer is 1 nm or more in a region overlapping with the gate electrode layer. It could be below.

[0019] Another embodiment of the disclosed invention is a method for forming an oxide semiconductor layer on an insulating surface, A conductive layer is formed on the insulating layer, and the conductive layer is etched to form a source electrode layer and a drain electrode layer. By forming a polar layer and performing heat treatment, the c-axis is aligned in a direction substantially perpendicular to the surface of the oxide semiconductor layer. and forming a crystalline region in which the oxide semiconductor layer, the source electrode layer, and the drain electrode layer are A gate insulating layer is formed to cover the crystalline region, and a gate electrode is formed in a region on the gate insulating layer that overlaps the crystalline region. The method for manufacturing a semiconductor device includes forming a pole layer.

[0020] Another embodiment of the disclosed invention is a method for forming a first gate electrode layer on an insulating surface, A first gate insulating layer is formed so as to cover the electrode layer, and an oxide semiconductor is formed on the first gate insulating layer. a conductive layer is formed over the oxide semiconductor layer, and the conductive layer is etched. The source electrode layer and the drain electrode layer are formed, and heat treatment is performed to form the oxide semiconductor A crystalline region in which the c-axis is oriented in a direction substantially perpendicular to the surface of the layer is formed, and the oxide semiconductor layer, the source electrode a second gate insulating layer is formed to cover the electrode layer and the drain electrode layer; A method for manufacturing a semiconductor device, comprising forming a second gate electrode layer in a region overlapping a crystalline region on an edge layer It is the law.

[0021] In the above, the heat treatment is carried out at a temperature of 550°C to 850°C, preferably 550°C to 750°C. The etching may be performed under the following temperature conditions: A part of the source electrode layer may be removed. An insulating layer having substantially the same shape as the drain electrode layer may be formed.

[0022] In addition, the source electrode layer and the gate electrode layer are formed by using a material with low affinity for oxygen in the portion in contact with the oxide semiconductor layer. A drain electrode layer may also be formed.

[0023] In addition, an oxide semiconductor layer having an amorphous structure is formed as the oxide semiconductor layer, and the oxide semiconductor layer other than the crystalline region is formed. A region (for example, a region other than the channel formation region) may be left as an amorphous structure.

[0024] In this specification, the terms "above" and "below" refer to the positional relationship of a component "directly above" or "below." For example, the term "gate electrode on a gate insulating layer" does not necessarily mean "directly below." If the expression "layer" is used, it excludes those that include other components between the gate insulating layer and the gate electrode layer. In addition, the terms "upper" and "lower" are merely used for the convenience of explanation, and Except where otherwise applicable, this also includes cases where the top and bottom are reversed.

[0025] In addition, the terms "electrode" and "wiring" used in this specification and the like do not limit the functionality of these components. For example, an "electrode" may be used as part of a "wiring." Furthermore, the terms "electrode" and "wiring" are used interchangeably to refer to the plural "electrodes" and "wirings." This also includes cases where the "wire" is formed as a single unit.

[0026] Also, the functions of "source" and "drain" may differ depending on whether transistors with different polarities are used or not. However, they may be swapped when the direction of current changes during circuit operation. In this specification, the terms "source" and "drain" can be used interchangeably. It shall be possible.

[0027] In this specification, "electrically connected" means "something that has some kind of electrical effect." This includes cases where the device is connected via a " is not subject to any particular restrictions as long as it enables the transmission and reception of electrical signals between connected objects.

[0028] For example, "things that have some kind of electrical action" include electrodes, wiring, and transistors. These include switching elements, resistor elements, inductors, capacitors, and other various functions. This includes elements such as [Effects of the Invention]

[0029] In the disclosed invention, a highly purified oxide semiconductor layer is used in a semiconductor device. hydrogen, which is a factor in making an oxide semiconductor n-type, must be eliminated from the oxide semiconductor layer as much as possible; Alternatively, oxygen that is insufficient in the oxide semiconductor layer is supplied to the oxide semiconductor layer, and the oxide semiconductor layer is free from oxygen deficiency. The concept includes at least one of: reducing defects that occur due to the

[0030] The purification is performed to make the oxide semiconductor layer intrinsic (i-type). Generally, it is n-type, so the off-current is high. If the off-current is high, the switching characteristics will be insufficient. Therefore, the oxide semiconductor layer is highly purified to form an i-type Or approach it.

[0031] In addition, in the disclosed invention, an oxide semiconductor layer having a crystalline region is used in a semiconductor device.

[0032] In the oxide semiconductor layer having a crystalline region with electrical anisotropy, an oxide semiconductor layer having no crystalline region is Compared to semiconductor layers, oxide semiconductor layers have different electrical properties. In an oxide semiconductor layer having a crystalline region in which the c-axis is oriented in a direction substantially perpendicular to the surface of the semiconductor layer, The conductivity in the direction parallel to the surface of the oxide semiconductor layer is improved, and the conductivity in the direction perpendicular to the surface of the oxide semiconductor layer is improved. The insulation in the direction is improved.

[0033] In this way, by using an oxide semiconductor layer having a crystalline region in a semiconductor device, electrical characteristics This makes it possible to realize a new semiconductor device with excellent properties. [Brief explanation of the drawings]

[0034] [Figure 1] 1 is a cross-sectional view illustrating a semiconductor device. [Figure 2]FIG. 10 is a cross-sectional view of a transistor including an oxide semiconductor. [Figure 3] Energy band diagram (schematic diagram) at the A-A' cross section in Figure 2. [Figure 4] (A) shows the state when a positive voltage (VG>0) is applied to the gate (GE1), and (B) shows the state when a negative voltage (VG<0) is applied to the gate (GE1). [Figure 5] A diagram showing the relationship between the vacuum level, the work function of a metal (φM), and the electron affinity of an oxide semiconductor (χ). [Figure 6] FIG. 1 is a diagram showing the energy required for hot carrier injection in silicon (Si). [Figure 7] This is a diagram showing the energy required for hot carrier injection in an In-Ga-Zn-O oxide semiconductor (IGZO). [Figure 8] FIG. 10 is a diagram showing the results of a device simulation regarding short channel effects. [Figure 9] FIG. 10 is a diagram showing the results of a device simulation regarding short channel effects. [Figure 10] A diagram showing CV (Capacitance Voltage) characteristics. [Figure 11] A graph showing the relationship between Vg and (1 / C)2. [Figure 12] 1A to 1C are cross-sectional views illustrating a manufacturing process of a semiconductor device. [Figure 13] 1A to 1C are cross-sectional views illustrating a manufacturing process of a semiconductor device. [Figure 14] 1 is a cross-sectional view illustrating a semiconductor device. [Figure 15] 1 is a cross-sectional view illustrating a semiconductor device. [Figure 16] 1A to 1C are diagrams illustrating a semiconductor device. [Figure 17] 1 is a cross-sectional view illustrating a semiconductor device. [Figure 18] 1A to 1C are cross-sectional views illustrating a manufacturing process of a semiconductor device. [Figure 19] 1A to 1C are cross-sectional views illustrating a manufacturing process of a semiconductor device. [Figure 20] 1A to 1C are cross-sectional views illustrating a manufacturing process of a semiconductor device. [Figure 21] 1 is a cross-sectional view illustrating a semiconductor device. [Figure 22] 1 is a cross-sectional view illustrating a semiconductor device. [Figure 23] 1A to 1C illustrate electronic devices using semiconductor devices. DETAILED DESCRIPTION OF THE INVENTION

[0035] An example of an embodiment of the present invention will be described below with reference to the drawings. and the present invention is not limited to the above description, and may be modified in various forms and forms without departing from the spirit and scope of the present invention. It will be readily apparent to those skilled in the art that various modifications may be made to the details. The present invention is not to be construed as being limited to the description of the embodiment shown in the accompanying drawings.

[0036] In addition, the position, size, range, etc. of each component shown in the drawings are not necessarily the same as those in the actual embodiment for ease of understanding. Therefore, the disclosed invention may not necessarily represent the actual position, size, range, etc. The position, size, range, etc. are not necessarily limited to those disclosed in the drawings, etc.

[0037] In this specification, ordinal numbers such as "first," "second," and "third" are used to avoid confusion of components. It should be noted that the numbers are added to avoid confusion and are not intended to limit the number.

[0038] (Embodiment 1) In this embodiment, a structure and a manufacturing method of a semiconductor device according to one embodiment of the disclosed invention will be described. This will be described with reference to FIGS. 1 to 16.

[0039] <Configuration of Semiconductor Device> FIG. 1 is a cross-sectional view showing a transistor 150, which is an example of the configuration of a semiconductor device. Although transistor 150 is described as being an n-type transistor, it may also be a p-type transistor. It can also be used as a

[0040] The transistor 150 is formed by an oxide semiconductor layer 101 provided over a substrate 100 with an insulating layer 102 interposed therebetween. 106a, a crystalline region 110 in the oxide semiconductor layer 106a, and the oxide semiconductor layer 106a. The source or drain electrode layer 108a and the source or drain electrode layer 108b are electrically connected to each other. The drain electrode layer 108b, the oxide semiconductor layer 106a, the source electrode layer or the drain electrode layer The gate insulating layer 108 covers the electrode layer 108a and the source or drain electrode layer 108b. 12 and a gate electrode layer 114 on a gate insulating layer 112 (see FIG. 1). 1A, a source electrode layer or drain electrode layer 108a and a source electrode layer 1B shows the case where the drain electrode layer 108b has a stacked structure. The drain electrode layer 108a and the source or drain electrode layer 108b are single layers. In the case of a single-layer structure, a good tapered shape is required. This state is easy to achieve.

[0041] Moreover, an interlayer insulating layer 116 and an interlayer insulating layer 118 are provided on the transistor 150. Note that the interlayer insulating layer 116 and the interlayer insulating layer 118 are not essential components. , may be omitted as appropriate.

[0042] The oxide semiconductor layer 106a is made of a quaternary metal oxide, In—Sn—Ga—Zn—O system. materials, and ternary metal oxide materials such as In-Ga-Zn-O and In-Sn-Zn-O In-Al-Zn-O based materials, Sn-Ga-Zn-O based materials, Al-Ga -Zn-O based materials, Sn-Al-Zn-O based materials, and binary metal oxides such as In- Zn-O based materials, Sn-Zn-O based materials, Al-Zn-O based materials, Zn-Mg-O Materials based on the system, Sn-Mg-O materials, In-Mg-O materials, and single-component metal oxides In-O based materials, Sn-O based materials, Zn-O based materials, etc. are used.

[0043] Among these, In-Ga-Zn-O oxide semiconductor materials have a sufficiently high resistance in the absence of an electric field. It is possible to sufficiently reduce the electron current and the field effect mobility is high, so it is It is suitable as a semiconductor material for use in devices.

[0044] A typical example of an In-Ga-Zn-O oxide semiconductor material is InGaO3(ZnO). m (m>0). Also, M is used instead of Ga, and InMO3(Zn O) m There are oxide semiconductor materials that are written as (m>0), where M is gallium. (Ga), aluminum (Al), iron (Fe), nickel (Ni), manganese (Mn), It refers to one or more metal elements selected from the group consisting of cobalt (Co), etc. For example, M includes Ga, Ga and Al, Ga and Fe, Ga and Ni, and Ga and Mn. The above composition is derived from the crystal structure. Please note that this is merely an example.

[0045] The oxide semiconductor layer 106a is formed by sufficiently removing impurities such as hydrogen and supplying oxygen. Specifically, the oxide semiconductor layer 106a is preferably highly purified by The hydrogen concentration is 5×10 19 / cm3 Below 5×10 18 / cm 3 Below, more hope Preferably 5 x 10 17 / cm 3 In addition, the hydrogen concentration is sufficiently reduced and oxygen is supplied. The oxide semiconductor layer 106a is purified by the addition of the impurity element. The carrier density in silicon (1×10 14 / cm 3 is sufficiently small compared to the A high carrier density value (e.g., 1×10 12 / cm 3 Less than 1.45 x 10 10 / cm 3 In this way, the i-type or substantially i-type oxide semiconductor By using such a material, the transistor 150 can be provided with excellent off-state current characteristics. For example, when the drain voltage Vd is +1V or +10V, and the gate voltage Vg is In the range of -5V to -20V, the off-state current is 1×10 -13 A or below. The hydrogen concentration in the oxide semiconductor layer 106a was measured by secondary ion mass spectrometry (SIMS). The data were measured using Daily Ion Mass Spectroscopy (DISA).

[0046] Here, the oxide semiconductor layer 106a includes a crystalline region 110. In the region including the surface of the gate insulating layer 112, that is, the region including the portion in contact with the gate insulating layer 112, Equivalent.

[0047] The crystalline region 110 has a c-axis oriented in a direction substantially perpendicular to the surface of the oxide semiconductor layer 106a. For example, the crystalline region 110 may be a region having a c-axis of an oxide semiconductor. The region may be one containing crystal grains oriented in a direction substantially perpendicular to the surface of the layer 106a. Here, "substantially perpendicular" means a state within ±10° from the perpendicular direction. The crystalline region 110 is formed in the vicinity of the surface of the oxide semiconductor layer 106a (for example, at a distance (depth) from the surface The thickness of the oxide semiconductor layer 106a may be 10 nm or less, or may be 10 nm or less. You can do that too.

[0048] Moreover, the crystalline region 110 is preferably a plate-shaped crystal (plate-shaped crystal). The crystals (plate crystals) are crystals that have developed in a planar manner and have a thin plate-like shape. The thickness of the crystalline region is preferably 2 nm or more and 10 nm or less.

[0049] Note that the oxide semiconductor layer 106a may have an amorphous structure or a non-single-crystal structure (microcrystalline structure) using any of the above materials. On the other hand, the crystalline region 110 can have any of the following structures: It is preferable that the crystal region 110 has a structure such as a non-single crystal structure. It is preferable that the crystallinity of the semiconductor layer 106a be higher than that of the other regions.

[0050] The oxide semiconductor layer 106a includes the crystalline region 110, and thus has electrical anisotropy. Given.

[0051] Note that the surface of the oxide semiconductor layer 106a is a channel formation region (a region overlapping with the gate electrode layer). It is desirable that the surface has at least a predetermined flatness in the oxide semiconductor region. The difference in height of the surface of the conductor layer 106a is 1 nm or less (preferably, The crystalline region 110 of the oxide semiconductor layer 106a is formed by polycrystal or the like. When the crystal grains are composed of a single crystal, the ab planes of adjacent crystal grains may not coincide. This means that the layers parallel to the a-axis and b-axis are displaced between the crystal grains. The existence of such a gap may reduce the electrical conductivity, so In the hole-forming region, the layers parallel to the a-axis and b-axis are preferably coincident.

[0052] As described above, the oxide semiconductor layer 106a which is highly purified and has the crystalline region 110 is By using this, a semiconductor device having good electrical characteristics can be realized.

[0053] In addition, the crystalline region 110 is more stable than other regions of the oxide semiconductor layer 106a. By forming this, impurities (such as moisture) can be prevented from entering the oxide semiconductor layer 106a. Therefore, the reliability of the oxide semiconductor layer 106a can be improved. The crystalline region 110 has a higher crystallinity than the other regions of the oxide semiconductor layer 106a. Since this region is stable, a stable transistor can be produced by using this region as the channel formation region. characteristics can be obtained.

[0054] Below, we will explain the significance of purifying oxide semiconductors and making them intrinsic (i-type), The advantages of configuring a semiconductor device using this method will be briefly described below.

[0055] <Intrinsic oxide semiconductor> There has been much research into the properties of oxide semiconductors, such as DOS (density of state). However, these studies include the idea of ​​sufficiently reducing the defect level itself. In one embodiment of the disclosed invention, water and hydrogen, which may cause an increase in DOS, are removed from an oxide semiconductor. By removing the oxide from the inside, a highly purified and intrinsic (i-type) oxide semiconductor is manufactured. This is based on the idea of ​​sufficiently reducing DOS itself. This makes it possible to manufacture extremely excellent industrial products.

[0056] When removing hydrogen and water, oxygen may also be removed at the same time. Therefore, oxygen is supplied to the dangling bonds of the metal that are generated due to oxygen deficiency, and D By reducing the OS, oxide semiconductors can be further purified and made intrinsic (i-type). For example, an oxide film containing excess oxygen is formed in close proximity to the channel forming region, and By performing heat treatment at a temperature of 0°C to 400°C, typically around 250°C, the oxide It is possible to supply oxygen from the film and reduce DOS caused by oxygen defects. During the first to third heat treatments described below, the inert gas may be replaced with a gas containing oxygen. After the first to third heat treatments, the substrate is heated in an oxygen atmosphere or in an atmosphere from which hydrogen and water have been sufficiently removed. By undergoing a temperature decreasing process in air, oxygen can be supplied into the oxide semiconductor.

[0057] The cause of deterioration in the characteristics of oxide semiconductors is excess hydrogen, which is 0.1 to 0.2 eV below the conduction band. This is thought to be due to shallow levels due to oxygen vacancies and deep levels due to oxygen vacancies. The technical idea of ​​thoroughly removing hydrogen and providing sufficient oxygen to eliminate defects is correct. It would be something like that.

[0058] Note that oxide semiconductors are generally n-type. However, in one embodiment of the disclosed invention, By removing impurities such as i and supplying oxygen, which is a constituent element of oxide semiconductors, In this respect, unlike silicon, which is made i-type by adding impurity elements, It can be said that this technology contains a technological concept that has never been seen before.

[0059] <Process advantages compared to other semiconductor materials> Semiconductor materials that can be compared to oxide semiconductors include silicon carbide (e.g., 4H-Si C). Oxide semiconductors and 4H-SiC have several things in common. The carrier density of oxide semiconductors is one example. Rear is 10 -7 / cm 3 This is estimated to be about 6.7× in 4H-SiC. 10 -11 / cm 3 This is an extremely low value, similar to the intrinsic carrier density of silicon (1.4 5×10 10 / cm 3 If you compare it to the level of Cut.

[0060] The energy band gap of oxide semiconductors is 3.0 to 3.5 eV, and 4H-S The energy band gap of iC is 3.26 eV, so it is called a wide-gap semiconductor. In this respect, oxide semiconductors and silicon carbide have in common.

[0061] On the other hand, there is a significant difference between oxide semiconductors and silicon carbide. The process temperature is 1500℃ to 2000℃. However, it is difficult to form a laminated structure with semiconductor elements using other semiconductor materials. This is because the semiconductor substrate and semiconductor elements are destroyed. It can be produced by heat treatment at 850°C or less, preferably 750°C or less. After forming an integrated circuit using a semiconductor material, a semiconductor element is formed using an oxide semiconductor. This becomes possible.

[0062] In addition, unlike silicon carbide, it is possible to use a substrate with low heat resistance, such as a glass substrate. Furthermore, compared to silicon carbide, it has the advantage that it does not require high-temperature heat treatment. This has the advantage that the energy cost can be sufficiently reduced. In silicon, crystal defects and trace impurities that are unintentionally mixed in can cause carrier generation. Therefore, theoretically, silicon carbide can have a low carrier density equivalent to that of the oxide semiconductor of the present invention. However, in reality, due to the reasons mentioned above, 12 / cm 3 A carrier density of less than The above is also true for nitride nitride, which is also known as a wide-gap semiconductor. The same can be said for the comparison of lithium and oxide semiconductors.

[0063] <Conduction mechanism of transistors using oxide semiconductors> Here, the conduction mechanism of a transistor using an oxide semiconductor will be explained with reference to FIGS. 2 to 5. In the following explanation, an ideal situation is assumed for ease of understanding. Not all of the information provided reflects the actual situation. It is noted that this is merely an inventive step and does not affect the validity of the invention.

[0064] FIG. 2 is a cross-sectional view of a transistor (thin film transistor) using an oxide semiconductor. An oxide semiconductor layer (OS) is provided on the gate electrode (GE1) via a gate insulating layer (GI). A source electrode (S) and a drain electrode (D) are provided thereon. An insulating layer is provided to cover the drain electrode (D).

[0065] FIG. 3 shows an energy band diagram (schematic diagram) in the cross section A-A' of FIG. The black circles (●) in 3 represent electrons, and the white circles (○) represent holes, each with a charge (-q, +q ) and a positive voltage (V D >0) is applied, and the dashed line indicates the gate voltage When no voltage is applied to the electrode (V G =0), the solid line indicates a positive voltage (V G >0) When no voltage is applied to the gate electrode, the high potential barrier This indicates an off state in which no carriers (electrons) are injected from the electrode to the oxide semiconductor, and no current flows. On the other hand, when a positive voltage is applied to the gate, the potential barrier decreases, and the on-state in which current flows is established. Indicates the state.

[0066] FIG. 4 shows an energy band diagram (schematic diagram) in the cross section taken along line BB' in FIG. Figure 4(A) shows the gate electrode (GE1) with a positive voltage (V G >0) is a given state, This shows the on-state where carriers (electrons) flow between the source electrode and the drain electrode. In addition, FIG. 4(B) shows a case where a negative voltage (V G <0) is applied. This shows the case where the transistor is in the off state (a state in which minority carriers do not flow).

[0067] Figure 5 shows the relationship between the vacuum level and the work function (φ M ) and the electron affinity (χ) of the oxide semiconductor. show.

[0068] At room temperature, electrons in metals are degenerate, and the Fermi level is located within the conduction band. Conventional oxide semiconductors are n-type, and their Fermi level (E F ) is located in the center of the band gap The intrinsic Fermi level (E i ) and is located closer to the conduction band. It is known that some hydrogen atoms act as donors in semiconductors, which is one of the factors that cause them to become n-type. There are.

[0069] In contrast, an oxide semiconductor according to one embodiment of the disclosed invention can convert hydrogen, which is a factor in making the oxide semiconductor n-type, into an oxide. The oxide semiconductor is made of a material that contains as few impurity elements as possible, other than the main components of the oxide semiconductor. By purifying it to such a high level, it becomes genuine (type i) or is intended to become genuine. In other words, instead of adding impurity elements to make it i-type, impurities such as hydrogen and water are removed as much as possible. By doing so, it is possible to obtain a highly purified i-type (intrinsic semiconductor) or something close to it. This results in the Fermi level (E F ) is the intrinsic Fermi level (E i ) It is possible.

[0070] The band gap (E g ) is 3.15 eV, and the electron affinity (χ) is 4.3 V It is said that the work function of titanium (Ti) that constitutes the source and drain electrodes is is approximately equal to the electron affinity (χ) of the oxide semiconductor. In this case, In this case, no Schottky barrier is formed for electrons.

[0071] At this time, the electrons are transported between the gate insulating layer and the highly purified oxide semiconductor, as shown in FIG. The electrons move near the interface with the oxide semiconductor (the lowest energetically stable part of the oxide semiconductor).

[0072] Also, as shown in FIG. 4(B), when a negative potential is applied to the gate electrode (GE1), Since the number of holes, which are carriers, is substantially zero, the current is a value that is infinitely close to zero.

[0073] In this way, high purity oxide semiconductors are used to minimize the inclusion of elements (impurity elements) other than the main components of the oxide semiconductor. By this, the gate insulating layer becomes intrinsic (i-type) or substantially intrinsic. Therefore, the gate insulating layer must have a good interface with the oxide semiconductor. Specifically, for example, power frequencies from the VHF band to the microwave band are required. Insulating layers are produced by CVD using high-density plasma generated by a large number of processes, and by sputtering. It is preferable to use an insulating layer manufactured by a method such as the above.

[0074] The oxide semiconductor is highly purified while the interface between the oxide semiconductor and the gate insulating layer is improved. For example, the channel width (W) of a transistor can be reduced to 1×10 4 μm, channel length When (L) is 3 μm, 10 -13 Off-state current of less than A, sub- A threshold swing value (S value) (gate insulating layer thickness: 100 nm) can be achieved.

[0075] In this way, the oxide semiconductor is highly oxidized so that elements other than the main components (impurity elements) are not included as much as possible. Purification can improve the operation of the transistor.

[0076] <Resistance to Hot Carrier Degradation of Transistors Using Oxide Semiconductors> Next, the resistance to hot carrier degradation of a transistor using an oxide semiconductor is discussed with reference to FIGS. 7 will be used for the following explanation. In the following explanation, an ideal situation will be assumed for ease of understanding. The following explanation is for illustrative purposes only and may not necessarily reflect the actual situation. However, I would like to add that this is just one consideration.

[0077] The main cause of hot carrier degradation is channel hot electron injection (CHE injection). and drain avalanche hot carrier injection (DAHC injection). For simplicity, only electrons are considered.

[0078] CHE injection is an injection into the semiconductor layer that has energy greater than or equal to the barrier of the gate insulating layer. This refers to the phenomenon in which electrons that have become electrons are injected into the gate insulating layer, etc. This is achieved by accelerating electrons through a low electric field.

[0079] DAHC injection is a method in which new electrons generated by the collision of electrons accelerated by a high electric field are injected into the gate. The difference between DAHC injection and CHE injection is that the impact ions The question is whether or not avalanche breakdown occurs due to the breakdown of the semiconductor. Electrons with kinetic energy greater than the band gap are required.

[0080] Figures 6 and 7 show the structure of silicon (Si) and In-Ga-Zn-O oxide semiconductor (IGZ). The energy required for various hot carrier injections estimated from the band structure of the SiO2 / SiO2 system is shown in Fig. 6 and 7, the left side represents CHE injection and the right side represents DAHC injection.

[0081] In silicon, the degradation caused by DAHC implantation is more severe than that caused by CHE implantation. This is because the band gap of silicon is small and avalanche breakdown occurs easily. Since only a small number of carriers (e.g., electrons) are accelerated without collisions in the electron chamber, Although the probability of CHE injection due to this is low, the gate insulating layer is As the number of electrons that can cross the barrier increases, the number of electrons injected into the gate insulating layer This is because it will increase.

[0082] In the case of In-Ga-Zn-O oxide semiconductors, the energy required for CHE injection is silicon The energy required for DAHC injection is not significantly different from that in the case of Therefore, the required energy for CHE injection is about the same as that for DAHC injection. stomach.

[0083] On the other hand, just like silicon, only a small number of carriers (e.g., electrons) are accelerated without collisions. Therefore, the probability of CHE injection is low. Therefore, it has high resistance to carrier degradation.

[0084] <Short-Channel Effect in Transistors Using Oxide Semiconductors> Next, regarding the short-channel effect in a transistor using an oxide semiconductor, FIGS. 8 and 9 are described. 9 will be used for the following explanation. In the following explanation, an ideal situation will be assumed for ease of understanding. The following explanation is for illustrative purposes only and may not necessarily reflect the actual situation. However, I would like to add that this is just one consideration.

[0085] The short channel effect becomes apparent as transistors become smaller (reduced channel length (L)). The short channel effect is a degradation of electrical characteristics caused by the drain effect extending to the source. Specific examples of short channel effects include a decrease in threshold voltage and an S value. Increased current and leakage current.

[0086] Here, a device simulation is used to determine a structure that can suppress short channel effects. Specifically, we investigated the structure of the oxide semiconductor layer by varying the carrier density and the thickness of the oxide semiconductor layer. Four types of models were prepared to confirm the relationship between channel length (L) and threshold voltage (Vth). The model used a bottom-gate transistor with a carrier density of 1. 7×10 -8 / cm 3 , or 1.0 × 10 15 / cm 3 and an oxide semiconductor. The thickness of the layer was set to either 1 μm or 30 nm. A Ga-Zn-O oxide semiconductor is used as the gate insulating layer, and a 100 nm thick silicon oxynitride layer is used as the gate insulating layer. A bare membrane was used.

[0087] There is no significant difference in the calculation results between the top gate structure and the bottom gate structure.

[0088] The calculation results are shown in Figures 8 and 9. Figure 8 shows the results for a carrier density of 1.7 × 10 -8 / cm 3 of In this case, the carrier density is 1.0×10 15 / cm 3 This is the case. In a transistor using an oxide semiconductor, by reducing the thickness of the oxide semiconductor layer, This shows that the short channel effect can be suppressed. For example, when the channel length is about 1 μm, In this case, even if the oxide semiconductor layer has a sufficiently low carrier density, its thickness is 3 nm to 5 nm. If the thickness is about 0 nm, preferably about 3 nm to 20 nm, the short channel effect can be sufficiently suppressed. It is understood that this is possible.

[0089] <Carrier density in oxide semiconductors> One of the technical ideas of the disclosed invention is to make the carrier density in the oxide semiconductor layer sufficiently small. The aim is to obtain the intrinsic (i-type) state as close as possible. The method of forming the oxide semiconductor layer and the carrier density measured in the oxide semiconductor layer are shown in FIGS. This will be explained with reference to 1.

[0090] The carrier density in the oxide semiconductor layer was measured by fabricating a MOS capacitor using the oxide semiconductor layer. , CV measurement of the MOS capacitor (Capacitance Voltage Mea This can be determined by evaluating the results (CV characteristics) of the confirmation test.

[0091] Carrier density is measured by the following steps (1)-(3): (1) MOS capacitor gate (2) Obtain the CV characteristics by plotting the relationship between the gate voltage Vg and the capacitance C. From the V characteristics, the gate voltage Vg and (1 / C) 2 and obtain a graph that shows the relationship between In the weak inversion region, (1 / C) 2 (3) The obtained differential value is Rear Density N d In equation (1), e is the elementary charge. , ε0 is the dielectric constant of a vacuum, and ε is the relative dielectric constant of the oxide semiconductor.

[0092]

number

[0093] As a sample for measurement, a MOS capacitor having the following structure was used. MOS capacitor structure: A 300 nm thick titanium layer is formed on a glass substrate. A 100 nm thick titanium nitride layer is formed on the surface of the substrate, and an In-Ga-Zn-O system is deposited on the titanium nitride layer. The oxide semiconductor layer is 2 μm thick and uses an oxide semiconductor (a-IGZO). A 300 nm thick silicon oxynitride layer is formed on the semiconductor layer, and a 300 nm thick silver layer is formed on the silicon oxynitride layer. It has layers.

[0094] The oxide semiconductor layer was formed using a target for forming an oxide semiconductor film containing In, Ga, and Zn. (In:Ga:Zn=1:1:0.5 [atomic ratio]) by sputtering method The oxide semiconductor layer was formed in a mixed atmosphere of argon and oxygen (flow ratio: The gas flow rate was Ar:O2=30(sccm):15(sccm).

[0095] Figure 10 shows the CV characteristics, and Figure 11 shows the relationship between Vg and (1 / C) 2 The relationship between these is shown in the figure. (1 / C) in the weak inversion region of 11 2 The carrier obtained from the differential value of The density is 6.0 x 10 10 / cm 3 It was.

[0096] In this way, an oxide semiconductor that has been made i-type or substantially i-type (for example, an oxide semiconductor having a carrier density of 1×10 12 / cm 3 less than 1.45 x 10 10 / cm 3 (less than) By using such a gate insulating film, a transistor with excellent off-state current characteristics can be obtained.

[0097] As described above, by using an oxide semiconductor, in particular, a highly purified and intrinsic oxide semiconductor, It is understood that various effects can be obtained. By realizing a crystalline structure of an oxide semiconductor layer, a new semiconductor device with excellent characteristics can be developed. The placement is realized.

[0098] <Method for manufacturing semiconductor device> Next, a method for manufacturing a transistor 150, which is an example of a semiconductor device, will be described with reference to FIGS. This will be described with reference to FIG.

[0099] First, an insulating layer 102 is formed on a substrate 100. Then, an oxide semiconductor is formed on the insulating layer 102. Then, the body layer 106 is formed (see FIG. 12(A)).

[0100] The substrate 100 may be any substrate having an insulating surface, and may be, for example, a glass substrate. The glass substrate is preferably an alkali-free glass substrate. Examples of the glass include aluminosilicate glass, aluminoborosilicate glass, and barium borate glass. The substrate 100 may be a glass material such as silicon dioxide glass. Insulating substrates made of insulators such as quartz substrates and sapphire substrates, and semiconductor substrates made of silicon and other semiconductor materials. The surface of a semiconductor substrate is covered with an insulating material, and the conductive material is made of a conductor such as metal or stainless steel. The surface of the substrate may be covered with an insulating material.

[0101] The insulating layer 102 functions as a base and is formed by using a CVD method, a sputtering method, or the like. The insulating layer 102 can be formed using silicon oxide, silicon nitride, silicon oxynitride, or nitride. The film is formed to contain silicon oxide, aluminum oxide, hafnium oxide, tantalum oxide, etc. The insulating layer 102 may have a single-layer structure or a stacked-layer structure. The thickness of the insulating layer 102 is not particularly limited, but is, for example, 10 nm or more and 500 nm or less. Here, the insulating layer 102 is not an essential component, so the insulating layer 10 It is also possible to configure the system without providing 2.

[0102] If the insulating layer 102 contains hydrogen, water, or the like, hydrogen may enter the oxide semiconductor layer or water may be released from the insulating layer 102. The oxygen in the oxide semiconductor layer is extracted by the hydrogen, which deteriorates the characteristics of the transistor. Therefore, the insulating layer 102 is formed so as to contain as little hydrogen and water as possible. It is desirable.

[0103] For example, when using a sputtering method, remove any remaining moisture in the processing chamber. It is desirable to form an insulating layer 102. In addition, in order to remove residual moisture in the processing chamber, Adsorption type vacuum pumps such as cryopumps, ion pumps, and titanium sublimation pumps It is preferable to use a pump. A turbo pump with a cold trap is used. The processing chamber is evacuated using a cryopump or the like to ensure that hydrogen, water, etc. are sufficiently removed. Therefore, the concentration of impurities contained in the insulating layer 102 can be reduced.

[0104] Furthermore, when forming the insulating layer 102, impurities such as hydrogen and water are preferably present at a concentration of about ppm (preferably It is desirable to use a high purity gas with a concentration reduced to about ppb.

[0105] The oxide semiconductor layer 106 is made of a quaternary metal oxide material, In—Sn—Ga—Zn—O. and ternary metal oxide materials such as In-Ga-Zn-O and In-Sn-Zn-O. Materials, In-Al-Zn-O based materials, Sn-Ga-Zn-O based materials, Al-Ga-Z nO-based materials, Sn-Al-Zn-O-based materials, and binary metal oxides such as In-Zn -O based materials, Sn-Zn-O based materials, Al-Zn-O based materials, Zn-Mg-O based materials Materials, Sn-Mg-O based materials, In-Mg-O based materials, and single-component metal oxides, I It can be formed using Sn-O based materials, Sn-O based materials, Zn-O based materials, etc. do.

[0106] Among these, In-Ga-Zn-O oxide semiconductor materials have a sufficiently high resistance in the absence of an electric field. It is possible to sufficiently reduce the electron current and the field effect mobility is high, so it is It is suitable as a semiconductor material for use in devices.

[0107] A typical example of an In-Ga-Zn-O oxide semiconductor material is InGaO3(ZnO). m (m>0). Also, M is used instead of Ga, and InMO3(Zn O) m There are oxide semiconductor materials that are written as (m>0), where M is gallium. (Ga), aluminum (Al), iron (Fe), nickel (Ni), manganese (Mn), It refers to one or more metal elements selected from the group consisting of cobalt (Co), etc. For example, M includes Ga, Ga and Al, Ga and Fe, Ga and Ni, and Ga and Mn. The above composition is derived from the crystal structure. Please note that this is merely an example.

[0108] In this embodiment, the oxide semiconductor layer 106 is an In—Ga—Zn—O-based oxide semiconductor. An amorphous oxide semiconductor layer is formed by a sputtering method using a film formation target. do.

[0109] Examples of targets for forming the oxide semiconductor layer 106 by a sputtering method include: A metal oxide target containing zinc oxide as the main component can be used. The composition ratio of the oxide semiconductor film formation target containing Ga and Zn is In:Ga:Zn= The formula is 1:x:y (x is 0 or more and 2 or less, y is 1 or more and 5 or less). For example, In:Ga:Zn =1:1:1 [atom ratio] (x=1, y=1), (i.e., In2O3:Ga2O3 A target having a composition ratio of ZnO=1:1:2 (molar ratio) may also be used. In addition, the oxide semiconductor film deposition target was In:Ga:Zn=1:1:0.5 [at om ratio] or In:Ga:Zn=1:1:2 [atom The composition ratio is In:Ga:Zn=1:0:1 (x=0, y=1). In this embodiment, a target that is intentionally oxidized by subsequently performing a heat treatment is used. In order to crystallize the oxide semiconductor layer, an oxide semiconductor layer that is likely to crystallize is used. It is preferable to use a target for forming a semiconductor film.

[0110] The relative density of the oxide semiconductor in the oxide semiconductor film formation target is 80% or more, preferably 90% or more. 5% or more, more preferably 99.9% or more. For forming oxide semiconductor films with high relative density By using a target, it is possible to form an oxide semiconductor layer with a dense structure. .

[0111] The oxide semiconductor layer 106 is formed in a rare gas (typically, argon) atmosphere or an oxygen atmosphere. It is preferable to use a mixed atmosphere of oxygen or a rare gas (typically argon) and oxygen. Specifically, impurities such as hydrogen, water, hydroxyl groups, and hydrides are present at concentrations of about several ppm. It is preferable to use a high-purity gas atmosphere in which the concentration has been reduced to a level of about several ppb. be.

[0112] When the oxide semiconductor layer 106 is formed, for example, the substrate is placed in a processing chamber maintained in a reduced pressure state. The substrate temperature is maintained at 100°C or higher and 600°C or lower, preferably 200°C or higher and 400°C or lower. Then, the sputtering gas from which hydrogen and water have been removed while removing the remaining moisture in the processing chamber. The oxide semiconductor layer 106 is formed by introducing a metal oxide as a target. By forming the oxide semiconductor layer 106 while This reduces the amount of impurities and also reduces damage caused by sputtering. To remove the residual moisture, it is preferable to use an adsorption type vacuum pump. For example, Cryopumps, ion pumps, titanium sublimation pumps, etc. can be used. Alternatively, a turbo pump with a cold trap may be used. The treatment chamber is evacuated using a vacuum pump, and hydrogen, water, etc. are removed from the treatment chamber. The impurity concentration of 6 can be reduced.

[0113] The oxide semiconductor layer 106 is formed under the following conditions: the distance between the substrate and the target is 1 70 mm, pressure 0.4 Pa, direct current (DC) power 0.5 kW, atmosphere oxygen (oxygen 10 0%) atmosphere, or argon (100% argon) atmosphere, or a mixture of oxygen and argon It is possible to apply conditions such as a mixed atmosphere. This reduces dust (powder or flake-like material formed during film formation) and improves film thickness distribution. The thickness of the oxide semiconductor layer 106 is preferably greater than or equal to 2 nm and less than or equal to 200 nm. However, depending on the oxide semiconductor material and application, the thickness is preferably 5 nm or more and 30 nm or less. The appropriate thickness varies depending on the material and application. That's fine.

[0114] Before the oxide semiconductor layer 106 was formed by a sputtering method, argon gas was introduced. The deposition on the surface of the insulating layer 102 is removed by reverse sputtering, which generates plasma. Here, the reverse sputtering is a method of sputtering a sputter target in a normal sputtering. On the other hand, by bombarding the surface with ions, the surface is This refers to a method of modifying the surface. The method of bombarding the treated surface with ions is called argon bombardment. A method of applying a high frequency voltage to the surface to be treated in an atmosphere to generate plasma near the substrate. In addition, an atmosphere of nitrogen, helium, oxygen, etc. may be used instead of the argon atmosphere. That's fine.

[0115] Next, the oxide semiconductor layer 106 is processed by a method such as etching using a mask. An island-shaped oxide semiconductor layer 106a is formed (see FIG. 12B).

[0116] The oxide semiconductor layer can be etched by either dry etching or wet etching. Of course, both of them can be used in combination. The etching conditions (etching gas, etc.) can be adjusted to suit the material so that the desired shape can be etched. The etching solution, etching time, temperature, etc. are set appropriately.

[0117] As dry etching, parallel plate type RIE (Reactive Ion Etching) ng) method and ICP (Inductively Coupled Plasma) In this case, the etching conditions are (The amount of power applied to the coil-type electrode, the amount of power applied to the substrate-side electrode, the amount of power applied to the substrate-side electrode Temperature, etc. must be set appropriately.

[0118] Etching gases that can be used for dry etching include, for example, chlorine-containing gases ( Chlorine-based gases, such as chlorine (Cl2), boron trichloride (BCl3), silicon tetrachloride (SiCl4 ), carbon tetrachloride (CCl4), etc. Also, gases containing fluorine (fluorine-based gases) , such as carbon tetrafluoride (CF4), sulfur hexafluoride (SF6), nitrogen trifluoride (NF3), trifluoride Fluoromethane (CHF3), hydrogen bromide (HBr), oxygen (O2), and A gas containing a rare gas such as helium (He) or argon (Ar) may also be used. .

[0119] The etching solution that can be used for wet etching is a mixture of phosphoric acid, acetic acid, and nitric acid. Ammonia solution, hydrogen peroxide solution (31% by weight: 28% by weight ammonia solution, 5% by weight ammonia solution) :2:2) and other etching solutions such as ITO07N (Kanto Chemical Co., Ltd.) are also available. That's fine.

[0120] After that, the oxide semiconductor layer 106a is preferably subjected to heat treatment (first heat treatment). By the first heat treatment, water (including a hydroxyl group) and hydrogen in the oxide semiconductor layer 106a are removed. The temperature of the first heat treatment is, for example, 300° C. or higher and lower than 550° C. Preferably, the temperature can be 400° C. or higher and lower than 550° C. The second heat treatment (heat treatment for forming a crystalline region) may also be performed. The temperature of the heat treatment is preferably 550°C or higher and 850°C or lower.

[0121] The heat treatment is carried out by, for example, placing the substrate 100 in an electric furnace using a resistance heating element, and heating the substrate 100 in a nitrogen atmosphere. The oxide semiconductor layer 106a is heated in the atmosphere for 1 hour at 450° C. Do not allow it to come into contact with water or hydrogen.

[0122] Heat treatment equipment is not limited to electric furnaces, and may be heat conduction or heat radiation from a medium such as heated gas. For example, a GRTA (Gas Rap id Thermal Anneal) equipment, LRTA (Lamp Rapid The RTA (Rapid Thermal Anneal) equipment ) equipment can be used. The LRTA equipment uses halogen lamps, metal halide lamps, etc. , xenon arc lamp, carbon arc lamp, high-pressure sodium lamp, high-pressure mercury lamp This is a device that heats the workpiece by radiating light (electromagnetic waves) emitted from a lamp such as a lamp. The GRTA device is a device that performs heat treatment using high-temperature gas. The gas used is argon. or an inert gas such as nitrogen that does not react with the material to be treated by heat treatment. It is used.

[0123] For example, as the first heat treatment, the substrate is placed in an inert gas atmosphere heated to a high temperature of 650°C to 700°C. GRTA process involves placing a substrate in the chamber, heating it for a few minutes, and then removing the substrate from the inert gas atmosphere. GRTA treatment allows high-temperature heat treatment in a short time. Because it is a long-term heat treatment, it can be applied even to temperature conditions that exceed the heat resistance temperature of the substrate. For example, when using a glass substrate, the substrate may shrink at temperatures exceeding the heat resistance temperature (distortion point). However, this is not a problem if the heat treatment is performed for a short time. Alternatively, the inert gas may be replaced with a gas containing oxygen. This is because the heat treatment can reduce defects caused by oxygen deficiency.

[0124] The inert gas atmosphere is nitrogen or a rare gas (helium, neon, argon, etc.). It is desirable to use an atmosphere containing ) as the main component and not containing water, hydrogen, etc. For example, nitrogen and rare gases such as helium, neon, and argon introduced into a heat treatment device Purity should be 6N (99.9999%) or higher, preferably 7N (99.99999%) or higher ( That is, the impurity concentration is set to 1 ppm or less, preferably 0.1 ppm or less.

[0125] In any case, the first heat treatment reduces impurities and makes the silicon nitride into an i-type or substantially i-type. By forming the oxide semiconductor layer 106a, the transistor 150 can have excellent characteristics. This can be achieved.

[0126] The first heat treatment is performed on the oxide semiconductor layer 106 before it is processed into the island-shaped oxide semiconductor layer 106a. In this case, the substrate 100 is removed from the heating device after the first heat treatment. The wafer is then taken out and subjected to a photolithography process.

[0127] The first heat treatment has the effect of removing hydrogen and water, so the first heat treatment is called dehydration treatment. The dehydration treatment or the dehydrogenation treatment may be called hydrogenation treatment or the like. After the formation of the oxide semiconductor layer 106a, a source electrode layer or a drain electrode layer was stacked on the oxide semiconductor layer 106a. After forming the gate insulating layer on the source electrode layer or the drain electrode layer, In addition, such dehydration and dehydrogenation treatments can be carried out in a single process. This may be done multiple times.

[0128] Next, the conductive layer 108 is formed in contact with the oxide semiconductor layer 106a (see FIG. 12C). (see).

[0129] The conductive layer 108 is formed by a PVD method such as a sputtering method, or a CVD method such as a plasma CVD method. The conductive layer 108 can be formed using a method such as a metal thin film deposition (MgSO 4 ) or a metal thin film deposition (MgSO 4 ). An element selected from tantalum, titanium, molybdenum, and tungsten, or the above-mentioned elements It can be formed using alloys containing manganese, magnesium, zirconium, etc. Alternatively, a material containing one or more of aluminum and beryllium may be used. Titanium, tantalum, tungsten, molybdenum, chromium, neodymium, scandium Alternatively, a material containing one or more elements selected from the above may be used.

[0130] The conductive layer 108 may be formed using a conductive metal oxide. Materials include indium oxide (In2O3), tin oxide (SnO2), and zinc oxide (ZnO). , indium oxide tin oxide alloy (In2O3-SnO2, sometimes abbreviated as ITO) , indium oxide zinc oxide alloy (In2O3-ZnO), or these metal oxide materials The material may contain silicon or silicon oxide.

[0131] The conductive layer 108 may have a single-layer structure or a stacked structure of two or more layers. A three-layer structure in which an aluminum film is laminated on a titanium film, and a titanium film is laminated on the aluminum film. A layer structure, such as a molybdenum film on which an aluminum film is stacked and a molybdenum film on which an aluminum film is stacked, A three-layer laminate structure in which an aluminum film and a tungsten film are laminated can also be applied. Two-layer laminated structure with copper film and tungsten film, two-layer laminated structure with aluminum film It is also possible to use a two-layer structure in which a tungsten film and a molybdenum film are laminated. In the case of a single layer structure, for example, a single layer of titanium film If a single layer structure of titanium film is used, it is possible to obtain a good result during subsequent etching. In this example, the titanium film and the aluminum film are etched to form a tapered shape. A three-layer structure consisting of an aluminum film and a titanium film will be applied.

[0132] Note that a portion of the conductive layer 108 in contact with the oxide semiconductor layer 106a has an oxygen-removing effect. Materials with low affinity for oxygen (materials with low affinity for oxygen) may be used. For example, titanium nitride, tungsten nitride, platinum, etc. The structure of the conductive layer 108 is the same as that described above. Similarly, the conductive layer 108 may have a single layer structure or a stacked layer structure. For example, a two-layer structure of a titanium nitride film and a titanium film, a two-layer structure of a titanium nitride film and a tungsten film, Two-layer structure of titanium nitride film and copper-molybdenum alloy film, tantalum nitride film and tungsten film two-layer structure of tantalum nitride film and copper film, two-layer structure of titanium nitride film, tungsten film and titanium A three-layer structure of the membrane, etc. can be adopted.

[0133] By using a material with a low oxygen-extracting effect as described above for the conductive layer 108, the oxygen-extracting effect can be reduced. Prevents the oxide semiconductor layer from becoming n-type due to removal, and prevents transistors caused by uneven n-type The adverse effects on the characteristics can be suppressed.

[0134] As mentioned above, a material with high barrier properties such as a titanium nitride film or a tantalum nitride film is used as an oxide film. By using the insulating film in the portion in contact with the oxide semiconductor layer 106a, the intrusion of impurities into the oxide semiconductor layer 106a can be prevented. This suppresses the adverse effects on transistor characteristics.

[0135] Next, the conductive layer 108 is selectively etched to form the source or drain electrode layer 10 8a, a source electrode layer or a drain electrode layer 108b is formed (see FIG. 12(D)). An insulating layer is formed on the conductive layer 108, and the insulating layer is etched to form a source electrode layer or On the drain electrode layer, an insulating layer having substantially the same shape as the source electrode layer and the drain electrode layer is formed. In this case, the gate electrode layer may be formed by a source electrode layer or a drain electrode layer. The capacitance (so-called gate capacitance) can be reduced. It is used with the intention that it is not necessary for the two to be identical, and the range in which they can be considered identical is For example, differences in the case where the layers are formed by a single etching process are allowed. Furthermore, the thickness does not need to be the same.

[0136] For the exposure when forming the mask used for etching, ultraviolet rays, KrF laser light, or ArF laser light are used. It is preferable to use the following. In particular, when performing exposure with a channel length (L) of less than 25 nm, Extreme ultraviolet rays have extremely short wavelengths ranging from a few nm to a few tens of nm. It is preferable to use ultraviolet light to expose the mask. Therefore, the channel length (L) of the transistor to be formed later can be It is also possible to make the channel length 10 nm or more and 1000 nm or less. By reducing the thickness, the operating speed can be improved. The transistors used have a small off-state current, which helps prevent increases in power consumption due to miniaturization. Cut.

[0137] When the conductive layer 108 is etched, the oxide semiconductor layer 106a is not removed. The materials and etching conditions are adjusted as appropriate. Therefore, in this step, a part of the oxide semiconductor layer 106a is etched, and the groove portion ( In some cases, the oxide semiconductor layer may have a recess.

[0138] In order to reduce the number of masks used and the number of processes, an exposure method is used in which the transmitted light has multiple intensities. A resist mask is formed using a multi-tone mask, which is a mask, and an etching process is performed using this. The resist mask formed using the multi-tone mask has a plurality of thicknesses. The shape becomes stepped, and the shape can be further deformed by ashing. It can be used for multiple etching processes. It is possible to form resist masks corresponding to at least two different patterns. This reduces the number of exposure masks and the corresponding photolithography process. This allows for simplification of the process.

[0139] Next, the oxide semiconductor layer 106a is subjected to heat treatment (second heat treatment). As a result, a crystalline region 110 is formed in a region including the surface of the oxide semiconductor layer 106a (FIG. 1). 3(A)). Note that the range of the crystalline region 110 is the same as that of the oxide semiconductor layer 106a. The thickness of the oxide semiconductor layer 106a may vary depending on the material and the conditions of the heat treatment. It is also possible to form the crystalline region 110 up to the lower interface.

[0140] The second heat treatment can be the same as the first heat treatment. Heat treatment using an electric furnace, heat treatment using heat conduction from a medium such as heated gas, heat radiation Heat treatment by irradiation or the like can be applied.

[0141] However, it is desirable that the treatment atmosphere does not contain oxygen. If the source electrode layer or the drain electrode layer 108a or the like is not present, oxidation of the source electrode layer or the drain electrode layer 108a or the like can be suppressed. A specific example of the atmosphere is an atmosphere from which hydrogen and water have been sufficiently removed. An inert gas (nitrogen, rare gas, etc.) atmosphere can be used. The temperature conditions are 5 The temperature is 50°C or higher and 850°C or lower, preferably 550°C or higher and 750°C or lower. This is because the second heat treatment can grow good crystals under the optimum conditions. be.

[0142] Although there is no essential requirement for the present invention regarding the upper limit of the heat treatment temperature, If the heat resistance is low, the upper limit of the heat treatment temperature must be set within the range of the heat resistance.

[0143] When GRTA treatment is applied, the heat treatment time is preferably 1 minute or more and 100 minutes or less. For example, it is recommended to carry out GRTA treatment at 650°C for about 3 to 6 minutes. By applying the GRTA treatment, the heat treatment can be performed in a short time, so that the substrate 100 In other words, compared to when heat treatment is performed for a long time, In addition, the upper limit of the heat treatment temperature can be increased. It is easy to form the crystalline region 110 in the region including the plane.

[0144] In the second heat treatment, it is desirable that the treatment atmosphere does not contain hydrogen (including water). For example, the purity of the inert gas introduced into the heat treatment device is set to 6N (99.9999%, i.e., no impurities). The impurity concentration is 1 ppm or less), preferably 7N (99.99999%, i.e., impurity concentration In addition, hydrogen (including water) may be used instead of inert gas. Sufficiently reduced oxygen gas, N2O gas, ultra-dry air (dew point below -40°C, preferably - 60°C or less) may also be used.

[0145] Note that the second heat treatment can be performed at any timing after the oxide semiconductor layer 106 is formed. Therefore, for example, a heat treatment that serves as both the first heat treatment and the second heat treatment may be performed. In this case, only one of the first heat treatment and the second heat treatment is performed. The second heat treatment may be carried out not only once but also multiple times.

[0146] In the crystalline region 110 thus formed, the c-axis of the oxide semiconductor crystal is oriented in the oxidized state. The orientation is such that the orientation is substantially perpendicular to the surface of the compound semiconductor layer. This refers to a state within ±10° from the perpendicular direction.

[0147] For example, an In—Ga—Zn—O-based oxide semiconductor material is used for the oxide semiconductor layer 106a. In this case, the crystalline region 110 is InGaO3(ZnO) m (m: integer) and I Such crystals may include crystals represented by n2Ga2ZnO7. Therefore, the c-axis is oriented in a direction substantially perpendicular to the surface of the oxide semiconductor layer 106a. do.

[0148] Here, the above-mentioned crystal contains any one of In, Ga, and Zn, and has an a-axis and It can be understood as a stacked structure of layers parallel to the a-axis and b-axis. In general, the crystals described above are composed of layers containing In and layers not containing In (Ga or The layer has a structure in which layers containing Zn or Zn are stacked in the c-axis direction.

[0149] In the In-Ga-Zn-O oxide semiconductor crystal, the a-axis and The conductivity in the direction parallel to the b-axis is good. In semiconductor crystals, electrical conduction is mainly controlled by In, and The 5s orbital of In overlaps with the 5s orbital of the adjacent In, forming a carrier path. On the other hand, in the direction perpendicular to the layer (i.e., the c-axis direction), , the insulation properties are improved.

[0150] The oxide semiconductor layer 106a includes the crystalline region 110, and thus has electrical anisotropy. In the above example, the conductivity in the direction parallel to the surface of the oxide semiconductor layer 106a is increased. On the other hand, the insulating properties are improved in the direction perpendicular to the surface of the oxide semiconductor layer 106a. Therefore, by using the oxide semiconductor layer 106a having such a crystalline region 110, Therefore, a semiconductor device having excellent electrical characteristics can be realized.

[0151] In addition, when an amorphous structure or the like is to remain below the crystalline region 110, the crystalline region 110 is This is preferable because the flowing carriers are not affected by the interface with the insulating layer 102 .

[0152] Next, the gate insulating layer 106a was removed from the oxide semiconductor layer 106a without exposing it to the air. The gate insulating layer 112 is formed by a CVD method or a sputtering method (see FIG. 13(B)). The gate insulating layer 112 can be formed by a deposition method or the like. Silicon, silicon oxynitride, silicon nitride oxide, aluminum oxide, hafnium oxide, tantalum oxide The gate insulating layer 112 is preferably formed to include a single layer structure. The thickness of the gate insulating layer 112 is not particularly limited, but For example, it can be set to 10 nm or more and 500 nm or less.

[0153] Note that an oxide semiconductor that has been made i-type or substantially i-type by removing impurities or the like is (Highly purified oxide semiconductors) are extremely sensitive to interface states and interface charges. Therefore, high quality is required for the gate insulating layer 112.

[0154] For example, high density plasma CVD using microwaves (e.g., 2.45 GHz) can This is advantageous in that it allows the formation of a high-quality gate insulating layer 112 that is dense and has a high dielectric strength. The oxide semiconductor layer and the high-quality gate insulating layer are in close contact with each other, reducing the interface state density. This is because it is possible to improve the interface characteristics.

[0155] Of course, if a good insulating layer can be formed as the gate insulating layer 112, sputtering is also possible. It is also possible to apply other methods such as a coating method or a plasma CVD method. An insulating layer whose film quality or interface characteristics are modified by treatment may also be applied. In addition, the quality of the gate insulating layer 112 is good and the interface state with the oxide semiconductor layer is low. It is sufficient to provide a material that can reduce density and form a good interface.

[0156] In this way, the interface characteristics with the gate insulating layer 112 are improved, and impurities in the oxide semiconductor are removed. By excluding substances, especially hydrogen and water, the gate bias and thermal stress test (BT test: For example, at 85°C, 2 x 10 6 V / cm, 12 hours, etc.), the threshold voltage (Vt It is possible to obtain a stable transistor in which h) does not fluctuate.

[0157] Thereafter, it is desirable to carry out a third heat treatment in an inert gas atmosphere or an oxygen atmosphere. The temperature of the heat treatment is 200°C or higher and 400°C or lower, preferably 250°C or higher and 350°C or lower. For example, heat treatment may be performed at 250°C for 1 hour in a nitrogen atmosphere. By using the third heat treatment, it is possible to reduce variations in the electrical characteristics of the transistors. It is also possible to supply oxygen to the oxide semiconductor layer 106a depending on the oxide semiconductor layer 106a. When the purpose is to supply oxygen to the semiconductor layer 106a, a silicon dioxide film is used as the gate insulating layer 112. After forming the silicon oxide film by the quartz crystal deposition method, it is preferable to perform the third heat treatment described above. be.

[0158] In this embodiment, the third heat treatment is performed after the gate insulating layer 112 is formed. The timing of the third heat treatment is not particularly limited as long as it is performed after the second heat treatment. The heat treatment is not an essential step.

[0159] Next, a region overlapping with the oxide semiconductor layer 106a (particularly, a crystalline region) on the gate insulating layer 112 is A gate electrode layer 114 is formed in the region overlapping with the gate electrode 110 (see FIG. 13(C)). The electrode layer 114 is formed by selectively removing a conductive layer formed on the gate insulating layer 112. It can be formed by patterning.

[0160] The conductive layer can be formed by a PVD method such as a sputtering method or a CVD method such as a plasma CVD method. The conductive layer can be formed using aluminum, chromium, copper, or tantalum. , titanium, molybdenum, tungsten, or a material containing the above elements. It can be formed using alloys containing manganese, magnesium, zirconium, beryl Alternatively, a material containing titanium or a combination of titanium and aluminum may be used. selected from the group consisting of tantalum, tungsten, molybdenum, chromium, neodymium, and scandium A material containing one or more of the above elements may also be used.

[0161] The conductive layer may be formed using a conductive metal oxide. Indium oxide (In2O3), tin oxide (SnO2), zinc oxide (ZnO), Indium tin oxide alloy (In2O3-SnO2, sometimes abbreviated as ITO), oxide Indium-zinc oxide alloy (In2O3-ZnO), or these metal oxide materials It is possible to use a material containing silicon or silicon oxide.

[0162] The conductive layer may have a single layer structure or a laminated structure of two or more layers. Single layer structure of aluminum film containing titanium, and two layer structure of titanium film laminated on aluminum film. and a three-layer structure in which a titanium film, an aluminum film and another titanium film are laminated. Here, a conductive layer is formed using a material containing titanium and processed into the gate electrode layer 114 .

[0163] Next, an interlayer insulating layer 116 and an interlayer insulating layer 117 are formed on the gate insulating layer 112 and the gate electrode layer 114. An insulating layer 118 is formed (see FIG. 13(D)). The film 8 can be formed by using a PVD method, a CVD method, or the like. silicon oxide, silicon nitride, hafnium oxide, aluminum oxide, tantalum oxide, etc. The insulating film can be formed using a material containing an inorganic insulating material. The insulating layer 116 and the interlayer insulating layer 118 are stacked in a stacked structure. It may be a single layer or a laminated structure of three or more layers.

[0164] It is desirable that the interlayer insulating layer 118 be formed so that its surface is flat. By forming the interlayer insulating layer 118 so that the surface is flat, it is possible to form an electrode on the interlayer insulating layer 118. This is because electrodes, wiring, etc. can be formed in a suitable manner.

[0165] As a result, the transistor 15 using the oxide semiconductor layer 106a having the crystalline region 110 0 is completed.

[0166] The crystalline region 110 is formed in the oxide semiconductor layer 106a by the method described in this embodiment. Therefore, a semiconductor device with good electrical characteristics can be realized.

[0167] In addition, by the method described in this embodiment, the hydrogen concentration in the oxide semiconductor layer 106a is 5×10 1 9 / cm 3 The off-state current of the transistor is 1×10 -13 After A In this way, the hydrogen concentration is sufficiently reduced and oxygen is supplied, resulting in a high purity By using the oxide semiconductor layer 106a, a semiconductor device with excellent characteristics can be realized. This can be done.

[0168] As described above, the disclosed invention realizes a semiconductor device with a new structure having excellent characteristics. will be done.

[0169] <Variations> Next, regarding modifications of the semiconductor device shown in FIGS. 1 to 13, FIGS. 14 to 16 will be described. 14 to 16. Most of the components of the semiconductor device shown in FIGS. 13. Therefore, only the differences will be described here. explain.

[0170] The transistor 150 illustrated in FIG. 14A includes an oxide semiconductor layer 106 having a recess (groove). The recess includes the source or drain electrode layer 108a and This is formed by etching when forming the source or drain electrode layer 108b. For this reason, the recess is formed in the region overlapping the gate electrode layer 114. The recessed portion makes it possible to reduce the thickness of the semiconductor layer in the channel forming region. This contributes to suppressing short channel effects.

[0171] The transistor 150 shown in FIG. 14B includes a source electrode layer or a drain electrode layer 108a. and an insulating film having substantially the same shape as the source electrode layer or the drain electrode layer 108b is formed on the source electrode layer or the drain electrode layer 108b. In this case, the source electrode layer or the drain electrode layer is formed of an insulating layer 109a. The capacitance between the drain electrode layer and the gate electrode layer (so-called gate capacitance) can be reduced. The expression "substantially the same" does not necessarily mean that the two are exactly the same. The term is used for the same purpose and includes the range in which they can be considered the same. Differences in thickness formed by etching are permitted. It is not necessary.

[0172] The transistor 150 shown in FIG. 14C includes an oxide semiconductor layer 106 having a recess (groove). a, and a source or drain electrode layer 108a and a source electrode layer Alternatively, an insulating layer 109a having substantially the same shape as the drain electrode layer 108b and The insulating layer 109b is included. That is, the features of the transistor 150 in FIG. This structure has the same characteristics as the transistor 150 shown in FIG. The effect is the same as that in the cases of FIG. 14(A) and FIG. 14(B).

[0173] In the transistor 150 shown in FIG. 15A, the source or drain electrode layer 108 a, and the source or drain electrode layer 108b are in contact with the oxide semiconductor layer 106a. The part where the oxygen is extracted is made of a material with low oxygen-removing effect (a material with low affinity for oxygen, such as nitride). Conductive layer 107a and conductive layer 107b are made of titanium, tungsten nitride, platinum, etc. By having such a conductive layer with a low oxygen extraction effect, This prevents the oxide semiconductor layer from becoming n-type due to the non-uniform conversion of the oxide semiconductor layer to n-type. This can suppress adverse effects on the transistor characteristics.

[0174] In FIG. 15A, the source or drain electrode layer 108a and the and the source electrode layer or the drain electrode layer 108b are employed. The structure is not limited to this. A single layer structure of a conductive layer made of a material with a low oxygen-extracting effect can be used. In the case of a single layer structure, for example, titanium nitride In the case of a laminated structure, for example, a titanium nitride film can be used. A two-layer structure of silicon film and titanium film can be adopted.

[0175] The transistor 150 shown in FIG. 15B is an oxide semiconductor having a crystalline region 110 extending over the entire top surface. 1 to 13, the crystalline region 1 The crystalline region 110 is formed by a heat treatment (first heat treatment) prior to the formation of the conductive layer 108. In this case, the first heat treatment also serves as the second heat treatment. Therefore, the second heat treatment may be omitted. In addition, the anisotropy of the oxide semiconductor layer 106a can be further increased. do.

[0176] The transistor 150 shown in FIG. 15C includes a source electrode layer or a drain electrode layer 108a. and the source or drain electrode layer 108b in contact with the oxide semiconductor layer 106a. A conductive layer 1 made of a material with low oxygen-removing effect (a material with low affinity for oxygen) is formed in the portion where the conductive layer 1 is to be formed. 107a and a conductive layer 107b, and a crystalline region 110 extending over the entire upper portion. That is, the transistor 150 shown in FIG. This has both the features of the transistor 150 shown in FIG. The effects resulting from the configuration are similar to those in the cases of FIGS. 15(A) and 15(B).

[0177] FIG. 16 shows a modified example of the semiconductor device, in which a material other than an oxide semiconductor (for example, silicon) is provided at the bottom. a transistor 250 using silicon, and a transistor using an oxide semiconductor thereon The structure of the transistor 150 using an oxide semiconductor is shown in FIG. It is similar to the transistor 150 shown in A).

[0178] The transistor 250 includes a channel forming region 21 provided in a substrate 200 including a semiconductor material. 6, and the impurity region 214 and the high concentration impurity region 215 provided so as to sandwich the channel forming region 216. The pure region 220 (collectively referred to as the impurity region) and the channel forming region 21 6, and a gate insulating layer 208a provided on the gate insulating layer 208a. The electrode layer 210a and the source electrode layer or the drain electrode layer electrically connected to the impurity region 214 are 16, the source electrode layer 230a and the drain electrode layer 230b. The substrate 200 including a semiconductor material may be, for example, a silicon substrate or an SOI substrate. Applies.

[0179] Here, a sidewall insulating layer 218 is provided on the side surface of the gate electrode layer 210a. In addition, when viewed from a direction perpendicular to the main surface of the substrate 200, the sidewall insulating layer The region that does not overlap with the semiconductor substrate 218 has a high concentration impurity region 220. A metal compound region 224 is in contact with the substrate 200. A transistor 250 is also formed on the substrate 200. An element isolation insulating layer 206 is provided to surround the transistor 250. An interlayer insulating layer 226 and an interlayer insulating layer 228 are provided. The source or drain electrode layer 230a and the source or drain electrode layer 230b are formed between the interlayer insulating layer 226 and the The metal compound region 22 is formed through an opening formed in the interlayer insulating layer 228 and the insulating layer 234. 4. That is, the source electrode layer or drain electrode layer 230a, The source or drain electrode layer 230b is formed by the metal compound region 224 and is highly impurity-doped. The insulating layer 234 is electrically connected to the impurity region 220 and the impurity region 214. It is preferable that the surface is sufficiently flat. Specifically, the height difference is 3 nm or less, and preferably It is advisable to planarize the surface to 1 nm or less using CMP (chemical mechanical polishing) or the like. By forming such a flat insulating layer 234, the flatness of each element formed on the insulating layer 234 can be improved. This is because it can improve

[0180] The transistor 150 includes an oxide semiconductor layer 106a (crystal region) provided over the insulating layer 102. 110) and the oxide semiconductor layer 106a. The source or drain electrode layer 108a, the source or drain electrode layer 108b, and the The drain electrode layer 108b, the oxide semiconductor layer 106a, the source electrode layer or the drain electrode layer The source electrode layer 108a and the drain electrode layer 108b are provided so as to cover the The gate insulating layer 112 and the oxide semiconductor layer 106a are formed on the gate insulating layer 112 and overlap with each other. and a gate electrode layer 114 provided in the region (see FIG. 16). , if the insulating layer 234 is sufficiently planarized, the insulating layer 102 formed thereon, This is preferable because the surface of the oxide semiconductor layer 106a is also very flat. This is because the crystallinity of the crystalline region formed in the flat oxide semiconductor layer 106a is excellent. do.

[0181] Moreover, an interlayer insulating layer 116 and an interlayer insulating layer 118 are provided on the transistor 150. Here, the gate insulating layer 112, the interlayer insulating layer 116, and the interlayer insulating layer 118 have , the source or drain electrode layer 108a, the source or drain electrode layer 10 8b, and the electrode layer 254d and the electrode layer 2 54e are the source or drain electrode layer 108a, the source or drain electrode layer 108b, and the The electrode layer 254d is formed in contact with the drain electrode layer 108b. Similarly to e, the insulating layer 102, the gate insulating layer 112, the interlayer insulating layer 116, and the interlayer insulating layer 118, the electrode layer 236a, the electrode layer 236b, and the electrode layer 236c. Contacting electrode layers 254a, 254b, and 254c are formed.

[0182] An insulating layer 256 is provided on the interlayer insulating layer 118, and a buried insulating layer 256 is provided on the insulating layer 256. The electrode layer 258a, the electrode layer 258b, the electrode layer 258c, and the electrode layer 258d are Here, the electrode layer 258a is in contact with the electrode layer 254a, and the electrode layer 258 b is in contact with the electrode layer 254b, and the electrode layer 258c is in contact with the electrode layer 254c and the electrode layer 254 d, and electrode layer 258d contacts electrode layer 254e.

[0183] That is, the source electrode layer or drain electrode layer 108a of the transistor 150 is 30c, electrode layer 236c, electrode layer 254c, electrode layer 258c, and electrode layer 254d. Electrically connected to other elements (such as transistors made of materials other than oxide semiconductors) Furthermore, the source electrode layer or the drain electrode layer 1 of the transistor 150 is 08b is electrically connected to other elements via electrode layer 254e and electrode layer 258d. In addition, the electrodes involved in the connection (electrode layer 230c, electrode layer 236c, electrode layer 254c, electrode layer The configuration of the electrode layer 254d, etc. is not limited to the above, and may be added or omitted as appropriate. be.

[0184] In addition, the above-mentioned various electrodes (including wiring) are made of a material containing copper. By using a material containing copper for a part of the electrodes, the conductivity of the electrodes can be improved. Such electrodes and wiring are formed in openings formed in an insulating layer by, for example, PVD or After forming a barrier film (titanium film, titanium nitride film, etc.) by CVD method, It can be formed by using a method for forming a copper film (so-called damascene method), or the like.

[0185] As shown in FIG. 16, in one embodiment of the disclosed invention, various substrates (semiconductor substrate, insulating substrate, metal substrate, Oxide semiconductors with crystalline regions on any surface, such as metal substrates, insulating films, semiconductor films, and metal films That is, a crystalline oxide layer can be formed on a substrate on which an integrated circuit is formed. This makes it possible to easily form semiconductor layers, making it easy to realize three-dimensional integration. It is Noh.

[0186] As described above, one embodiment of the disclosed invention can be modified and used in various ways. In addition, the modified examples are not limited to the above examples. For example, the modified examples shown in FIGS. 14(A), 14(B), and 14 (C), Fig. 15(A), Fig. 15(B), Fig. 15(C), Fig. 16 are appropriately combined to create another variation. It is possible to use it as an example. Of course, within the scope of the description, etc., modifications and You are free to add omissions, etc.

[0187] As described above, the configurations, methods, etc. shown in this embodiment may be applied to the configurations, methods, etc. shown in other embodiments. They can be used in any suitable combination.

[0188] (Embodiment 2) In this embodiment, a semiconductor device having a different configuration from the semiconductor device according to the previous embodiment and A manufacturing method thereof will be described with reference to FIGS. The configuration has many points in common with the configuration shown in the previous embodiment, so the following will mainly focus on Only the differences will be explained.

[0189] <Configuration of Semiconductor Device> FIG. 17 is a cross-sectional view showing a transistor 150, which is an example of the configuration of a semiconductor device.

[0190] The difference from the configuration shown in FIG. 1 is that a gate electrode layer 101a is provided below an oxide semiconductor layer 106a. That is, the transistor 150 shown in FIG. An electrode layer 101a, an insulating layer 102 covering the gate electrode layer 101a, and an oxide layer on the insulating layer 102. the oxide semiconductor layer 106a, the crystalline region 110 in the oxide semiconductor layer 106a, and the oxide semiconductor layer a source or drain electrode layer 108a electrically connected to the source or drain electrode layer 106a; the source or drain electrode layer 108b, the oxide semiconductor layer 106a, the source or drain electrode layer 108b, The source or drain electrode layer 108a and the source or drain electrode layer 108b are covered with a and a gate electrode layer 114 on the gate insulating layer 112 (FIG. 17). Here, the insulating layer 102 also functions as a gate insulating layer. ) includes a source or drain electrode layer 108a and a FIG. 17B shows a case where the source electrode layer 108b has a laminated structure. When the source electrode layer 108a and the source or drain electrode layer 108b have a single layer structure, In the case of a single-layer structure, a good tapered shape can be achieved. is easy.

[0191] Similar to the structure shown in FIG. 1, the oxide semiconductor layer 106a includes a crystalline region 110. The region includes the surface of the oxide semiconductor layer 106a, that is, the region in contact with the gate insulating layer 112. This corresponds to the area containing the position.

[0192] Moreover, an interlayer insulating layer 116 and an interlayer insulating layer 118 are provided on the transistor 150. Note that the interlayer insulating layer 116 and the interlayer insulating layer 118 are not essential components. , may be omitted as appropriate.

[0193] Details of each component can be found in the previous embodiment and will be omitted here.

[0194] As shown in FIG. 17, a highly purified oxide semiconductor having a crystalline region 110 is used. By using the layer 106a, a semiconductor device having good electrical characteristics can be realized. Cut.

[0195] In addition, the crystalline region 110 is more stable than other regions of the oxide semiconductor layer 106a. By forming this, impurities (such as moisture) can be prevented from entering the oxide semiconductor layer 106a. Therefore, the reliability of the oxide semiconductor layer 106a can be improved. It is possible.

[0196] Furthermore, by having the gate electrode layer 101a, which is a so-called back gate, This makes it easy to adjust the electrical characteristics of the transistor 150. The potential of the gate electrode layer 114 may be the same as that of the gate electrode layer 114, or may be different from that of the gate electrode layer 114. A potential may be applied, or the electrode may be in a floating state.

[0197] <Method for manufacturing semiconductor device> Next, a method for manufacturing a transistor 150, which is an example of the structure of a semiconductor device, will be described with reference to FIGS. This will be explained with reference to FIG.

[0198] First, a conductive layer 101 is formed on a substrate 100 (see FIG. 18(A)). For details, the previous embodiment can be referred to, and therefore a detailed description will be omitted.

[0199] The conductive layer 101 is formed by a PVD method such as a sputtering method or a CVD method such as a plasma CVD method. The conductive layer 101 can be formed by a method. An element selected from tantalum, titanium, molybdenum, and tungsten, or the above-mentioned elements It can be formed using alloys containing manganese, magnesium, zirconium, etc. Alternatively, a material containing one or more of aluminum and beryllium may be used. Titanium, tantalum, tungsten, molybdenum, chromium, neodymium, scandium Alternatively, a material containing one or more elements selected from the above may be used.

[0200] The conductive layer 101 may be formed using a conductive metal oxide. Materials include indium oxide (In2O3), tin oxide (SnO2), and zinc oxide (ZnO). , indium oxide tin oxide alloy (In2O3-SnO2, sometimes abbreviated as ITO) , indium oxide zinc oxide alloy (In2O3-ZnO), or these metal oxide materials The material may contain silicon or silicon oxide.

[0201] The conductive layer 101 may have a single-layer structure or a stacked structure of two or more layers. In one embodiment of the disclosed invention, after the conductive layer 101 is formed, a heat treatment is performed at a relatively high temperature. Therefore, it is desirable to form the conductive layer 101 using a material with high heat resistance. Suitable materials include titanium, tantalum, tungsten, and molybdenum. It is also possible to use polysilicon or the like in which the conductivity is increased by adding a pure element.

[0202] Next, the conductive layer 101 is selectively etched to form a gate electrode layer 101a. An insulating layer 102 is formed to cover the base electrode layer 101a (see FIG. 18(B)).

[0203] For the exposure when forming the mask used for etching, ultraviolet rays, KrF laser light, or ArF laser light are used. It is preferable to use the following. In particular, when performing exposure with a channel length (L) of less than 25 nm, Extreme ultraviolet rays have extremely short wavelengths ranging from a few nm to a few tens of nm. It is preferable to use ultraviolet light to expose the mask. It has a high resolution and a large depth of focus, making it suitable for miniaturization.

[0204] The gate electrode layer 101a is a so-called back gate. By this, it is possible to control the electric field in the oxide semiconductor layer 106a. The electrical characteristics of the transistor 150 can be controlled. The wiring may be electrically connected to other wirings or electrodes and be given a certain potential, or may be insulated. It may be in a floating state.

[0205] Incidentally, the "gate electrode" usually refers to a gate electrode whose potential can be intentionally controlled. In the specification, the term "gate electrode" is used even when the potential is not intentionally controlled. For example, for an isolated, floating conductive layer as described above, The gate electrode layer is also sometimes called a "gate electrode layer."

[0206] The insulating layer 102 functions as a base and also as a gate insulating layer. The insulating layer 102 can be formed by using a CVD method, a sputtering method, or the like. Silicon oxide, silicon nitride, silicon oxynitride, silicon nitride oxide, aluminum oxide, hafnium oxide The insulating layer 102 is preferably formed to contain tantalum oxide, tantalum oxide, or the like. The insulating layer 102 may have a single layer structure or a multilayer structure. However, it can be set to, for example, 10 nm or more and 500 nm or less.

[0207] If the insulating layer 102 contains hydrogen, water, or the like, hydrogen may enter the oxide semiconductor layer or water may be released from the insulating layer 102. The oxygen in the oxide semiconductor layer is extracted by the hydrogen, which deteriorates the characteristics of the transistor. Therefore, the insulating layer 102 is formed so as to contain as little hydrogen and water as possible. It is desirable.

[0208] For example, when using a sputtering method, remove any remaining moisture in the processing chamber. It is desirable to form an insulating layer 102. In addition, in order to remove residual moisture in the processing chamber, Adsorption type vacuum pumps such as cryopumps, ion pumps, and titanium sublimation pumps It is preferable to use a pump. A turbo pump with a cold trap is used. The processing chamber is evacuated using a cryopump or the like to ensure that hydrogen, water, etc. are sufficiently removed. Therefore, the concentration of impurities contained in the insulating layer 102 can be reduced.

[0209] Furthermore, when forming the insulating layer 102, impurities such as hydrogen and water are preferably present at a concentration of about several ppm. It is preferable to use a high purity gas whose concentration has been reduced to about several ppb.

[0210] The insulating layer 102 is required to have high quality, similar to the gate insulating layer 112. Therefore, it is preferable to form the insulating layer 102 by a method similar to that for the gate insulating layer 112. Details are omitted since the previous embodiment can be referred to.

[0211] Next, the oxide semiconductor layer 106 is formed over the insulating layer 102 (see FIG. 18C). The above embodiment can also be referred to for details of the semiconductor layer 106.

[0212] Next, the oxide semiconductor layer 106 is processed by a method such as etching using a mask. An island-shaped oxide semiconductor layer 106a is formed (see FIG. 19A). It should be noted that the layer 106a is formed in a region overlapping the gate electrode layer 101a. For details, please refer to the previous embodiment.

[0213] After that, the oxide semiconductor layer 106a is preferably subjected to heat treatment (first heat treatment). By the first heat treatment, water (including a hydroxyl group) and hydrogen in the oxide semiconductor layer 106a are removed. The temperature of the first heat treatment is, for example, 300° C. or higher and lower than 550° C. Preferably, the temperature can be 400° C. or higher and lower than 550° C. The second heat treatment (heat treatment for forming a crystalline region) may also be performed. The temperature of the heat treatment is preferably 550° C. or more and 850° C. or less. In this regard, the previous embodiment can be referred to and therefore a detailed description will be omitted.

[0214] Next, the conductive layer 108 is formed in contact with the oxide semiconductor layer 106a (see FIG. 19B). Then, the conductive layer 108 is selectively etched to form a source electrode layer or a drain electrode layer. The electrode layer 108a and the source or drain electrode layer 108b are formed (see FIG. 19(C)). The conductive layer 108, the source electrode layer or the drain electrode layer 108a, the source electrode layer or the drain electrode layer 108b, The drain electrode layer 108b, the etching process, and other details are the same as those of the previous embodiment. This can be taken into consideration.

[0215] Next, the oxide semiconductor layer 106a is subjected to heat treatment (second heat treatment). As a result, a crystalline region 110 is formed in a region including the surface of the oxide semiconductor layer 106a (see FIG. 20(A)). Note that the range of the crystalline region 110 is the same as that of the oxide semiconductor layer 106a. The thickness of the oxide semiconductor layer 106 may vary depending on the material used and the conditions of the heat treatment. It is also possible to form the crystalline region 110 up to the lower interface of a. For details, the above embodiment can be referred to.

[0216] Next, the gate insulating layer 106a was removed from the oxide semiconductor layer 106a without exposing it to the air. 20B, an oxide semiconductor film is formed on the gate insulating layer 112. The gate electrode layer 11 is formed in the region overlapping the layer 106a (particularly, the region overlapping the crystalline region 110). 20(C) , the gate insulating layer 112 and the gate electrode layer 14 are formed. An interlayer insulating layer 116 and an interlayer insulating layer 118 are formed on the insulating film 14 (see FIG. 20(D)). The above embodiments can also be referred to for details of the above steps.

[0217] The crystalline region 110 is formed in the oxide semiconductor layer 106a by the method described in this embodiment. Therefore, a semiconductor device with good electrical characteristics can be realized.

[0218] In addition, by the method described in this embodiment, the hydrogen concentration in the oxide semiconductor layer 106a is 5×10 1 9 / cm 3 The off-state current of the transistor is 1×10 -13 After A In this way, the hydrogen concentration is sufficiently reduced and oxygen is supplied, resulting in a high purity By using the oxide semiconductor layer 106a, a semiconductor device with excellent characteristics can be realized. This can be done.

[0219] Furthermore, by having a gate electrode layer, which is a so-called back gate, the electric potential of the semiconductor device can be increased. This makes it easier to adjust the atmospheric properties.

[0220] As described above, the disclosed invention realizes a semiconductor device with a new structure having excellent characteristics. will be done.

[0221] <Variations> Next, regarding modifications of the semiconductor device shown in FIGS. 17 to 20, FIGS. 21 and 2 2. Note that many of the components of the semiconductor device shown in FIGS. 17 to 20, the differences will be described here. This will only be explained in this section.

[0222] The transistor 150 illustrated in FIG. 21A includes an oxide semiconductor layer 106 having a recess (groove). The recess includes the source or drain electrode layer 108a and This is formed by etching when forming the source or drain electrode layer 108b. For this reason, the recess is formed in the region overlapping the gate electrode layer 114. The recessed portion makes it possible to reduce the thickness of the semiconductor layer in the channel forming region. This contributes to suppressing short channel effects.

[0223] The transistor 150 shown in FIG. 21B includes a source electrode layer or a drain electrode layer 108a. and an insulating film having substantially the same shape as the source electrode layer or the drain electrode layer 108b is formed on the source electrode layer or the drain electrode layer 108b. In this case, the source electrode layer or the drain electrode layer is formed of an insulating layer 109a. The capacitance between the drain electrode layer and the gate electrode layer (so-called gate capacitance) can be reduced. The expression "substantially the same" does not necessarily mean that the two are exactly the same. It is used for the same purpose and includes the range that can be considered the same. Differences in thickness formed by the coating process are permitted. is not required.

[0224] The transistor 150 shown in FIG. 21C includes an oxide semiconductor layer 106 having a recess (groove). a, and a source or drain electrode layer 108a and a source electrode layer Alternatively, an insulating layer 109a having substantially the same shape as the drain electrode layer 108b and The insulating layer 109b is included. That is, the features of the transistor 150 in FIG. This structure has the characteristics of the transistor 150 shown in FIG. The effect is the same as that in the cases of FIG. 21(A) and FIG. 21(B).

[0225] In the transistor 150 shown in FIG. 22A, the source or drain electrode layer 108 a, and the source or drain electrode layer 108b are in contact with the oxide semiconductor layer 106a. The part where the oxygen is extracted is made of a material with low oxygen-removing effect (a material with low affinity for oxygen, such as nitride). Conductive layer 107a and conductive layer 107b are made of titanium, tungsten nitride, platinum, etc. By having such a conductive layer with a low oxygen extraction effect, This prevents the transistor from becoming n-type due to the uneven n-type conversion, and suppresses the adverse effects on transistor characteristics caused by the uneven n-type conversion. It is possible.

[0226] In FIG. 22A, the source or drain electrode layer 108a and and the source electrode layer or the drain electrode layer 108b are employed. The structure is not limited to this. A single layer structure of a conductive layer made of a material with a low oxygen-extracting effect can be used. In the case of a single layer structure, for example, titanium nitride In the case of a laminated structure, for example, a titanium nitride film can be used. A two-layer structure of silicon film and titanium film can be adopted.

[0227] The transistor 150 shown in FIG. 22B is an oxide semiconductor having a crystalline region 110 extending over the entire top surface. 17 to 20, the crystalline region The crystalline region 110 is formed by a heat treatment (first In this case, the first heat treatment also serves as the second heat treatment. Therefore, the second heat treatment may be omitted. In addition, the anisotropy of the oxide semiconductor layer 106a can be further increased. be.

[0228] The transistor 150 shown in FIG. 22C includes a source electrode layer or a drain electrode layer 108a. and the source or drain electrode layer 108b in contact with the oxide semiconductor layer 106a. A conductive layer 1 made of a material with low oxygen-removing effect (a material with low affinity for oxygen) is formed in the portion where the conductive layer 1 is to be formed. 107a and a conductive layer 107b, and a crystalline region 110 extending over the entire upper portion. That is, the transistor 150 shown in FIG. This has both the features of the transistor 150 shown in FIG. The effects resulting from the configuration are similar to those in the cases of FIGS. 22(A) and 22(B).

[0229] As described in the above embodiment, a material other than an oxide semiconductor (for example, a transistor 250 using an oxide semiconductor in the upper part; A configuration including a capacitor 150 can also be adopted (see FIG. 16). The configuration of the transistor 150 is similar to that of the transistor 150 shown in FIG. In this regard, the above embodiment can be referred to.

[0230] As described above, one embodiment of the disclosed invention can be modified and used in various ways. In addition, the modified examples are not limited to the above examples. For example, the modified examples shown in FIGS. 21(A), 21(B), and 21 (C), Fig. 22(A), Fig. 22(B), Fig. 22(C), etc. may be appropriately combined to produce another modified example. Of course, within the scope of the description, etc., modifications and omissions may be made. You are free to add other things as well.

[0231] As described above, the configurations, methods, etc. shown in this embodiment may be applied to the configurations, methods, etc. shown in other embodiments. They can be used in any suitable combination.

[0232] (Embodiment 3) In this embodiment, an example of an electronic device equipped with the semiconductor device obtained in the above embodiment will be described. The semiconductor device obtained in the above embodiment has an excellent property not found in the prior art. Therefore, electronic devices with new configurations can be provided using the semiconductor device. It is possible to provide

[0233] FIG. 23A shows a notebook personal computer including the semiconductor device according to the above embodiment. The computer is composed of a main body 301, a housing 302, a display unit 303, a keyboard 304, etc. The semiconductor device according to the disclosed invention is integrated and mounted on a circuit board or the like. The display unit 30 is mounted inside the housing 302. The semiconductor device according to the disclosed invention can be applied to an integrated circuit board or the like. By applying the present invention to the above, high speed operation of the circuit can be realized. By applying the semiconductor device according to the present invention to the display portion 303, a high-quality image can be displayed. In this way, the semiconductor device according to the disclosed invention can be applied to a personal computer. This makes it possible to provide a personal computer with excellent performance.

[0234] FIG. 23B shows a personal digital assistant (PDA) including the semiconductor device according to the above embodiment. The main body 311 includes a display unit 313, an external interface 315, an operation button 314, etc. The disclosed invention also includes a stylus 312 as an accessory for operation. Such a semiconductor device is integrated and mounted on a circuit board or the like, and is then mounted on the main body 311. In addition, the semiconductor device according to the present invention can be applied to the display portion 313. By applying the semiconductor device of the present invention to a circuit board or the like, high-speed operation of the circuit can be realized. In addition, the semiconductor device according to the present invention can be applied to the display portion 313. As a result, a high-quality image can be displayed. By applying this device to a personal digital assistant (PDA), it is possible to achieve a highly functional personal digital assistant (PDA). can be provided.

[0235] FIG. 23C shows an example of electronic paper including the semiconductor device according to the above embodiment. The electronic book 320 is shown. The electronic book 320 is made up of two housings, housing 321 and housing 323. The housing 321 and the housing 323 are integrated by a shaft portion 337. The opening and closing operation can be performed around the axis 337. 320 can be used like a paper book.

[0236] The housing 321 incorporates a display unit 325, and the housing 323 incorporates a display unit 327. The semiconductor device according to the disclosed invention is integrated and mounted on a circuit board or the like, and is housed in a housing 3. 23 or the inside of the housing 321. The display unit 327 is The display unit 325 and the display unit 327 can display a continuous screen. Alternatively, a different screen may be displayed. By configuring it this way, for example, text can be displayed on the display unit on the right (display unit 325 in FIG. 23(C)). In addition, an image can be displayed on the left display unit (display unit 327 in FIG. 23(C)). By applying this to integrated circuit boards, high-speed circuit operation can be achieved. By applying the semiconductor device according to the present invention to the display portion 327, high-quality images can be displayed. It can be shown.

[0237] FIG. 23C shows an example in which an operation unit and the like are provided on the housing 321. The body 321 includes a power supply 331, operation keys 333, a speaker 335, etc. You can turn the page by pressing the arrow 333. In addition, there is a keyboard and a pointer on the same surface as the display unit of the housing. The back and sides of the housing may be provided with an external Connection terminals (earphone jack, USB terminal, AC adapter and USB cable, etc.) terminals that can be connected to various cables, a recording medium insertion section, etc. Furthermore, the electronic book 320 may be configured to have the function of an electronic dictionary.

[0238] The electronic book 320 may also be configured to be able to send and receive information wirelessly. It is also possible to purchase and download desired book data from the child book server. It is possible.

[0239] Electronic paper can be applied to any field that displays information. For example, in addition to e-books, posters, advertisements on trains and other vehicles, credit cards, etc. The present invention can be applied to the display of various cards such as credit cards. By applying the semiconductor device according to the present invention to electronic paper, it is possible to obtain electronic paper with excellent performance. can be provided.

[0240] FIG. 23D shows a mobile phone including the semiconductor device according to the above embodiment. The phone is made up of two housings, housing 340 and housing 341. Housing 341 has a front display panel 342, speaker 343, microphone 344, pointing device 3 46, a camera lens 347, an external connection terminal 348, etc. The mobile phone includes a solar cell 349 for charging the mobile phone, an external memory slot 350, etc. The antenna is built into the housing 341. The semiconductor device is integrated and mounted on a circuit board or the like, and is installed inside the housings 340 and 341. can be.

[0241] The display panel 342 has a touch panel function, and in FIG. 23(D) an image is displayed. The display panel 342 displays the operation keys 345 according to the present invention. The display panel 342 can be applied with a semiconductor device according to the present invention. By applying this setting, high-quality images can be displayed. A booster circuit is implemented to boost the voltage output from the solar battery cell 349 to the voltage required for each circuit. In addition to the above configuration, it is equipped with a non-contact IC chip, a small recording device, etc. It can also be configured as:

[0242] The display direction of the display panel 342 changes appropriately depending on the usage mode. The camera lens 347 is located on the same surface as the camera 42, making it possible to make video calls. The speaker 343 and microphone 344 are not limited to voice calls, but also video calls, recording, playback Furthermore, the housing 340 and the housing 341 can be slid, and as shown in FIG. It can be folded from the unfolded state to the overlapping state, making it possible to make it compact and portable. It is Noh.

[0243] The external connection terminal 348 can be connected to various cables such as an AC adapter or a USB cable. The external memory slot 350 can store a recording medium. It can insert and store and move larger amounts of data. In addition to the above functions, The device may also have an infrared communication function, a television receiving function, etc. By applying the semiconductor device to a mobile phone, it is possible to provide a mobile phone with excellent performance. Cut.

[0244] FIG. 23E shows a digital camera including the semiconductor device according to the previous embodiment. The digital camera comprises a main body 361, a display unit (A) 367, an eyepiece 363, and an operation switch 364. , a display unit (B) 365, a battery 366, etc. Such a semiconductor device can be applied to the display portion (A) 367 and the display portion (B) 365. The semiconductor device according to the invention disclosed herein is applied to the display portion (A) 367 and the display portion (B) 365. As a result, a high-quality image can be displayed. By applying this device to a digital camera, it is possible to provide a digital camera with excellent performance. Cut.

[0245] FIG. 23F shows a television set including the semiconductor device according to the above embodiment. In the vision device 370, a display unit 373 is built into a housing 371. In this case, the stand 375 is used to hold the case in place. The display portion 373 is provided with a semiconductor device according to the present invention. By applying this, high-speed operation of the switching element becomes possible, and the area of ​​the display unit 373 can be increased. It can be realized.

[0246] The television device 370 can be operated using an operation switch provided on the housing 371 or a separate remote control. This can be done by operating the operating device 380. The remote control operating device 380 has an operating key 379. This allows you to control the channel and volume, and to operate the image displayed on the display unit 373. In addition, the remote control operation device 380 can receive the output from the remote control operation device 380. A display unit 377 for displaying the information may be provided.

[0247] It is preferable that the television device 370 is configured to include a receiver, a modem, etc. The receiver can receive general television broadcasts. By connecting to a wired or wireless communication network, The purpose of this communication is to communicate information between two parties (one party) or two-way (between a sender and a receiver, or between receivers). In this way, the semiconductor device according to the disclosed invention can be applied to a television set. This makes it possible to provide a television device with excellent performance.

[0248] The structures, methods, and the like described in this embodiment may be combined as appropriate with the structures, methods, and the like described in other embodiments. Can be used in combination [Explanation of symbols]

[0249] 100 boards 101 Conductive layer 101a gate electrode layer 102 Insulating layer 106 Oxide semiconductor layer 106a Oxide semiconductor layer 107a Conductive layer 107b Conductive layer 108 Conductive layer 108a Source electrode layer or drain electrode layer 108b Source electrode layer or drain electrode layer 109a Insulating layer 109b Insulating layer 110 Crystal region 112 Gate insulating layer 114 gate electrode layer 116 Interlayer insulating layer 118 Interlayer insulation layer 150 transistors 200 boards 206 Element isolation insulating layer 208a Gate insulating layer 210a gate electrode layer 214 Impurity region 216 Channel formation region 218 Sidewall insulating layer 220 High concentration impurity region 224 Metal compound area 226 Interlayer insulation layer 228 Interlayer Insulation Layer 230a Source electrode layer or drain electrode layer 230b Source electrode layer or drain electrode layer 230c electrode layer 234 Insulating Layer 236a Electrode layer 236b Electrode layer 236c electrode layer 250 transistors 254a Electrode layer 254b Electrode layer 254c electrode layer 254d Electrode layer 254e Electrode layer 256 insulating layer 258a Electrode layer 258b Electrode layer 258c electrode layer 258d Electrode layer 301 Main Unit 302 Case 303 Display section 304 keyboard 311 Main Unit 312 Stylus 313 Display section 314 Operation Button 315 External Interface 320 e-books 321 Case 323 Case 325 Display section 327 Display section 331 Power supply 333 Operation Key 335 Speaker 337 Shaft 340 Case 341 Case 342 Display Panel 343 Speaker 344 Microphone 345 Operation Key 346 Pointing Device 347 Camera Lenses 348 External connection terminal 349 Solar Cells 350 external memory slot 361 Main Unit 363 Eyepiece 364 Operation Switch 365 Display section (B) 366 Battery 367 Display section (A) 370 Television Equipment 371 Case 373 Display section 375 Stand 377 Display section 379 Operation Key 380 Remote Controlled Device

Claims

[Claim 1] an oxide semiconductor layer having a crystalline region on an insulating surface; a source electrode layer and a drain electrode layer in contact with the oxide semiconductor layer; a gate insulating layer covering the oxide semiconductor layer, the source electrode layer, and the drain electrode layer; a gate electrode layer on the gate insulating layer in a region overlapping the crystalline region; and The crystalline region is a region having crystals whose c-axes are oriented in a direction substantially perpendicular to the surface of the oxide semiconductor layer.

Images