Semiconductor device

Abstract

In a transistor including an oxide semiconductor, the presence of hydrogen in the oxide semiconductor leads to poor electrical characteristics of the transistor. Thus, a semiconductor device having favorable electrical characteristics is provided.SOLUTION: An insulating layer which is in contact with an oxide semiconductor layer where a channel region is formed is formed by a plasma CVD method using silicon halide. Since the insulating layer formed in this manner has a hydrogen concentration of less than 6 * 10 20 atoms / cm3 and a halogen concentration of 1 * 10 20 atoms / cm3 or more, it is possible to prevent hydrogen from diffusing into the oxide semiconductor layer, and hydrogen existing in the oxide semiconductor layer can be inactivated or desorbed by halogen, so that a semiconductor device having favorable electrical characteristics can be provided.SELECTED DRAWING: Figure 1

Description

[Technical Field]

[0001] The present invention relates to a semiconductor device including an oxide semiconductor and a manufacturing method thereof.

[0002] In this specification, a semiconductor device is a device that can function by utilizing semiconductor characteristics. Generally, electro-optical devices, semiconductor circuits, and electronic devices are all semiconductor devices. [Background technology]

[0003] In recent years, in liquid crystal display devices and light-emitting display devices, such as flat panel displays, The transistors used in many of these devices are made of amorphous silicon or polycrystalline silicon on a glass substrate. It is made of silicon semiconductors such as crystalline silicon.

[0004] Recently, technology that uses oxide semiconductors in transistors instead of silicon semiconductors has been attracting attention. do.

[0005] For example, oxide semiconductors include zinc oxide, which is a single-component metal oxide, and There are In-Ga-Zn-O oxides, and transistors are fabricated using them. The technology for use in the switching elements of the pixels of the device has been disclosed (Patent Documents 1 to 5). (See Reference 3). [Prior art documents] [Patent documents]

[0006] [Patent Document 1] Japanese Patent Application Laid-Open No. 2006-165528 [Patent Document 2] Japanese Patent Application Laid-Open No. 2007-96055 [Patent Document 3] Japanese Patent Application Laid-Open No. 2007-123861 Summary of the Invention [Problem to be solved by the invention]

[0007] A transistor that uses an oxide semiconductor for the channel region has a threshold voltage (V th ) but my When the potential of the gate electrode is the same as the potential of the source electrode (V gs =0 V), there is also the problem of a certain amount of drain current flowing.

[0008] In view of this situation, one embodiment of the invention disclosed in this specification is a semiconductor device having good electrical properties. An object of the present invention is to provide a semiconductor device. [Means for solving the problem]

[0009] To solve the above problem, a gate insulating film in contact with an oxide semiconductor layer in which a channel region is formed is formed. The layer is an insulating layer having a low hydrogen content and containing a halogen such as fluorine or chlorine. Therefore, the migration of hydrogen from the gate insulating layer to the oxide semiconductor layer is suppressed, and the oxide semiconductor In order to inactivate or desorb hydrogen present in the layer, a hydrogen-containing oxide semiconductor layer is The amount can be reduced.

[0010] Specifically, when the hydrogen concentration is 6×10 20 atoms / cm 3 Less than 2 x 10 20 atoms / cm 3 Less than 5 × 10, more preferably 19 atoms / cm 3 is as follows: , and the halogen concentration is 1×10 19 atoms / cm 3 or more, preferably 1 × 10 2 0 atoms / cm 3The gate insulating layer described above is used.

[0011] One embodiment of the present invention is a semiconductor device including a gate electrode layer, an oxide semiconductor layer in which a channel region is formed, and an oxide semiconductor layer. a source electrode layer and a drain electrode layer electrically connected to the oxide semiconductor layer; a gate insulating layer located between the oxide semiconductor layer and the gate insulating layer via the oxide semiconductor layer; a layer facing the oxide semiconductor layer and in contact with the oxide semiconductor layer, the layer having a hydrogen concentration of 6×10 20 atoms / cm 3 less than , preferably 2 x 10 20 atoms / cm 3 Less than 5 × 10, more preferably 19 at oms / cm 3 The halogen concentration is 1×10 19 atoms / cm 3 That's all, Preferably 1 x 10 20 atoms / cm 3 The semiconductor device has the insulating layer described above. .

[0012] Another embodiment of the present invention is a method for manufacturing a semiconductor device, comprising: forming an oxide semiconductor layer on a gate electrode layer via the gate insulating layer; Another embodiment of the present invention is a bottom-gate transistor in which a gate electrode The transistor has a top gate structure in which the oxide semiconductor layer is overlapped with the gate insulating layer. It is a pedestrian.

[0013] In another embodiment of the present invention, the gate insulating layer is formed of silicon oxide, silicon oxynitride, or silicon nitride. an oxide insulating layer which is silicon oxide, hafnium oxide, aluminum oxide, or tantalum oxide; To do this.

[0014] The gate insulating layer includes a first gate insulating layer in contact with the gate electrode layer and an oxide semiconductor layer. The second gate insulating layer may be formed by disposing a water-based insulating layer on the first gate insulating layer. By using a material with a low content of halogen and containing halogen, The migration of hydrogen from the oxide semiconductor layer to the oxide semiconductor layer is suppressed, and the hydrogen present in the oxide semiconductor layer is In order to passivate or desorb hydrogen, the hydrogen content in the oxide semiconductor layer is reduced. This can be done.

[0015] In another aspect of the present invention, the gate insulating layer comprises a first gate insulating layer in contact with the gate electrode layer; a second gate insulating layer in contact with the oxide semiconductor layer, Concentration is 6 x 10 20 atoms / cm 3 Less than 2 x 10 20 atoms / cm 3 Less than 5 × 10, more preferably 19 atoms / cm 3 The second gate insulator The concentration of halogen in the edge layer is 1×10 19 atoms / cm 3 More than 1x, preferably 1x 10 20 atoms / cm 3 The semiconductor device is characterized by the above.

[0016] Furthermore, in other insulating layers that constitute the semiconductor device and are in contact with the oxide semiconductor layer, By using materials with low hydrogen content and containing halogen, the oxide semiconductor is This suppresses the migration of hydrogen to the conductor layer and inactivates the hydrogen present in the oxide semiconductor layer. Therefore, the hydrogen content in the oxide semiconductor layer can be reduced. .

[0017] Another embodiment of the present invention is a method for manufacturing an insulating layer in contact with an oxide semiconductor layer, in which the hydrogen concentration is 6×1020 at oms / cm 3 Less than 2 x 10 20 atoms / cm 3 The following is more preferably is 5 x 10 19 atoms / cm 3 The halogen concentration is 1×10 20 ato ms / cm 3 or more, preferably 1 × 10 21 atoms / cm 3 The above features are This is a semiconductor device.

[0018] Another embodiment of the present invention is a semiconductor device including: The hydrogen concentration in the insulating layer is 6×10 20 atoms / cm 3 Less than 2 x 10 20 a toms / cm 3 Less than 5 × 10, more preferably 19 atoms / cm 3 is as follows: The concentration of halogen is 1×10 20 atoms / cm 3 or more, preferably 1 × 10 21 at oms / cm 3 The thickness of the insulating layer is the thickness of the oxide semiconductor layer and the thickness of the gate insulating layer. The sum of the thicknesses of the top-gate transistors and the The semiconductor device has the following features.

[0019] Another embodiment of the present invention is a semiconductor device including an insulating layer provided over a substrate and an oxide semiconductor layer in contact with the insulating layer. a pair of conductive regions provided in contact with the oxide semiconductor layer; a gate electrode layer provided on the conductive region with an insulating film interposed therebetween, A top-gate transistor characterized by not being in contact with a The semiconductor device has the following.

[0020] Another embodiment of the present invention is a semiconductor device in which silicon tetrafluoride (SiF), ... It can be obtained by using silicon halide such as silicon chloride (SiCl4) as a raw material gas. The semiconductor device is provided with an insulating film whose main component is silicon oxide. The insulating film is preferably one in which the ratio of silicon among elements other than oxygen in the insulating film is 70% or more. is 90% or more. [Effects of the Invention]

[0021] According to one embodiment of the present invention, a semiconductor device with favorable electrical characteristics can be provided. [Brief explanation of the drawings]

[0022] [Figure 1] 1A and 1B are a top view and a cross-sectional view illustrating a semiconductor device (transistor). [Figure 2] FIG. 1 is a diagram showing a cluster model centered on a gallium atom. [Figure 3] FIG. 1 is a diagram showing a reaction formula and an energy diagram for a hydrogen atom elimination reaction. [Figure 4] FIG. 1 is a diagram showing a model used for calculating binding energy. [Figure 5] FIG. 1 is a diagram showing a reaction formula and an energy diagram for a hydrogen atom elimination reaction. [Figure 6] 1A to 1C are cross-sectional views illustrating a method for manufacturing a transistor. [Figure 7] 1A to 1C are cross-sectional views illustrating a method for manufacturing a transistor. [Figure 8] 1A to 1C are cross-sectional views illustrating a method for manufacturing a transistor. [Figure 9] 1A to 1C are cross-sectional views illustrating a method for manufacturing a transistor. [Figure 10] FIG. 10 is a diagram showing the hydrogen concentration and fluorine concentration contained in a silicon oxide layer. [Figure 11] FIG. 1 is an external view showing an example of an electronic book. [Figure 12] FIG. 1 is an external view showing an example of a television device and a digital photo frame. [Figure 13] FIG. 1 is a perspective view showing an example of a portable computer. DETAILED DESCRIPTION OF THE INVENTION

[0023] Hereinafter, embodiments of the present invention will be described in detail with reference to the accompanying drawings. The present invention is not limited to the following description, and the embodiments and aspects thereof may be modified without departing from the spirit and scope of the present invention. It will be readily apparent to those skilled in the art that various modifications may be made to the details. The present invention should not be construed as being limited to the description of the following embodiments. In explaining the configuration of the invention using the same reference numerals, the same elements are used in common among different drawings. When referring to similar items, the same hatch pattern is used and no particular symbol is attached. For convenience, the insulating layer may not be shown in the top view. The size, layer thickness, or area of ​​each component shown may be exaggerated for clarity. Therefore, it is not necessarily limited to that scale.

[0024] When it is stated that A and B are connected, it means that A and B are electrically connected. This includes the case where A and B are directly connected, and the case where A and B are directly connected. The object (e.g., device, element, circuit, wiring, electrode, terminal, conductive film, layer, etc.) do.

[0025] In addition, the function of the "source" and "drain" in a transistor is to control the flow of current during circuit operation. For this reason, in this specification, The terms "source" and "drain" may be used interchangeably.

[0026] (Embodiment 1) In this embodiment, a semiconductor device according to one embodiment of the present invention will be described with reference to FIG. Although FIG. 1 shows a transistor as a semiconductor device, it may be a diode or other device. can also be implemented in the same way.

[0027] FIG. 1(A) is a top view of a transistor. FIG. 1(B) is a top view of a transistor along A1-B1 in FIG. The transistor has a base insulating layer 102 and a gate electrode formed on a substrate 101. a layer 103, a gate insulating layer 104, and an oxide semiconductor layer 106 in which a channel region is formed. , the source electrode layer 107a, the drain electrode layer 107b, the oxide semiconductor layer 106, and the source electrode layer 107b. and an insulating layer 108 that covers the source electrode layer 107a and the drain electrode layer 107b.

[0028] In the transistor illustrated in FIG. 1, the oxide semiconductor layer 106 is connected to the gate insulating layer 104 via the gate insulating layer 104. The transistor has a bottom gate structure and is formed to overlap the top electrode layer 103. In the transistor shown in FIG. 1, the source electrode layer 107a and the drain electrode layer 107b are It is a top contact type formed in contact with a part of the upper surface of the compound semiconductor layer 106 .

[0029] In addition to the top-contact type, bottom-gate transistors also have a source electrode layer. and a drain electrode layer is formed in contact with a part of the lower surface of the semiconductor layer in which the channel region is formed. In this embodiment, a top contact type will be described. However, even in the case of a bottom contact type, the present embodiment can be implemented with reference to the present invention.

[0030] The transistor shown in FIG. 1 has a portion of the upper surface of the gate insulating layer 104 and a portion of the lower surface of the oxide semiconductor layer 106. Therefore, in the process of manufacturing the transistor, the gate insulating layer 10 When a large amount of hydrogen is present in the oxide semiconductor layer 104, the hydrogen diffuses into the oxide semiconductor layer 106, and the oxide semiconductor layer 1 When the hydrogen content in the oxide semiconductor layer 106 increases, the amount of hydrogen in the oxide semiconductor layer 106 increases. As a result, the number of carriers in the compound semiconductor layer 106 increases. V th ) fluctuates in the negative direction, and the potential of the gate electrode becomes the same as the potential of the source electrode. In this case (V gs = 0V), a transistor with poor electrical characteristics in which a drain current flows. It becomes a star.

[0031] In order to remove the hydrogen diffused from the oxide semiconductor layer 106, the oxide semiconductor layer 106 is subjected to a heat treatment. However, this method requires additional manufacturing steps for the transistor, which increases costs and reduces manufacturing time. Heat treatment at about 400°C is not effective enough. I also know that it isn't.

[0032] On the other hand, according to the findings of the present inventors, hydrogen in the gate insulating layer 104 in contact with the oxide semiconductor layer 106 Concentration 6×10 20 atoms / cm 3 Less than 2 x 10 20 atoms / cm 3 Less than 5 × 10, more preferably 19 atoms / cm 3 and the halogen concentration is Degrees to 1×10 19 atoms / cm 3 or more, preferably 1 × 10 20 atoms / cm 3 In this case, the transfer of hydrogen from the gate insulating layer 104 to the oxide semiconductor layer 106 is suppressed. At the same time, hydrogen present in the oxide semiconductor layer 106 is inactivated or desorbed. Therefore, the hydrogen content in the oxide semiconductor layer 106 can be reduced. It became clear that:

[0033] That is, the gate insulating layer 104 in contact with the oxide semiconductor layer 106 is treated to have the above-mentioned hydrogen concentration and halide concentration. By using a gate insulating layer with a high density of GaN, it is possible to obtain a good transistor without increasing the number of manufacturing steps. In particular, the maximum process temperature is set to 40 A transistor that can be heated to temperatures below 0°C, preferably 350°C or less, while still having practical reliability and characteristics. Of course, the maximum process temperature is not a limitation in practicing the present invention. The maximum temperature of the process may be 400°C or higher.

[0034] The oxide semiconductor layer 106, the source electrode layer 107a, and the drain electrode layer 107b The insulating layer 108 covering the oxide semiconductor layer 106 is in contact with a part of the upper surface of the oxide semiconductor layer 106. The hydrogen concentration in layer 108 is 6×10 20 atoms / cm 3 Less than 2 x 10 20 a toms / cm 3 Less than 5 × 10, more preferably 19 atoms / cm 3 Below, Haloge The concentration of 1×10 19 atoms / cm 3 or more, preferably 1 × 10 20atoms / c m 3 In this manner, transfer of hydrogen from the insulating layer 108 to the oxide semiconductor layer 106 is suppressed. At the same time, hydrogen present in the oxide semiconductor layer 106 is inactivated or desorbed. Therefore, the hydrogen content in the oxide semiconductor layer 106 can be reduced, and Therefore, a semiconductor device having excellent electrical characteristics can be obtained.

[0035] The substrate 101 is not particularly limited as long as it can withstand the subsequent manufacturing steps. The substrate 101 may be a glass substrate, a ceramic substrate, a quartz substrate, or a sapphire substrate. semiconductor substrates made of semiconductor materials such as silicon; metal or stainless steel substrates; A conductive substrate made of any conductor, or a semiconductor substrate or a conductive substrate with its surface covered with an insulating material A coated substrate or the like can be used. A plastic substrate can also be used as appropriate. Cut.

[0036] In addition, the glass substrate is heated to 600°C or higher during the transistor manufacturing process. When doing so, it is advisable to use a material with a strain point of 730°C or higher. For example, aluminosilicate Glass materials such as vitreous glass, aluminoborosilicate glass, and barium borosilicate glass are used. It is used.

[0037] The base insulating layer 102 prevents the diffusion of impurity elements from the substrate 101 and also serves to This prevents the substrate from being etched during the etching process in the manufacturing process. Although there is no limitation on the thickness of the insulating layer 102, for the above reasons, the thickness of the underlying insulating layer 102 is set to 50 nm. It is preferable that the above is set.

[0038] The base insulating layer 102 may be made of silicon oxide, silicon oxynitride, silicon nitride, silicon nitride oxide, or hafnium oxide. A single-layer or two-layer structure is used with an insulating layer such as tantalum oxide, aluminum oxide, or tantalum oxide. The laminated structure described above is formed.

[0039] Here, silicon oxynitride refers to a material whose composition contains more oxygen than nitrogen. For example, oxygen should be between 50 atomic % and 70 atomic % and nitrogen should be between 0.5 atomic % and 10 atomic %. The content of silicon is in the range of 25 atomic % to 35 atomic %. Silicon nitride oxide refers to a material whose composition contains more nitrogen than oxygen. For example, oxygen is 5 atomic % or more and 30 atomic % or less, and nitrogen is 20 atomic % or more and 55 atomic % or less. % or less, and silicon content in the range of 25 atomic % to 35 atomic %.

[0040] The above range is determined by Rutherford Backscattering (RBS) Electron scattering spectrometry (HFS) and hydrogen forward scattering spectrometry (HFS). This is measured using Fluorescence Intensity Forward Scattering (FIS). The total content of the constituent elements does not exceed 100 atomic percent.

[0041] The gate electrode layer 103 is formed on the base insulating layer 102. The material of the gate electrode layer 103 is , molybdenum, titanium, chromium, tantalum, tungsten, platinum, palladium, osmium Metallic materials such as aluminum, alloy materials whose main components are these metallic materials, or nitrides of these metals It can be used as a single layer or a laminate. If the metal material can withstand high temperatures, aluminum or copper can also be used. Aluminum or copper is a high melting point metal material to avoid problems of heat resistance and corrosion. High melting point metal materials include molybdenum, titanium, chromium, Tantalum, tungsten, neodymium, scandium, etc. can be used.

[0042] The gate electrode layer 103 may have a single layer structure or may be made of a laminate of two or more films made of different materials. For example, the gate electrode layer 103 having a stacked structure may be formed by depositing a molybdenum film on an aluminum film. Two-layer structure with a molybdenum film laminated on a copper film, or two-layer structure with a molybdenum film laminated on a copper film, or copper Two-layer structure with titanium nitride film or tantalum nitride film laminated on the film, titanium nitride film and molyb It is preferable that the gate electrode has a two-layer structure in which a gate electrode and a silicon film are laminated. The layer 103 may be an aluminum film, an aluminum-silicon alloy film, an aluminum-titanium alloy film, or a silicon-based alloy film. An alloy film of tungsten or an alloy film of aluminum and neodymium is used as an intermediate layer, and a nitride film is used as the intermediate layer. It is preferable to have a structure in which a tungsten film, a titanium nitride film or a titanium film is disposed above and below it. I wish.

[0043] The gate electrode layer 103 may be formed of indium oxide, an alloy of indium oxide and tin oxide, or Zinc oxide, zinc aluminum oxide, zinc aluminum oxide nitride, For the insulating layer, a transparent oxide conductor such as zinc gallium oxide or polycrystalline silicon can be used. can.

[0044] In addition, the gate electrode layer 103 is made of In-ON system, In-Zn-ON system, In-Ga-O- Oxynitrides such as N-based and In-Ga-Zn-ON-based may also be used. -Ga-Zn-ON oxynitrides are oxynitrides containing at least In, Ga, and Zn. There is no particular limitation on the composition ratio. Elements other than In, Ga, and Zn may also be included. stomach.

[0045] The thickness of the gate electrode layer 103 is not particularly limited, and may be made of a metal material, an alloy material, or other chemical material. The thickness can be determined appropriately taking into consideration the electrical resistance of the conductive film made of the compound and the time required for the manufacturing process. For example, it may be formed to a thickness of 10 nm to 500 nm.

[0046] A gate insulating layer 104 is provided over the gate electrode layer 103. As described above, the gate Since the insulating layer 104 is in contact with the oxide semiconductor layer 106, the hydrogen concentration of the gate insulating layer 104 is 6×10 20 atoms / cm 3 Less than 2 x 10 20 atoms / cm 3 below , and more preferably 5 × 10 19 atoms / cm 3 The fluorine concentration is 1x1 0 19 atoms / cm 3 or more, preferably 1 × 10 20 atoms / cm 3 That's all It is good.

[0047] This suppresses the transfer of hydrogen from the gate insulating layer 104 to the oxide semiconductor layer 106. At the same time, hydrogen present in the oxide semiconductor layer 106 is inactivated or desorbed. Therefore, the amount of hydrogen contained in the oxide semiconductor layer 106 can be reduced. The thickness of the edge layer 104 is determined appropriately taking into consideration the dielectric strength and the manufacturing process of the transistor. It is possible.

[0048] If the gate insulating layer 104 satisfies the above hydrogen concentration and fluorine concentration, the gate insulating layer 104 is 02 can be used, but in this embodiment, plasma CVD (Pl asma Enhanced Chemical Vapor Deposition) The silicon oxide layer formed by this method will be described.

[0049] The plasma CVD method is a method in which deposition gases are supplied as raw materials to a reaction chamber in a plasma CVD device. The plasma CVD method uses plasma energy to form a film. For example, compared to sputtering, a film with better step coverage can be formed.

[0050] Plasma CVD equipment includes capacitively coupled high-frequency plasma CVD equipment that uses a high-frequency power source, and inductive Inductively coupled high-frequency plasma CVD equipment, magnetron and dielectric as microwave sources A microwave plasma CVD apparatus (electron Cyclotron resonance plasma CVD equipment) and other helicon wave plasma CVD equipment. In the plasma CVD method described in this specification, glow discharge plasma is used for film formation. In addition, the plasma CVD method involves heating the substrate while This can be done.

[0051] As the deposition gas to be used as the raw material, a gas that does not contain hydrogen in the composition formula is selected, and silicon oxide is In other words, fluorine (SiH4) is used as the deposition gas, not silane (SiH4). Silicon carbide (e.g., SiF4) or silicon chloride (e.g., SiCl4) is used. Nitrous oxide (N2O), which has a reduced content of hydrogen and water, is used as the oxidizing gas. Or oxygen, with other gases such as argon added to stabilize the plasma. The gas should also have a low content of hydrogen and water.

[0052] Furthermore, when forming a silicon oxide layer by plasma CVD, After removing impurities such as hydrogen and water remaining in the reactor or adsorbed on the inner wall of the reactor, The deposition gas is formed by using the gas having the above composition while heating the inner wall of the reaction chamber. When silicon fluoride is used, the hydrogen concentration of the gate insulating layer 104 is set to 6×10 20 atom s / cm 3 Less than 2 x 10 20 atoms / cm 3 Below, more preferably 5 x10 19 atoms / cm 3 The fluorine concentration is 1×10 19 atoms / cm 3 End , preferably 1 x 10 20 atoms / cm 3 It can be more than that.

[0053] In addition, when a silicon oxide layer containing fluorine is formed on the gate electrode layer 103, The resulting fluorine may etch the gate electrode layer 103, but the gate insulating layer This can be prevented by forming two or more insulating layers. The fluorine concentration of the first gate insulating layer is 1×10 19 atoms / cm 3 Less than preferred It's nice.

[0054] The second gate insulating layer in contact with the oxide semiconductor layer 106 is made of silicon tetrafluoride. The fluorine concentration of the silicon oxide layer used is 1×10 19 atoms / cm 3 That's all, I prefer 1×10 20 atoms / cm3 The insulating layer must be at least 100%. The gate insulating layer is made of silicon tetrafluoride or the like, and the second gate insulating layer is made of silicon oxide. For example, the first gate insulating layer may have a thickness that is not lost when the first gate insulating layer is formed. The insulating layer exemplified as the base insulating layer 102 can be used.

[0055] The oxide semiconductor layer 106 in which the channel region is formed is formed on and in contact with the gate insulating layer 104. The thickness of the oxide semiconductor layer 106 is 10 nm to 300 nm, preferably 20 nm to 100 nm.

[0056] The oxide semiconductor layer 106 is an In—Ga—Zn—O-based oxide containing In, Ga, and Zn. As the oxide semiconductor, other oxides include In-Sn, which is a quaternary oxide. -Ga-Zn-O system, ternary oxides such as In-Sn-Zn-O system and In-Al-Zn -O system, Sn-Ga-Zn-O system, Al-Ga-Zn-O system, Sn-Al-Zn-O system, , binary oxides such as In-Zn-O, In-Ga-O, Sn-Zn-O, and Al- Zn-O, Zn-Mg-O, Sn-Mg-O, In-Mg-O, and indium oxide The insulating layer can be formed using In—Ga, tin oxide, zinc oxide, or the like. The Zn-O oxide is an oxide containing at least In, Ga, and Zn. There is no particular limitation on the composition ratio, and elements other than In, Ga, and Zn may be contained.

[0057] The oxide semiconductor layer 106 has the chemical formula InMO3(ZnO) m (m>0) It can be formed using an oxide, where M is Ga, Al, Mn, or Co. For example, M may be Ga, Ga, and Examples include Al, Ga and Mn, or Ga and Co.

[0058] The source electrode layer 107a and the drain electrode layer 107b are formed by the gate insulating layer 104 and the oxide The source electrode layer 107a and the drain electrode layer 10 7b can be made of the same material and thickness as the gate electrode layer 103.

[0059] The insulating layer 108, which functions as a passivation film or an interlayer insulating film, is formed on the source electrode layer 1. The oxide semiconductor layer 106 is formed on and in contact with the drain electrode layer 107a, the drain electrode layer 107b, and the oxide semiconductor layer 106. The insulating layer 108 can be formed in the same manner as the gate insulating layer 104. Since the gate insulating layer 104 is in contact with a part of the top surface of the gate insulating layer 106, a silicon oxide layer similar to the gate insulating layer 104 is used. The migration of hydrogen from the insulating layer 108 to the oxide semiconductor layer 106 is suppressed, and the oxide semiconductor In order to inactivate or desorb hydrogen present in the oxide semiconductor layer 106, The hydrogen content in 06 can be reduced.

[0060] In the process of forming the insulating layer 108, the same process as that of the gate insulating layer 104 is performed. Similarly, the fluorine contained in the deposition gas causes the source electrode layer 107a and the drain electrode layer Therefore, the thickness of the insulating layer 108 is It should be decided appropriately taking into consideration the above.

[0061] The insulating layer 108 may be formed by a method capable of reducing the hydrogen content. Silicon oxide is formed by a silicon target or silicon oxide target. Preferably, a silicon oxide target, more preferably a silicon dioxide target, Preferably, the hydroxyl group concentration is 1000 ppm or less, or the hydrogen concentration is 3.5 × 10 1 9 atoms / cm 3 The silicon oxide target used is as follows: The gases to be supplied are a rare gas such as argon and oxygen. The gas to be used should have impurities such as hydrogen, water, hydroxyl groups or hydrides of 1 ppm or less, preferably 1 It is preferable to use a high purity gas that has been removed to below ppb.

[0062] The following describes how fluorine inactivates hydrogen present in the oxide semiconductor layer 106, or The effect of desorption is explained using quantum chemical calculations. The quantum chemical calculations shown below involve Gaussian Density Functional Theory (DFT) using Gaussian basis In density functional theory (DFT), exchange-correlation interactions are expressed in terms of electron density. The calculation is fast and highly accurate because it is approximated by a functional of the one-electron potential. In this embodiment, the mixed functional B3LYP is used to calculate the exchange and correlation energy. Define the weight of each parameter.

[0063] In addition, the basis functions applied to all atoms are three contraction functions for each valence orbital. The basis function of the triple split valence basis set is 6-311G. With this basis function, the 1s to 3s orbitals are taken into account for hydrogen atoms, and the 1s to 3s orbitals are taken into account for oxygen atoms. If present, the 1s-4s and 2p-4p orbitals are considered. As a polarization basis set, p-function is added to hydrogen atoms and d-function is added to atoms other than hydrogen atoms. The quantum chemistry calculation program used was Gaussian 09 manufactured by Conflex Corporation. There are.

[0064] In this embodiment, hydrogen atoms present in the oxide semiconductor layer 106 are substituted with oxygen atoms or metal atoms. Since the hydrogen-containing structure in the oxide semiconductor layer 106 is bonded to the α- 1) and structural formula (α-2). In (α-2), coordinate bonds are not taken into consideration, and only ionic bonds are taken into consideration. The oxide semiconductor layer 106 in the above-described In (indium) and Ga (gallium) and Zn (zinc), and the following structural formula (α-1) and structural formula (α-2) The metal atom shown in (α-2) is Ga (gallium).

[0065] [ka]

[0066] The reaction process of fluorine atoms with hydrogen in the oxide semiconductor layer 106 is as shown in (Equation 1). There are two reactions: the reaction shown in (Equation 2) and the reaction shown in (Equation 2).

[0067] Ga-OH + F →HF + Ga-O (Eq. 1)

[0068] Ga-H + F →HF + Ga (Eq. 2)

[0069] In formula 1, fluorine radicals react with the hydrogen atoms of hydroxyl groups to form HF (hydrogen fluoride) molecules. In formula (2), the fluorine radical reacts with the hydrogen atom bonded to the gallium atom. The reaction forms HF (hydrogen fluoride) molecules. " represents a radical.

[0070] In this quantum chemical calculation, the above structural formula (α-1) and structural formula (α-2) are A simple cluster model was used to calculate the activation energy for the above reaction. and evaluates the likelihood of a reaction occurring.

[0071] Quantum chemical calculations were performed on the reaction of (Equation 1), and the analyzed reaction path and energy diagram were The ram is shown in Figure 3.

[0072] In Figure 3, in the initial state (1), the hydroxyl group and the fluorine radical are assumed to be infinitely far apart. In the energy diagram, the energy of the initial state (1) is used as the reference. Intermediate (2) In this case, the fluorine radical approaches the gallium atom, breaking the Ga-O bond and forming a hydroxyl radical. This reaction produces a Ga-F bond, and the potential of intermediate (2) The energy is -1.67 eV.

[0073] In intermediate (3), the hydrogen atom of the hydroxyl radical combines with a fluorine atom to form an HF molecule. The activation energy, which is the difference in potential energy between intermediate (2) and intermediate (3), is The energy is calculated to be 0.61 eV. In intermediate (4), oxygen radicals and HF molecules interact with each other. They interact with each other, and in the final state (5), the oxygen radical and the HF molecule are infinitely far apart.

[0074] In reality, HF may be desorbed from the oxide semiconductor layer 106 or may remain there for some reason. Even if HF remains in the oxide semiconductor layer 106, the water in the HF molecule may Since the element is not bonded to the oxide semiconductor (i.e., is passivated), It does not become a carrier source for the conductor.

[0075] In intermediate (2), the fluorine radical approaches the gallium atom, forming the Ga-O bond. The bond energy of the Ga-O bond is 4.37 This is due to the fact that the bond energy of the Ga-F bond is 5.31 eV.

[0076] The bond energy of the Ga-O bond here is the state in which a hydroxyl group is bonded to a gallium atom. (See Figure 4(A)) and the hydroxyl radicals are infinitely far apart. This is the calculated value of the potential energy difference between the two states (see Figure 4(B)). The bond energy of the Ga-F bond is the state in which fluorine is bonded to a gallium atom (Figure 4( C)) and the potential energy of the fluorine radicals in the state where they are infinitely far apart ( This is the calculated value of the difference in potential energy between the two points (see Figure 4(D)).

[0077] The reaction of combining hydrogen and fluorine in the oxide semiconductor layer 106 shown in (Equation 1) starts from the initial state (1 The energy difference between the initial state (1) and the final state (5) indicates that this reaction is exothermic. It can be said that the reaction proceeds easily.

[0078] Next, quantum chemical calculations were performed on the reaction of (Equation 2), and the analyzed reaction path and energy diagram were The diagram is shown in Figure 5.

[0079] In Figure 5, in the initial state (1), the hydrogen atom and the fluorine radical are infinitely far apart. In the energy diagram, the energy of the initial state (1) is used as the reference. In (2), the fluorine radical approaches the gallium atom, breaking the Ga-H bond and forming a hydrogen radical. This reaction produces a Ga-F bond. The energy of the electrons is -1.99 eV.

[0080] In intermediate (3), a hydrogen radical combines with a fluorine atom to form an HF molecule. The activation energy, which is the difference in potential energy between (2) and intermediate (3), is 0. In intermediate (4), the oxygen atom bonded to the gallium atom and the HF The molecules are interacting, and in the final state (5), the HF molecules are separated by an infinite distance.

[0081] Similar to (Equation 1), in intermediate (2), when the fluorine radical approaches the gallium atom, G The reason why the a-H bond breaks and the Ga-F bond is formed is the same as explained in (Equation 1). In particular, the Ga-F bond is more stable than the Ga-H bond in terms of bond energy. This is due to the following.

[0082] In the reaction of desorbing hydrogen from the oxide semiconductor layer 106 shown in Formula 2, the initial state ( The energy difference between (1) and the final state (5) indicates that this is an exothermic reaction. It can be said that the reaction of desorbing the

[0083] As described above, hydrogen present in the oxide semiconductor layer 106 is inactivated by fluorine, or It can be detached.

[0084] Next, a method for manufacturing the semiconductor device shown in FIG. 1 will be described with reference to FIGS.

[0085] An insulating base layer 102 is formed on a substrate 101. The substrate 101 and the insulating base layer 102 are In this embodiment, a glass substrate is used as the substrate 101. The insulating base layer 102 can also be formed by plasma CVD. In the manufacturing method of the device, the target is silicon oxide, and the gas supplied during formation is argon, etc. A silicon oxide layer of 200 nm is formed by RF sputtering using rare gas and oxygen. .

[0086] Next, a conductive film that functions as a gate electrode layer 103 is formed. The device was fabricated using a DC sputtering method with a titanium target, with a thickness of 150 nm. A titanium film having a thickness of 1000 nm is then deposited. After that, a first photolithography step and an etching step are performed. This is carried out to form a gate electrode layer 103 having a thickness of 150 nm.

[0087] The conductive film may be etched by either wet etching or dry etching. From the viewpoint of miniaturization of elements, it is preferable to use dry etching. The etching gas and etching solution should be selected appropriately depending on the material to be etched. can.

[0088] Note that the side surface of the gate electrode layer 103 is preferably tapered. On the 3, a conductive film that will become an oxide semiconductor film, a source electrode layer, and a drain electrode layer in a later process is formed. Therefore, if the side surface of the gate electrode layer 103 is tapered, the alignment at the step portion is difficult. This is effective in preventing disconnection of the wire. To do this, etching may be performed while the resist mask is being recessed.

[0089] Next, the gate insulating layer 104 is formed by plasma CVD. The inner wall of the reaction chamber is heated to release impurities from the inner wall of the reaction chamber. The impurities released from the inner wall of the reaction chamber are removed by fluorine such as nitrogen trifluoride (NF3). The removal is performed by plasma cleaning using a fluorine compound. A capacitively coupled plasma CVD device using a power supply is used.

[0090] The temperature to which the inner wall of the reaction chamber in the plasma CVD device is heated is set to 100°C or higher and 350°C or lower. The temperature is preferably 100°C or higher and 125°C or lower, and the heating time is preferably at least 30 minutes or longer. It is preferable to carry out the heating process for 60 minutes or more. Also, this heating process should be carried out while evacuating the air. It is also possible.

[0091] There is no particular limitation on the plasma cleaning method. Regarding the method of generating plasma and cleaning in the reaction chamber where cleaning is performed, In this example, plasma is generated in advance outside the reaction chamber where cleaning is performed. The generated plasma is supplied to the reaction chamber to perform cleaning. It may also be training.

[0092] The plasma cleaning in the present semiconductor device manufacturing method includes a plasma processing step and an exhaust step. The specific plasma cleaning conditions are nitrogen trifluoride at 400sccm The pressure in the reaction chamber is kept between 10 Pa and 200 Pa. The electrode spacing is adjusted to 15mm to 60mm, and the frequency range is 13.56MHz to 60MHz. High frequency power supply: 500W to 2000W (power per unit electrode area (power density) As a result, it is 1W / cm 2 ~4W / cm 2 ) to generate plasma, and the The more preferable plasma cleaning conditions are nitrogen trifluoride and The gas was supplied into the reaction chamber at a flow rate of 600 sccm, the pressure in the reaction chamber was set to about 70 Pa, and the The pole spacing was adjusted to 50 mm, and the output was 900 W (converted to power density) at a 60 MHz high frequency power source. Approximately 1.8W / cm 2 ) for 7 minutes.

[0093] Then, silicon tetrafluoride is used as a deposition gas, and sulfurous acid is used as an oxidation gas. Nitrogen chloride and argon as an additive gas were supplied to the reaction chamber, and plasma energy was assisted. In addition, when the gate insulating layer 104 is formed as a two-layer structure, a silicon oxide film is formed to a thickness of 200 nm. The first gate insulating layer in contact with the gate electrode layer 103 is subjected to oxidation using silane as a deposition gas. A silicon film is formed to a thickness of 150 nm and deposited on the second gate insulating layer in contact with the oxide semiconductor layer 105. A silicon oxide film of 50 nm thickness can be formed by using silicon tetrafluoride as the reactive gas. The structure obtained in this process is shown in FIG. 6(A).

[0094] Next, a 50 nm thick oxide semiconductor film is formed by DC sputtering. The conductor film is formed in contact with the gate insulating layer 104, and therefore, the conductive film is formed in contact with the gate insulating layer 104. The fluorine in the oxide semiconductor film inactivates or releases hydrogen present in the oxide semiconductor film. Furthermore, oxygen is supplied from the gate insulating layer 104 to defects in the oxide semiconductor film. In this form, DC sputtering is used, but vacuum evaporation, pulsed laser deposition, CV It may be formed by using the D method or the like.

[0095] In the method for manufacturing a semiconductor device, In (indium), Ga (gallium), and Zn (zinc) ) containing oxide semiconductor target (molar ratio In2O3:Ga2O3:ZnO=1:1 :1, or In2O3:Ga2O3:ZnO=1:1:2) The semiconductor device uses an In-Ga-Zn-O-based oxide semiconductor film obtained by the above method. In the fabrication method, DC sputtering was used, the flow rate of argon was set to 30 sccm, and The flow rate of the raw material is set to 15 sccm.

[0096] Before the oxide semiconductor film was formed by a sputtering method, argon gas was introduced. It is preferable to perform reverse sputtering to generate plasma. In this method, a voltage is applied to the substrate side using an RF power supply in an atmosphere of argon, nitrogen, helium, etc. This is a method of forming plasma near the substrate and modifying the surface. It may be carried out in an atmosphere containing chlorine (Cl2), carbon tetrafluoride (CF4), etc. It may be carried out in a relaxed atmosphere.

[0097] When forming the oxide semiconductor film, the substrate temperature is set to 100° C. or higher and lower than 550° C., preferably 2 The substrate is heated to a temperature between 00°C and 400°C. In addition, a sputtering gas from which hydrogen and water have been removed is introduced, and the oxide semiconductor target is The oxide semiconductor film is formed by heating the substrate. This can further reduce moisture contained in the oxide semiconductor film. This can reduce damage caused by the gun.

[0098] To remove moisture from the processing chamber, it is preferable to use an adsorption type vacuum pump. For example, a cryopump, ion pump, or titanium sublimation pump can be used. Alternatively, a turbo pump with a cold trap may be used. By using a pump or other device to evacuate the chamber, hydrogen and water can be removed. Therefore, the concentrations of these elements in the oxide semiconductor film can be reduced.

[0099] Thereafter, a second photolithography process and an etching process are performed to form an island-shaped An oxide semiconductor layer 105 is formed. A structure obtained through the steps up to this point is shown in FIG.

[0100] Next, the sample is heated in an inert gas atmosphere (nitrogen, helium, neon, argon, etc.) or at a temperature below the dew point of the sample. The oxide semiconductor layer 1 is grown in a dry air atmosphere with a low moisture content, such as at a temperature of 60°C or less. For example, heat treatment may be performed at 100°C or higher and 400°C or lower for 10 minutes or longer. This can be done by heat treatment.

[0101] Heat treatment is carried out using an electric furnace, a GRTA (Gas Rapture Treatment) method using heated gas, etc. id Thermal Anneal (LRTA) method or lamp light Rapid Thermal Annealing (RTA) and other instantaneous heating methods can be used. For example, when heat treatment is performed using an electric furnace, the temperature rise rate can be set to 0.1°C / min. The temperature drop rate must be between 0.1℃ / min and 15℃ / min. It is preferable that:

[0102] In this method for manufacturing a semiconductor device, heat treatment is performed on the oxide semiconductor layer 105 to remove moisture and water. The oxide semiconductor layer 106 is formed from which the atoms are desorbed. The fluorine contained in 4 inactivates or deactivates hydrogen present in the oxide semiconductor film. Furthermore, oxygen is supplied from the gate insulating layer 104 to the defects in the oxide semiconductor layer 106. will be done.

[0103] In addition, under an inert gas atmosphere (nitrogen, helium, neon, argon, etc.), 00℃ to 750℃ (or a temperature below the distortion point of the glass substrate) for 1 minute to 10 minutes Preferably, the temperature is 600°C for 3 to 6 minutes. The RTA method can be used to perform thermal annealing in a short time. Since dehydration or dehydrogenation can be performed immediately, processing can be performed even at temperatures exceeding the strain point of the glass substrate. can be done.

[0104] In the heat treatment, an inert gas (nitrogen, helium, neon, argon, etc.) It is preferable that the rare gas does not contain moisture, hydrogen, etc. The purity of nitrogen or rare gases such as helium, neon, and argon is 6N (99.999%). 9%) or more, preferably 7N (99.99999%) or more (i.e., impurity concentration of 1 ppm It is preferable to set the concentration to 0.1 ppm or less.

[0105] Note that the heat treatment is not limited to that performed after the island-shaped oxide semiconductor layer 105 is formed, but may be performed after the island-shaped oxide semiconductor layer 105 is formed. The heat treatment may be performed on the oxide semiconductor film before the formation of the oxide layer 105. The heat treatment may be performed multiple times. After the heat treatment, the oxide semiconductor layer 106 may be partly crystallized. .

[0106] Here, the exposed surface of the oxide semiconductor layer 106 is treated with oxygen, ozone, or nitrous oxide. Plasma treatment may be performed. By performing the plasma treatment, defects in the oxide semiconductor layer 106 can be removed. The structure obtained through these steps is shown in Figure 6(C).

[0107] Next, a conductive film is formed, and a third photolithography step and an etching step are performed. The conductive film forms a source electrode layer 107a and a drain electrode layer 107b. In the method for manufacturing a semiconductor device, the titanium target A titanium film with a thickness of 150 nm was formed by DC sputtering using a laser. The source electrode layer 107a and the drain electrode layer 107b are formed by a lithography process and an etching process. Form 07b.

[0108] Then, the insulating layer 108 is formed. A silicon oxide layer having a thickness of 50 nm is formed using the same gas and method. After forming the layer 8, a heat treatment may be performed. The heat treatment may be performed in an inert gas atmosphere (nitrogen, The heating is preferably carried out under a temperature of 200°C or higher and 40°C or lower. It is recommended to do this at 0°C or below. Alternatively, you can also do the RTA treatment described above. The structure obtained through the process is shown in FIG. 6(D).

[0109] The structure described in this embodiment prevents diffusion of hydrogen into the oxide semiconductor layer 106. The hydrogen in the oxide semiconductor layer 106 can be deactivated or desorbed, and the A semiconductor device having favorable electrical characteristics can be obtained. The above configuration can be appropriately combined with the configurations shown in other embodiments in this specification.

[0110] (Embodiment 2) In this embodiment, silicon tetrafluoride is used as the deposition gas, and suboxide is used as the gas for oxidizing silicon tetrafluoride. Nitrogen was used as the gas for generating stable plasma, and argon was also used. Silicon oxide with a low hydrogen concentration obtained by the CVD method is used as the base insulation for top-gate transistors. An example of use as an edge layer will be described with reference to FIG.

[0111] An insulating base layer 202 containing silicon oxide as a main component is formed on a substrate 201. As mentioned above, 2 is formed by plasma CVD using silicon tetrafluoride. The method for forming the gate insulating layer 104 in Embodiment 1 can be referred to. Five times or more the sum of the thicknesses of the oxide semiconductor layer and the gate insulating layer to be formed subsequently It would be good if that were the case.

[0112] At such a thickness, the amount of fluorine that diffuses from the insulating underlayer is sufficient, so the oxide The hydrogen present in the semiconductor layer and the gate insulating layer is inactivated, or the oxide semiconductor layer The thickness of the insulating underlayer is greater than that of the oxide semiconductor layer and the gate insulating layer. If the thickness is less than twice the sum of the thicknesses of the edge layers, the amount of fluorine is insufficient to prevent such No effect is obtained.

[0113] Then, an In-Ga-Zn-O oxide film having a thickness of 10 to 30 nm is formed as an oxide semiconductor film. A film of oxide is formed by sputtering. Then, it is etched to form island-shaped oxide films. The semiconductor layer 203 is obtained. The oxide semiconductor layer 203 is subjected to heat treatment to reduce the hydrogen concentration. This state is shown in Figure 7(A).

[0114] Next, a conductive film is formed to cover the base insulating layer 202 and the oxide semiconductor layer 203. For example, a multilayer film of titanium and aluminum may be formed by sputtering. Then, this is etched to form a source electrode layer 204a and a drain electrode layer 204b. At this time, the relationship between the etching rate of the conductive film and the etching rate of the oxide semiconductor layer 203 is Therefore, the surface of the oxide semiconductor layer 203 may also be etched.

[0115] Here, fluorine and fluorine are used as the material for the bottom surfaces of the source electrode layer 204a and the drain electrode layer 204b. Reactive metallic materials (e.g. titanium, tungsten, molybdenum, aluminum or When a nitride thereof is used, the source electrode layer 204a and the drain electrode layer 204b However, it is preferable that the insulating base layer 202 is not in contact with the insulating base layer 202 .

[0116] The source electrode layer 204a and the drain electrode layer 204b made of these materials are formed on the insulating base layer 2. When the source electrode layer 204a and the drain electrode layer 202 come into contact with each other, a chemical reaction occurs at the interface. Therefore, as shown in FIG. 7(B), the source electrode layer 204a The drain electrode layer 204b is preferably provided only over the oxide semiconductor layer 203.

[0117] The bottom surfaces of the source electrode layer 204a and the drain electrode layer 204b are made of a material such as an oxide conductor. If the material is used, the above problem does not occur.

[0118] Furthermore, a base insulating layer 202, an oxide semiconductor layer 203, a source electrode layer 204a, a drain electrode layer 204b, and a The electrode layer 204b is covered with a silicon oxynitride film having a thickness of 10 to 30 nm by a plasma CVD method. The gate insulating layer 205 is formed by using the plasma CVD method. Therefore, a gate insulating film with excellent electrical conductivity can be obtained.

[0119] Here, it is preferable that the gas used does not contain fluorine or chlorine. When a gas having such a property is used, the source electrode layer 204a and the drain electrode layer 204b are etched during film formation. This is because there is a risk that the information may be used.

[0120] Therefore, it is preferable to use silane and ammonia as the deposition gas. The silicon oxynitride obtained by the above method contains a large amount of hydrogen. However, as mentioned above, These hydrogen atoms are inactivated because fluorine is supplied from the insulating underlayer 202 having a sufficient thickness. The state up to this point is shown in FIG. 7(B).

[0121] Next, a conductive film is formed to cover the gate insulating layer 205, and is etched to form a gate electrode. A gate electrode layer 206 is formed. A gate insulating layer 205 and a conductive film for forming a gate electrode layer are deposited. It is desirable to carry out the deposition continuously without exposing it to the atmosphere.

[0122] Then, an insulating layer of silicon oxide having a thickness of 100 to 300 nm is formed by plasma CVD. Then, an insulating layer 207 is deposited on the insulating layer 208, which has a flat surface, using an organic resin or the like. The layer 207 is also deposited in order to avoid etching of the gate electrode layer 206 during deposition. The reactive gas is silane or TEOS (tetraethoxysilane, Si(OC2H5 )4) is recommended.

[0123] Although a large amount of hydrogen is contained in the insulating layer 207, the insulating layer 207 and the channel region of the transistor The regions are separated by the gate electrode layer 206, which is less likely to cause reliability problems. To further improve reliability and prevent etching of the gate electrode layer 206, an insulating layer 207 is a multilayered first insulating layer having a thickness of 20 to 100 nm in contact with the gate electrode layer 206. The first insulating layer is formed using the above-mentioned silane or TEOS, and the second insulating layer above it is formed using fluoride. It may also be formed using silicon (for example, silicon tetrafluoride).

[0124] Finally, the gate insulating layer 205, the insulating layer 207, and the insulating layer 208 are covered with the source electrode layer 204a, A contact hole reaching the drain electrode layer 204b is provided, and the electrodes 209a and 209b are The state up to this point is shown in Figure 7(C).

[0125] By the above steps, a top-gate transistor can be fabricated. Although silicon fluoride is used as the deposition gas for the insulating layer 202, silicon chloride may also be used. It goes without saying that this embodiment can be combined with other embodiments.

[0126] (Embodiment 3) In this embodiment, silicon oxide having a low hydrogen concentration obtained by using silicon tetrafluoride as a deposition gas is used. An example of using this as a base insulating layer of a top-gate transistor will be explained with reference to Figure 8. do.

[0127] An insulating base layer 302 containing silicon oxide as a main component is formed on a substrate 301. As mentioned above, 2 is formed by plasma CVD using silicon tetrafluoride. The method for forming the gate insulating layer 104 in Embodiment 1 can be referred to. Five times or more the sum of the thicknesses of the oxide semiconductor layer and the gate insulating layer to be formed subsequently It would be good if that were the case.

[0128] Then, an In—Ga—Zn—O based oxide semiconductor film having a thickness of 10 to 30 nm is formed as an oxide semiconductor film 303. A conductive film 3 is formed by sputtering to cover the oxide semiconductor film 303. As the conductive film, for example, a tungsten film is formed by sputtering. That's fine.

[0129] Furthermore, a resist is applied onto the conductive film 304, and photolithography is performed using a multi-tone mask. A resist mask 305 having at least two portions with different thicknesses formed by a patterning method. The state up to this point is shown in Figure 8(A).

[0130] Then, the first etching is performed using this resist mask 305. By adiabatic dry etching, the conductive film 304 and the portion not covered with the resist mask are removed. The first etching is performed on the oxide semiconductor film 303. The first etching is performed on the oxide semiconductor film 303. A conductive layer 303a and a conductive layer 304a having substantially the same shape as the conductive layer 303a are obtained (see FIG. 8(B)).

[0131] In the dry etching, the resist mask 305 is also etched, and the resist mask 305 is removed as shown in FIG. As shown in FIG. 1, the resist mask 305 is separated into two resist masks 305a and 305b. On the other hand, etching of the resist mask 305 does not occur in wet etching. Furthermore, even in dry etching, depending on the conditions, the resist mask 305 is hardly etched. In such cases, a separate ashing process is performed. The resist mask 305 is etched to have a shape as shown in FIG. 8(B).

[0132] Next, a second etching is performed using two resist masks 305a and 305b. This etching is required to selectively etch the conductive layer 304a. In addition, a method is adopted in which the side surface of the conductive layer 304a after etching is tapered. In this manner, the source electrode layer 304b and the drain electrode layer 304c are obtained. (See FIG. 8(C)).

[0133] The source electrode layer 304b and the drain electrode layer 304c are obtained by forming the base insulating layer 302. In the process up to this stage, a multi-tone mask is used, so the pattern can be formed in one photolithography process. In contrast, in the second embodiment, the source electrode layer 204a and the drain electrode layer 2 Two photolithography steps are required to obtain 04b.

[0134] In the second embodiment, in order to form the oxide semiconductor layer 203, an oxide semiconductor In the conventional method, it was necessary to apply a resist to the oxide semiconductor film 3. No resist is applied to the oxide semiconductor layer 303a. The surface of the body layer 303a can be kept clean.

[0135] As is clear from the above process, the source electrode layer 304b and the drain electrode layer 304c Since the insulating film 303 is formed only on the oxide semiconductor layer 303a, it is not in contact with the base insulating layer 302. do not have.

[0136] Furthermore, a base insulating layer 302, an oxide semiconductor layer 303a, a source electrode layer 304b, a drain electrode layer 304b, and a The electrode layer 304c is covered with a silicon oxynitride film having a thickness of 10 to 30 nm by a plasma CVD method. A gate insulating layer 306 made of the above is formed. The state up to this point is shown in FIG.

[0137] Next, a conductive film is formed to cover the gate insulating layer 306, and is etched to form a gate electrode. Then, a pole layer 307 is formed by sputtering to a thickness of 100 to 300 nm. An insulating layer 308 made of silicon oxide is deposited, and then an insulating layer with a flat surface is formed by organic resin or the like. Then, the gate insulating layer 306, the insulating layer 308 and the insulating layer 309 are subjected to a soaking. Contact holes are provided to reach the source electrode layer 304b and the drain electrode layer 304c. Electrode 310a and electrode 310b are formed. The state up to this point is shown in FIG.

[0138] By the above steps, a top-gate transistor can be fabricated. Although silicon fluoride is used as the deposition gas for the insulating layer 302, silicon chloride may also be used. It goes without saying that this embodiment can be combined with other embodiments.

[0139] (Fourth embodiment) In this embodiment, silicon oxide having a low hydrogen concentration obtained by using silicon tetrafluoride as a deposition gas is used. as an insulating base layer for a top-gate transistor provided on a multilayer wiring circuit. This will be explained with reference to FIG.

[0140] Wiring 402a and wiring 402b are provided on substrate 401. 402b is not limited to a simple wiring, but may be a gate voltage of a transistor provided on the substrate 401. It may be a polar layer, a source electrode, a drain electrode, or wiring extending from them. That is, even if a transistor using a semiconductor material such as silicon is provided on the substrate 401, good.

[0141] The wiring 402a and the wiring 402b are covered with a silicon nitride oxide film by a plasma CVD method. A silicon nitride oxide film 403 is formed. It is preferable that the silicon nitride oxide film 403 contains an appropriate amount of hydrogen. The silicon nitride oxide film 403 is used to separate the wiring 402a, the wiring 402b, and the surface of the substrate 401. By covering the transistor, hydrogen can be supplied to the transistor. If the transistor is made of silicon or germanium, hydrogen will damage the semiconductor. It is possible to terminate dangling bonds in the conductor material, improving transistor characteristics. This can be done.

[0142] The thickness of the silicon nitride oxide film 403 is preferably determined taking into consideration several factors. First, it must be determined taking into consideration the effect of hydrogenation. Thus, the silicon nitride oxide film 403 also serves as an etching stopper in the planarization process. Thirdly, in the etching process after planarization, Since the insulating layer (formed on the silicon nitride oxide film 403) is etched together with the insulating layer, The difference in etching rate between the insulating layer and the silicon nitride oxide film 403 does not impair flatness. It is necessary to be at a certain level.

[0143] From the first and second requirements, it is desirable that the silicon nitride oxide film 403 be thick. Considering these factors, the thickness of the silicon nitride oxide film 403 is The thickness may be, for example, 50 to 200 nm.

[0144] Next, a base insulating layer 404 containing silicon oxide as a main component is formed. As shown in the figure, it is formed using silicon tetrafluoride by the plasma CVD method. This allows the wiring 402a and the wiring 402b to be formed with good step coverage on their side surfaces. The thickness of the edge layer 404 is determined by the thickness of the oxide semiconductor layer and the gate insulating layer that are subsequently formed. The thickness of the base insulating layer 404 is preferably five times or more the sum of the thicknesses of the layers 402 and 403. It is advisable to make the film thicker in anticipation of this. Shown below.

[0145] Thereafter, the insulating base layer 404 is planarized by a known chemical mechanical polishing (CMP) method. This etching process can be stopped when the silicon nitride oxide film 403 is exposed. Silicon oxide has a lower etching rate in the CMP method than silicon dioxide, This is because the insulating base layer 40 functions as a topper. The state up to this point is shown in FIG. 9(B). 4 is divided by the silicon nitride oxide film 403 (base insulating layer 404a). The surface is almost flat.

[0146] Thereafter, the silicon nitride oxide film 403 and the base insulating layer 404a are roughly removed by dry etching. The same thickness is etched to obtain a flat surface. At this stage, the etching is stopped when the surface of the insulating base layer 404a is exposed. The state is changed to that shown by 404b in FIG. 9(C).

[0147] Thereafter, a top-gate transistor is fabricated in the same manner as in the second and third embodiments. That is, an In-Ga-Zn-O based film having a thickness of 10 to 20 nm is formed by oxidation. A compound semiconductor layer 405 is formed, and a source electrode layer 406a and a drain electrode layer 406b are formed thereon. Furthermore, a gate insulating layer 407 is formed (see FIG. 9C).

[0148] Here, the oxide semiconductor layer 405 is in contact with the wiring 402a and the source electrode layer 406a. The source electrode layer 402a and the source electrode layer 406a overlap with each other with the oxide semiconductor layer 405 interposed therebetween. When an oxide semiconductor and a conductor are in ohmic contact, the oxide semiconductor In the region up to a depth of about 10 nm, the carrier concentration is 1×10 19 / cm 3 degree or Since the thickness is more than this, the wiring 402 is substantially the same as the wiring 402 although the oxide semiconductor layer 405 is present therebetween. a and the source electrode layer 406a can be considered to be electrically connected.

[0149] To achieve ohmic contact, the wiring 402a and the source electrode layer 406a are made of an oxide semiconductor. It is necessary to make an ohmic contact at the interface with the wiring 402. The work function of the oxide semiconductor layer 405 is It is preferable to use a material having an electron affinity smaller than that of the oxide semiconductor layer 405. For example, In the case of an In-Ga-Zn-O oxide semiconductor, the electron affinity is about 4.3 eV. Therefore, titanium or titanium nitride is preferably used. The same applies to 6b.

[0150] Next, a conductive film is formed to cover the gate insulating layer 407, and is etched to form a gate electrode. Then, an insulating layer 409 made of silicon nitride and a surface layer made of organic resin or the like are formed. A flat insulating layer 410 is formed. Then, the insulating layer 410 is formed on the gate insulating layer 407 and the insulating layer 409. The layer 410 is provided with contact holes that reach the source electrode layer 406a and the drain electrode layer 406b. Electrodes 411a and 411b are formed by providing a conductive film 411b on the insulating film 411. The state up to this point is shown in FIG.

[0151] Through the above steps, a top-gate transistor can be manufactured. It can be combined with the embodiments.

[0152] (Embodiment 5) The transistor described in the above embodiment is manufactured, and the transistor is used in a pixel portion and a driving By using the semiconductor device in an operating circuit, a semiconductor device (also called a display device) having a display function can be manufactured. In addition, a part or the whole of a driver circuit using a transistor may be formed on the same substrate as the pixel portion. Furthermore, the above-described embodiment can be applied to the formation of a body and a system on panel. A semiconductor device including a memory cell is manufactured using a transistor using an oxide semiconductor material. It is also possible.

[0153] The display device includes a display element. The display element includes a liquid crystal element (also called a liquid crystal display element), a light-emitting element, A light-emitting element (also called a light-emitting display element) can be used. This category includes elements whose brightness is controlled by the light emitted from the light source, specifically inorganic EL (Electroluminescent) Also, electronic inks and other electronic devices are also included. A display medium whose contrast changes due to mechanical action can also be applied.

[0154] The display device also includes a panel in which a display element is sealed, and a controller for the panel. Furthermore, the display device is manufactured by a method for manufacturing the display device. In the process, the element substrate corresponds to one form before the display element is completed, and the element substrate is Each of the plurality of pixels includes a means for supplying a current to the display element. The pixel electrode of the display element may be formed only, or the conductive film that becomes the pixel electrode may be formed. may be in a state after forming the first insulating film 101 and before etching to form the pixel electrode. All forms apply.

[0155] In this specification, the term "display device" refers to an image display device, a display device, or an optical device. It also refers to connectors, such as FPC (Flexible Printed Circuit) integrated circuit) or TAB (Tape Automated Bon ding) tape or TCP (Tape Carrier Package) Modules with printed wiring boards attached to the end of TAB tape or TCP or the display element is mounted on an IC (integrated circuit) using the COG (Chip On Glass) method. The display device also includes all modules in which the display device (circuit) is directly mounted.

[0156] (Sixth embodiment) A display including a transistor manufactured by the manufacturing method of a transistor described in the above embodiment. The device can be applied to electronic paper that displays images by driving electronic ink. The printer can be used in any electronic device that displays information. For example, electronic paper can be used to display electronic books, posters, digital signs, etc. Names, PIDs (Public Information Displays), trains, etc. This can be applied to in-vehicle advertisements, displays on various cards such as credit cards, etc. An example of an electronic device is shown in Figure 11.

[0157] The electronic book 501 in FIG. 11 is composed of two housings, housing 502 and housing 503. The housing 502 and the housing 503 are integrated by a shaft portion 508. This structure allows the book to move like a paper book. It becomes possible to perform the work.

[0158] The housing 502 incorporates a display unit 504 and a photoelectric conversion device 505, and the housing 503 incorporates a display The display unit 504 and the display unit 506 are incorporated. The screen may be configured to display one continuous screen, or different screens. By configuring the display to display different screens, for example, the display on the right side (display unit 504 in FIG. 11) ) and an image can be displayed on the left display section (display section 506 in FIG. 11). Cut.

[0159] 11 shows an example in which the housing 502 is provided with an operation unit and the like. 2, it is provided with a power switch 509, operation keys 510, a speaker 511, etc. The page can be turned using the operation keys 510. The device may be configured to include a keyboard, a pointing device, etc. , external connection terminals (earphone terminal, USB terminal, or AC adapter and USB cable) A configuration including a terminal that can be connected to various cables such as a recording medium insertion section, Furthermore, the electronic book 501 may be configured to have a function as an electronic dictionary. .

[0160] The electronic book 501 may also be configured to be capable of transmitting and receiving information wirelessly. It is also possible to purchase and download desired book data from the child book server. It is possible.

[0161] (Embodiment 7) The semiconductor device disclosed in this specification can be applied to various electronic devices (including gaming machines). The electronic device can be, for example, a television device (television or television receivers), computer monitors, digital cameras and digital video cameras cameras, digital photo frames, mobile phones (also called mobile phones or mobile phone devices), ), portable game machines, personal digital assistants, audio playback devices, large game machines such as pachinko machines, etc. There is.

[0162] A television set 512 in FIG. 12A has a display unit 514 built in a housing 513. The display unit 514 can display images. The configuration shows that the housing 513 is supported by 515.

[0163] The television device 512 can be operated using an operation switch provided on the housing 513 or a separate remote control. This can be done by the operation device 518. The operation keys 51 provided on the remote control operation device 518 7, the channel and volume can be controlled, and the image displayed on the display unit 514 can be adjusted. The image can be operated by the remote control 518. A display unit 516 for displaying information output from the

[0164] The television device 512 is configured to include a receiver, a modem, etc. It can receive general television broadcasts and can also receive wired or wireless signals via a modem. By connecting to a communication network, it can be one-way (sender to receiver) or two-way It is also possible to communicate information in both directions (between a sender and a receiver, or between receivers). be.

[0165] A digital photo frame 519 in FIG. 12B has a display unit 521 built into a housing 520. The display unit 521 is capable of displaying various images, for example, a digital camera image. By displaying image data taken with a camera or other device, it can function like a regular photo frame. This can be done.

[0166] The digital photo frame 519 has an operation unit, an external connection terminal (USB terminal, USB A configuration including a terminal that can be connected to various cables, a recording medium insertion section, etc. These components may be incorporated on the same surface as the display unit, but may also be provided on the side or back. For example, it is preferable to use a recording medium for a digital photo frame. Insert a memory that stores image data taken with a digital camera into the insertion section. The captured image data can be displayed on the display unit 521.

[0167] The digital photo frame 519 may also be configured to be capable of transmitting and receiving information wirelessly. It is also possible to configure the device to wirelessly import and display desired image data.

[0168] FIG. 13 is a perspective view showing an example of a portable computer. The display shows the hinge unit connecting the upper housing 522 and the lower housing 523 in a closed state. An upper housing 522 having a keyboard 524 and a lower housing 523 having a keyboard 525 are stacked together. It is convenient to carry and can be easily operated by the user. In this case, the hinge unit is opened and the input operation is performed while looking at the display unit 524. It is possible.

[0169] The lower housing 523 also includes a keyboard 525 and a pointing device for inputting data. If the display unit 524 is a touch input panel, a part of the display unit Input operations can also be performed by touching the screen. The lower housing 523 has a computing function unit such as a disk. It has an external connection port 526 into which a communication cable conforming to the communication standard is inserted.

[0170] The upper housing 522 further includes a display unit 528 that can be slid into the upper housing 522 and stored therein. It has a large display screen. The orientation of the screen can be adjusted by the user. The retractable display unit 528 can also be used as a touch input panel. If you do this, you can perform input operations by touching part of the retractable display unit.

[0171] The display unit 524 or the retractable display unit 528 may be a liquid crystal display panel, an organic light emitting element, or an infrared light emitting element. A video display device such as a light-emitting display panel with a light-emitting element is used.

[0172] The portable computer shown in FIG. 13 is equipped with a receiver and can receive television broadcasts. The image can be displayed on the display unit 524 or the display unit 528. The hinge unit connecting the main body 522 and the lower housing 523 is closed, and the display unit 52 Slide the 8 to expose the entire screen, and adjust the screen angle to watch TV. The hinge unit can be opened to prevent the display unit 524 from displaying anything, and the TV It only activates the circuitry that displays the broadcast, so it consumes the minimum amount of power. This is useful in portable computers with limited battery capacity. [Example]

[0173] The gate insulating layer 104, the gate insulating layer 205, and the gate insulating layer 3 described in the above embodiment 06, gate insulating layer 407, insulating layer 108, base insulating layer 202, base insulating layer 302, and A silicon oxide film (sample A) that can be used as the insulating base layer 404 was fabricated. The results of evaluation of the hydrogen concentration and fluorine concentration are shown in FIG.

[0174] The method for fabricating sample A will be explained. Sample A was fabricated using the plasma CVD method. The inner wall temperature of the reaction chamber of the Zuma CVD device was heated to 115°C for 60 minutes. The gas containing impurities remaining or adsorbed on the catalyst was released.

[0175] Next, nitrogen trifluoride (NF3) was supplied into the reaction chamber at a flow rate of 600 sccm. The pressure was set to about 70 Pa, the gap was adjusted to 50 mm, and a 60 MHz high frequency power source was used. A power of 900 W was output for 7 minutes, and the inner wall of the reaction chamber was heated to 115°C. Cleaning was performed to remove gases containing impurities. The electrode area in the VD device is 490 cm 2 is.

[0176] After plasma cleaning, the inner wall temperature of the reaction chamber was heated to 115°C, and silicon oxide was removed. A film was formed on the wafer with a target thickness of 200 nm. Silicon fluoride was used at a flow rate of 6 sccm, and nitrous oxide was used as an additive gas at a flow rate of 1000 sccm. Argon was supplied as an inert gas into the reaction chamber at a flow rate of 1000 sccm. The pressure is adjusted to 133 Pa, the gap is adjusted to 10 mm, and a silicon oxide film is formed. The temperature of the silicon wafer was adjusted to 400°C, and the wafer was heated with a 60MHz high frequency power supply at 800W. A silicon oxide film was formed.

[0177] Next, the SIMS measurement results for sample A are shown in FIG. 10. In FIG. 10, the vertical axis is The horizontal axis represents the hydrogen concentration or fluorine concentration contained in sample A, and the horizontal axis represents the silicon oxide film surface of sample A. The hydrogen concentration profile of sample A is shown by a solid line. The fluorine concentration profile of sample A is shown by the dashed line. The quantitative range is 20 nm, and the horizontal axis indicates silicon wafers above 200 nm.

[0178] From Figure 10, the hydrogen concentration of sample A is 3.4 × 10 within the quantitative range. 19 atoms / c m 3 The fluorine concentration of sample A is 9.2 × 10 in the quantitative range. 20 atom s / cm 3 It was confirmed that this was the case.

[0179] Hydrogen release is suppressed, and hydrogen present in the oxide semiconductor layer is inactivated or desorbed. It has been found that the silicon oxide film that can be deposited has the above hydrogen concentration and fluorine concentration. Ta.

[0180] The silicon oxide film shown in this example is used as the gate insulating layer 104, the gate insulating layer 205, and the gate insulating layer 206. layer 306, gate insulating layer 407, insulating layer 108, underlying insulating layer 202, underlying insulating layer 302, By using the above-mentioned compound for the base insulating layer 404, a semiconductor device having favorable electrical characteristics can be manufactured. It is possible. [Explanation of symbols]

[0181] 101 Substrate 102 Undercoat insulation layer 103 gate electrode layer 104 Gate insulating layer 105 Oxide semiconductor layer 106 Oxide semiconductor layer 107a Source electrode layer 107b Drain electrode layer 108 Insulating layer 201 Substrate 202 Undercoat insulation layer 203 Oxide semiconductor layer 204a Source electrode layer 204b Drain electrode layer 205 Gate insulating layer 206 gate electrode layer 207 Insulating layer 208 Insulating layer 209a electrode 209b Electrode 301 Substrate 302 Undercoat insulation layer 303 Oxide semiconductor film 303a Oxide semiconductor layer 304 Conductive film 304a conductive layer 304b Source electrode layer 304c Drain electrode layer 305 Resist mask 305a resist mask 305b resist mask 306 Gate insulating layer 307 Gate electrode layer 308 Insulation Layer 309 Insulation Layer 310a electrode 310b electrode 401 Substrate 402a wiring 402b wiring 403 Silicon oxynitride film 404 Undercoat insulation layer 404a Undercoat insulation layer 404b Undercoat insulation layer 405 Oxide semiconductor layer 406a Source electrode layer 406b Drain electrode layer 407 Gate insulating layer 408 gate electrode layer 409 Insulating Layer 410 Insulating layer 411a electrode 411b Electrode 501 e-books 502 Case 503 Case 504 Display section 505 Photoelectric conversion device 506 Display section 507 Photoelectric conversion device 508 Shaft 509 Power Switch 510 Operation Key 511 Speaker 512 Television equipment 513 Case 514 Display section 515 Stand 516 Display section 517 Operation Key 518 Remote Controlled Machine 519 Digital Photo Frame 520 chassis 521 Display section 522 Upper housing 523 Lower housing 524 Display section 525 keyboard 526 external connection port 527 Pointing Device 528 Display section

Claims

[Claim 1] A substrate; a first insulating layer on the substrate; an oxide semiconductor layer on the first insulating layer; a second insulating layer having a region functioning as a gate insulating layer on the oxide semiconductor layer; a first conductive layer on the second insulating layer, the first conductive layer having a region that functions as a gate electrode, a thickness of the first insulating layer is more than twice the sum of a thickness of the oxide semiconductor layer and a thickness of the second insulating layer; 1. A semiconductor device comprising: a first insulating layer having a region in which the concentration of fluorine is 1×10 19 atoms / cm 3 or more;

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