semiconductor memory device

Abstract

There is room for further consideration regarding access to each memory cell in the semiconductor device. [Solution] A semiconductor memory device includes a memory array and a read / write circuit. The memory array includes a plurality of memory cells. The read / write circuit reads and writes data from and to any of the memory cells. The semiconductor memory device also includes a plurality of first word lines, a first memory area, and a second memory area.

Description

[Technical Field]

[0001] The invention disclosed in this specification relates to a semiconductor memory device. [Background technology]

[0002] 2. Description of the Related Art Conventionally, there are semiconductor memory devices that are capable of reading and writing data in a nonvolatile manner.

[0003] As an example of the related prior art, Patent Document 1 can be mentioned. [Prior art documents] [Patent documents]

[0004] [Patent Document 1] Japanese Patent Application Publication No. 2019-087551

[0005] [overview] The semiconductor device disclosed in Patent Document 1 leaves room for further consideration regarding access to each memory cell.

[0006] The semiconductor memory device disclosed herein includes a memory array and a read / write circuit. The memory array includes a plurality of memory cells and is configured to be able to read and write data from and to each of the memory cells. The read / write circuit is configured to supply a control voltage to any of the memory cells to write data to or read data stored in any of the memory cells. The memory array includes a first storage area including a plurality of memory cells and configured to apply the control voltage to the plurality of memory cells via a plurality of first word lines and a plurality of bit lines, and a second storage area including a plurality of memory cells and configured to apply the control voltage to the plurality of memory cells via second word lines separate from the first word lines and the bit lines. [Brief explanation of the drawings]

[0007] [Figure 1]FIG. 1 is a block diagram showing the overall configuration of a semiconductor memory device 100. As shown in FIG. [Figure 2] FIG. 2 is a diagram showing the internal configuration of the memory array 1. As shown in FIG. [Figure 3] FIG. 3 is a diagram showing the configuration of the read / write circuit 2. As shown in FIG. [Figure 4] FIG. 4 is a timing chart of serial signals exchanged between an external device (for example, a central processing circuit such as a microcomputer) and the semiconductor memory device 100. In FIG. [Figure 5] FIG. 5 is a timing chart of serial signals exchanged between an external device and the semiconductor memory device 100. In FIG. [Figure 6] FIG. 6 is a diagram showing a modified example of the semiconductor memory device 100. In FIG.

[0008] [Detailed explanation] <Overall Configuration of Semiconductor Storage Device 100> First, the overall configuration of the semiconductor memory device 100 of the present disclosure will be described. The semiconductor memory device 100 of this configuration example is configured to be able to write / read data in a non-volatile manner. The semiconductor memory device 100 is, for example, an EEPROM (Electrically Erasable Programmable Read-Only Memory).

[0009] 1 is a block diagram showing the overall configuration of a semiconductor memory device 100. As shown in FIG.

[0010] The memory array 1 includes a main storage area 8 and a trimming information storage area 9.

[0011] The main memory area 8 is a main write destination area for data written to the semiconductor memory device 100. Data written to the semiconductor memory device 100 from outside is basically written to the main memory area 8.

[0012] The trimming information storage area 9 is a storage area allocated as a redundant area for the main storage area 8. Trimming information is stored in advance in the trimming information storage area 9. The trimming information is information relating to manufacturing variations in the semiconductor storage device 100. The trimming information is used during trimming operations, which will be described later. The trimming information storage area 9 has a smaller storage capacity than the main storage area 8.

[0013] The main storage area 8 and the trimming information storage area 9 are configured to include a plurality of memory cells 7, word lines W1 to Wm, and bit lines B1 to Bn.

[0014] The word lines W1 to Wm are m gate lines laid out in the X-axis direction (m is a natural number equal to or greater than 1). The bit lines B1 to Bn are n bit lines laid out in the Y-axis direction (n is a natural number equal to or greater than 1). The memory cells 7 are arranged in an m×n matrix along the word lines W1 to Wm and bit lines B1 to Bn.

[0015] The trimming information storage area 9 is configured to include a smaller number of memory cells 7 than the main storage area 8. For example, the trimming information storage area 9 is made up of memory cells 7 arranged in a plurality of columns and one row.

[0016] The read / write circuit 2 is configured to supply a control voltage Vx and a control voltage Vy to the memory array 1 to write / read data to / from any one of the memory cells 7. Here, this any one of the memory cells 7 (i.e., the one to be accessed) may be referred to as a selected cell 7b. The selected cell 7b may be a single memory cell 7 or multiple memory cells 7.

[0017] The control voltage Vx here is defined as a general term that includes the write voltage supplied when writing data to each memory cell 7 and the read voltage supplied when reading data stored in each memory cell 7. Similarly, the control voltage Vy is defined as a general term that includes the write voltage and the read voltage.

[0018] The specific configuration of the read / write circuit 2 is as follows: The read / write circuit 2 includes an X decoder 3, a Y decoder 4, a sense amplifier 5, and a controller 6.

[0019] The controller 6 controls the X decoder 3 and the Y decoder 4 so as to supply the control voltages Vx and Vy to the selected cell 7b.

[0020] In response to an instruction (control signal) from the controller 6, the X decoder 3 selects one of the word lines W1 to Wm that corresponds to the cell address of the selected cell 7b and supplies the control voltage Vx to the selected word line. Here, the selected word line W1 to Wm is also simply referred to as the selected word line. The control voltage Vx is supplied to the memory array 1 via the selected word line.

[0021] The Y decoder 4 selects one of the bit lines B1 to Bn corresponding to the cell address of the selected cell 7b in response to an instruction (=control signal) from the controller 6, and supplies the control voltage Vy to the selected bit line B1 to Bn. Here, the selected bit line B1 to Bn is also simply referred to as the selected bit line. The control voltage Vy is supplied to the memory array 1 via the selected bit line.

[0022] In this way, both the control voltages Vx and Vy are supplied to the selected cell 7b via the selected word line and the selected bit line. This allows data to be written to / read from the selected cell 7b. At this time, one or both of the control voltages Vx and Vy are not supplied to memory cells 7 other than the selected cell 7b. Therefore, data is not written to / read from (i.e., accessed by) the memory cells 7 other than the selected cell 7b.

[0023] The sense amplifier 5 is connected to each memory cell 7. The sense amplifier 5 detects whether or not a drain current is flowing in the selected cell 7b. If a drain current is flowing, it detects that bit data "1" has been written in the selected cell 7b. If no drain current is flowing, it detects that bit data "0" has been written in the selected cell 7b.

[0024] <About write / read operations> The operation of writing data to the selected cell 7b (write operation) is as follows: In response to a write command input from outside the device, the controller 6 controls each part of the device (X decoder 3, Y decoder 4, etc.) and writes the requested data to the memory array 1. Specifically, the controller 6 controls the X decoder 3 and Y decoder 4 to supply a control voltage Vx to the selected word line and a control voltage Vy to the selected bit line.

[0025] At this time, the controller 6 controls the writing of data after performing trimming. Specifically, the controller 6 accesses the trimming information storage area 9 via the X decoder 3, Y decoder 4, and sense amplifier 5, and reads out the trimming information. Based on the read trimming information, the controller 6 then adjusts the control voltages Vx and Vy to eliminate variations between products, and writes the data into the selected cell 7b.

[0026] The operation of reading data from the selected cell 7b (read operation) is as follows: In response to a read command input from outside the device, the controller 6 controls each part of the device (X decoder 3, Y decoder 4, sense amplifier 5, etc.) to read the requested data from the memory array 1 and output it to the outside of the device. Specifically, the controller 6 controls the X decoder 3 and Y decoder 4 to supply a control voltage Vx to the selected word line and a control voltage Vy to the selected bit line.

[0027] <Considerations about defective chips> Incidentally, the semiconductor memory device described above (corresponding to the semiconductor memory device 100) has been trending toward larger capacities. Along with this trend, the ratio of the area occupied by the memory array (corresponding to the memory array 1) to the chip area of ​​the semiconductor memory device has also been increasing.

[0028] Here, if a foreign substance (e.g., a particle, etc.) adheres to a memory cell (corresponding to memory cell 7) in a fabrication process included in the front-end of the semiconductor manufacturing process, there is a risk of bit corruption in this memory cell. When a memory cell with bit corruption is accessed (when a write operation / read operation is performed), there is a risk of unexpected errors, etc. occurring. For this reason, a semiconductor memory device including a memory cell with bit corruption is treated as a defective chip and is discarded or otherwise disposed of depending on the degree of defect.

[0029] In the above-mentioned large-capacity semiconductor memory devices, the number of memory cells increases due to an increase in the area of ​​the memory array. Such semiconductor devices are prone to containing memory cells with corrupted bits. As a result, there is a risk that such large-capacity semiconductor memory devices will experience a decrease in yield due to disposal processing and an increase in chip disposal losses.

[0030] To address such problems, the semiconductor memory device 100 of the present disclosure is capable of suppressing a decrease in yield and an increase in waste loss. The following describes in detail the characteristic features of the semiconductor memory device 100 of the present disclosure.

[0031] <Detailed Configuration of Semiconductor Storage Device 100> Fig. 2 is a diagram showing the internal configuration of the memory array 1. Fig. 2 shows a case where the selected cell 7b and the defective cell 7a match. As shown in Fig. 2, the memory array 1 of the present disclosure includes a redundancy area 10 in addition to the main storage area 8 and trimming information storage area 9 described above.

[0032] The redundant area 10 is a redundant area for the main memory area 8, separate from the trimming information memory area 9. The redundant area 10 has a smaller storage capacity than the main memory area 8. In other words, the cell area of ​​the redundant area 10 is smaller than the cell area of ​​the main memory area 8. For example, the redundant area 10 consists of multiple columns (here, n columns) x 1 row of memory cells 7.

[0033] Each memory cell 7 in the redundant region 10 is connected to a word line Wm. Each memory cell 7 in the redundant region 10 is connected to a bit line B1 to Bn. The bit lines B1 to Bn are commonly connected to each memory cell 7 included in the main memory region 8, the trimming information memory region 9, and the redundant region 10.

[0034] Specifically, for example, bit line B1 is connected in parallel to the memory cells 7 in the first column in all areas of the main storage area 8, trimming information storage area 9, and redundant area 10. The same is true for bit lines B2 to Bn.

[0035] The memory cells 7 included in the main storage area 8 are connected to word lines W2 to Wm-1. The word line Wm is connected to the memory cells 7 included in the trimming information storage area 9.

[0036] The trimming information storage area 9 stores defect information in addition to the above-mentioned trimming information. The defect information is information (e.g., the cell address of the defective cell 7a) of the defective cells 7a among the memory cells 7 included in the memory array 1, in which a defect (such as a corrupted bit) has occurred. For ease of explanation, the defective memory cells 7a among the memory cells 7 are referred to as defective cells 7a. The defective cell 7a may be understood to refer to a single memory cell 7 or may be understood as a collective term for multiple memory cells 7.

[0037] This defect information is stored in advance in the trimming information storage area 9 before the semiconductor memory device 100 is shipped from the factory. For example, in the manufacturing process of the semiconductor memory device 100, a defective cell 7a is detected in the memory array 1 during an inspection process. Then, defect information corresponding to this detection result is stored in the trimming information storage area 9, and the semiconductor memory device 100 is shipped to the market.

[0038] As described above, the controller 6 accesses the trimming information storage area 9 in response to a read command / write command input from outside the device. Then, the controller 6 reads out the defect information and then writes / reads data to / from the memory array 1. Specifically, the process is as follows.

[0039] When writing data to the memory array 1, a write signal S1 is input to the controller 6. The write signal S1 stores a write command. Upon receiving the write signal S1, the controller 6 accesses the trimming information storage area 9. Then, based on the defect information (more specifically, the cell address of the defective cell 7a) stored in the trimming information storage area 9, the controller 6 determines whether the selected cell 7b (=the memory cell 7 to which data is to be written by the write command) matches the defective cell 7a.

[0040] If it is determined that the selected cell 7b does not match the defective cell 7a, the controller 6 allows the supply of the control voltages Vx and Vy to the selected cell 7b without changing the cell address (the cell address of the selected cell 7b) included in the write signal S1. As a result, the data to be written included in the write signal S1 is written to the selected cell 7b as is.

[0041] More specifically, if it is determined that the selected cell 7b does not match the defective cell 7a, the controller 6 controls the X-decoder 3 to supply the control voltage Vx to one of the word lines W1 to Wm-1 corresponding to the selected cell 7b as the selected word line. At this time, the controller 6 also controls the Y-decoder 4 to supply the control voltage Vy to one of the bit lines B1 to Bn corresponding to the selected cell 7b as the selected bit line.

[0042] On the other hand, if it is determined that the selected cell 7b and the defective cell 7a match (as shown in FIG. 2), the controller 6 refuses to supply the control voltages Vx and Vy to the defective cell 7a. That is, in this case, the controller 6 changes the cell address of the selected cell 7b to a cell address within the redundant area 10. As a result, the data to be written, which is included in the write signal S1, is written to an arbitrary cell address in the redundant area 10 instead of the defective cell 7a.

[0043] More specifically, the process is as follows. If it is determined that the selected cell 7b and the defective cell 7a match, the controller 6 controls the X-decoder 3 to supply a control voltage Vx to the word line Wm as the selected word line based on the read defect information. At this time, the controller 6 also controls the Y-decoder 4 to supply a control voltage Vy to the bit line B1-Bn corresponding to the selected cell 7b as the selected bit line. Therefore, after the cell address change, the selected cell 7b will have an address in the same column as the defective cell 7a but in a different row (a row in the redundant area 10). In this way, the data write operation to the defective cell 7a is avoided.

[0044] Furthermore, when a control signal (=read signal S2) including a read command is input to the controller 6, the behavior is the same as that of the write command described above. Specifically, it is as follows.

[0045] When data is read from the memory array 1, a read signal S2 is input to the controller 6. The read signal S2 stores a read command. Upon receiving the read signal S2, the controller 6 first accesses the trimming information storage area 9. Then, based on the defect information (more specifically, the cell address of the defective cell 7a) stored in the trimming information storage area 9, the controller 6 determines whether the selected cell 7b (=the memory cell 7 to be written to by the write command) matches the defective cell 7a.

[0046] If it is determined that the selected cell 7b does not match the defective cell 7a, the controller 6 allows the supply of the control voltages Vx and Vy to the selected cell 7b without changing the cell address (the cell address of the selected cell 7b) included in the write signal S1. As a result, data is read from the selected cell 7b with the cell address included in the read signal S2 unchanged.

[0047] More specifically, the process is as follows: If it is determined that the selected cell 7b does not match the defective cell 7a, the controller 6 controls the X-decoder 3 to supply a control voltage Vx to one of the word lines W1 to Wm-1 corresponding to the selected cell 7b as the selected word line. The controller 6 also controls the Y-decoder 4 to supply a control voltage Vy to one of the bit lines B1 to Bn corresponding to the selected cell 7b as the selected bit line. The controller 6 then controls the sense amplifier 5 to determine whether a current flows through the selected cell 7b and reads out the data ("1" or "0") stored in the memory cell 7.

[0048] On the other hand, if it is determined that the selected cell 7b and the defective cell 7a match (as shown in FIG. 2), the controller 6 refuses to supply the control voltages Vx and Vy to the defective cell 7a. That is, in this case, the controller 6 changes the cell address of the selected cell 7b to a cell address within the redundant area 10. As a result, data is read from the memory cell 7 having a cell address different from the cell address included in the read signal S2 (= the cell address of the defective cell 7a).

[0049] More specifically, the process is as follows: If it is determined that the selected cell 7b and the defective cell 7a match, the controller 6 controls the X-decoder 3 to supply a control voltage Vx to the word line Wm as the selected word line. At this time, the controller 6 also controls the Y-decoder 4 to supply a control voltage Vy to the bit line B1-Bn corresponding to the selected cell 7b as the selected bit line. Therefore, after the cell address change, the selected cell 7b is assigned an address in the same column as the defective cell 7a but in a different row (a row in the redundant area 10). This prevents the data from being read from the defective cell 7a.

[0050] Note that, if a write operation to the defective cell 7a is instructed before a read operation, data is written to a memory cell 7 located in the same column as the defective cell 7a but in a different row (a row in the redundant area 10) instead of the defective cell 7a, as described above. Then, if a read operation to the defective cell 7a is instructed, data is read from a memory cell 7 located in the same column as the defective cell 7a but in a different row (a row in the redundant area 10) instead of the defective cell 7a, as described above. In other words, data that was originally intended to be written to the defective cell 7a during a write operation and was written to a memory cell 7 in the redundant area 10 instead of the defective cell 7a can also be properly read from the redundant area 10 during a read operation while avoiding access to the defective cell 7a.

[0051] As described above, according to the semiconductor memory device 100 of this embodiment, access to the defective cell 7a can be avoided when writing / reading data to / from the memory array 1. This makes it possible to prevent unexpected errors and the like from occurring. Therefore, even if a defect such as a garbled bit occurs in any of the memory cells 7, the semiconductor memory device 100 can be used as normal without being discarded. This makes it possible to prevent a decrease in the yield of the semiconductor memory device 100 and an increase in disposal losses.

[0052] <Detailed configuration of read / write circuit 2> Next, we will explain the detailed configuration of the read / write circuit 2. Fig. 3 is a diagram showing the configuration of the read / write circuit 2. As shown in Fig. 3, the read / write circuit 2 includes a redundancy control circuit 11 in addition to the configuration described above.

[0053] The redundancy control circuit 11 is connected to the X decoder 3 and the memory array 1. The redundancy control circuit 11 is configured to permit or deny the supply of a control voltage Vx supplied from the X decoder 3 to each memory cell 7.

[0054] The redundancy control circuit 11 includes a comparison circuit 12 and a write enable circuit 20. Furthermore, each of the word lines W1 to Wm-1 includes a first supply line Wa1 to Wam and a second supply line Wb1 to Wbm.

[0055] The first supply line Wa1 is connected to the trimming information storage area 9 (more specifically, each memory cell 7 of the trimming information storage area 9). Each of the first supply lines Wa2 to Wam-1 is connected to the main storage area 8 (more specifically, each memory cell 7 of the main storage area 8). The first supply line Wam is connected to the redundancy area 10 (more specifically, each memory cell 7 of the redundancy area 10).

[0056] The second supply lines Wb1 to Wbm-1 are connected to the comparator circuit 12, the write enable circuit 20 (more specifically, the first input terminals of the logic gates LG1 to LGm-1, which will be described later), and the X-decoder 3. The second supply line Wbm is connected to the comparator circuit 12, the input terminal of the buffer circuit 14, and the write enable circuit 20 (more specifically, the input terminal of the inverter circuit 13).

[0057] The comparison circuit 12 is connected to the sense amplifier 5. The sense amplifier 5 accesses the trimming information storage area 9 to read out the defect information (more specifically, the cell address of the defective cell 7a) and generates a defect information signal S3. The sense amplifier 5 inputs the defect information signal S3 to the comparison circuit 12.

[0058] The comparator circuit 12 is configured to be able to detect the voltage conditions of the word lines W1 to Wm-1 (more specifically, second supply lines Wb1 to Wbm-1, which will be described later). The comparator circuit 12 generates a redundancy control signal S4 based on the input defect information signal S3 and the voltage conditions of the word lines W1 to Wm-1.

[0059] Specifically, when the voltage state of the word lines W1 to Wm-1 (more specifically, second supply lines Wb1 to Wbm-1 described later) matches the defect information included in the defect information signal S3 (more specifically, the word line connected to the defective cell 7a), the comparison circuit 12 sets the redundancy control signal S4 to high level. When they do not match, the comparison circuit 12 sets the redundancy control signal S4 to low level.

[0060] In response to an instruction from the controller 6, the X decoder 3 selects one of the second supply lines Wb1 to Wbm-1 that corresponds to the cell address of the selected cell 7b (=the one connected to the first input terminal of the logic gates LG1 to LGm-1 that are connected to the first supply lines Wa1 to Wam-2 that are connected to the selected cell 7b), and applies a control voltage Vx.

[0061] The write permission circuit 20 is configured to permit or deny writing of data to the main memory area 8 according to the redundancy control signal S4 and the voltage state of the word lines W1 to Wm-1. Specifically, it is as follows.

[0062] The write enable circuit 20 includes an inverter circuit 13, logic gates LG1 to LGm-1, and a buffer circuit .

[0063] The output terminal of the inverter circuit 13 is connected to the second input terminals of the logic gates LG1 to LGm-1. The inverter circuit 13 outputs an output voltage from the output terminal, which is an inverted version of the logic level of the voltage supplied to the input terminal.

[0064] The output terminal of the buffer circuit 14 is connected to the first supply line Wa1. The buffer circuit 14 performs a predetermined buffering process on the input voltage to generate an output voltage. For example, when a high-level input voltage is input, the buffer circuit 14 supplies an output voltage equivalent to the control voltage Vx to the first supply line Wa1.

[0065] The logic gates LG1 to LGm-1 are AND gates. That is, each of the logic gates LG1 to LGm-1 sets the output voltage to a high level only when the input voltages at both the first input terminal and the second input terminal are at a high level. Otherwise, the output voltage is set to a low level.

[0066] When the redundancy control signal S4 is at a low level, a high-level output voltage is supplied to the first input terminals of the logic gates LG1 to LGm-1. At this time, if a high-level control voltage Vx is supplied to the second input terminals of the logic gates LG1 to LGm-1, the logic gates LG1 to LGm-1 supply an output voltage equivalent to the control voltage Vx to the memory cells 7 of the main memory area 8 via the first supply lines Wam1 to Wam-1. At this time, writing of data to the main memory area 8 is permitted.

[0067] Conversely, when the redundancy control signal S4 is at a high level, a low-level output voltage is supplied to the first input terminals of the logic gates LG1 to LGm-1. At this time, the logic gates LG1 to LGm-1 output a low-level voltage regardless of the logical level of the voltage input to their second input terminals. Therefore, the control voltage Vx is not supplied to the memory cells 7 of the main memory area 8. At this time, writing data to the main memory area 8 is denied.

[0068] At this time, the buffer circuit 14 receives the low-level redundancy control signal S4 and supplies a high-level output voltage corresponding to the control voltage Vx to the first supply line Wam, so that the data that was rejected from being written to the main memory area 8 is written to the memory cells 7 of the redundancy area 10.

[0069] As described above, the defect information (=information about the defective cell 7a) is stored in the trimming information storage area 9. For example, as shown in Fig. 2, the most significant bit of the trimming information storage area 9 is allocated as a storage area for the above-mentioned trimming information (trimming information storage area 9a). The second most significant bit (the bit one bit lower than the most significant bit) and the third most significant bit (the bit two bits lower than the most significant bit) are allocated as defect information storage area 9b.

[0070] The defect information storage area 9b stores information about the word line connected to the defective cell 7a in advance. For example, as shown in Figure 3, assume that the memory cell 7 connected to the word line W2 and the bit line B1 is the defective cell 7a. In this case, "1" or "0" meaning "second" when the word line W2 is considered to be the second most significant word line is stored in each memory cell 7 in the defect information storage area 9b.

[0071] Here, two bits of the trimming information storage area 9 are allocated as the defect information storage area 9b, but three or more bits may be allocated. When the cell area (number of memory cells 7) is relatively large (when the number of memory cells 7 is relatively large), a large number of defective cells 7a may exist. In this case, a large number of memory cells 7 of the trimming information storage area 9 are allocated as the defect information storage area 9b. This allows information on each defective cell 7a to be stored in advance in the defect information storage area 9b, even if a large number of defective cells 7a exist.

[0072] When reading trimming information, the sense amplifier 5 reads the most significant bit of the trimming information storage area 9. When reading defect information, the sense amplifier 5 reads the second most significant bit and the third most significant bit.

[0073] <Operation example 1 of read / write circuit 2> The operation of the read / write circuit 2 will be described below using a specific example. For example, as shown in Figure 3, assume that the memory cell 7 connected to the word line W2 and the bit line B1 (not shown) is a defective cell 7a. In this case, the trimming information storage area 9 stores the word line W2 as defect information.

[0074] In this case, assume that a read / write command (write signal S1 / read signal S2) for the defective cell 7a is input to the controller 6. Then, the controller 6 inputs control signals to the X decoder 3, the Y decoder 4 (not shown), and the sense amplifier 5. In response to the input of this control signal, the X decoder 3 attempts to supply a control voltage Vx to the defective cell 7a. More specifically, at this time, the X decoder 3 supplies the control voltage Vx to the second supply line Wb2. In addition, in response to the input of the control signal, the Y decoder 4 supplies a control voltage Vy to the bit line B1 (not shown).

[0075] Furthermore, upon receiving the control signal, the sense amplifier 5 accesses the trimming information storage area 9 and reads out the defect information. The sense amplifier 5 then generates a defect information signal S3 that includes the read defect information and inputs it to the comparison circuit 12. The defect information signal S3 here includes information about the word line W2 as information related to the cell address of the defective cell 7a.

[0076] The comparator circuit 12 detects that the control voltage Vx is being supplied to the second supply line Wb2. Then, based on the defect information signal S3 (more specifically, the information on the word line W2), the comparator circuit 12 denies the supply of the control voltage Vx to the main memory area 8. More specifically, this is as follows.

[0077] At this time, the comparison circuit 12 detects that the defect information signal S3 (more specifically, the information on the second supply line Wb2 corresponding to the word line W2 included in the defect information signal S3) matches the voltage status of the second supply lines Wb1 to Wbm-1. Then, the comparison circuit 12 raises the redundancy control signal S4 to a high level.

[0078] As a result, the inverter circuit 13 inputs a low-level output voltage to the second input terminals of the logic gates LG1 to LGm-1. Then, a high-level voltage (corresponding to the control voltage Vx) is applied to the first input terminal of the logic gate LG2, and a low-level voltage is applied to the second input terminal. Therefore, the logic gate LG2 outputs a low-level voltage. In other words, the logic gate LG2 does not supply the control voltage Vx to the first supply line Wa2. Therefore, the control voltage Vx is not supplied to the defective cell 7a, and access (write / read) to the memory cell 7 is denied.

[0079] At this time, a high-level redundancy control signal S4 is input to the input terminal of the buffer circuit 14. In response to this, the buffer circuit 14 performs a predetermined buffering process to generate an output voltage equivalent to the control voltage Vx, and supplies this to the first supply line Wam. This allows data to be written to or read from the memory cells 7 in the redundancy area 10.

[0080] <Operation example 2 of read / write circuit 2> Similarly, suppose that the memory cell 7 connected to the word line W2 and the bit line B1 (not shown) is a defective cell 7a. In this case, suppose that a read / write command (write signal S1 / read signal S2) for the memory cell 7 connected to the word line W3 (not shown) and the bit line B1 is input to the controller 6.

[0081] In this case, the X decoder 3 supplies the control voltage Vx to the second supply line Wb3. The comparator circuit 12 detects the voltage conditions of the second supply lines Wb1 to Wbm-1 and determines that they do not match the defect information. The comparator circuit 12 then sets the redundancy control signal S4 to low level.

[0082] Then, inverter circuit 13 supplies a high-level output voltage to the second input terminals of logic gates LG1 to LGm-1. As a result, a high-level voltage is supplied to the first and second input terminals of logic gate LG3. Therefore, logic gate LG3 outputs a high-level voltage (corresponding to control voltage Vx). Therefore, control voltages Vx and Vy are supplied to memory cells 7 connected to word line W3 and bit line B1, and data is written / read.

[0083] <Regarding control timing during read operations> 4 is a timing chart of serial signals exchanged between an external device (for example, a central processing circuit such as a microcomputer) and the semiconductor memory device 100. Fig. 4 shows a timing chart when a read command for reading data from the memory array 1 is input to the semiconductor memory device 100. Fig. 4 also shows, from top to bottom, a chip select signal CSB, a clock signal SCL, a data signal SDA, a Y decoder enable signal (YDEC_EN), an X decoder enable signal (XDEC_EN), a sense amplifier enable signal (SAMP_EN), and a trim set signal (TRIMSET).

[0084] 4, when communication is performed between the semiconductor memory device 100 and an external device (central control circuit), the chip select signal CSB first falls to a low level. Then, the clock signal SCL starts oscillating at a predetermined frequency. The oscillation start point is defined as time t1.

[0085] At time t2, data communication is initiated by the data signal SDA. The data signal SDA includes address bits indicating the access destination address (read destination address) and command bits indicating a read command. Then, at time t3, the semiconductor memory device 100 executes the read operation described above.

[0086] The controller 6 reads out the defect information from the trimming information storage area 9 before the read command is executed (before time t3) and generates the defect information signal S3. Specifically, the process is as follows.

[0087] Between time t1 and time t2, the sense enable signal falls to low level, causing the sense amplifier 5 to stop operating. Thereafter, by time t2, the Y decoder enable signal rises to high level, causing the Y decoder 4 to generate a control voltage Vy. Thereafter, at time t2a, before time t3, the X decoder enable signal rises to high level, causing the X decoder 3 to generate a control voltage Vx.

[0088] The controller 6 generates a defect information signal S3 to permit / deny supply of the control voltage Vx to the memory cells 7 of the main storage area 8 between time t2a and time t3.

[0089] Then, after time t2a, at time t2b before time t3, the trim set signal rises to high level, causing the trimming operation described above to be executed. Then, when time t3 arrives, the read operation is executed as described above.

[0090] <Control timing during write operation> Fig. 5 is a timing chart of serial signals exchanged between an external device and the semiconductor memory device 100. Fig. 5 shows a timing chart when a write command for writing data to the memory array 1 is input to the semiconductor memory device 100. Fig. 5 also shows, from top to bottom, a chip select signal CSB, a clock signal SCL, a data signal SDA, a Y decoder enable signal (YDEC_EN), an X decoder enable signal (XDEC_EN), a sense amplifier enable signal (SAMP_EN), and a trim set signal (TRIMSET).

[0091] 5, when communication is performed between the semiconductor memory device 100 and the central control circuit, the chip select signal CSB first falls to a low level. Then, the clock signal SCL starts oscillating at a predetermined frequency. The oscillation start point is assumed to be time t11.

[0092] At time t12, data communication is initiated by the data signal SDA. The data signal SDA includes address bits indicating the access destination address (write destination address) and command bits indicating a write command. Then, at time t13, the semiconductor memory device 100 executes the write operation as described above.

[0093] The controller 6 reads out the defect information from the trimming information storage area 9 before the write command is executed (before time t13) and generates the defect information signal S3. Specifically, the process is as follows.

[0094] Between time t11 and time t12, the sense enable signal falls to low level, causing the sense amplifier 5 to stop operating. Thereafter, by time t12, the Y decoder enable signal rises to high level, causing the Y decoder 4 to generate the control voltage Vy. Thereafter, at time t12a, before time t13, the X decoder enable signal rises to high level, causing the X decoder 3 to generate the control voltage Vx.

[0095] The controller 6 generates the defect information signal S3 and permits / denies the supply of the control voltage Vx to the memory cells 7 of the main storage area 8 between time t12a and time t13.

[0096] Then, after time t12a, at time t12b before time t13, the trim set signal rises to high level, causing the trimming operation described above to be executed. Then, when time t13 arrives, the write operation is executed as described above.

[0097] Data can also be written to the trimming information storage area 9 by an operation similar to the write operation described above. That is, a control voltage Vx is supplied to the word line W1, and a control voltage Vy is supplied to any one of the bit lines B1 to Bn. This allows data to be written to any one of the memory cells 7 in the trimming information storage area 9.

[0098] In this way, for example, if a user who has acquired the semiconductor memory device 100 finds a defective cell 7a that occurred after shipping from the factory, the defect information can be updated. This allows the user to avoid accessing a new defective cell 7a even if a defective cell 7a occurs due to aging or unexpected damage.

[0099] <Modification> The present disclosure is not limited to the above-described embodiments, and various modifications are possible within the scope of the present disclosure. For example, although the semiconductor memory device 100 is described as being an EEPROM, it may be another non-volatile memory (e.g., a mask ROM, a PROM, an EPROM, a flash memory, etc.).

[0100] Although the redundant area 10 in the above embodiment is described as consisting of one row of memory cells 7, it may be made up of multiple rows of memory cells 7 as shown in FIG. 6. In this case, the redundant areas 10 in each row are designated as redundant area 10a and redundant area 10b. More specifically, the configuration is as follows.

[0101] In this case, the read / write circuit 2 includes a redundancy control circuit 11a corresponding to the redundancy control circuit 11 mentioned above, and a redundancy control circuit 11b.

[0102] The redundancy control circuit 11a includes a comparison circuit 12a corresponding to the comparison circuit 12, and a write enable circuit 20a corresponding to the write enable circuit 20. The write enable circuit 20a includes an inverter circuit 13a corresponding to the inverter circuit 13, a buffer circuit 14a corresponding to the buffer circuit 14, and logic gates LG1 to LGm-2.

[0103] The redundancy control circuit 11b includes a comparison circuit 12b corresponding to the comparison circuit 12, and a write enable circuit 20b corresponding to the write enable circuit 20. The write enable circuit 20b includes an inverter circuit 13b corresponding to the inverter circuit 13, a buffer circuit 14b corresponding to the buffer circuit 14, and logic gates LG2 to LGm-1.

[0104] The first supply lines Wa1 to Wam-2 are treated as a pair, that is, each memory cell 7 is connected to the same pair of first supply lines Wa1 to Wam-2.

[0105] In this case, even if multiple defective cells 7a occur in the memory array 1, the access destination can be changed to the memory cells 7 in the redundant area 10a or the memory cells 7 in the redundant area 10b. Therefore, even if multiple defective cells 7a occur, it is possible to write / read data to / from the semiconductor memory device 100 while avoiding access to the defective cells 7a.

[0106] <Additional Notes> The semiconductor memory device (100) disclosed in the specification comprises a memory array (1) including a plurality of memory cells (7) and configured to be able to read and write data to each of the memory cells (7), and a read / write circuit (2) configured to supply control voltages (Vx, Vy) to any of the memory cells (7) to write data to any of the memory cells (7) or read data stored in any of the memory cells (7). The memory array (1) is configured to include a first memory area (8) including a plurality of memory cells (7) and configured to apply the control voltages (Vx, Vy) to the plurality of memory cells (7) via a plurality of first word lines (W2 to Wm-1) and a plurality of bit lines (B1 to Bn), and a second memory area (10) including a plurality of memory cells (7) and configured to apply the control voltages (Vx, Vy) to the plurality of memory cells (7) via a second word line (Wm) different from each of the first word lines (W2 to Wm-1) and each of the bit lines (B1 to Bn) (first configuration).

[0107] In the semiconductor memory device (100) according to the first configuration, the memory array (1) has a third memory area (9) that stores defect information for memory cells (7) that correspond to defective cells (7a) among the memory cells (7), and the read / write circuit (2) accesses the third memory area (9) when reading data stored in the first memory area (8) and when writing data to the first memory area (8), and reads or writes data from or to the first memory area (8) based on the defect information (second configuration).

[0108] In the semiconductor memory device (100) according to the second configuration, when the read / write circuit (2) determines that the memory cell (7) to which the data is to be written is a defective cell (7a) when writing data to the first memory area (8), the read / write circuit (2) may be configured to write the data to the second memory area (10) instead of the first memory area (8) (third configuration).

[0109] In a semiconductor memory device (100) according to a third configuration, the read / write circuit (2) includes a decoder (3) configured to supply control voltages (Vx, Vy) to first word lines (W2 to Wm-1) corresponding to any of the first word lines (W2 to Wm-1), and a redundancy control circuit (11) configured to permit or deny supply of the control voltages (Vx, Vy) to any of the first word lines based on the control voltages (Vx, Vy) and defect information, and the redundancy control circuit (11) is preferably configured to supply the control voltages (Vx, Vy) to the second word line (Wm) when refusing to supply the control voltages (Vx, Vy) to any of the first word lines (W2 to Wm-1) (fourth configuration).

[0110] In a semiconductor memory device (100) according to a third or fourth configuration, a read / write circuit (2) includes a sense amplifier (5) configured to access a third storage area (9) and generate a defect information signal (S3) based on defect information, and a first word line (word line W1 to Wm-1) includes first supply lines (Wa1 to Wam-1) connected to the first storage area (8) and second supply lines (Wb1 to Wbm-1) connected to a decoder (3), and the decoder (3) supplies control voltages (Vx, Vy) to the first supply lines (Wa1 to Wam-1). The redundancy control circuit (11) may be configured to include a comparison circuit (12) connected to each second supply line (Wb1 to Wbm-1), capable of detecting control voltages (Vx, Vy), and generating a redundancy control signal (S4) based on the detection result and the defect information signal (S3), and a write permission circuit (20) connected to each second supply line (Wb1 to Wbm-1) and configured to permit or prohibit writing of data to the first memory area (8) based on the redundancy control signal (S4) and the control voltages (Vx, Vy) (fifth configuration).

[0111] In a semiconductor memory device (100) according to a fifth configuration, the write permission circuit (20) includes a plurality of logic gates (LG1 to LGm-1) individually connected to each of the first supply lines (Wa1 to Wam-1), an inverter circuit (13) configured to receive an input of a redundancy control signal (S4) and output an output voltage whose logical level is inverted from that of the redundancy control signal (S4), and a buffer circuit (14) configured to generate a voltage corresponding to a control voltage (Vx, Vy) based on the redundancy control signal (S4) and supply it to the second word line (Wm), and the logic gates (LG1 to LGm-1) may be configured to permit or deny writing of data to the first memory area (8) based on the result of a combination of the logical level of the voltage of the first supply line (Wa1 to Wam-1) connected thereto and the logical level of the redundancy control signal (S4) (sixth configuration).

[0112] In the semiconductor memory device (100) according to any one of the first to sixth configurations, the second storage area (10) may be configured as a redundant area for the first storage area (8) (seventh configuration).

[0113] In the semiconductor memory device (100) according to any one of the second to sixth configurations, the third storage area (9) may store trimming information relating to its own manufacturing variations, and the read / write circuit (2) may be configured to write data based on the trimming information (eighth configuration).

[0114] In the semiconductor memory device (100) according to any one of the first to eighth configurations, the memory array (1) may be configured to include a plurality of second memory areas (10) (ninth configuration). [Explanation of symbols]

[0115] 1 Memory Array 2 Read / write circuit 3 x Decoders 4 Y decoder 5 Sense Amplifier 6 Controller 7 memory cells 7a Bad cell 7b Selected cell 8 Main storage area (first storage area) 9. Trimming information storage area (third storage area) 9a Trimming information storage area 9b Defect information storage area 10 Redundant area (third storage area) 10a Redundant area 10b Redundant area 11 Redundant control circuit 11a Redundant control circuit 11b Redundant control circuit 12 Comparison circuit 12a Comparison circuit 12b Comparison circuit 13 Inverter circuit 13a Inverter circuit 13b Inverter circuit 14 Buffer circuit 14a Buffer circuit 14b Buffer circuit 20 Write enable circuit 20a Write enable circuit 20b Write enable circuit 100 Semiconductor memory device B1 bit line B1~Bn bit lines CSB Chip Select Signal LG1~LGm logic gates SDA Data signal Vx, Vy control voltage W1~Wm word lines Wam1~Wam 1st supply line Wb1~Wbm 2nd supply line

Claims

1. a memory array including a plurality of memory cells, configured to enable data to be read from and written to each of the memory cells; a read / write circuit configured to provide a control voltage to any one of the memory cells to write the data to the any one of the memory cells or to read data stored therein; Equipped with The memory array comprises: a first storage area including a plurality of the memory cells and configured such that the control voltage is applied to the plurality of memory cells via a plurality of first word lines and a plurality of bit lines; a second storage area including a plurality of the memory cells, the second storage area being configured so that the control voltage is applied to the plurality of memory cells via second word lines different from the first word lines and the bit lines; A semiconductor memory device comprising:

2. the memory array has a third storage area storing defect information for those of the memory cells that correspond to defective cells, 2. The semiconductor memory device of claim 1, wherein the read / write circuit accesses the third memory area when reading the data stored in the first memory area and when writing the data to the first memory area, and reads or writes the data to the first memory area based on the defect information.

3. 3. The semiconductor memory device according to claim 2, wherein when the read / write circuit writes the data to the first memory area, if the read / write circuit determines that the bit to which the data is to be written is the defective cell, the read / write circuit writes the data to be written to the second memory area instead of the first memory area.

4. The read / write circuit a decoder configured to provide the control voltage to the first word line corresponding to the one of the first word lines; a redundancy control circuit configured to allow or deny supply of the control voltage to any of the ones based on the control voltage and the fault information; Including, 4. The semiconductor memory device according to claim 3, wherein said redundancy control circuit supplies said control voltage to said second word line when refusing to supply said control voltage to said arbitrary one.

5. the read / write circuit includes a sense amplifier configured to access the third storage area and generate a defect information signal based on the defect information; the first word line includes a first supply line connected to the first storage area and a second supply line connected to the decoder; the decoder supplies the control voltage to each of the first supply lines; The redundancy control circuit includes: a comparison circuit connected to each of the second supply lines, capable of detecting the control voltage supplied to each of the second supply lines, and generating a redundancy control signal based on the detection result and the defect information signal; a write enable circuit connected to each of the second supply lines and configured to enable or disable writing of data to the first memory area based on the redundancy control signal and the control voltage.

6. The write enable circuit a plurality of logic gates individually connected to each of the voltage supply lines; an inverter circuit configured to receive the redundancy control signal and output an output voltage that is an inverted version of the redundancy control signal; a buffer circuit configured to generate a voltage corresponding to the control voltage based on the redundancy control signal and supply the voltage to the second word line; Including, 6. The semiconductor memory device according to claim 5, wherein each of the logic gates permits or denies writing of the data to the first memory area based on the result of a combination of the logic level of the voltage of the first supply line connected to the logic gate and the logic level of the redundancy control signal.

7. 2. The semiconductor memory device according to claim 1, wherein the second storage area is set as a redundant area for the first storage area.

8. the third storage area stores trimming information relating to its own manufacturing variations; 3. The semiconductor memory device according to claim 2, wherein the read / write circuit writes the data based on the trimming information.

9. 2. The semiconductor memory device according to claim 1, wherein the memory array comprises a plurality of the second memory areas.

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