Semiconductor device and electronic system including the same

Abstract

To provide a semiconductor device capable of improving reliability and productivity.SOLUTION: The semiconductor device includes a memory cell structure located in a cell array region, an electrode stack structure located at least in a connection region and including a plurality of electrodes and a plurality of interlayer insulating layers alternately stacked, and a plurality of electrode contact portions respectively penetrating at least a portion of the electrode stack structure and electrically connected to the plurality of electrodes. The plurality of electrode contact portions include a first contact portion and a second contact portion. The first contact portion includes a first conductive portion and a first sidewall insulating layer disposed between the electrode stack structure and the first conductive portion. The second contact portion includes a second conductive portion and a second sidewall insulating layer located between the electrode stack structure and the second conductive portion and having a shape or structure different from that of the first sidewall insulating layer.SELECTED DRAWING: Figure 1

Description

[Technical Field]

[0001] The present disclosure relates to a semiconductor device and an electronic system including the same. [Background technology]

[0002] In electronic systems requiring data storage, semiconductor devices capable of storing large amounts of data are required. Accordingly, methods for increasing the data storage capacity of semiconductor devices have been studied. For example, as one method for increasing the data storage capacity of semiconductor devices, a semiconductor device including memory cells arranged three-dimensionally instead of two-dimensionally has been proposed. Summary of the Invention [Problem to be solved by the invention]

[0003] The embodiments provide a semiconductor device and a manufacturing method thereof, as well as an electronic system, that can improve reliability and productivity. [Means for solving the problem]

[0004] A semiconductor device according to an embodiment includes a memory cell structure located in a cell array region, an electrode stack structure located at least in a connection region and including a plurality of electrodes and a plurality of interlayer insulating layers alternately stacked with each other, and a plurality of electrode contact portions each penetrating at least a portion of the electrode stack structure and electrically connected to the plurality of electrodes. The plurality of electrode contact portions include a first contact portion and a second contact portion. The first contact portion includes a first conductive portion and a first sidewall insulating layer located between the electrode stack structure and the first conductive portion. The second contact portion includes a second conductive portion and a second sidewall insulating layer located between the electrode stack structure and the second conductive portion and having a different shape or structure from the first sidewall insulating layer.

[0005] An electronic system according to the embodiment includes a main board, the semiconductor device disposed on the main board, and a controller electrically connected to the semiconductor device on the main board.

[0006] A semiconductor device according to an embodiment includes a memory cell structure located in a cell array region, an electrode stack structure located at least in a connection region and including a plurality of electrodes and a plurality of interlayer insulating layers that are alternately stacked with each other, and a plurality of electrode contact portions that penetrate at least a portion of the electrode stack structure and are electrically connected to the plurality of electrodes, respectively. The plurality of electrode contact portions include contact portions including a conductive portion and a sidewall insulating layer located between the electrode stack structure and the conductive portion. The sidewall insulating layer includes a first portion located above the contact portion and a second portion located below the first portion and having a thickness smaller than that of the first portion. [Effects of the Invention]

[0007] According to the embodiment, a plurality of through holes can be formed using a binary partial etching process, thereby simplifying the process of forming a gate contact portion and reducing the area of ​​the connection region. By forming at least a first layer of a sidewall insulating layer before the subsequent partial etching process, damage to the stacked structure or electrode stacked structure that may occur during the subsequent partial etching process can be prevented, and through holes having a relatively large depth can be stably formed. This improves the reliability and productivity of semiconductor devices. [Brief explanation of the drawings]

[0008] [Figure 1] 1 is a partial cross-sectional view schematically illustrating a semiconductor device according to an embodiment. [Figure 2] 2 is an enlarged cross-sectional view showing an example of a channel structure included in the semiconductor device shown in FIG. 1. FIG. [Figure 3] 2 is a cross-sectional view showing a connecting region of the cell region included in the semiconductor device shown in FIG. [Figure 4] FIG. 4 is a cross-sectional view showing part A in FIG. 3. [Figure 5]FIG. 4 is a cross-sectional view showing part B of FIG. 3. [Figure 6] FIG. 4 is a cross-sectional view showing a portion C in FIG. 3. [Figure 7] 1A to 1C are partial cross-sectional views showing a method for manufacturing a semiconductor device according to an embodiment of the present invention. [Figure 8] 1A to 1C are partial cross-sectional views showing a method for manufacturing a semiconductor device according to an embodiment of the present invention. [Figure 9] 1A to 1C are partial cross-sectional views showing a method for manufacturing a semiconductor device according to an embodiment of the present invention. [Figure 10] 1A to 1C are partial cross-sectional views showing a method for manufacturing a semiconductor device according to an embodiment of the present invention. [Figure 11] 1A to 1C are partial cross-sectional views showing a method for manufacturing a semiconductor device according to an embodiment of the present invention. [Figure 12] 1A to 1C are partial cross-sectional views showing a method for manufacturing a semiconductor device according to an embodiment of the present invention. [Figure 13] 1A to 1C are partial cross-sectional views showing a method for manufacturing a semiconductor device according to an embodiment of the present invention. [Figure 14] 1A to 1C are partial cross-sectional views showing a method for manufacturing a semiconductor device according to an embodiment of the present invention. [Figure 15] 1A to 1C are partial cross-sectional views showing a method for manufacturing a semiconductor device according to an embodiment of the present invention. [Figure 16] 1A to 1C are partial cross-sectional views showing a method for manufacturing a semiconductor device according to an embodiment of the present invention. [Figure 17] 1A to 1C are partial cross-sectional views showing a method for manufacturing a semiconductor device according to an embodiment of the present invention. [Figure 18] 1A to 1C are partial cross-sectional views showing a method for manufacturing a semiconductor device according to an embodiment of the present invention. [Figure 19] FIG. 10 is a cross-sectional view showing a gate contact portion included in a semiconductor device according to another embodiment. [Figure 20] FIG. 10 is a cross-sectional view showing a gate contact portion included in a semiconductor device according to another embodiment. [Figure 21] FIG. 10 is a cross-sectional view showing a gate contact portion included in a semiconductor device according to another embodiment. [Figure 22] FIG. 10 is a partial cross-sectional view schematically illustrating a semiconductor device according to a further embodiment. [Figure 23]1 is a diagram illustrating a schematic diagram of an electronic system including a semiconductor device according to an example embodiment. [Figure 24] 1 is a perspective view schematically illustrating an electronic system including a semiconductor device according to an exemplary embodiment. [Figure 25] 1 is a cross-sectional view schematically illustrating a semiconductor package according to an exemplary embodiment. [Figure 26] 1 is a cross-sectional view schematically illustrating a semiconductor package according to an exemplary embodiment. DETAILED DESCRIPTION OF THE INVENTION

[0009] The present invention relates to a method for manufacturing a semiconductor device, a semiconductor device for manufacturing a semiconductor device, and a semiconductor device for manufacturing a semiconductor device.

[0010] To clearly explain the present disclosure, parts that are irrelevant to the description will be omitted and the same reference numerals will be used throughout the specification to refer to the same or similar components.

[0011] Furthermore, the size and thickness of each component shown in the drawings are arbitrarily shown for the convenience of explanation, and the present disclosure is not limited to the drawings. For the convenience of explanation and / or simple illustration, the thickness of some layers and regions are enlarged or exaggerated.

[0012] Furthermore, when a layer, film, region, plate, or other part is said to be "on" another part, this does not only mean that it is "directly on top" of that other part, but also includes cases where there is another part in between. Conversely, when a part is said to be "directly on top" of another part, it means that there is no other part in between. Furthermore, being "on" a reference part means that it is located above or below the reference part, and does not necessarily mean that it is located "on" in the opposite direction of gravity.

[0013] Also, throughout the specification, when a part is said to "comprise" a certain element, this means that it may further include other elements, not excluding other elements, unless otherwise specified.

[0014] Also, throughout the specification, "in a plane" or "when viewed from a plane" may mean when the part in question is viewed from above, and "in a cross section" or "when viewed from a cross section" may mean when the part in question is viewed from the side across a vertical cross section.

[0015] A semiconductor device and a method for manufacturing the same according to an embodiment will be described in detail below with reference to FIGS.

[0016] FIG. 1 is a partial cross-sectional view schematically showing a semiconductor device 10 according to an embodiment, and FIG. 2 is an enlarged cross-sectional view showing an example of a channel structure CH included in the semiconductor device 10 shown in FIG.

[0017] 1 and 2, a semiconductor device 10 according to an embodiment may include a cell region 100 including memory cell structures and a circuit region 200 including peripheral circuit structures that control the operation of the memory cell structures. As an example, the circuit region 200 and the cell region 100 may correspond to a first structure 1100F and a second structure 1100S of a semiconductor device 1100 included in an electronic system 1000 shown in FIG. 23. Alternatively, the circuit region 200 and the cell region 100 may correspond to a first structure 3100 and a second structure 3200 of a semiconductor chip 2200 shown in FIG. 25.

[0018] Here, the circuit region 200 may include a peripheral circuit structure formed on a first substrate 210, and the cell region 100 may be a memory cell structure and may include a gate stack structure 120 and a channel structure CH formed on a second substrate 110. A first wiring unit 280 may be included in the circuit region 200, and a second wiring unit 180 electrically connected to the memory cell structure may be included in the cell region 100.

[0019] In an exemplary embodiment, the cell region 100 may be located on the circuit region 200. This eliminates the need to secure an area corresponding to the circuit region 200 separately from the cell region 100, thereby reducing the area of ​​the semiconductor device 10. However, the embodiment is not limited to this, and the circuit region 200 may be located next to the cell region 100. Various other modifications are possible.

[0020] The circuit region 200 may include a first substrate 210, and a circuit element 220 and a first wiring part 280 formed on one surface (top surface in FIG. 1) of the first substrate 210.

[0021] The first substrate 210 may be a semiconductor substrate containing a semiconductor material. For example, the first substrate 210 may be a semiconductor substrate made of a semiconductor material, or may be a semiconductor substrate in which a semiconductor layer is formed on a base substrate. For example, the first substrate 210 may be made of single-crystal or polycrystalline silicon, epitaxial silicon, germanium, silicon-germanium, silicon-on-insulator, or germanium-on-insulator.

[0022] The circuit elements 220 formed on the first substrate 210 may include various circuit elements that control the operation of the memory cell structures provided in the cell region 100. As an example, the circuit elements 220 may constitute peripheral circuit structures such as a decoder circuit (reference numeral 1110 in FIG. 23), a page buffer (reference numeral 1120 in FIG. 23), and a logic circuit (reference numeral 1130 in FIG. 23).

[0023] The circuit element 220 may include, for example, a plurality of transistors, but is not limited to this example. The circuit element 220 may include not only active elements such as transistors, but also passive elements such as capacitors, resistors, and inductors.

[0024] A first wiring unit 280 located on the first substrate 210 may be electrically connected to the circuit element 220. In an exemplary embodiment, the first wiring unit 280 may include multiple wiring layers 286 spaced apart by interlayer insulating layers 282 and connected to each other by contact vias 284 to form desired paths. The wiring layers 286 or the contact vias 284 may include various conductive materials, and the interlayer insulating layers 282 may include various insulating materials. For example, the interlayer insulating layers 282 may include at least one of silicon oxide, silicon nitride, and silicon oxynitride.

[0025] The cell region 100 may include a cell array region 102 and a connection region 104. In the cell array region 102, a gate stack structure 120 and a channel structure CH may be formed on a second substrate 110. Structures for connecting the gate stack structure 120 and / or the channel structure CH formed in the cell array region 102 to the circuit region 200 or an external circuit may be located in the cell array region 102 and / or the connection region 104.

[0026] In one embodiment, the second substrate 110 may include a semiconductor layer containing a semiconductor material. For example, the second substrate 110 may be a semiconductor substrate made of a semiconductor material, and may be a semiconductor layer formed on a base substrate. For example, the second substrate 110 may be made of silicon, germanium, silicon-germanium, silicon-on-insulator (SOI), germanium-on-insulator (GOI), or the like. In this case, the semiconductor layer included in the second substrate 110 may be doped with p-type or n-type impurities. For example, p-type impurities may include boron (B), gallium (Ga), or the like, and n-type impurities may include phosphorus (P), arsenic (As), or the like. However, the embodiment is not limited to the material of the second substrate 110, the conductivity type of the impurities doped into the semiconductor layer, or the material.

[0027] In the cell array region 102, a gate stack structure 120 including interlayer insulating layers 132 and gate electrodes 130 alternately stacked on one surface (for example, the top surface) of the second substrate 110, and a channel structure CH extending through the gate stack structure 120 in a direction intersecting (for example, perpendicular to) the second substrate 110 (the Z-axis direction in the figure) may be formed.

[0028] In an exemplary embodiment, horizontal conductive layers 112, 114 may be included between the second substrate 110 and the gate stack structure 120 in the cell array region 102, electrically connecting (for example, directly connecting) the channel structure CH to the second substrate 110. The horizontal conductive layers 112, 114 may include a first horizontal conductive layer 112 and / or a second horizontal conductive layer 114 sequentially positioned on the second substrate 110. The first horizontal conductive layer 112 may function as a part of a common source line of the semiconductor device 10. For example, the first horizontal conductive layer 112 may function as a common source line together with the second substrate 110.

[0029] The first and second horizontal conductive layers 112 and 114 may include a semiconductor material (e.g., polycrystalline silicon). For example, the first horizontal conductive layer 112 may include a polycrystalline silicon layer containing impurities. The embodiment is not limited thereto, and the second horizontal conductive layer 114 may be formed of a different material (e.g., an insulating material) from the first horizontal conductive layer 112, or the second horizontal conductive layer 114 may not be provided.

[0030] A gate stack structure 120 in which interlayer insulating layers 132 and gate electrodes 130 are alternately stacked may be located on the second substrate 110 (for example, on the first and second horizontal conductive layers 112, 114 formed on the second substrate 110).

[0031] The gate electrode 130 may include various conductive materials. For example, the gate electrode 130 may include a metal material such as tungsten (W), copper (Cu), or aluminum (Al), polycrystalline silicon, a metal nitride (e.g., titanium nitride (TiN), tantalum nitride (TaN), or the like), or a combination thereof. As shown in the enlarged view of FIG. 2 , a portion of the blocking layer 156 (e.g., the first blocking layer 156a) made of an insulating material may be located outside the gate electrode 130. The interlayer insulating layer 132 may include various insulating materials. For example, the interlayer insulating layer 132 may include silicon oxide, silicon nitride, silicon oxynitride, a low-k material having a dielectric constant lower than that of silicon oxide, or a combination thereof.

[0032] In one embodiment, a channel structure CH may be formed through the gate stack structure 120 and extending in a direction (Z-axis direction in the figure) intersecting (for example, perpendicular to) the second substrate 110.

[0033] The channel structure CH may include a channel layer 140 and a gate dielectric layer 150 located on the channel layer 140 between the gate electrode 130 and the channel layer 140. The channel structure CH may further include a core insulating layer 142 located inside the channel layer 140, or as another example, the core insulating layer 142 may not be provided. The channel structure CH may further include a channel pad 144 disposed on the channel layer 140 and / or the gate dielectric layer 150. The gate dielectric layer 150 located between the gate electrode 130 and the channel layer 140 may include a tunneling layer 152, a charge storage layer 154, and a blocking layer 156 sequentially formed on the channel layer 140.

[0034] Each channel structure CH constitutes one memory cell string, and a plurality of channel structures CH may be arranged spaced apart from each other while forming rows and columns on a plane. For example, a plurality of channel structures CH may be arranged in various patterns, such as a lattice pattern or a zigzag pattern, on a plane. The channel structures CH may have a columnar shape. For example, when viewed in cross section, the channel structures CH may have inclined side surfaces such that the width becomes narrower as they approach the second substrate 110 according to the aspect ratio. However, the embodiment is not limited thereto, and the arrangement, structure, shape, etc. of the channel structures CH may be variously modified.

[0035] The channel layer 140 may include a semiconductor material, such as polycrystalline silicon. The core insulating layer 142 may include various insulating materials. For example, the core insulating layer 142 may include silicon oxide, silicon nitride, silicon oxynitride, or a combination thereof.

[0036] The tunneling layer 152 may include an insulating material (e.g., silicon oxide, silicon oxynitride, etc.) that allows charge tunneling. The charge storage layer 154 is used as a data storage region and may include polycrystalline silicon, silicon nitride, etc. The blocking layer 156 may include an insulating material that can prevent undesired charge inflow into the gate electrode 130. For example, the blocking layer 156 may include silicon oxide, silicon nitride, silicon oxynitride, a high-k material having a higher dielectric constant than silicon oxide, or a combination thereof. In one embodiment, the blocking layer 156 may include a first blocking layer 156a that includes a portion extending horizontally along the gate electrode 130 and a second blocking layer 156b that extends vertically between the first blocking layer 156a and the charge storage layer 154.

[0037] The materials and stacked structures of the channel layer 140, the core insulating layer 142, and the gate dielectric layer 150 may be variously modified, and the embodiment is not limited thereto.

[0038] A channel pad 144 may be disposed to cover the upper surface of the core insulating layer 142 and be electrically connected to the channel layer 140. The channel pad 144 may include a conductive material, for example, but is not limited to, polycrystalline silicon doped with impurities.

[0039] In an exemplary embodiment, the gate stack structure 120 may include multiple gate stack portions 121 and 122 stacked sequentially. This allows for an increase in the number of stacked gate electrodes 130, thereby increasing the number of memory cells in a stable structure. Although FIG. 1 illustrates the gate stack structure 120 including two gate stack portions 121 and 122, the gate stack structure 120 may include one or three or more gate stack portions.

[0040] As described above, when the plurality of gate stack portions 121 and 122 are provided, the channel structure CH may include a plurality of channel portions CH1 and CH2 that are connected to each other by penetrating the plurality of gate stack portions 121 and 122. The plurality of channel portions CH1 and CH2 may have sloped side surfaces that narrow toward the second substrate 110 according to the aspect ratio when viewed in cross section, and a bend may be formed at the boundary between the plurality of channel portions CH1 and CH2 due to the difference in width. Alternatively, the plurality of channel portions CH1 and CH2 may have sloped side surfaces that are continuous without a bend. FIG. 2 illustrates an example in which the gate dielectric layer 150, the channel layer 140, and the core insulating layer 142 of the plurality of channel portions CH1 and CH2 extend to each other to form an integral structure. As another example, the gate dielectric layer 150, the channel layer 140, and the core insulating layer 142 of the plurality of channel portions CH1 and CH2 may be formed separately and electrically connected to each other, or a separate channel pad may be additionally provided at the boundary between the plurality of channel portions CH1 and CH2. Thus, the embodiment is not limited to the configuration of the plurality of channel portions CH1 and CH2.

[0041] In one embodiment, the gate stack 120 may be divided into a plurality of sections on a plane by isolation structures 146 that extend in a direction intersecting (for example, perpendicular to) the second substrate 110 (the Z-axis direction in the figure) and penetrate the gate stack 120. An upper isolation region 148 may be formed on the gate stack 120. The isolation structures 146 and / or upper isolation regions 148 may extend in a direction extending in the gate electrode 130 (the X-axis direction in the figure) and may be provided in a plurality of sections spaced apart at predetermined intervals in a direction intersecting the gate electrode 130 (the Y-axis direction in the figure).

[0042] The isolation structure 146 or the upper isolation region 148 may be filled with various insulating materials. For example, the isolation structure 146 or the upper isolation region 148 may include an insulating material such as silicon oxide, silicon nitride, or silicon oxynitride. However, the embodiment is not limited thereto, and the structure, shape, material, etc. of the isolation structure 146 or the upper isolation region 148 may be modified in various ways.

[0043] A connection region 104 and a second wiring unit 180 may be provided to connect the gate stack structure 120 and the channel structure CH provided in the cell array region 102 to the circuit region 200 or an external circuit. The connection region 104 may be disposed on the periphery of the cell array region 102, and a portion of the second wiring unit 180 may be located therein.

[0044] Here, the second wiring unit 180 may include all of the gate electrode 130, the channel structure CH, the horizontal conductive layers 112, 114, and / or components that electrically connect the second substrate 110 to the circuit region 200 or an external circuit. For example, the second wiring unit 180 may include the bit line 182, the gate contact unit 190, the source contact unit 186, the input / output connecting line 188, contact vias 180a connected thereto, and connecting line 180b connecting these lines.

[0045] The bit line 182 may extend in a direction (Y-axis direction) that intersects with the extension direction (X-axis direction in the figure) of the gate electrode 130. The bit line 182 may be electrically connected to a channel structure CH, e.g., a channel pad 144, through a contact via 180a, e.g., a bit line contact via, that penetrates the interlayer insulating layer 132.

[0046] In the connection region 104, a plurality of gate contact portions 190 may be electrically connected to the plurality of gate electrodes 130 through the gate stack structure 120. In this embodiment, the gate stack structure 120 may be located at least in the connection region 104. More specifically, the gate stack structure 120 may be located both in the cell array region 102 and the connection region 104. For example, the extension lengths of the plurality of gate electrodes 130 in the connection region 104 may be substantially the same. Here, "substantially the same" includes having a difference within a process tolerance (e.g., within 10%).

[0047] As such, in some embodiments, a portion (e.g., a stepped portion) of the gate stack structure 120 may not be removed to electrically connect the gate electrode 130 and the gate contact portion 190. The connection structure between the gate contact portions 190 and the gate electrodes 130 will be described in more detail later.

[0048] In the connection region 104, the source contact portion 186 may penetrate the cell insulating layer 132a and be electrically connected to the horizontal conductive layers 112, 114 and / or the second substrate 110, and the input / output connecting wiring 188 may penetrate the gate stack structure 120 or be disposed outside the gate stack structure 120 and be electrically connected to the first wiring portion 280 of the circuit region 200. The cell insulating layer 132a may refer to an insulating layer formed on and / or around the gate stack structure 120.

[0049] 1 illustrates an example in which the source contact portion 186 and / or the input / output connecting line 188 have slanted side surfaces that narrow toward the second substrate 110 according to the aspect ratio when viewed in cross section, and have a bent portion at the boundary between the plurality of gate stack portions 121 and 122. However, the embodiment is not limited thereto. The source contact portion 186 and / or the input / output connecting line 188 may not have a bent portion at the boundary between the plurality of gate stack portions 121 and 122. Various other modifications are possible.

[0050] 1 illustrates an example in which the interconnection 180b is formed in a single layer on the same plane as the bit line 182, and a separate insulating layer 132b is positioned in the portion other than the interconnection 180b. However, the embodiment is not limited to this. Therefore, the interconnection 180b may include multiple wiring layers and may further include contact vias for electrical connection with the bit line 182, the gate contact portion 190, the source contact portion 186, and / or the input / output interconnection 188.

[0051] The second wiring portion 180 is electrically connected to the first wiring portion 280, and the bit line 182, gate electrode 130, horizontal conductive layers 112, 114 and / or second substrate 110 electrically connected to the channel structure CH may be electrically connected to the circuit element 220 in the circuit region 200.

[0052] 1, the connection structure between the gate contact portions 190 and the gate electrodes 130 will be described in detail with reference to FIGS. 3 to 6. FIG.

[0053] Fig. 3 is a cross-sectional view showing the connection region 104 of the cell region 100 included in the semiconductor device 10 shown in Fig. 1. Fig. 4 is a cross-sectional view showing part A in Fig. 3, Fig. 5 is a cross-sectional view showing part B in Fig. 3, and Fig. 6 is a cross-sectional view showing part C in Fig. 3.

[0054] 1, 3 to 6, in the connection region 104, a plurality of gate contact portions 190 may penetrate a portion of the gate stack structure 120 and be electrically connected (e.g., in contact with) the plurality of gate electrodes 130, respectively.

[0055] In the embodiment, each gate contact portion 190 extends downward from the upper surface of the gate stack 120 toward the lower surface and may penetrate a portion of the gate stack 120 in a direction intersecting the second substrate 110 (for example, a vertical direction perpendicular to the second substrate 110) (the Z-axis direction in the figure). Herein, the upper surface of the gate stack 120 may refer to the surface located on the second wiring unit 180 side in the vertical direction, and the lower surface of the gate stack 120 may refer to the surface opposite the second wiring unit 180 or the surface located on the second substrate 110 side in the vertical direction. Unless otherwise specified, in this specification, with respect to the cell region 100, the upper surface or upper surface may refer to the portion or surface located on the second wiring unit 180 side, and the lower surface or lower surface may refer to the portion or surface opposite the second wiring unit 180 or the portion or surface located on the second substrate 110 side.

[0056] Each gate contact portion 190 may penetrate a portion of the gate stack structure 120 to have a depth sufficient to reach a connecting gate electrode 130c among the plurality of gate electrodes 130. The plurality of gate contact portions 190 may be provided to be connected to the plurality of gate electrodes 130, respectively. Because the plurality of gate electrodes 130 are located at different heights in the vertical direction (the Z-axis direction in the figure), the plurality of gate contact portions 190 may have different depths sufficient to reach the plurality of gate electrodes 130, respectively.

[0057] For example, the first gate contact portion 1901 may be electrically connected to the first gate electrode 1301. The nth gate contact portion may be electrically connected to the nth gate electrode, and the kth gate contact portion may be connected to the kth gate electrode, where n may be a natural number greater than 1 and less than k, and k may correspond to the total number of the gate electrodes 130 or the total number of the gate contact portions 190.

[0058] In the figure, the gate electrode 130 is illustrated as including first to sixteenth gate electrodes 1301 to 1316. In this case, the first to fifth gate contact portions 1901 to 1905 may be electrically connected to the first to fifth gate electrodes 1301 to 1305, respectively, the sixth to twelfth gate contact portions may be electrically connected to the sixth to twelfth gate electrodes 1306 to 1312, respectively, and the thirteenth to sixteenth gate contact portions 1913 to 1916 may be electrically connected to the thirteenth to sixteenth gate electrodes 1313 to 1316, respectively. In this manner, the plurality of gate contact portions 190 may be electrically connected to the plurality of gate electrodes 130, respectively.

[0059] For the sake of clarity and simplicity, the figure illustrates an example in which the depths of the gate contact portions 190 gradually increase with increasing distance from the cell array region 102, but the embodiment is not limited thereto. The arrangement of the gate contact portions 190 may be modified in various ways.

[0060] When viewed with respect to one gate contact portion 190 as a reference, the plurality of gate electrodes 130 may include a connecting gate electrode 130c electrically connected to one gate contact portion 190, and may include a through gate electrode 130p and / or a remaining gate electrode 130r. The through gate electrode 130p is a gate electrode 130 that is penetrated by the gate contact portion 190 but is electrically insulated from the gate contact portion 190 by the sidewall insulating layer 190i of the gate contact portion 190, and may correspond to the gate electrode 130 located above the connecting gate electrode 130c. The remaining gate electrode 130r is a gate electrode 130 that is not penetrated by the gate contact portion 190 but is electrically insulated from the gate contact portion 190, and may correspond to the gate electrode 130 located below the connecting gate electrode 130c.

[0061] In the first gate contact portion 1901, the first gate electrode 1301 may correspond to the connecting gate electrode 130c, and the gate electrode 130 located below the connecting gate electrode 130c may correspond to the remaining gate electrode 130r. In the nth gate contact portion, the nth gate electrode may correspond to the connecting gate electrode 130c, the gate electrode 130 located above the connecting gate electrode 130c may correspond to the through gate electrode 130p, and the gate electrode 130 located below the connecting gate electrode 130c may correspond to the remaining gate electrode 130r. In the kth gate contact portion (the 16th gate contact portion 1916 in FIG. 3 ), the kth gate electrode (the 16th gate electrode 1316 in FIG. 3 ) may correspond to the connecting gate electrode 130c, and the gate electrode 130 located above the connecting gate electrode 130c may correspond to the through gate electrode 130p.

[0062] In an embodiment, each gate contact portion 190 may be electrically connected to (e.g., in contact with) an upper surface of the connecting gate electrode 130c. However, the embodiment is not limited thereto. Each gate contact portion 190 may be electrically connected to (e.g., in contact with) another portion (e.g., a side surface) of the connecting gate electrode 130c.

[0063] In an embodiment, each gate contact portion 190 may include a conductive portion 190 c and a sidewall insulating layer 190 i located between the conductive portion 190 c and the gate stack 120 .

[0064] In each gate contact portion 190, a sidewall insulating layer 190i may be located between at least a side surface of the conductive portion 190c and a side surface of the through gate electrode 130p to electrically insulate the conductive portion 190c from the through gate electrode 130p. The sidewall insulating layer 190i may not be located on a lower surface of the conductive portion 190c and / or an upper surface of the connecting gate electrode 130c. That is, the sidewall insulating layer 190i may not be located between an upper surface of the connecting gate electrode 130c and a lower surface of the gate contact portion 190. For example, the lower surface of the sidewall insulating layer 190i may contact the connecting gate electrode 130c or may be located between the upper and lower surfaces of the interlayer insulating layer 132 located on the connecting gate electrode 130c.

[0065] According to this, the sidewall insulating layer 190i may surround the entire side surface of the gate contact portion 190 corresponding to the through gate electrode 130p, thereby providing stable insulation between the gate contact portion 190 and the through gate electrode 130p. Note that the embodiment is not limited to this, and the position of the sidewall insulating layer 190i, the connection position between the gate contact portion 190 and the connection gate electrode 130c, etc. may be modified in various ways.

[0066] For example, the conductive portion 190c may have a pillar shape (for example, a pillar shape having a circular or polygonal planar shape), and the sidewall insulating layer 190i may have various planar shapes such as an annular shape, a ring shape, or a frame shape surrounding the conductive portion 190c.

[0067] In the drawings, the gate contact portion 190 or the conductive portion 190c is illustrated as having sloped side surfaces that narrow in width as they approach the second substrate 110 due to the aspect ratio when viewed in cross section. However, the embodiments are not limited thereto, and the shape and structure of the gate contact portion 190 or the conductive portion 190c may be modified in various ways.

[0068] In the embodiment, the gate contact portion 190 located inside the through hole PH may be electrically connected to an upper portion of the connecting gate electrode 130c. For example, a plurality of through holes PH may be included that individually penetrate the gate stack structure 120 and are spaced apart across the gate stack structure 120, with one gate contact portion 190 located in each through hole PH, and a lower surface of a conductive portion 190c of one gate contact portion 190 located inside one through hole PH may be located (e.g., in contact with) an upper surface of the connecting gate electrode 130c. For example, a plurality of gate contact portions 190 may be located in a plurality of through holes PH that are spaced apart from each other, in one-to-one correspondence with the plurality of gate contact portions 190. In the embodiment, the through holes PH may have various planar shapes, such as a circular, polygonal, or elliptical shape, and the embodiment is not limited to the planar shape of the through holes PH.

[0069] As a result, a pad region (e.g., a pad insulating layer) through which the gate contact portions 190 penetrate together, or another insulating layer (e.g., a pad insulating layer) located between the gate contact portions 190 other than the interlayer insulating layer 132, or a portion (e.g., a stepped portion) where a portion of the gate stack structure 120 is removed for electrical connection of the gate contact portions 190 may not be provided. That is, the gate contact portions 190 can be individually electrically connected to the gate electrodes 130 without a pad region or pad insulating layer. This simplifies the process of electrically connecting the gate contact portions 190 to the gate electrodes 130 and reduces the area of ​​the connection region 104.

[0070] On the other hand, in a comparative example including a pad region, a process of etching a portion of a gate stack structure (e.g., a process of forming a stepped portion), a process of forming a pad insulating layer covering the stepped portion of the gate stack structure, and a process of electrically connecting multiple gate contact portions penetrating one pad insulating layer to multiple gate electrodes are required. This may complicate the processes of forming the pad region and the gate contact portions. Furthermore, in order to prevent misalignment of the gate contact portions in the pad region or pad insulating layer through which multiple gate contact portions pass, a sufficient width between the multiple gate contact portions must be ensured. This allows the area of ​​the connection region to be increased.

[0071] In an embodiment, the plurality of gate contact portions 190 may include a first contact portion 192 and a second contact portion 196 having sidewall insulating layers 190i with different shapes or structures. More specifically, the first contact portion 192 may include a first conductive portion 192c and a first sidewall insulating layer 192i located between the gate stack 120 and the first conductive portion 192c. The second contact portion 196 may include a second conductive portion 196c and a second sidewall insulating layer 196i located between the gate stack 120 and the second conductive portion 196c and having a shape or structure different from that of the first sidewall insulating layer 192i.

[0072] 4 and 5, the first conductive portion 192c of the first contact portion 192 includes a conductive material and may fill at least a portion of the through-hole PH except for the first sidewall insulating layer 192i. For example, the first conductive portion 192c may include tungsten (W), copper (Cu), aluminum (Al), etc., and may further include a diffusion barrier layer. Note that the embodiment is not limited to the material of the first conductive portion 192c.

[0073] The first sidewall insulating layer 192i of the first contact portion 192 may include a first portion R1 and a second portion R2 having a thickness smaller than that of the first portion R1. Here, the thickness T1 of the first portion R1 or the thickness T2 of the second portion R2 may be a thickness measured in a direction perpendicular to the side surface of the first sidewall insulating layer 192i. Here, the thickness T1 of the first portion R1 may refer to the average thickness of the first portion R1 or the thickness of the portion adjacent to the second portion R2, and the thickness T2 of the second portion R2 may refer to the average thickness of the second portion R2 or the thickness of the portion adjacent to the first portion R1.

[0074] When viewed in the vertical direction (the Z-axis direction in the figure), the first portion R1 may be located on an upper portion of the first contact portion 192 and spaced apart from a lower surface of the first contact portion 192. For example, the upper surface of the first portion R1 may be located adjacent to the upper surface of the first contact portion 192 (e.g., located on the same plane as the upper surface of the first contact portion 192). The lower surface of the first portion R1 may be located spaced apart from the lower surface of the first contact portion 192. The lower surface of the first portion R1 may be located spaced apart from the lower surface of the first contact portion 192 across a portion corresponding to at least one through gate electrode 130p (e.g., a plurality of through gate electrodes 130p).

[0075] When viewed in the vertical direction (the Z-axis direction in the figure), the second portion R2 may be located below the first portion R1. In this case, the second portion R2 may include a portion corresponding to at least one of the plurality of gate electrodes 130.

[0076] In an embodiment, the first sidewall insulating layer 192i may include a first layer 190a partially located in the first portion R1 and a second layer 190b located in both the first portion R1 and the second portion R2 and on the inner surface of the first layer 190a.

[0077] More specifically, the first layer 190a may be located on (e.g., in contact with) the side surface of the gate stack 120 at the first portion R1. The second layer 190b may be located on (e.g., in contact with) the inner surface of the first layer 190a at the first portion R1, and may be located on (e.g., in contact with) the side surface of the gate stack 120 at the second portion R2. However, the embodiment is not limited thereto. In another embodiment, another layer may be located between two adjacent portions of the gate stack 120, the first layer 190a, and the second layer 190b.

[0078] The inner surface of the first sidewall insulating layer 192i (e.g., the second layer 190b) may contact the outer surface of the first conductive portion 192c. However, the embodiment is not limited thereto, and another layer may be located between the inner surface of the first sidewall insulating layer 192i (e.g., the second layer 190b) and the outer surface of the first conductive portion 192c.

[0079] In this manner, the first portion R1 may include both the first layer 190a and the second layer 190b, and the second portion R2 may include only the second layer 190b without the first layer 190a. That is, the first portion R1 and the second portion R2 may have different stacking structures, and therefore may have different thicknesses.

[0080] The inner surface of the first sidewall insulating layer 192i (e.g., the second layer 190b) may have an inclined surface inclined with respect to the vertical direction of the semiconductor device 10 (the Z-axis direction in the figure) without a step or bend. The outer surface of the first sidewall insulating layer 192i (e.g., the first layer 190a and the second layer 190b) may have an inclined surface inclined with respect to the vertical direction, and a step S may be formed between the first portion R1 and the second portion R2. However, the embodiment is not limited thereto. As another example, the inner surface of the first sidewall insulating layer 192i (e.g., the second layer 190b) may have a vertical surface parallel to the vertical direction of the semiconductor device 10 (the Z-axis direction in the figure) without a step or bend. The outer surface of the first sidewall insulating layer 192i (e.g., the first layer 190a and the second layer 190b) may have a vertical surface parallel to the vertical direction, and a step S may be formed between the first portion R1 and the second portion R2.

[0081] The first layer 190a may be an insulating layer that protects a stack structure (reference numeral 120s in FIG. 7, the same applies hereinafter) for forming the gate stack structure 120 in a subsequent partial etching process (e.g., a fourth partial etching process E4). For example, the first layer 190a may be an insulating layer that protects the stack structure 120s in a subsequent partial etching process using a hard mask. The first layer 190a may be referred to as a protection layer, a cover layer, a liner layer, a first insulating layer, etc. By protecting the stack structure 120s with the first layer 190a, the depth of the through hole PH formed in the subsequent partial etching process can be increased, thereby reducing the process time and cost for forming the through hole PH. This will be described in more detail in the method for manufacturing the semiconductor device 10.

[0082] The second layer 190b may be an insulating layer formed in the through holes PH to electrically insulate the through gate electrodes 130p and the first conductive portions 192c after all the processes for forming the through holes PH are performed. The second layer 190b may be referred to as an electrical insulating layer, a second insulating layer, etc.

[0083] When the first layer 190a and the second layer 190b contain different materials, the boundary between the first layer 190a and the second layer 190b can be identified. Even when the first layer 190a and the second layer 190b contain the same material, the boundary between the first layer 190a and the second layer 190b can be identified due to the manufacturing process. For example, the first layer 190a and the second layer 190b may be formed using different processes and have different compositions or properties, or the properties of the inner surface of the first layer 190a may change due to the passage of time between the process of forming the first layer 190a and the process of forming the second layer 190b, making it possible to identify the boundary between the first layer 190a and the second layer 190b. Even if the first layer 190a and the second layer 190b contain the same material and it is difficult to identify the boundary between the first layer 190a and the second layer 190b, the positions of the first layer 190a and the second layer 190b can be determined or predicted by the difference in thickness between the first portion R1 and the second portion R2 or the step S located between the first portion R1 and the second portion R2.

[0084] For example, the distance between the inner surface of the gate electrode 130 corresponding to the first portion R1 and the first conductive portion 192c may be greater than the distance between the inner surface of the gate electrode 130 corresponding to the second portion R2 and the first conductive portion 192c. Here, the distance between the inner surface of the gate electrode 130 and the first conductive portion 192c may be the distance between the inner surface of the gate electrode 130 adjacent to the first conductive portion 192c and the outer surface of the first conductive portion 192c, measured in the extension direction of the gate electrode 130. When a plurality of gate electrodes 130 corresponding to the first portion R1 are provided and a plurality of gate electrodes 130 corresponding to the second portion R2 are provided, the plurality of gate electrodes 130 corresponding to the first portion R1 may have sloping inner surfaces parallel to the sloping outer surfaces of the first conductive portions 192c, and the plurality of gate electrodes 130 corresponding to the second portion R2 may have sloping inner surfaces parallel to the sloping outer surfaces of the first conductive portions 192c. The plurality of gate electrodes 130 corresponding to the first portion R1 and the plurality of gate electrodes 130 corresponding to the second portion R2 may be located at positions spaced apart from each other by an amount corresponding to the step S.

[0085] In some embodiments, the first layer 190a and / or the second layer 190b may include various insulating materials. For example, the first layer 190a and the second layer 190b may include the same material, or the first layer 190a and the second layer 190b may include different materials.

[0086] For example, first layer 190a may include an oxide (e.g., silicon oxide), an oxynitride (e.g., silicon oxynitride), a low-k material having a dielectric constant lower than that of silicon oxide, or a combination thereof. First layer 190a may include a single layer or multiple layers. For example, second layer 190b may include an oxide (e.g., silicon oxide), a nitride (e.g., silicon nitride), an oxynitride (e.g., silicon oxynitride), a low-k material having a dielectric constant lower than that of silicon oxide, or a combination thereof. Second layer 190b may include a single layer or multiple layers.

[0087] In one embodiment, the thickness difference TD between the thickness T1 of the first portion R1 and the thickness T2 of the second portion R2 in a direction perpendicular to the side surface of the first sidewall insulating layer 192i, the height of the step S, or the thickness of the first layer 190a may be 0.5 nm or more (e.g., 1 nm or more). Accordingly, the first layer 190a has a thickness of 0.5 nm or more (e.g., 1 nm or more) and can stably perform its role of protecting the stacked structure 120s.

[0088] For example, in a direction perpendicular to the side surface of the first sidewall insulating layer 192i, the thickness difference TD between the thickness T1 of the first portion R1 and the thickness T2 of the second portion R2, the height of the step S, or the thickness of the first layer 190a may be 20 nm or less (e.g., 10 nm or less, as an example, 5 nm or less). In this way, the thickness of the first layer 190a may be reduced to ensure a sufficient area or volume of the first conductive portion 192c.

[0089] However, the embodiment is not limited thereto, and the thickness of the first layer 190a can be less than 0.5 nm (for example, less than 1 nm) or greater than 20 nm (for example, 10 nm, for example, 5 nm).

[0090] In one embodiment, the ratio T2 / T1 of the thickness T2 of the second portion R2 to the thickness T1 of the first portion R1 in a direction perpendicular to the side of the first sidewall insulating layer 192i may be 0.5 to 1. Alternatively, the thickness difference TD between the thickness T1 of the first portion R1 and the thickness T2 of the second portion R2 in a direction perpendicular to the side of the first sidewall insulating layer 192i, the height of the step S, or the thickness of the first layer 190a may be the same as or smaller than the thickness T2 of the second portion R2 or the thickness of the second layer 190b. The first layer 190a may have a relatively small thickness sufficient to protect the stack structure 120s in a subsequent partial etching process, and the second layer 190b may have a relatively large thickness sufficient to improve the electrical insulation characteristics of the gate stack structure 120 and the first conductive portion 192c. However, embodiments are not limited thereto. In another embodiment, the ratio T2 / T1 of the thickness T2 of the second portion R2 to the thickness T1 of the first portion R1 in the direction perpendicular to the side surface of the first sidewall insulating layer 192i may be less than 0.5. In another embodiment, the thickness difference TD between the thickness T1 of the first portion R1 and the thickness T2 of the second portion R2, the height of the step S, or the thickness of the first layer 190a may be greater than the thickness T2 of the second portion R2 or the thickness of the second layer 190b.

[0091] In one embodiment, the thickness difference TD between the thickness T1 of the first portion R1 and the thickness T2 of the second portion R2 in a direction perpendicular to the side surface of the first sidewall insulating layer 192i, the height of the step S, or the thickness of the first layer 190a may be smaller than the thickness of the interlayer insulating layer 132 or the thickness of the gate electrode 130 in the vertical direction (the Z-axis direction in the figure). The first layer 190a may have a relatively small thickness sufficient to protect the stacked structure 120s in a subsequent partial etching process. However, the embodiment is not limited thereto. In other embodiments, the thickness difference TD between the thickness T1 of the first portion R1 and the thickness T2 of the second portion R2, the height of the step S, or the thickness of the first layer 190a may be the same as or greater than the thickness of the interlayer insulating layer 132 or the thickness of the gate electrode 130.

[0092] However, the embodiments are not limited to these, and the thickness difference TD between the thickness T1 of the first portion R1 and the thickness T2 of the second portion R2, the height of the step S, the thickness of the first layer 190a, the thickness of the second layer 190b, etc. may be modified in various ways.

[0093] For clear understanding, the drawings illustrate the first layer 190a and the second layer 190b as including portions sequentially located on the upper surface of the gate stack structure 120, and show the portions of the first layer 190a and the second layer 190b located on the upper surface of the gate stack structure 120, as well as the boundary of the gate stack structure 120. However, the embodiments are not limited thereto. Depending on the embodiment, the portions of the first layer 190a and / or the second layer 190b located on the upper surface of the gate stack structure 120 may be removed. Alternatively, the boundaries of the portions of the first layer 190a and / or the second layer 190b located on the upper surface of the gate stack structure 120 may not be visible in the final structure.

[0094] As shown in FIG. 6 , the second conductive portion 196c of the second contact portion 196 may include a conductive material and may fill at least a portion of the through-hole PH except for the second sidewall insulating layer 196i. For example, the second conductive portion 196c may include tungsten (W), copper (Cu), aluminum (Al), or the like, and may further include a diffusion barrier layer. The second conductive portion 196c may include the same conductive material as the first conductive portion 192c and may be formed together with the first conductive portion 192c in the same process. However, embodiments are not limited thereto. In other embodiments, the second conductive portion 196c may include a different conductive material than the first conductive portion 192c and may be formed separately from the first conductive portion 192c in a different process. Thus, embodiments are not limited to the material of the second conductive portion 196c.

[0095] The second sidewall insulating layer 196i of the second contact portion 196 may have a different shape or structure from the first sidewall insulating layer 192i. For example, the second sidewall insulating layer 196i may not include a layer included in the first sidewall insulating layer 192i, may include a layer not included in the first sidewall insulating layer 192i, or may have differences in the shape, arrangement, relative positional relationship, etc. of the layers included in the first sidewall insulating layer 192i (e.g., the first layer 190a and the second layer 190b).

[0096] For example, the second sidewall insulating layer 196i may entirely include a portion corresponding to the first portion R1 of the first sidewall insulating layer 192i (e.g., a portion having the same material, structure, or thickness as the first portion R1), but may not include a portion corresponding to the second portion R2. That is, the first sidewall insulating layer 192i and the second sidewall insulating layer 196i may differ from each other in the arrangement or relative positions of the first layer 190a and the second layer 190b.

[0097] In the embodiment, the second sidewall insulating layer 196i may include a first layer 190a and a second layer 190b that extend entirely and continuously from the top surface to the bottom surface of the second contact portion 196. That is, the portion of the second sidewall insulating layer 196i that includes the first layer 190a and the second layer 190b (i.e., the portion corresponding to the first portion R1) may be located entirely from the top surface to the bottom surface of the second contact portion 196.

[0098] More specifically, the first layer 190a of the second sidewall insulating layer 196i may be located on the side surface of the gate stack 120, and the second layer 190b may be located on the inner surface of the first layer 190a. That is, the second sidewall insulating layer 196i may not include a portion of the second layer 190b that contacts the side surface of the gate stack 120. For example, the first layer 190a of the second sidewall insulating layer 196i may contact the side surface of the gate stack 120, and the second layer 190b may contact the first layer 190a. However, the embodiment is not limited thereto. In other embodiments, another layer may be located between the first layer 190a and the side surface of the gate stack 120, or between the second layer 190b and the first layer 190a.

[0099] The inner surface of the second sidewall insulating layer 196i (e.g., second layer 190b) may contact the outer surface of the second conductive portion 196c. However, the embodiment is not limited thereto, and another layer may be located between the inner surface of the second sidewall insulating layer 196i (e.g., second layer 190b) and the outer surface of the second conductive portion 196c.

[0100] In this manner, the first layer 190a and the second layer 190b are located together throughout the entire second sidewall insulating layer 196i, allowing the second sidewall insulating layer 196i to have the same overall stacked structure. Therefore, the second sidewall insulating layer 196i may have the same overall thickness. Here, the term "the same overall thickness" may refer to a case where there is a thickness difference due to process error (e.g., a thickness difference of 10% or less, or a thickness difference of less than 0.5 nm). However, the embodiment is not limited thereto.

[0101] The inner surface of the second sidewall insulating layer 196i (e.g., the second layer 190b) may have an inclined surface inclined with respect to the vertical direction of the semiconductor device 10 (the Z-axis direction in the figure) without a step or bend. The outer surface of the second sidewall insulating layer 196i (e.g., the first layer 190a) may have an inclined surface inclined with respect to the vertical direction without a step or bend. However, the embodiment is not limited thereto. As another example, the inner surface of the second sidewall insulating layer 196i (e.g., the second layer 190b) may have a vertical surface parallel to the vertical direction of the semiconductor device 10 (the Z-axis direction in the figure) without a step or bend. The outer surface of the second sidewall insulating layer 196i (e.g., the first layer 190a) may have a vertical surface parallel to the vertical direction.

[0102] In an embodiment, the first contact portion 192 may include a plurality of first contact portions 192 having different depths, and the second contact portion 196 may include a plurality of second contact portions 196 having different depths. In this case, the plurality of first contact portions 192 may include a first basic contact portion 193 and may further include a first additional contact portion 194.

[0103] The process of forming the plurality of contact portions 190 (e.g., the plurality of first contact portions 192 and the plurality of second contact portions 196) may include a preceding partial etching process (see FIGS. 8 to 10) and a process of forming the first layer 190a (see FIG. 11) performed before the process of forming the first layer 190a, a subsequent partial etching process (see FIG. 13) and / or an additional etching process EA (see FIG. 14) performed after the process of forming the first layer 190a, a process of forming the second layer 190b (see FIG. 15), and a process of forming the conductive portion 190c (see FIG. 17).

[0104] In this case, the multiple partial etching processes (preceding partial etching process and succeeding partial etching process) may etch the interlayer insulating layer 132 and the layer located thereover (e.g., the sacrificial insulating layer (reference numeral 130s in FIG. 7 ; the same applies hereinafter)) in a binary system to form the through-hole PH. For example, the preceding partial etching process and / or the succeeding partial etching process may etch 1, 2, 4, ..., 2(m-1)-th power of the interlayer insulating layer 132 and the sacrificial insulating layer 130s located thereover. Here, m is a natural number greater than 1 and may represent the total number of partial etching processes. The mth partial etching process is the longest partial etching process that performs the deepest etching process, and may perform an etching process deeper than the other partial etching processes and the additional etching process EA.

[0105] For example, the first partial etching process E1 can etch one interlayer insulating layer 132, which is 2 to the power of 0, and the nth partial etching process can etch 2 to the power of (n-1) interlayer insulating layers 132 and the sacrificial insulating layers 130s located thereon.

[0106] By repeating the partial etching process using the binary system in this manner, it is possible to form a plurality of through holes PH having different depths with a small number of etching processes. For example, by repeating the partial etching process using the binary system four times, it is possible to form 15 through holes PH having different depths, by repeating the partial etching process using the binary system five times, it is possible to form 31 through holes PH having different depths, and by repeating the partial etching process using the binary system six times, it is possible to form 63 through holes PH having different depths. This effectively reduces the number of etching processes.

[0107] As described above, for clarity and simplicity, the figures illustrate the inclusion of 16 gate electrodes 130. In this case, four partial etching processes, i.e., first to fourth partial etching processes E1, E2, E3, and E4, and one additional etching process EA, are performed to form 16 through holes PH corresponding to the 16 gate contact portions 190, respectively. Hereinafter, the first to third partial etching processes E1, E2, and E3 correspond to the preceding partial etching process, and the fourth partial etching process E4 corresponds to the following partial etching process. However, the embodiments are not limited thereto. Therefore, the number of gate electrodes 130 may be varied, the number of partial etching processes and / or the number of additional etching processes EA may be varied, and the number of preceding partial etching processes and / or the number of following partial etching processes may be varied.

[0108] Here, the process of forming the first contact portion 192 may include a preceding partial etching process, a process of forming the first layer 190a, a subsequent partial etching process and / or an additional etching process EA, a process of forming the second layer 190b, and a process of forming the conductive portion 190c.

[0109] The process of forming the first basic contact portion 193 of the first contact portion 192 may include a preceding partial etching process, a process of forming the first layer 190a, a subsequent partial etching process, a process of forming the second layer 190b, and a process of forming the conductive portion 190c. For example, referring to Figures 3 and 4, the fifteenth gate contact portion 1915, which is the first basic contact portion 193, may be formed by performing first to third partial etching processes E1, E2, and E3 of the preceding partial etching process, forming the first layer 190a on the inner surface of the portion formed by the first to third partial etching processes E1, E2, and E3, and performing a fourth partial etching process E4 of the subsequent partial etching process to form the second layer 190b and the conductive portion 190c. As a result, a first portion R1 where the first layer 190a and the second layer 190b are both located may be located in the portion formed by the first to third partial etching processes E1, E2, and E3, and a second portion R2 where the second layer 190b is located may be located in the portion formed by the fourth partial etching process E4.

[0110] The process of forming the first additional contact portion 194 of the first contact portion 192 may include a preceding partial etching process, a process of forming the first layer 190a, a subsequent partial etching process (an additional etching process EA), a process of forming the second layer 190b, and a process of forming the conductive portion 190c. For example, referring to FIGS. 3 and 5, the sixteenth gate contact portion 1916, which is the first additional contact portion 194, may be formed by performing first to third partial etching processes E1, E2, and E3 of the preceding partial etching process, forming the first layer 190a on the inner surface of the portion formed by the first to third partial etching processes E1, E2, and E3, and performing a fourth partial etching process E4 of the subsequent partial etching process and an additional etching process EA to form the second layer 190b and the conductive portion 190c. As a result, a first portion R1 where the first layer 190a and the second layer 190b are both located may be located in the portion formed by the first to third partial etching processes E1, E2, and E3, and a second portion R2 where the second layer 190b is located may be located in the portion formed by the fourth partial etching process E4 and the additional etching process EA.

[0111] The process of forming the second contact portion 196 may include a preceding partial etching process, a process of forming the first layer 190a, a process of forming the second layer 190b, and a process of forming the conductive portion 190c. That is, the process of forming the second contact portion 196 may not include a subsequent partial etching process and / or an additional etching process EA. For example, referring to FIGS. 3 and 6, the fifth gate contact portion 1905, which is the second contact portion 196, may be formed by performing the first and third partial etching processes E1 and E3 of the preceding partial etching process, forming the first layer 190a on the inner surface of the portion formed by the first and third partial etching processes E1 and E3, and forming the second layer 190b and the conductive portion 190c. As a result, the first layer 190a and the second layer 190b may be located together in the entire portion formed by the first and third partial etching processes E1 and E3. As a result, the second layer 190b may not have a portion where it is located without the first layer 190a (for example, a portion corresponding to the second portion R2 of the first sidewall insulating layer 192i).

[0112] In some embodiments, the depth of each of the first contact portions 192 may be greater than the depth of each of the second contact portions 196. As described above, this is because the first contact portions 192 are formed by additionally performing a subsequent partial etching process and / or an additional etching process EA, compared to the second contact portions 196.

[0113] In the embodiment, the number of the first contact portions 192 may be greater than the number of the second contact portions 196. The total number of through holes PH having different depths that can be formed by performing the first partial etching process E1 to the nth partial etching process may correspond to the sum of all of 1, 2, 4, ..., 2 to the (n-1)th power, or the value obtained by subtracting 1 from 2 to the (n-1)th power (i.e., 2n-1-1). Also, the total number of through holes PH having different depths that can be formed by performing the (n+1)th partial etching process may correspond to the nth power of 2 (i.e., 2n). That is, the total number of through holes PH having different depths that can be formed by performing the first partial etching process E1 to the nth partial etching process may correspond to the nth power of 2 (i.e., 2n). The number of through holes PH having different depths that can be formed by performing the (n+1)th partial etching process may be greater than the number of through holes PH. For example, the total number of through holes PH having different depths that can be formed by performing the first to third partial etching processes E1, E2, and E3 may be seven, and the total number of through holes PH having different depths that can be formed by performing the fourth partial etching process E4 may be eight. The first contact portion 192 may further include a first additional contact portion 194 that is formed by performing an additional etching process EA.

[0114] However, the embodiment is not limited to this example, and the number of first contact portions 192 may be equal to or less than the number of second contact portions 196 depending on the order of the partial etching steps and the additional etching step EA performed in binary.

[0115] In the embodiment, in each first contact portion 192, the number of gate electrodes 130 (e.g., connecting gate electrodes 130c and / or remaining gate electrodes 130r) located corresponding to the second portion R2 may be greater than the number of gate electrodes 130 (e.g., through gate electrodes 130p) located corresponding to the first portion R1. The number of interlayer insulating layers 132 that can be etched by performing the first partial etching process E1 through the nth partial etching process may correspond to the sum of 1, 2, 4, ..., 2 to the (n-1)th power or the sum of 2 to the (n-1)th power minus 1 (i.e., 2n-1-1). The number of interlayer insulating layers 132 that can be etched by performing the (n+1)th partial etching process may correspond to the nth power of 2 (i.e., 2n). That is, the number of interlayer insulating layers 132 that can be formed by performing the (n+1)th partial etching process may be greater than the number of interlayer insulating layers 132 that can be etched by performing the first partial etching process E1 through the nth partial etching process. Therefore, the number of gate electrodes 130 located in the portion corresponding to the (n+1)th partial etching process may be greater than the number of gate electrodes 130 located in the portions corresponding to the first partial etching process E1 to the nth partial etching process. For example, the total number of interlayer insulating layers 132 that can be etched by performing the first to third partial etching processes E1, E2, and E3 may be seven, and the total number of gate electrodes 130 located thereon may be six. The number of interlayer insulating layers 132 that can be etched by performing the fourth partial etching process E4 may be eight, and the number of gate electrodes 130 located thereon may be seven or eight.

[0116] Therefore, the number of gate electrodes 130 located corresponding to the second portion R2 formed by the subsequent partial etching process may be greater than the number of gate electrodes 130 located corresponding to the first portion R1. The second portion R2 may further include a portion formed by performing the additional etching process EA.

[0117] However, the embodiment is not limited thereto, and depending on the order of the partial etching processes and the additional etching process EA performed in binary order, the number of gate electrodes 130 located corresponding to the second portion R2 may be equal to or less than the number of gate electrodes 130 located corresponding to the first portion R1.

[0118] In one embodiment, the subsequent partial etching process performed after the process of forming the first layer 190a may include an mth partial etching process of the longest partial etching process. For example, if the partial etching process includes first to fourth partial etching processes E1, E2, E3, and E4, the subsequent partial etching process may include a fourth partial etching process E4. In this manner, the gate stack structure 120 is formed in the longest partial etching process, which performs an etching process to the maximum depth, so that the first layer 190a can stably protect the stack structure 120s.

[0119] However, the embodiment is not limited to this. Therefore, the subsequent partial etching process may include a plurality of partial etching processes, or the order of the plurality of partial etching processes performed in binary may be changed. Various other modifications are possible.

[0120] According to the embodiment, a plurality of through holes PH for forming a plurality of gate contact portions 190 are formed using a partial etching process based on a binary system, thereby simplifying the process of forming the gate contact portions 190 and reducing the area of ​​the connection region 104. By forming the first layer 190a before the subsequent partial etching process, damage to the stacked structure 120s that may occur in the subsequent partial etching process can be prevented, and through holes PH having a relatively large depth can be stably formed. As a result, the reliability and productivity of the semiconductor device 10 can be improved.

[0121] In particular, when the number of gate electrodes 130 included in the gate stack structure 120 increases to increase memory capacity, the number of gate contact portions 190 also increases, and the gate contact portions 190 may have a larger aspect ratio. When the embodiment is applied to this, the area of ​​the connection region 104 may be more effectively reduced, and the through hole PH having a relatively large depth may be more stably formed.

[0122] A method for manufacturing a semiconductor device according to one embodiment will be described in more detail below with reference to Figures 7 to 18. Detailed descriptions of parts that have already been described will be omitted, and parts that have not been described will be described in detail.

[0123] 7 to 18 are partial cross-sectional views illustrating a method for manufacturing a semiconductor device according to an embodiment. Figures 7, 16, and 18 illustrate both the cell array region 102 and the connection region 104, corresponding to a portion of Figure 1, while Figures 8 to 15 and 17 illustrate the connection region 104, corresponding to Figure 3. Hereinafter, the method for manufacturing the semiconductor device 10 will be described, focusing on the gate stack structure 120, the channel structure CH, the isolation structure 146, and the gate contact portion 190.

[0124] 7, a second substrate 110 and a stacked structure 120s may be formed on the circuit region 200, and a channel sacrificial layer 122s may be formed to penetrate the stacked structure 120s. In this case, the stacked structure 120s may be formed after forming the horizontal insulating layer 116 and the second horizontal conductive layer 114 on the second substrate 110, and the channel sacrificial layer 122s may be formed to penetrate the stacked structure 120s, the horizontal insulating layer 116, and the second horizontal conductive layer 114.

[0125] More specifically, the second substrate 110 may be formed on the circuit region 200, and the horizontal insulating layer 116, the second horizontal conductive layer 114, and the laminated structure 120s may be formed on the second substrate 110. In this case, the interlayer insulating layer 132 and the sacrificial insulating layer 130s may be alternately stacked to form the laminated structure 120s.

[0126] Here, the sacrificial insulating layer 130s may be formed to correspond to a portion where the gate electrode 130 will be formed, as a layer to be replaced with a gate electrode (reference numeral 130 in FIG. 16 , the same applies hereinafter) through a subsequent process. At least a portion of the horizontal insulating layer 116 may be formed to include a portion where the first horizontal conductive layer 112 will be formed, as a layer to be replaced with a first horizontal conductive layer (reference numeral 112 in FIG. 16 , the same applies hereinafter) through a subsequent process.

[0127] The horizontal insulating layer 116 and / or the sacrificial insulating layer 130s may be formed of other materials than the interlayer insulating layer 132. For example, the interlayer insulating layer 132 may include silicon oxide, silicon nitride, silicon oxynitride, a low-k material, etc., and the sacrificial insulating layer 130s may include at least one of silicon, silicon oxide, silicon carbide, and silicon nitride, and may be formed of other materials than the interlayer insulating layer 132.

[0128] In an exemplary embodiment, the stacked structure 120s may include a plurality of stacked structures 120d, 120e sequentially stacked on the second substrate 110, and the channel sacrificial layer 122s may include a plurality of channel sacrificial portions penetrating the plurality of stacked structures 120d, 120e, although the embodiment is not limited thereto.

[0129] In the embodiment, the stacked structure 120s may be formed in the region where the channel sacrificial layer 122s is located in the cell array region 102, and may be formed in the region where the gate contact portion (reference numeral 190 in FIG. 17, the same below) is located in the connection region 104.

[0130] A preliminary through hole may be formed through the stacked structure 120s corresponding to a portion where a channel structure (reference symbol CH in FIG. 16 , the same applies hereinafter) will be formed, and a sacrificial material may be filled in the preliminary through hole to form a channel sacrificial layer 122s. The preliminary through hole may be formed by an etching process (e.g., a dry etching process), and the process of filling the preliminary through hole may be performed by various processes (e.g., a deposition process). The channel sacrificial layer 122s may include at least one of polycrystalline silicon, tungsten, titanium nitride, and carbon. However, embodiments are not limited thereto, and the channel sacrificial layer 122s may include various materials.

[0131] 8 to 14, a plurality of partial etching processes (e.g., first to fourth partial etching processes E1, E2, E3, and E4) and / or an additional etching process EA may be performed to form a plurality of through holes PH to form a plurality of gate contact portions 190. The first layer 190a may be formed between two consecutive processes included in the plurality of partial etching processes.

[0132] 8 to 14 and the accompanying description illustrate an example in which there are 16 sacrificial insulating layers 130s and first to fourth partial etching processes E1, E2, E3, and E4 and one additional etching process EA are performed. For clarity, FIGS. 8 to 14 illustrate the locations of first to fifth through holes PH1 to PH5 corresponding to the first to fifth gate contact portions and thirteenth to sixteenth through holes PH13 to PH16 corresponding to the thirteenth to sixteenth gate contact portions. However, embodiments are not limited thereto, and the number of sacrificial insulating layers 130s may vary, and the number of partial etching processes and / or the number of additional etching processes EA may vary depending on the number of sacrificial insulating layers 130s.

[0133] In an embodiment, the number of interlayer insulating layers 132 (vertical positions or levels) located on each sacrificial insulating layer 130s can be converted into a binary system, and multiple partial etching processes (e.g., first to fourth partial etching processes E1, E2, E3, E4) and / or additional etching processes EA can be performed accordingly to form multiple through holes PH having different depths.

[0134] The multiple partial etching processes (e.g., first to fourth partial etching processes E1, E2, E3, and E4) may correspond to cyclic etching processes in which a mask is formed, etching is performed in a binary system, and then the mask is removed. For example, the multiple partial etching processes may form the through-hole PH by etching the interlayer insulating layer 132 and a layer located thereover (e.g., a sacrificial insulating layer (reference numeral 130s in FIG. 7 ) (the same applies hereinafter) in a binary system. For example, the multiple partial etching processes may etch 1, 2, 4, ..., 2(m-1)-th power of the interlayer insulating layer 132 and the sacrificial insulating layer 130s located thereover. Here, m may be a natural number greater than 1 and represent the total number of partial etching processes. The mth partial etching process is the longest partial etching process, which performs an etching process to a maximum depth, and may perform an etching process to a depth greater than the other partial etching processes and the additional etching process EA.

[0135] For example, the position of the topmost first interlayer insulating layer (i.e., 1) is converted to binary 1, so a first partial etching process E1 is performed to etch the topmost first interlayer insulating layer to form a first through-hole PH1 reaching the first sacrificial insulating layer. The position of the fifth interlayer insulating layer (i.e., 5) is converted to binary 101, so a first partial etching process E1 and a third partial etching process E3 are performed to form a fifth through-hole PH5 reaching the fifth sacrificial insulating layer. The position of the fifteenth interlayer insulating layer (i.e., 15) is converted to binary 1111, so a first partial etching process E1, a second partial etching process E2, a third partial etching process E3, and a fourth partial etching process E4 are performed to form a fifteenth through-hole PH15 reaching the fifteenth sacrificial insulating layer. The position of the 16th interlayer insulating layer (i.e., 16), which is the 16th from the top, is the value obtained by adding 1 to 1111 converted to binary, so after performing the first partial etching process E1, the second partial etching process E2, the third partial etching process E3, and the fourth partial etching process E4, an additional etching process EA can be performed to form a 16th through hole PH16 that reaches the 16th sacrificial insulating layer.

[0136] In this embodiment, the first layer 190a may be formed between two consecutive partial etching processes (e.g., first to fourth partial etching processes E1, E2, E3, and E4). In this regard, when the first layer 190a is used as a reference, a partial etching process performed before the process of forming the first layer 190a may be referred to as a preceding partial etching process, and a partial etching process performed after the process of forming the first layer 190a may be referred to as a succeeding partial etching process. The fourth partial etching process E4, which performs the partial etching to the maximum depth, may be referred to as the longest partial etching process.

[0137] In an embodiment, a step of forming the first layer 190a may be performed before the longest portion etching step. For example, the first layer 190a may be formed between the third partial etching step E3 and the fourth partial etching step E4 of the longest portion etching step. The first to third partial etching steps E1, E2, and E3 may be preceding partial etching steps, and the fourth partial etching step E4 of the longest portion etching step may be a succeeding partial etching step.

[0138] 8, in the first partial etching process E1, portions of the plurality of through holes PH to be subjected to the first partial etching process E1 may be selectively etched. For example, in the first partial etching process E1, one interlayer insulating layer 132 (e.g., the uppermost first interlayer insulating layer) may be etched in portions corresponding to the first through hole PH1, the third through hole PH3, the fifth through hole PH5, the seventh through hole, the ninth through hole, the eleventh through hole, the thirteenth through hole PH13, the fifteenth through hole PH15, and the sixteenth through hole PH16.

[0139] Here, the first partial etching step E1 of the preceding partial etching process can use a photoresist layer containing a photosensitive material as a mask. For example, after forming a photoresist layer on the stacked structure 120s, a patterning process for forming first openings P1 can be performed in the area where the first partial etching step E1 is to be performed, thereby forming the first photoresist mask M1. The patterning process for forming the first openings P1 can be performed using a photolithography process. In this way, since an etching process is not used in the patterning process for forming the first openings P1, the first photoresist mask M1 can be formed without damaging the stacked structure 120s.

[0140] Then, a first partial etching process E1 may be performed to etch one interlayer insulating layer 132 (e.g., the uppermost first interlayer insulating layer) in a portion exposed through the first opening P1 of the first photoresist mask M1. The first partial etching process E1 may be performed using various etching processes (e.g., a dry etching process). After the etching process is performed, the first photoresist mask M1 may be removed. Various processes may be used to remove the first photoresist mask M1.

[0141] 9 , the second partial etching process E2 may selectively etch portions of the through holes PH where the second partial etching process E2 is to be performed. For example, the second partial etching process E2 may etch two interlayer insulating layers 132 and one or two sacrificial insulating layers 130s located thereon in portions corresponding to the second through hole PH2, the third through hole PH3, the sixth through hole PH14, the seventh through hole PH10, the eleventh through hole PH11, the fourteenth through hole PH15, the fifteenth through hole PH15, and the sixteenth through hole PH16. More specifically, the two interlayer insulating layers 132 and one sacrificial insulating layer 130s located thereon may be etched in portions corresponding to the second through hole PH2, the sixth through hole PH14, the tenth through hole, and the fourteenth through hole PH14, where the second partial etching process E2 is first performed. In the areas corresponding to the third through hole PH3, the seventh through hole, the eleventh through hole, the fifteenth through hole PH15, and the sixteenth through hole PH16, where the second partial etching process E2 is performed after the first partial etching process E1, two interlayer insulating layers 132 and two sacrificial insulating layers 130s located thereon can be etched.

[0142] Here, the second partial etching step E2 of the preceding partial etching step can use a photoresist layer containing a photosensitive material as a mask. For example, after forming a photoresist layer on the stacked structure 120s, a patterning process for forming second openings P2 can be performed in the areas where the second partial etching step E2 will be performed, thereby forming the second photoresist mask M2. The patterning process for forming the second openings P2 can be performed using a photolithography process. In this way, since the patterning process for forming the second openings P2 does not use an etching process, the second photoresist mask M2 can be formed without damaging the stacked structure 120s.

[0143] Then, a second partial etching process E2 may be performed to etch the two interlayer insulating layers 132 and one or two sacrificial insulating layers 130s located thereon in the portions exposed through the second openings P2 of the second photoresist mask M2. The second partial etching process E2 may be performed using various etching processes (e.g., dry etching processes). After the etching process is performed, the second photoresist mask M2 may be removed. Various processes may be used to remove the second photoresist mask M2.

[0144] 10 , the third partial etching process E3 may selectively etch portions of the through holes PH that are to be subjected to the third partial etching process E3. For example, the third partial etching process E3 may etch four interlayer insulating layers 132 and three or four sacrificial insulating layers 130s located thereon in portions corresponding to the fourth through hole PH4, the fifth through hole PH5, the sixth through hole, the seventh through hole, the twelfth through hole, the thirteenth through hole PH13, the fourteenth through hole PH14, the fifteenth through hole PH15, and the sixteenth through hole PH16. More specifically, the four interlayer insulating layers 132 and three sacrificial insulating layers 130s located thereon may be etched in a portion corresponding to the fourth through hole PH4, where the third partial etching process E3 is first performed. In the areas corresponding to the fifth through hole PH5, the sixth through hole, the seventh through hole, the twelfth through hole, the thirteenth through hole PH13, the fourteenth through hole PH14, the fifteenth through hole PH15 and the sixteenth through hole PH16, where the third partial etching process E3 is performed after the first partial etching process E1 and / or the second partial etching process E2, the four interlayer insulating layers 132 and the four sacrificial insulating layers 130s located thereon can be etched.

[0145] Here, the third partial etching step E3 of the preceding partial etching step can use a photoresist layer containing a photosensitive material as a mask. For example, a photoresist layer can be formed on the stacked structure 120s, and then a patterning process can be performed to form third openings P3 in the areas where the third partial etching step E3 will be performed, thereby forming the third photoresist mask M3. The patterning process to form the third openings P3 can be performed using a photolithography process. In this way, since the patterning process to form the third openings P3 does not use an etching process, the third photoresist mask M3 can be formed without damaging the stacked structure 120s.

[0146] Then, a third partial etching process E3 may be performed to etch the four interlayer insulating layers 132 and the three or four sacrificial insulating layers 130s located thereon in the portions exposed through the third openings P3 of the third photoresist mask M3. The third partial etching process E3 may be performed using various etching processes (e.g., dry etching processes). After the etching process is performed, the third photoresist mask M3 may be removed. Various processes may be used to remove the third photoresist mask M3.

[0147] After performing the first to third partial etching steps E1, E2, and E3 of the preceding partial etching step in this manner, the first layer 190a can be formed as shown in Fig. 11. As a result, the first layer 190a can be formed between the first to third partial etching steps E1, E2, and E3 of the preceding partial etching step and the fourth partial etching step E4 of the following partial etching step.

[0148] The first layer 190a may be formed inside the plurality of through-holes PH. For example, the first layer 190a may be formed on the inner surface and the lower surface of each of the plurality of through-holes PH, and may also be formed on the upper surface of the stacked structure 120s. The process of forming the first layer 190a may be performed by various processes (e.g., a deposition process, etc.). However, the embodiment is not limited thereto.

[0149] 12 and 13, the fourth partial etching process E4 may selectively etch portions of the through holes PH that are to be subjected to the fourth partial etching process E4. For example, the fourth partial etching process E4 may etch eight interlayer insulating layers 132 and seven or eight sacrificial insulating layers 130s located thereon in portions corresponding to the eighth to twelfth through holes PH13, PH14, PH15, and PH16.

[0150] Here, the hard mask layer HML or the hard mask HM can be used as a mask in the fourth partial etching process E4, which is the subsequent partial etching process. For example, as shown in FIG. 12, a hard mask layer HML can be formed on the stacked structure 120s, and a patterning mask layer PM can be formed having an opening P that exposes a portion corresponding to the fourth opening (reference symbol P4 in FIG. 13). A patterning process can be performed to remove the portion of the hard mask layer HML exposed by the opening P in the patterning mask layer PM. In this case, the hard mask layer HML patterning process can use an etching material that etches the hard mask layer HML more than the material contained in the first layer 190a and / or the stacked structure 120s, or that etches the hard mask layer HML while not etching the material contained in the first layer 190a and / or the stacked structure 120s. This allows the formation of a hard mask HM having a fourth opening P4, as shown in FIG. 13.

[0151] The hard mask HM may include various materials that have excellent selectivity and are easy to remove. For example, the hard mask HM may include a carbon-based material containing carbon. The hard mask HM may include a spin-on hard mask (SOH), an amorphous carbon layer (ACL), etc. However, the embodiment is not limited thereto, and the material of the hard mask HM may be variously modified.

[0152] A fourth partial etching process E4 may be performed to etch the eight interlayer insulating layers 132 and the seven or eight sacrificial insulating layers 130s located thereon in the portions exposed through the fourth openings P4 of the hard mask HM. The fourth partial etching process E4 may be performed using various etching processes (e.g., dry etching processes). In the fourth partial etching process E4, an etching material may be used that does not etch the hard mask HM or that etches the hard mask HM less than the stack structure 120s. After the etching process is performed, the hard mask HM may be removed. Various processes may be used to remove the hard mask HM.

[0153] The hard mask HM may not be etched or may be etched relatively less depending on the etching material used in the fourth partial etching process E4. For example, the hard mask HM may be etched less than the first to third photoresist masks M1, M2, and M3 depending on the etching material used in the partial etching process. This overcomes the limitation of the etching depth in the fourth partial etching process E4, which is the longest partial etching process. Furthermore, the through holes PH may be formed in the fourth partial etching process E4 so as to stably reach the desired layer, thereby ensuring a process margin.

[0154] Furthermore, in the fourth partial etching process E4 of the longest partial etching process, the hard mask HM may remain to a sufficient thickness. This prevents damage to the stack structure 120s that can occur when the mask remaining during the etching process is thin. For example, in a comparative example in which the mask (e.g., a photoresist mask) remaining during the etching process is thin, ions may be reflected from the side of the mask, causing undesired etching of the stack structure located in the upper portion of the through hole. As a result, if the diameter or width of the upper portion of the through hole is increased, interference with adjacent through holes may occur, significantly degrading electrical characteristics.

[0155] In this embodiment, the lower portion of the first layer 190a located on the sacrificial insulating layer 130s can protect the sacrificial insulating layer 130s during the patterning process of the hard mask layer HML. For example, during the process of removing the hard mask layer HML located in the through hole PH having a relatively large depth, the lower portion of the first layer 190a located in the through hole PH having a relatively small depth can protect the sacrificial insulating layer 130s located thereunder. This can prevent the sacrificial insulating layer 130s from being undesirably damaged or penetrated during the patterning process of the hard mask layer HML. This can allow the through hole PH to be stably formed so that the through hole PH reaches the desired position.

[0156] Furthermore, in the fourth partial etching process E4, the side portions of the first layer 190a located on the side surfaces of the laminated structure 120s can prevent damage to the side surfaces of the laminated structure 120s. For example, during the etching process, ions may be reflected from the side surfaces of the mask, causing etching of the side surfaces of the laminated structure 120s at the upper portions of the through-holes PH, but the side surfaces of the first layer 190a can prevent undesired etching of the side surfaces of the laminated structure 120s.

[0157] In this embodiment, the first layer 190a is formed before the longest portion etching process, thereby increasing the depth of the through-hole PH that can be formed in the longest portion etching process. This reduces the number of processes for forming the through-hole PH with a relatively large depth, thereby reducing manufacturing costs and time. In addition, in this embodiment, the first layer 190a is formed before the longest portion etching process, thereby minimizing damage to the stacked structure 120s that can occur in the longest portion etching process.

[0158] On the other hand, in the comparative example in which a photoresist mask is used in the longest portion etching process, the photoresist mask is easily etched, limiting the formation of through holes with a relatively large depth. Therefore, in order to perform an etching process with a larger depth, a relatively small etching process is repeated multiple times to form through holes of a desired depth. As a result, the number of processes for forming through holes is large, making it difficult to reduce manufacturing costs and time.

[0159] However, the embodiment is not limited to this, and the order in which the first layer 190a is formed, the number of times, etc. may be variously modified. Other examples will be described later with reference to FIGS.

[0160] In the embodiment, the plurality of through holes PH are formed using a plurality of partial etching processes based on a binary system, so that the number of etching processes for forming the plurality of through holes PH can be significantly reduced.

[0161] As shown in Figure 14, the additional etching process EA may selectively etch a portion where the additional etching process EA is to be performed. For example, the additional etching process EA may etch one interlayer insulating layer 132 and one sacrificial insulating layer 130s located thereon in a portion corresponding to the sixteenth through-hole PH16. Here, a photoresist layer may be used as a mask in the additional etching process EA. In this regard, the description of the photoresist layer with reference to Figures 8 to 10 may be applied.

[0162] In the embodiment, the through hole PH for performing the additional etching process EA is illustrated as being provided in the 16th through hole PH16, but a plurality of through holes PH for performing the additional etching process EA may be provided. In the additional etching process EA, a partial etching process based on a binary system may be performed, or a partial etching process performed sequentially may be performed.

[0163] In the above description, an example is given in which the additional etching step EA is performed after the multiple partial etching steps. However, the embodiment is not limited to this, and the additional etching step EA can be performed before the multiple partial etching steps or between two steps included in the multiple partial etching steps. For example, the additional etching step EA can be performed between the preceding partial etching step and the following partial etching step (for example, between the preceding partial etching step and the step of forming the first layer 190a). Various other modifications are possible.

[0164] 15, a second layer 190b may be formed inside the through-hole PH (e.g., on the inner surface of the through-hole PH and the first layer 190a located thereon) to form a sidewall insulating layer 190i. After the sidewall insulating layer 190i is formed, a through-hole sacrificial layer 190s may be formed on the first layer 190a and / or the second layer 190b on the inner surface of the through-hole PH. The through-hole sacrificial layer 190s may include at least one of polycrystalline silicon, tungsten, titanium nitride, and carbon. However, embodiments are not limited thereto, and the through-hole sacrificial layer 190s may include various materials.

[0165] Subsequently, as shown in FIG. 16, a channel structure CH, a gate electrode 130, and an isolation structure 146 may be formed.

[0166] More specifically, the through-hole may be formed by removing the channel sacrificial layer (reference numeral 122s in FIG. 7). The process of forming the through-hole may be performed using various etching processes (e.g., dry etching processes). In one embodiment, a gate dielectric layer (reference numeral 150 in FIG. 2, hereinafter the same), a channel layer (reference numeral 140 in FIG. 2, hereinafter the same), and a core insulating layer (reference numeral 142 in FIG. 2, hereinafter the same) may be sequentially formed in the through-hole, and then a channel pad (reference numeral 144 in FIG. 2, hereinafter the same) may be formed. The process of forming the gate dielectric layer 150, the channel layer 140, the core insulating layer 142, or the channel pad 144 may be performed using various processes (e.g., deposition processes, etc.).

[0167] An opening for the isolation structure may be formed in a region corresponding to the isolation structure 146 so as to penetrate the stacked structure 120s, the sacrificial insulating layer (reference numeral 130s in FIG. 15, the same applies hereinafter) may be replaced with the gate electrode 130, and an insulating material or the like may be filled in the opening for the isolation structure to form the isolation structure 146.

[0168] In one embodiment, the openings for the isolation structures may be formed by an etching process (e.g., a dry etching process). The sacrificial insulating layer 130s may be selectively removed by an etching process (e.g., a wet etching process) through the openings for the isolation structures. The gate electrode 130 may be formed by filling a conductive material in the area where the sacrificial insulating layer 130s has been removed. As a result, the area where the sacrificial insulating layer 130s was located may be replaced with the gate electrode 130. In this case, a process of forming a part (e.g., a first blocking layer (e.g., reference numeral 156a in FIG. 2) of the blocking layer (reference numeral 156 in FIG. 2)) may be further performed before the process of filling the conductive material constituting the gate electrode 130. However, the embodiment is not limited thereto. The process of filling the openings for the isolation structures may be performed by various processes (e.g., a deposition process).

[0169] According to an embodiment, an isolation structure opening may be formed to expose the horizontal insulating layer 116. An etching process through the isolation structure opening may remove at least a portion of the horizontal insulating layer 116 and a portion of the gate dielectric layer 150, and fill in the material that constitutes the first horizontal conductive layer 112 to form the first horizontal conductive layer 112.

[0170] According to an embodiment, an upper isolation region 148 may be formed in a portion of the gate stack structure 120. The upper isolation region 148 may be formed by forming an opening for the isolation pattern through an etching process using a mask layer and filling at least a portion of the opening for the isolation pattern with an insulating material. The process for forming the opening for the isolation pattern may be performed using various etching processes (e.g., a dry etching process). The process for forming the insulating material in the opening for the isolation pattern may be performed using various processes (e.g., a deposition process). The process for forming the opening for the isolation pattern and the process for forming the insulating material in the opening for the isolation pattern may be performed in various process orders.

[0171] In the embodiment, the isolation structure opening is formed after the through-hole PH, the sidewall insulating layer 190i, and the through-hole sacrificial layer 190s are formed. However, the embodiment is not limited thereto. The isolation structure opening may be formed before the through-hole PH is formed, and a sacrificial layer may be formed in the isolation structure opening. In this case, after the sacrificial layer located in the isolation structure opening is removed, a replacement process for the gate electrode 130, a replacement process for the first horizontal conductive layer 112, etc. may be performed.

[0172] 17, the through-hole sacrificial layer (reference numeral 190s in FIG. 16) is removed, and the lower portion of the second layer 190b (i.e., the portion located on the upper surface of the gate electrode 130) is removed. Then, the through-hole PH is filled with a conductive material to form the conductive portion 190c. This allows the gate contact portion 190 to be formed.

[0173] Next, as shown in FIG. 18, a second wiring portion 180 such as a bit line 182 connected to the channel structure CH may be formed.

[0174] According to this embodiment, the plurality of through holes PH are formed using a partial etching process based on a binary system, thereby reducing the number of processes for forming the plurality of through holes PH. In the preceding partial etching process performed before forming the first layer 190a, a photoresist layer is used as a mask to prevent damage to the stacked structure 120s. In the subsequent partial etching process performed after forming the first layer 190a, even if a hard mask HM is used as a mask, the first layer 190a prevents damage to the stacked structure 120s. As a result, the subsequent partial etching process can be performed using the hard mask HM, and the depth of the through holes PH can be increased, thereby reducing the number of etching processes for forming the through holes PH and reducing manufacturing costs and time.

[0175] In the figure, through-holes PH (e.g., thirteenth to sixteenth through-holes PH13, PH14, PH15, PH16) formed by a plurality of partial etching processes (e.g., first to fourth partial etching processes E1, E2, E3, E4) and / or an additional etching process EA are illustrated as being formed to penetrate a plurality of gate stack portions 121, 122. However, the embodiment is not limited thereto. The through-holes PH may be formed corresponding to the respective gate stack portions 121, 122, and the through-hole PH may include a plurality of portions corresponding to the plurality of gate stack portions 121, 122, respectively.

[0176] In the above description, the semiconductor device 10 is configured as a NAND flash memory device, and has a gate stack structure 120 and a channel structure CH as memory cell structures, and includes a gate contact portion 190 connected to a gate electrode 130.

[0177] However, embodiments are not limited thereto. Therefore, a semiconductor device may include an electrode stack structure formed by repeatedly stacking two layers containing different materials. In this case, the semiconductor device may include an electrode stack structure including a plurality of interlayer insulating layers and a plurality of electrodes that are alternately stacked. For example, the electrode stack structure may be formed by alternately stacking a plurality of semiconductor material layers (e.g., silicon layers) and a plurality of interlayer insulating layers (e.g., oxide layers). A plurality of electrode contact portions may be electrically connected to the plurality of electrodes, respectively. In this case, the plurality of electrode contact portions may have a shape or structure corresponding to the gate contact portion 190 described above. The above description of the electrical connection structure between the gate contact portion 190 and the gate electrode 130 may be applied to the electrode contact portion and the electrical connection structure of the electrodes, and the description of the gate contact portion 190 may be applied to the electrode contact portion. For example, a semiconductor device including an electrode contact portion having the shape or structure of the gate contact portion 190 described above may be a DRAM.

[0178] Although the above description illustrates an electrode stack structure including a plurality of electrodes and a plurality of interlayer insulating layers, the embodiments may also be applied to a stack structure in which two semiconductor material layers (e.g., a silicon layer and a silicon-germanium layer) including different materials are alternately stacked.

[0179] Hereinafter, semiconductor devices and manufacturing methods thereof according to the above-described and other embodiments will be described in more detail with reference to Figures 19 to 22. Detailed descriptions of parts that are the same as or very similar to parts already described will be omitted, and only other parts will be described in detail.

[0180] FIG. 19 is a cross-sectional view showing a gate contact portion included in a semiconductor device according to an embodiment. FIG. 19 shows a portion corresponding to FIG. 4. For clarity, an example is shown in which there are 16 gate electrodes 130 or sacrificial insulating layers, and through-holes PH are formed by performing first to fourth partial etching processes E1, E2, E3, and E4 and one additional etching process. However, the embodiment is not limited thereto, and the number of gate electrodes 130 or sacrificial insulating layers may be varied, and the number of partial etching processes and / or the number of additional etching processes may be varied depending on the number of gate electrodes 130 or sacrificial insulating layers.

[0181] 19, in some embodiments, the subsequent partial etching step performed after forming the first layer 190a may include multiple partial etching steps, i.e., the first layer 190a may not be performed immediately before the longest partial etching step.

[0182] This will be described using the fifteenth gate contact portion 1915 as an example. The fifteenth gate contact portion 1915 may be formed by performing first and second partial etching processes E1 and E2 of the preceding partial etching process to form a first layer 190a in the portion formed by the first and second partial etching processes E1 and E2, and then performing third and fourth partial etching processes E3 and E4 of the following partial etching process to form a second layer 190b and a conductive portion 190c. As a result, a first portion R1 in which both the first layer 190a and the second layer 190b are located may be located in the portion formed by the first and second partial etching processes E1 and E2, and a second portion R2 in which only the second layer 190b is located without the first layer 190a may be located in the portion formed by the third and fourth partial etching processes E3 and E4.

[0183] In this way, the order of the steps for forming the first layer 190a, the number of subsequent partial etching steps, etc. may be changed in various ways.

[0184] FIG. 20 is a cross-sectional view showing a gate contact portion included in a semiconductor device according to another embodiment. FIG. 20 shows a portion corresponding to FIG. 4. For clarity, an example is shown in which there are 16 gate electrodes 130 or sacrificial insulating layers, and through-holes PH are formed by performing first to fourth partial etching processes E1, E2, E3, and E4 and one additional etching process. However, the embodiment is not limited thereto, and the number of gate electrodes 130 or sacrificial insulating layers may be varied, and the number of partial etching processes and / or the number of additional etching processes may be varied depending on the number of gate electrodes 130 or sacrificial insulating layers.

[0185] 20, in an embodiment, the process of forming the first layer 190a can be performed in multiple steps. Hereinafter, to distinguish between them, the first layer 190a formed first may be referred to as a first cover layer 190e, and the first layer 190a formed later may be referred to as a second cover layer 190f.

[0186] This description will be given by taking as an example a case where the first cover layer 190e is formed between the second partial etching step E2 and the third partial etching step E3, and the second cover layer 190f is formed between the third partial etching step E3 and the fourth partial etching step E4. In this case, when viewed from the perspective of the first cover layer 190e, the first and second partial etching steps E2 may correspond to the preceding partial etching step, and the third partial etching step E3 may correspond to the following partial etching step. When viewed from the perspective of the second cover layer 190f, the third partial etching step E3 may correspond to the preceding partial etching step, and the fourth partial etching step E4 may correspond to the following partial etching step.

[0187] This will be described using the fifteenth gate contact portion 1915 of the first contact portion 192 as an example. First, the first and second partial etching processes E1 and E2 of the preceding partial etching process are performed on the first cover layer 190e. The first cover layer 190e is then formed in the portion formed by the first and second partial etching processes E1 and E2, and the third partial etching process E3 of the subsequent partial etching process is then performed. Then, the second cover layer 190f is formed in the second insulating portion IR2 formed by the first to third partial etching processes E1, E2, and E3, and the fourth partial etching process E4 of the subsequent partial etching process is then performed. Then, the second layer 190b and the first conductive portion 192c are formed. This allows the fifteenth gate contact portion 1915 to be formed.

[0188] The first sidewall insulating layer 192i of the first contact portion 192 may include a first portion R1 including a first insulating portion IR1 and a second insulating portion IR2, and a second portion R2 having a thickness smaller than that of the first portion R1. The first insulating portion IR1 may be a portion where the first cover layer 190e, the second cover layer 190f, and the second layer 190b are located, and the second insulating portion IR2 may be a portion where the second cover layer 190f and the second layer 190b are located without the first cover layer 190e. The second portion R2 may be a portion where the second layer 190b is located without the first layer 190a (i.e., the first cover layer 190e and the second cover layer 190f).

[0189] The thickness of the second insulating portion IR2 may be smaller than the thickness of the first insulating portion IR1, and the thickness of the second portion R2 may be smaller than the thickness of the second insulating portion IR2. Here, the thickness of the first insulating portion IR1 may mean the average thickness of the first insulating portion IR1 or the thickness of the portion adjacent to the second insulating portion IR2, the thickness of the second insulating portion IR2 may mean the average thickness of the second insulating portion IR2 or the thickness of the portion adjacent to the first insulating portion IR1 or the second portion R2, and the thickness of the second portion R2 may mean the average thickness of the second portion R2 or the thickness of the portion adjacent to the second insulating portion IR2.

[0190] When viewed in the vertical direction (the Z-axis direction in the figure), the first insulating portion IR1 may be located on the top of the first contact portion 192 and spaced apart from the bottom surface of the first contact portion 192. For example, the top surface of the first insulating portion IR1 may be located adjacent to the top surface of the first contact portion 192 (e.g., located on the same plane as the top surface of the first contact portion 192). The bottom surface of the first insulating portion IR1 may be located apart from the bottom surface of the first contact portion 192 across the second insulating portion IR2 and the second portion R2. The bottom surface of the first insulating portion IR1 may be located apart from the bottom surface of the first contact portion 192 across portions corresponding to the plurality of through gate electrodes 130p.

[0191] When viewed in the vertical direction (the Z-axis direction in the figure), the second insulating portion IR2 may be located between the first insulating portion IR1 and the second portion R2. Thus, the second insulating portion IR2 may be spaced apart from an upper surface of the first contact portion 192 across the first insulating portion IR1 and a lower surface of the first contact portion 192 across the second portion R2. The lower surface of the second insulating portion IR2 may be spaced apart from the lower surface of the first contact portion 192 across a portion corresponding to at least one through gate electrode 130p.

[0192] When viewed in the vertical direction (Z-axis direction in the drawing), the second portion R2 may be located below the second insulating portion IR2.

[0193] In an embodiment, the first sidewall insulating layer 192i may include a first cover layer 190e partially located in the first insulating portion IR1, a second cover layer 190f partially located in the first insulating portion IR1 and the second insulating portion IR2 and located on the inner surface of the first cover layer 190e, and a second layer 190b located in both the first insulating portion IR1, the second insulating portion IR2 and the second portion R2 and located on the inner surface of the second cover layer 190f.

[0194] More specifically, the first cover layer 190e may be located on (e.g., in contact with) the side surface of the gate stack 120 at the first insulating portion IR1. The second cover layer 190f may be located on (e.g., in contact with) the inner surface of the first cover layer 190e at the first insulating portion IR1 and on (e.g., in contact with) the inner surface of the gate stack 120 at the second insulating portion IR2. The second layer 190b may be located on (e.g., in contact with) the inner surface of the second cover layer 190f at the first insulating portion IR1 and the second insulating portion IR2 and on (e.g., in contact with) the side surface of the gate stack 120 at the second portion R2. Note that the embodiment is not limited thereto. In another embodiment, another layer may be located between two adjacent portions of the gate stack 120, the first cover layer 190e, the second cover layer 190f, and the second layer 190b.

[0195] The inner surface of the first sidewall insulating layer 192i (e.g., the second layer 190b) may contact the outer surface of the first conductive portion 192c. However, the embodiment is not limited thereto, and another layer may be located between the inner surface of the first sidewall insulating layer 192i (e.g., the second layer 190b) and the outer surface of the first conductive portion 192c.

[0196] Thus, the first insulating portion IR1 may have the first cover layer 190e, the second cover layer 190f, and the second layer 190b all positioned therein, the second insulating portion IR2 may have the second cover layer 190f and the second layer 190b positioned therein, and the second portion R2 may have only the second layer 190b positioned therein without the first cover layer 190e and the second cover layer 190f. That is, the first portion R1 and the second portion R2 may have different stacked structures depending on whether or not the first cover layer 190e and / or the second cover layer 190f are present, and the first insulating portion IR1 and the second insulating portion IR2 may have different stacked structures depending on whether or not the first cover layer 190e is present.

[0197] The inner surface of the first sidewall insulating layer 192i (e.g., the second layer 190b) may include an inclined surface inclined with respect to the vertical direction of the semiconductor device (the Z-axis direction in the figure) without a step or bend. The outer surface of the first sidewall insulating layer 192i (e.g., the first cover layer 190e, the second cover layer 190f, and the second layer 190b) may include an inclined surface inclined with respect to the vertical direction, with a first step between the first insulating portion IR1 and the second insulating portion IR2 and a second step between the second insulating portion IR2 and the second portion R2. Note that the embodiment is not limited thereto, and at least a portion of the inner surface and / or the outer surface of the first sidewall insulating layer 192i may include a vertical surface parallel to the vertical direction of the semiconductor device.

[0198] Regarding the first step or the second step, the description of step S in the embodiment described with reference to Figures 1 to 6 may be applied, regarding the thickness of first cover layer 190e or second cover layer 190f, the description of first layer 190a in the embodiment described with reference to Figures 1 to 6 may be applied, and regarding the thickness of second layer 190b, the description of second layer 190b in the embodiment described with reference to Figures 1 to 6 may be applied.

[0199] For example, the height of the first or second step, the thickness of the first cover layer 190e, or the thickness of the second cover layer 190f in a direction perpendicular to the side surface of the first sidewall insulating layer 192i may be 0.5 nm or more (e.g., 1 nm or more) or 20 nm or less (e.g., 10 nm or less, as an example, 5 nm or less). However, embodiments are not limited thereto, and the height of the first or second step, the thickness of the first cover layer 190e, or the thickness of the second cover layer 190f may be less than 0.5 nm (e.g., less than 1 nm) or may exceed 20 nm (e.g., 10 nm, as an example, 5 nm).

[0200] For example, the height of the first or second step, the thickness of the first cover layer 190e, or the thickness of the second cover layer 190f in the direction perpendicular to the side surface of the first sidewall insulating layer 192i may be equal to or smaller than the thickness of the second layer 190b. However, the embodiment is not limited thereto. In another embodiment, the height of the first or second step, the thickness of the first cover layer 190e, or the thickness of the second cover layer 190f may be greater than the thickness of the second layer 190b.

[0201] In one embodiment, the height of the first or second step in a direction perpendicular to the side surface of the first sidewall insulating layer 192i, the thickness of the first cover layer 190e, or the thickness of the second cover layer 190f may be smaller than the thickness of the interlayer insulating layer 132 or the thickness of the gate electrode 130 in the vertical direction (the Z-axis direction in the figure). However, the embodiment is not limited thereto. In other embodiments, the height of the first or second step, the thickness of the first cover layer 190e, or the thickness of the second cover layer 190f may be the same as or greater than the thickness of the interlayer insulating layer 132 or the thickness of the gate electrode 130.

[0202] For example, the thickness of the second cover layer 190f may be the same as or greater than the thickness of the first cover layer 190e. This is because etching is performed to a greater depth in the fourth partial etching process E4 performed after the second cover layer 190f is formed than in the third partial etching process E3 performed after the first cover layer 190e is formed. However, the embodiment is not limited thereto, and the thickness of the second cover layer 190f may be less than the thickness of the first cover layer 190e.

[0203] When the first cover layer 190e and the second cover layer 190f contain different materials, the boundary between the first cover layer 190e and the second cover layer 190f can be identified. Even when the first cover layer 190e and the second cover layer 190f contain the same material, the boundary between the first cover layer 190e and the second cover layer 190f can be identified due to the manufacturing process. For example, the first cover layer 190e and the second cover layer 190f may be formed using different processes and have different compositions or properties, or the properties of the inner surface of the first cover layer 190e may change due to the passage of time between the process of forming the first cover layer 190e and the process of forming the second cover layer 190f, making it possible to identify the boundary between the first cover layer 190e and the second cover layer 190f. Even if the first cover layer 190e and the second cover layer 190f contain the same material and it is difficult to identify the boundary between the first cover layer 190e and the second cover layer 190f, the positions of the first cover layer 190e and the second cover layer 190f can be determined or predicted based on the thickness difference or the first step.

[0204] As described above, when multiple first layers 190a are provided, the stacked structure can be protected through multiple partial etching processes. In the above description, the first cover layer 190e and the second cover layer 190f are formed before the third partial etching process E3 and the fourth partial etching process E4, respectively, which are performed consecutively. However, this is not intended to be limiting. The order of the processes for forming the multiple first layers 190a and the number of subsequent partial etching processes performed after each first layer 190a may be variously modified.

[0205] In the embodiment, the second sidewall insulating layer included in the second contact portion may entirely include the first portion R1 of the first sidewall insulating layer 192i, i.e., the portion corresponding to the first insulating portion IR1 and the second insulating portion IR2, but may not include the portion corresponding to the second portion R2. In this case, the outer surface of the second sidewall insulating layer may include a portion corresponding to the first step between the portion corresponding to the first insulating portion IR1 and the portion corresponding to the second insulating portion IR2.

[0206] FIG. 21 is a cross-sectional view showing a gate contact portion included in a semiconductor device according to another embodiment. FIG. 21 illustrates a portion corresponding to FIG. 4. Referring to FIG. 21, in the semiconductor device according to the embodiment, a recess R having a smaller thickness than other portions may be partially located on an inner surface of a first layer 190a included in a gate contact portion 190. For example, the recess R may be located in an upper portion of the gate stack structure. If ions are reflected from the side of a mask during a subsequent partial etching process, the first layer 190a may be partially etched to form the recess R. This effectively prevents damage to the stack structure due to partial etching of the first layer 190a when ions are reflected from the side of the mask and unwanted portions are etched.

[0207] 21 illustrates that the recessed portion R of the first layer 190a is formed corresponding to a part of the uppermost interlayer insulating layer 132 (i.e., the first interlayer insulating layer), but the embodiment is not limited thereto. The recessed portion R of the first layer 190a may be formed corresponding to at least a part of the interlayer insulating layer 132 or the gate electrode 130.

[0208] FIG. 22 is a partial cross-sectional view schematically illustrating a semiconductor device according to a further embodiment.

[0209] 22, the semiconductor device according to the embodiment may have a chip-to-chip (C2C) structure bonded by a wafer bonding method. That is, a lower chip including a circuit region 200a having peripheral circuit structures is fabricated on a first substrate 210, and an upper chip including a cell region 100a having memory cell structures is fabricated on a spare substrate, and then these are bonded to manufacture the semiconductor device.

[0210] The circuit region 200a may include a first substrate 210, a circuit element 220, a first wiring portion 280, and a first junction structure 200b electrically connected to the first wiring portion 280 and located on a surface facing the cell region 100a. The area other than the first junction structure 200b on the surface facing the cell region 100a may be covered with a first junction insulating layer 200i.

[0211] The cell region 100a may include a second substrate 110a, a gate stack structure 120, a channel structure CH, a second wiring portion 180, and a second junction structure 100b electrically connected to the second wiring portion 180 and positioned on a surface facing the circuit region 200a. The region other than the second junction structure 100b may be covered with a second junction insulating layer 100i.

[0212] In the embodiment, the second substrate 110a may be a semiconductor layer containing a semiconductor material. For example, the second substrate 110a may be a semiconductor layer containing single-crystal or polycrystalline silicon, germanium, silicon-germanium, etc. Alternatively, the second substrate 110a may further include an insulating layer. For example, after bonding the cell region 100a to the circuit region 200a, the preliminary substrate provided on the cell region 100a may be removed, and the semiconductor layer and / or insulating layer may be formed.

[0213] In one embodiment, the gate stack 120 is sequentially stacked on the lower side of the second substrate 110a in the figure, and may have a structure that is a vertical inversion of the gate stack 120 shown in FIG. 1. The channel structure CH penetrating the gate stack 120 may also have a vertical inversion of the channel structure CH shown in FIG. 2. As a result, the channel structure CH may have a sloped side surface that narrows from the circuit region 200a toward the second substrate 110a when viewed in cross section. The channel pad 144 and the second wiring part 180 located on the gate stack 120 may be located adjacent to the circuit region 200a.

[0214] For example, the first and / or second junction structures 200b and / or 100b may be made of aluminum, copper, tungsten, or an alloy containing these. As an example, the first and second junction structures 200b and 100b may include copper, and the cell region 100a and the circuit region 200a may be joined (for example, joined by direct contact) by copper-to-copper bonding.

[0215] In the embodiment, the channel structure CH may include a protruding portion CHP protruding from a surface of the gate stack 120 opposite the second wiring portion 180. The protruding portion CHP may not include a gate dielectric layer 150, and the channel layer 140 located at the protruding portion CHP may be exposed to the outside of the gate stack 120. The second substrate 110a may be electrically connected to the channel layer 140 located at the protruding portion CHP. However, the embodiment is not limited thereto, and horizontal conductive layers 112 and 114 may be included as shown in FIG. 1. Various other modifications are possible.

[0216] According to an example, the semiconductor device 20 may include an I / O pad and an I / O connection wiring electrically connected thereto. The I / O connection wiring may be electrically connected to a portion of the second junction structure 100b. The I / O pad may be located on, for example, an insulating film covering an outer surface of the second substrate 110a. According to an embodiment, a separate I / O pad electrically connected to the circuit region 200a may be provided.

[0217] As an example, the circuit region 200a and the cell region 100a may be parts corresponding to the first structure 1100F and the second structure 1100S, respectively, of the semiconductor device 1100 included in the electronic system 1000 shown in Fig. 23. Alternatively, the circuit region 200a and the cell region 100a may be regions including the first structure 4100 and the second structure 4200, respectively, of the semiconductor chip 2200a shown in Fig. 26.

[0218] An example of an electronic system including the semiconductor device described above will now be described in detail.

[0219] FIG. 23 is a diagram illustrating a schematic view of an electronic system including a semiconductor device according to an example embodiment.

[0220] 23 , an electronic system 1000 according to an exemplary embodiment may include a semiconductor device 1100 and a controller 1200 electrically coupled to the semiconductor device 1100. The electronic system 1000 may be a storage device including one or more semiconductor devices 1100 or an electronic device including a storage device. For example, the electronic system 1000 may be a solid state drive device (SSD device), a Universal Serial Bus (USB), a computing system, a medical device, or a communication device including one or more semiconductor devices 1100.

[0221] The semiconductor device 1100 may be a nonvolatile memory device, such as the NAND flash memory device described with reference to FIGS. 1 to 22. The semiconductor device 1100 may include a first structure 1100F and a second structure 1100S on the first structure 1100F. In an exemplary embodiment, the first structure 1100F may be disposed beside the second structure 1100S. The first structure 1100F may be a peripheral circuit structure including a decoder circuit 1110, a page buffer 1120, and a logic circuit 1130. The second structure 1100S may be a memory cell structure including a bit line BL, a common source line CSL, a word line WL, first and second gate upper lines UL1 and UL2, first and second gate lower lines LL1 and LL2, and a memory cell string CSTR between the bit line BL and the common source line CSL.

[0222] Each memory cell string CSTR in the second structure 1100S may include lower transistors LT1 and LT2 adjacent to a common source line CSL, upper transistors UT1 and UT2 adjacent to a bit line BL, and a plurality of memory cell transistors MCT disposed between the lower transistors LT1 and LT2 and the upper transistors UT1 and UT2. The number of lower transistors LT1 and LT2 and the number of upper transistors UT1 and UT2 may vary depending on the embodiment.

[0223] In an exemplary embodiment, the lower transistors LT1 and LT2 may comprise ground selection transistors, and the upper transistors UT1 and UT2 may comprise string selection transistors. The first and second gate lower lines LL1 and LL2 may be gate electrodes of the lower transistors LT1 and LT2, respectively. The word line WL may be the gate electrode of the memory cell transistor MCT, and the gate upper lines UL1 and UL2 may be gate electrodes of the upper transistors UT1 and UT2, respectively.

[0224] The common source line CSL, the first and second gate lower lines LL1 and LL2, the word line WL, and the first and second gate upper lines UL1 and UL2 may be electrically connected to the decoder circuit 1110 via a first connecting line 1115 extending from the first structure 1100F to the second structure 1100S. The bit line BL may be electrically connected to the page buffer 1120 via a second connecting line 1125 extending from the first structure 1100F to the second structure 1100S.

[0225] The decoder circuit 1110 and the page buffer 1120 in the first structure 1100F may perform a control operation on at least one memory cell transistor selected from the plurality of memory cell transistors MCT. The decoder circuit 1110 and the page buffer 1120 may be controlled by a logic circuit 1130. The semiconductor device 1100 may communicate with the controller 1200 via an input / output pad 1101 electrically connected to the logic circuit 1130. The input / output pad 1101 may be electrically connected to the logic circuit 1130 via an input / output connecting wiring 1135 extending to the second structure 1100S within the first structure 1100F.

[0226] The controller 1200 may include a processor 1210, a NAND controller 1220, and a host interface 1230. According to an embodiment, the electronic system 1000 may include multiple semiconductor devices 1100, in which case the controller 1200 may control the multiple semiconductor devices 1100.

[0227] The processor 1210 can control the overall operation of the electronic system 1000, including the controller 1200. The processor 1210 can operate with predetermined firmware and can control the NAND controller 1220 to access the semiconductor device 1100. The NAND controller 1220 can include a NAND interface 1221 that handles communication with the semiconductor device 1100. Control commands for controlling the semiconductor device 1100, data to be written to the memory cell transistors MCT of the semiconductor device 1100, data to be read from the memory cell transistors MCT of the semiconductor device 1100, etc. can be transferred via the NAND interface 1221. The host interface 1230 can provide a communication function between the electronic system 1000 and an external host. When a control command is received from the external host via the host interface 1230, the processor 1210 can control the semiconductor device 1100 in response to the control command.

[0228] FIG. 24 is a perspective view schematically illustrating an electronic system including a semiconductor device according to an exemplary embodiment.

[0229] 24, an electronic system 2000 according to an exemplary embodiment may include a main board 2001, a controller 2002 mounted on the main board 2001, one or more semiconductor packages 2003, and a DRAM 2004. The semiconductor packages 2003 and the DRAM 2004 may be connected to the controller 2002 by a wiring pattern 2005 formed on the main board 2001.

[0230] The main board 2001 may include a connector 2006 including a plurality of pins coupled to an external host. The number and arrangement of the pins in the connector 2006 may vary depending on the communication interface between the electronic system 2000 and the external host. In an exemplary embodiment, the electronic system 2000 may communicate with the external host via any one of interfaces such as a Universal Serial Bus (USB), a Peripheral Component Interconnect Express (PCI-Express), a Serial Advanced Technology Attachment (SATA), or an M-Phy for Universal Flash Storage (UFS). In an exemplary embodiment, the electronic system 2000 may operate using power supplied from the external host via the connector 2006. The electronic system 2000 may further include a Power Management Integrated Circuit (PMIC) that distributes power supplied from the external host to the controller 2002 and the semiconductor package 2003.

[0231] The controller 2002 can record data to and read data from the semiconductor package 2003, thereby improving the operating speed of the electronic system 2000.

[0232] The DRAM 2004 may be a buffer memory for alleviating the speed difference between the semiconductor package 2003 and an external host in terms of data storage space. The DRAM 2004 included in the electronic system 2000 may also operate as a type of cache memory and provide space for temporarily storing data in control operations for the semiconductor package 2003. When the electronic system 2000 includes the DRAM 2004, the controller 2002 may further include a DRAM controller for controlling the DRAM 2004 in addition to a NAND controller for controlling the semiconductor package 2003.

[0233] The semiconductor package 2003 may include first and second semiconductor packages 2003a and 2003b spaced apart from each other. Each of the first and second semiconductor packages 2003a and 2003b may include a semiconductor package including a plurality of semiconductor chips 2200. Each of the first and second semiconductor packages 2003a and 2003b may include a package substrate 2100, a semiconductor chip 2200 on the package substrate 2100, an adhesive layer 2300 disposed on a lower surface of each of the semiconductor chips 2200, a connecting structure 2400 electrically connecting the semiconductor chip 2200 and the package substrate 2100, and a molding layer 2500 covering the semiconductor chip 2200 and the connecting structure 2400 on the package substrate 2100.

[0234] The package substrate 2100 may be a printed circuit board including package top pads 2130. Each semiconductor chip 2200 may include input / output pads 2210. The input / output pads 2210 may correspond to the input / output pads 1101 in FIG. 23. Each of the semiconductor chips 2200 may include a gate stack structure 3210 and a channel structure 3220. The semiconductor chips 2200 may include the semiconductor devices described with reference to each of FIGS. 1 through 22.

[0235] In an exemplary embodiment, the connecting structure 2400 may be a bonding wire that electrically connects the I / O pads 2210 and the package upper pads 2130. Therefore, the semiconductor chips 2200 in each of the first and second semiconductor packages 2003a and 2003b may be electrically connected to each other by a bonding wire, and may be electrically connected to the package upper pads 2130 of the package substrate 2100. According to an embodiment, the semiconductor chips 2200 in each of the first and second semiconductor packages 2003a and 2003b may be electrically connected by a connecting structure including a through silicon via (TSV), instead of the connecting structure 2400 using a bonding wire.

[0236] In an exemplary embodiment, the controller 2002 and the semiconductor chip 2200 may be included in one package. For example, the controller 2002 and the semiconductor chip 2200 may be mounted on a separate interposer substrate other than the main substrate 2001, and the controller 2002 and the semiconductor chip 2200 may be connected to each other by wiring formed on the interposer substrate.

[0237] 25 and 26 are cross-sectional views schematically illustrating semiconductor packages according to respective exemplary embodiments. Each of Fig. 25 and Fig. 26 illustrates an exemplary embodiment of the semiconductor package 2003 of Fig. 24, and conceptually illustrates a region obtained by cutting the semiconductor package 2003 of Fig. 24 along cutting line II'.

[0238] 25, a package substrate 2100 in a semiconductor package 2003 may be a printed circuit board. The package substrate 2100 may include a package substrate body 2120, package upper pads 2130 disposed on an upper surface of the package substrate body 2120, package lower pads 2125 disposed on or exposed through a lower surface of the package substrate body 2120, and internal wiring 2135 electrically connecting the package upper pads 2130 and the package lower pads 2125 within the package substrate body 2120. The package upper pads 2130 may be electrically connected to a connecting structure 2400. The package lower pads 2125 may be connected to a wiring pattern 2005 of a main board 2001 of an electronic system 2000 via a conductive connecting portion 2800, as shown in FIG. 23.

[0239] The semiconductor chip 2200 may include a semiconductor substrate 3010 and a first structure 3100 and a second structure 3200 sequentially stacked on the semiconductor substrate 3010. The first structure 3100 may include a peripheral circuit region including peripheral wiring 3110. The second structure 3200 may include a common source line 3205, a gate stack structure 3210 on the common source line 3205, a channel structure 3220 and an isolation structure 3230 penetrating the gate stack structure 3210, a bit line 3240 electrically connected to the channel structure 3220, and a gate connecting wiring electrically connected to a word line (WL in FIG. 23) of the gate stack structure 3210.

[0240] In the semiconductor chip 2200 or semiconductor device according to the embodiment, the first layer is formed before the subsequent partial etching process, thereby preventing damage that may occur in the subsequent partial etching process, and through holes having a relatively large depth can be stably formed in the subsequent partial etching process, thereby improving the reliability and productivity of the semiconductor chip 2200 or semiconductor device.

[0241] Each of the semiconductor chips 2200 may include a through wiring 3245 electrically connected to the peripheral wiring 3110 of the first structure 3100 and extending into the second structure 3200. The through wiring 3245 may pass through the gate stack structure 3210 and may be further disposed outside the gate stack structure 3210. Each of the semiconductor chips 2200 may further include an input / output connecting wiring 3265 electrically connected to the peripheral wiring 3110 of the first structure 3100 and extending into the second structure 3200, and an input / output pad 2210 electrically connected to the input / output connecting wiring 3265.

[0242] In an exemplary embodiment, a plurality of semiconductor chips 2200 may be electrically connected to one another by bonding wire-type connecting structures 2400 in the semiconductor package 2003. As another example, a plurality of semiconductor chips 2200 or a plurality of components thereof may be electrically connected to one another by connecting structures including through electrodes.

[0243] Referring to FIG. 26, each of the semiconductor chips 2200a in the semiconductor package 2003A may include a semiconductor substrate 4010, a first structure 4100 on the semiconductor substrate 4010, and a second structure 4200 bonded to the first structure 4100 on the first structure 4100 using a wafer bonding method.

[0244] The first structure 4100 may include a peripheral circuit region including peripheral wiring 4110 and a first junction structure 4150. The second structure 4200 may include a common source line 4205, a gate stack structure 4210 between the common source line 4205 and the first structure 4100, a channel structure 4220 and an isolation structure 4230 penetrating the gate stack structure 4210, and a second junction structure 4250 electrically connected to the channel structure 4220 and a word line (reference symbol WL in FIG. 23 , the same applies hereinafter) of the gate stack structure 4210. For example, the second junction structure 4250 may be electrically connected to the channel structure 4220 and the word line WL via a bit line 4240 electrically connected to the channel structure 4220 and a gate connecting wiring electrically connected to the word line WL, respectively. The first junction structure 4150 of the first structure 4100 and the second junction structure 4250 of the second structure 4200 may be bonded to each other while in contact with each other. The bonded portions of the first junction structure 4150 and the second junction structure 4250 may be made of, for example, copper (Cu).

[0245] In the semiconductor chip 2200a or semiconductor device according to the embodiment, the first layer is formed before the subsequent partial etching process, thereby preventing damage that may occur in the subsequent partial etching process, and through holes having a relatively large depth can be stably formed in the subsequent partial etching process, thereby improving the reliability and productivity of the semiconductor chip 2200a or semiconductor device.

[0246] Each of the semiconductor chips 2200a may further include an I / O pad 2210 and an I / O connecting wire 4265 below the I / O pad 2210. The I / O connecting wire 4265 may be electrically connected to a portion of the second junction structure 4250.

[0247] In one embodiment, a plurality of semiconductor chips 2200a in a semiconductor package 2003A may be electrically connected to one another by bonding wire-type connecting structures 2400. As another example, a plurality of semiconductor chips 2200a or a plurality of components thereof may be electrically connected to one another by connecting structures including through electrodes.

[0248] Although the embodiments have been described in detail above, the scope of the present invention is not limited thereto. Various modifications and improvements made by those skilled in the art using the basic concept of the present invention defined in the claims also fall within the scope of the present invention. [Explanation of symbols]

[0249] 10: Semiconductor device 100: Cell area 130: Gate electrode 190: Gate contact part 190a: 1st layer 190b: 2nd layer 190i: Sidewall insulating layer 190c: Conductive part 200: Circuit area

Claims

1. a memory cell structure located in a cell array region; an electrode stack structure including a plurality of electrodes and a plurality of interlayer insulating layers alternately stacked on each other, the electrode stack structure being located at least in the connection region; a plurality of electrode contact portions each penetrating at least a portion of the electrode stack structure and electrically connected to the plurality of electrodes, The plurality of electrode contact portions are a first contact portion including a first conductive portion and a first sidewall insulating layer located between the electrode stack and the first conductive portion; and A semiconductor device comprising: a second contact portion including a second conductive portion; and a second sidewall insulating layer located between the electrode stack structure and the second conductive portion and having a different shape or structure from the first sidewall insulating layer.

2. a plurality of through holes are provided that individually penetrate the electrode stack structure and are spaced apart from each other across the electrode stack structure; The semiconductor device according to claim 1 , wherein said plurality of electrode contact portions are located inside said plurality of through-holes, respectively.

3. 2. The semiconductor device according to claim 1, wherein said first sidewall insulating layer includes a first portion and a second portion having a thickness smaller than that of said first portion.

4. 4. The semiconductor device according to claim 3, wherein the first contact portion includes a plurality of first contact portions having different depths from each other, the second contact portion includes a plurality of second contact portions having different depths from each other, and the depth of each of the plurality of first contact portions is greater than the depth of each of the plurality of second contact portions.

5. 4. The semiconductor device according to claim 3, wherein in the first contact portion, the number of electrodes among the plurality of electrodes that are positioned corresponding to the second portion is greater than the number of electrodes among the plurality of electrodes that are positioned corresponding to the first portion.

6. an inner surface of the first sidewall insulating layer having an inclined surface or a vertical surface that is inclined or parallel to the vertical direction; 4. The semiconductor device according to claim 3, wherein an outer surface of said first sidewall insulating layer has an inclined surface or a vertical surface inclined or parallel to said vertical direction, and has a step due to a difference in thickness between said first portion and said second portion.

7. The difference in thickness between the first portion and the second portion in a direction perpendicular to the side surface of the first sidewall insulating layer is 0.5 nm or more, or In a direction perpendicular to the side surface of the first sidewall insulating layer, the ratio of the thickness of the second portion to the thickness of the first portion is 0.5 to 1; or In a direction perpendicular to the side surface of the first sidewall insulating layer, the difference between the thickness of the first portion and the thickness of the second portion is smaller than the thickness of the second portion, or 4. The semiconductor device according to claim 3, wherein a difference in thickness between said first portion and said second portion in a direction perpendicular to the side surface of said first sidewall insulating layer is smaller than a thickness of said interlayer insulating layer or a thickness of said electrode.

8. The semiconductor device according to claim 3 , wherein the second sidewall insulating layer entirely includes a portion having the same material, structure, or thickness as the first portion.

9. the first and second sidewall insulating layers each include a first layer located on a side surface of the electrode stack structure and a second layer located on the first layer; 2. The semiconductor device according to claim 1, wherein the first sidewall insulating layer and the second sidewall insulating layer differ from each other in arrangement or relative positions of the first layer and the second layer.

10. the first sidewall insulating layer includes a first portion and a second portion having a thickness smaller than that of the first portion; 2. The semiconductor device according to claim 1, wherein the first portion includes a first insulating portion and a second insulating portion having a thickness smaller than that of the first insulating portion and positioned between the first insulating portion and the second insulating portion.

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