Method and apparatus for signaling of syntax elements in video coding

Abstract

To provide a method and an apparatus for video encoding.SOLUTION: Wherein the video encoding method comprises determining, by a decoder, whether one or more reference picture lists are signaled in a picture header (PH) associated with a picture and whether the one or more reference picture lists indicate that one or more slices associated with the picture are bi-predictive; The one or more reference picture lists are signaled in the PH, and in response to determining that the one or more reference picture lists indicate that the one or more slices are not bi-predictive, the decoder adds one or more constraints to one or more syntax elements of the PH.SELECTED DRAWING: Figure 6

Description

[Technical Field]

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS This application claims priority to U.S. Provisional Application No. 63 / 003,226, entitled "Signaling of Syntax Elements in Video Coding," filed March 31, 2020, which is incorporated by reference in its entirety for all purposes.

[0002] This disclosure relates to video encoding and compression, and more particularly, but not exclusively, to methods and apparatus for signaling syntax elements in video encoding. [Background technology]

[0003] Various video encoding techniques can be used to compress video data. Video encoding is performed according to one or more video encoding standards. For example, currently, several well-known video encoding standards include Versatile Video Coding (VVC), High Efficiency Video Coding (HEVC, also known as H.265 or MPEG-H Part 2), and Advanced Video Coding (AVC, also known as H.264 or MPEG-4 Part 10), which are jointly developed by ISO / IEC MPEG and ITU-T VECG. AOMedia Video 1 (AV1) was developed by the Alliance for Open Media (AOM) as the successor to its predecessor, VP9. Audio-Video Coding (AVS), which refers to digital audio and digital video compression standards, is another video compression standard series developed by the China Audio and Video Coding Standards Workgroup. Most existing video coding standards are built on the well-known hybrid video coding framework, i.e., by using block-based prediction methods (e.g., inter-prediction, intra-prediction) to reduce the redundancy present in a video image or sequence, and transform coding to compact the energy of the prediction error. An important goal of video coding technology is to compress video data into a format that uses a lower bitrate while avoiding or minimizing the degradation of video quality. Summary of the Invention [Problem to be solved by the invention]

[0004] This disclosure provides example techniques for signaling syntax elements in video coding. [Means for solving the problem]

[0005] According to a first aspect of the present disclosure, a method for video encoding is provided. The method includes a decoder determining whether one or more reference picture lists are signaled in a picture header (PH) associated with a picture, and whether the one or more reference picture lists indicate that one or more slices associated with the picture are bi-predictive. Further, the method includes the decoder adding one or more constraints to one or more syntax elements of the PH in response to determining that the one or more reference picture lists are signaled in the PH and that the one or more reference picture lists indicate that the one or more slices are not bi-predictive.

[0006] According to a second aspect of the present disclosure, there is provided a method for video encoding, the method including: a decoder using an enable flag to identify whether one or more temporal motion vector predictors are used for inter prediction of one or more slices associated with a PH of a picture; the method further including the decoder constraining a value of the enable flag according to a plurality of offsets applied to a size of the picture for scaling ratio calculation.

[0007] According to a third aspect of the present disclosure, an apparatus for video encoding is provided. The apparatus includes one or more processors and a memory configured to store instructions executable by the one or more processors. The one or more processors, upon execution of the instructions, are configured to perform the following: determine whether one or more reference picture lists are signaled in a PH associated with a picture, and whether the one or more reference picture lists indicate that one or more slices associated with the picture are bi-predictive. Further, the one or more processors are configured to perform the following in response to determining that the one or more reference picture lists are signaled in the PH and that the one or more reference picture lists indicate that one or more slices are not bi-predictive: add one or more constraints to one or more syntax elements of the PH.

[0008] According to a fourth aspect of the present disclosure, an apparatus for video encoding is provided. The apparatus includes one or more processors and a memory configured to store instructions executable by the one or more processors. The one or more processors, upon execution of the instructions, are configured to perform: using an enable flag to identify whether one or more temporal motion vector predictors are used for inter prediction of one or more slices associated with a PH of a picture. The one or more processors are further configured to perform: constraining a value of the enable flag according to a plurality of offsets applied to a size of the picture for scaling ratio calculation.

[0009] According to a fifth aspect of the present disclosure, there is provided a non-transitory computer-readable storage medium for video encoding, storing computer-executable instructions that, when executed by one or more computer processors, cause the one or more computer processors to perform a method for video encoding according to the first aspect of the present disclosure.

[0010] According to a sixth aspect of the present disclosure, there is provided a non-transitory computer-readable storage medium for video encoding, storing computer-executable instructions that, when executed by one or more computer processors, cause the one or more computer processors to perform a method for video encoding according to the second aspect of the present disclosure.

[0011] A more particular description of examples of the present disclosure will be made with reference to specific examples that are illustrated in the accompanying drawings, in which the examples will be described and explained with additional specificity and detail, considering that these drawings illustrate only some examples and therefore are not to be considered limiting in scope. [Brief explanation of the drawings]

[0012] [Figure 1] FIG. 1 is a block diagram illustrating an example video encoder according to some implementations of this disclosure. [Figure 2] FIG. 2 is a block diagram illustrating an example video decoder according to some implementations of this disclosure. [Figure 3] FIG. 1 illustrates an example of a picture divided into multiple coding tree units (CTUs), according to some implementations of the present disclosure. [Figure 4A] FIG. 10 is a schematic diagram illustrating a multi-type tree splitting mode according to some implementations of the present disclosure. [Figure 4B] FIG. 10 is a schematic diagram illustrating a multi-type tree splitting mode according to some implementations of the present disclosure. [Figure 4C] FIG. 10 is a schematic diagram illustrating a multi-type tree splitting mode according to some implementations of the present disclosure. [Figure 4D] FIG. 10 is a schematic diagram illustrating a multi-type tree splitting mode according to some implementations of the present disclosure. [Figure 5] 1 is a block diagram illustrating an example apparatus for video encoding according to some implementations of this disclosure. [Figure 6] 1 is a flowchart illustrating an example process for video encoding according to some implementations of this disclosure. [Figure 7] 1 is a flowchart illustrating an example process for video encoding according to some implementations of this disclosure. DETAILED DESCRIPTION OF THE INVENTION

[0013] Reference will now be made in detail to particular implementations, examples of which are illustrated in the accompanying drawings. In the following detailed description, numerous non-limiting specific details are set forth to aid in understanding the subject matter presented herein. However, it will be apparent to those skilled in the art that various alternatives may be used. For example, it will be apparent to those skilled in the art that the subject matter presented herein can be implemented in many types of electronic devices having digital video capabilities.

[0014] References throughout this specification to "one embodiment," "an embodiment," "an example," "some embodiments," "some examples," or similar language mean that the particular feature, structure, or characteristic described is included in at least one embodiment or example. A feature, structure, element, or characteristic described in connection with one or more embodiments may also be applicable to other embodiments, unless stated otherwise.

[0015] Throughout this disclosure, all terms such as "first," "second," "third," etc., do not imply any spatial or chronological order unless otherwise specified, but are used solely as nomenclature to refer to related elements, e.g., devices, components, compositions, steps, etc. For example, a "first device" and a "second device" may refer to two separately formed devices or two portions, components, or operating states of the same device, and may be arbitrarily named.

[0016] The terms "module," "sub-module," "circuit," "sub-circuit," "circuitry," "sub-circuitry," "unit," or "sub-unit" may include memory (shared, dedicated, or group) that stores code or instructions that can be executed by one or more processors. A module may include one or more circuits that may or may not contain stored code or instructions. A module or circuit may include one or more components that are directly or indirectly connected. These components may or may not be physically attached or located adjacent to each other.

[0017] As used herein, the terms "if" or "when" may be understood to mean "upon" or "in response to," depending on the context. When these terms appear in claims, they may not indicate that the associated limitation or feature is conditional or optional. For example, a method may include: i) when or if condition X exists, function or action X' is performed; and ii) when or if condition Y exists, function or action Y' is performed. The method may be implemented with both the ability to perform function or action X' and the ability to perform function or action Y'. Thus, functions X' and Y' may both be performed at different times during multiple executions of the method.

[0018] A unit or module may be implemented purely by software, purely by hardware, or by a combination of hardware and software. In a purely software implementation, for example, a unit or module may include functionally related code blocks or software components that are directly or indirectly linked together to perform a particular function.

[0019] 1 shows a block diagram illustrating an exemplary block-based hybrid video encoder 100 that can be used in conjunction with many video coding standards that use block-based processing. In encoder 100, a video frame is partitioned into multiple video blocks for processing. For each given video block, a prediction is formed based on either an inter-prediction or intra-prediction approach. In inter-prediction, motion estimation and motion compensation form one or more predictors based on pixels of previously reconstructed frames. In intra-prediction, a predictor is formed based on reconstructed pixels in a current frame. A mode decision may select the best predictor to predict the current block.

[0020] A prediction residual, which represents the difference between the current video block and its predictor, is sent to a transform circuit 102. The transform coefficients are then sent from the transform circuit 102 to a quantization circuit 104 for entropy reduction. The quantized coefficients are then provided to an entropy coding circuit 106 to generate a compressed video bitstream. As shown in FIG. 1, prediction-related information 110 from an inter-prediction circuit and / or an intra-prediction circuit 112, such as video block partition information, motion vectors, reference picture indexes, and intra-prediction modes, is also provided via the entropy coding circuit 106 and stored in a compressed video bitstream 114.

[0021] Decoder-related circuitry is also required in encoder 100 to reconstruct pixels for prediction purposes. First, a prediction residual is reconstructed via inverse quantization 116 and inverse transform circuitry 118. This reconstructed prediction residual is combined with block predictor 120 to generate unfiltered reconstructed pixels for the current video block.

[0022] Intra prediction (also called "spatial prediction") predicts a current video block using pixels from samples of previously coded neighboring blocks (called reference samples) within the same video picture and / or slice. Spatial prediction reduces spatial redundancy inherent in video signals.

[0023] Inter-prediction (also called "temporal prediction") predicts a current video block using reconstructed pixels from a previously coded video picture. Temporal prediction reduces the temporal redundancy inherent in a video signal. The temporal prediction signal for a given coding unit (CU) or coding block is typically signaled by one or more motion vectors (MVs), which indicate the amount and direction of motion between the current CU and its temporal reference. Furthermore, if multiple reference pictures are supported, one reference picture index is additionally sent, which is used to identify which reference picture in the reference picture store the temporal prediction signal belongs to.

[0024] After spatial prediction and / or temporal prediction are performed, an intra / inter mode decision circuit 121 within encoder 100 selects the best prediction mode, for example, based on a rate-distortion optimization method. Block predictor 120 is then subtracted from the current video block, and the resulting prediction residual is decorrelated using transform circuit 102 and quantization circuit 104. The resulting quantized residual coefficients are inverse quantized by inverse quantization circuit 116 and inverse transformed by inverse transform circuit 118 to form a reconstructed residual, which is then added back to the prediction block to form a reconstructed signal for the CU. Additionally, in-loop filtering 115, such as a deblocking filter, sample adaptive offset (SAO), and / or adaptive in-loop filter (ALF), may be applied to the reconstructed CU, which is then placed in a reference picture store in picture buffer 117 and used to encode future video blocks. To form the output video bitstream 114, the coding mode (inter or intra), prediction mode information, motion information, and quantized residual coefficients are all sent to the entropy coding unit 106 for further compression and packed to form the bitstream.

[0025] For example, a deblocking filter is available in the latest versions of AVC, HEVC, and VVC. HEVC defines an additional in-loop filter called SAO (sample adaptive offset) to further improve coding efficiency. For the latest version of the VVC standard, yet another in-loop filter called ALF (adaptive loop filter) is being actively researched and may well be included in the final standard.

[0026] These in-loop filter operations are optional. Performing these operations helps improve coding efficiency and visual quality. They can also be turned off as a decision made by encoder 100 to save computational complexity.

[0027] Note that intra prediction is typically based on unfiltered reconstructed pixels, while inter prediction is based on filtered reconstructed pixels if these filter options are turned on by the encoder 100.

[0028] Figure 2 is a block diagram illustrating an exemplary block-based video decoder 200 that can be used in conjunction with many video coding standards. This decoder 200 is similar to the reconstruction-related portions present in the encoder 100 of Figure 1. In the decoder 200, an incoming video bitstream 201 is first decoded by entropy decoding 202 to derive quantized coefficient levels and prediction-related information. The quantized coefficient levels are then processed by inverse quantization 204 and inverse transform 206 to obtain a reconstructed prediction residual. A block prediction mechanism implemented in an intra / inter mode selector 212 is configured to perform either intra prediction 208 or motion compensation 210 based on the decoded prediction information. A summer 214 is used to sum the reconstructed prediction residual from the inverse transform 206 with the prediction output generated by the block prediction mechanism to obtain a set of unfiltered reconstructed pixels.

[0029] The reconstructed blocks may further pass through an in-loop filter 209 before being stored in a picture buffer 213, which acts as a reference picture store. The reconstructed video in the picture buffer 213 may be sent to drive a display device and may also be used to predict future video blocks. In situations where the in-loop filter 209 is turned on, a filtering operation is performed on these reconstructed pixels to derive the final reconstructed video output 222.

[0030] The aforementioned video encoding / decoding standards, e.g., VVC, JEM, HEVC, and MPEG-4, Part 10, are conceptually similar. For example, they all use block-based processing. The block partitioning schemes in some standards are described in detail below.

[0031] High Efficiency Video Coding (HEVC) HEVC is based on a hybrid block-based motion compensation transform coding architecture. The basic unit of compression is called a CTU. The maximum CTU size is defined as two blocks of up to 64x64 luma pixels and 32x32 chroma pixels for a 4:2:0 chroma format. Each CTU contains one CU or can be recursively divided into four smaller CUs until a predefined minimum CU size is reached. Each CU (also named leaf CU) contains one or more prediction units (PUs) and a tree of transform units (TUs).

[0032] In general, except for monochrome content, a CTU may contain one luma coding tree block (CTB) and two corresponding chroma CTBs, a CU may contain one luma coding block (CB) and two corresponding chroma CBs, a PU may contain one luma prediction block (PB) and two corresponding chroma PBs, and a TU may contain one luma transform block (TB) and two corresponding chroma TBs. However, exceptions may occur because the minimum TB size is 4x4 for both luma and chroma (i.e., 2x2 chroma TBs are not supported for 4:2:0 color format), and each intra-chroma CB always has only one intra-chroma PB, regardless of the number of intra-luma PBs in the corresponding intra-luma CB.

[0033] For intra CUs, a luma CB can be predicted by one or four luma PBs, and each of two chroma CBs is always predicted by one chroma PB, where each luma PB has one intra luma prediction mode and two chroma PBs share one intra chroma prediction mode. Furthermore, for intra CUs, the TB size cannot be larger than the PB size. In each PB, intra prediction is applied to predict the samples of each TB within the PB from the reconstructed samples of the TB's neighborhood. In addition to 33 directional intra prediction modes, each PB also supports DC mode and planar mode, which predict flat regions and gradually changing regions, respectively.

[0034] For each inter PU, one of three prediction modes can be selected: inter, skip, and merge. Generally speaking, a motion vector competition (MVC) scheme is introduced to select a motion candidate from a given candidate set, including spatial and temporal motion candidates. Multiple references for motion estimation allow finding the best reference in two possible reconstructed reference picture lists (i.e., List 0 and List 1). In inter mode (referred to as AMVP mode, where AMVP stands for advanced motion vector prediction), an inter prediction indicator (List 0, List 1, or bidirectional prediction), a reference index, a motion candidate index, a motion vector difference (MVD), and a prediction residual are transmitted. For skip and merge modes, only a merge index is transmitted, and the current PU inherits the inter prediction indicator, reference index, and motion vector from the neighboring PU referenced by the coded merge index. For skip-coded CUs, the residual signal is also omitted.

[0035] Versatile Video Coding (VVC) At the 10th JVET Conference, held in San Diego, USA, from April 10 to 20, 2018, JVET defined the first draft of Versatile Video Coding (VVC) and its reference software implementation, VVC Test Model 1 (VTM1). The first new coding feature of VVC was decided to include a quadtree with nested multitype trees. A multitype tree is a coding block partitioning structure that includes both bipartitions and tripartites. Since then, the reference software VTM, which implements both encoding and decoding processes, has been developed and updated through subsequent JVET conferences.

[0036] In VVC, the input video picture is partitioned into blocks called CTUs. CTUs are then divided into CUs using a quadtree with a nested multi-type tree structure, and CUs define regions of pixels that share the same prediction mode (e.g., intra or inter). The term "unit" may define a region of an image that covers all components, such as luma and chroma. The term "block" may be used to define a region that covers a specific component (e.g., luma), and when considering a chroma sampling format such as 4:2:0, blocks of different components (e.g., luma vs. chroma) may have different spatial locations.

[0037] Division of the picture into CTUs FIG. 3 illustrates an example of a picture 300 divided into multiple CTUs 302, according to some implementations of this disclosure.

[0038] In VCC, a picture is divided into a sequence of CTUs. The concept of a CTU is the same as in HEVC. For a picture with a 3-sample array, a CTU consists of an NxN block of luma samples and two corresponding blocks of chroma samples.

[0039] The maximum allowed size of a luma block within a CTU is specified as 128x128 (however, the maximum size of a luma transform block is 64x64).

[0040] Segmentation of CTUs using a tree structure In HEVC, to adapt to various local characteristics, CTUs are divided into CUs using a quaternary-tree structure called a coding tree. The decision of whether to encode a picture area using inter-picture (temporal) or intra-picture (spatial) prediction is made at the leaf CU level. Each leaf CU can be further divided into one, two, or four PUs depending on the PU partition type. The same prediction process is applied within a PU, and related information is sent to the decoder for each PU. After obtaining a residual block by applying the prediction process based on the PU partition type, the leaf CU can be partitioned into transform units (TUs) according to another quaternary-tree structure similar to the coding tree of that CU. One of the important features of the HEVC structure is the concept of multiple partitions, including CUs, PUs, and TUs.

[0041] In VVC, a quadtree with nested multi-type trees using bipartite and tripartite segmentation structures replaces the concept of multiple segmentation unit types, i.e., it removes the distinction between CU, PU, ​​and TU concepts, appropriately excluding CUs whose size is too large for the maximum transform length, and supports greater flexibility in CU segmentation shapes. In the coding tree structure, CUs can have either square or rectangular shapes. CTUs are first segmented using a quadtree (also known as a quadtree) structure. The leaf nodes of the quadtree can then be further segmented using a multi-type tree structure.

[0042] 4A-4D are schematic diagrams illustrating multitype tree partitioning modes according to some implementations of the present disclosure. As shown in FIGS. 4A-4D, the multitype tree structure has four partition types: vertical bisection 402 (SPLIT_BT_VER), horizontal bisection 404 (SPLIT_BT_HOR), vertical trisection 406 (SPLIT_TT_VER), and horizontal trisection 408 (SPLIT_TT_HOR). The leaf nodes of the multitype tree are called CUs, and this segmentation is used for prediction and transform processing without further partitioning unless the CU is too large for the maximum transform length. This means that in most cases, CUs, PUs, and TUs have the same block size in a quad tree with a nested multitype tree coding block structure. An exception occurs when the maximum supported transform length is smaller than the width or height of the color component of the CU.

[0043] VVC Syntax In VVC, the first layer of syntax and signaling in the bitstream is the Network Abstraction Layer (NAL), which divides the bitstream into a set of NAL units. Some NAL units signal common control parameters, such as the Sequence Parameter Set (SPS) and Picture Parameter Set (PPS), to the decoder. Others contain video data. Video Coding Layer (VCL) NAL units contain slices of coded video. A coded picture is called an access unit and can be coded as one or more slices.

[0044] A coded video sequence begins with an Instantaneous Decoder Refresh (IDR) picture. All following video pictures are coded as slices. A new IDR picture signals the end of the previous video segment and the beginning of a new one. Each NAL unit begins with a one-byte header followed by a Raw Byte Sequence Payload (RBSP). The RBSP contains the coded slices. Slices are binarized and may be padded with zero bits to make them an integer number of bytes long. A slice consists of a slice header and slice data. Slice data is specified as a series of CUs.

[0045] The concept of a picture header, transmitted once per picture as the first VCL NAL unit of a picture, was adopted at the 16th JVET meeting. It was also proposed to group some syntax elements that were previously in slice headers into this picture header. Syntax elements that functionally only need to be transmitted once per picture can be moved to the picture header instead of being transmitted multiple times in the slices of a given picture.

[0046] In the VVC specification, the syntax table specifies a superset of all allowed bitstream syntaxes. Additional constraints on the syntax may be specified directly or indirectly in other clauses. Table 1 below is a syntax table for slice headers and picture headers in VVC. The semantics of some of the syntax are also shown after the syntax table. [Table 1] JPEG2026035867000003.jpg250157JPEG2026035867000004.jpg249157JPEG2026035867000005.jpg250153JPEG2026035867000006.jpg114153

[0047] Semantics of selected syntax elements ph_temporal_mvp_enabled_flag specifies whether a temporal motion vector predictor can be used for inter prediction of the slice associated with the PH. If ph_temporal_mvp_enabled_flag is equal to 0, the syntax elements of the slice associated with the PH shall constrain the temporal motion vector predictor not to be used when decoding the slice. Otherwise (if ph_temporal_mvp_enabled_flag is equal to 1), a temporal motion vector predictor may be used when decoding the slice associated with the PH. The value of ph_temporal_mvp_enabled_flag is inferred to be equal to 0 if not present. If there is no reference picture in the Decoded Picture Buffer (DPB) with the same spatial resolution as the current picture, the value of ph_temporal_mvp_enabled_flag shall be equal to 0.

[0048] The maximum number of subblock-based merge MVP candidates, MaxNumSubblockMergeCand, is derived as follows: if(sps_affine_enabled_flag) MaxNumSubblockMergeCand=5-five_minus_max_num_subblock_merge_cand else MaxNumSubblockMergeCand=sps_sbtmvp_enabled_flag&&ph_temporal_mvp_enabled_flag; Here, the value of MaxNumSubblockMergeCand is assumed to be in the range of 0 to 5 (inclusive).

[0049] slice_collocated_from_l0_flag equal to 1 specifies that the collocated picture used for temporal motion vector prediction is derived from reference picture list 0. slice_collocated_from_l0_flag equal to 0 specifies that the collocated picture used for temporal motion vector prediction is derived from reference picture list 1.

[0050] If slice_type is equal to B or P, ph_temporal_mvp_enabled_flag is equal to 1, and slice_collocated_from_l0_flag is not present, the following applies: - If rpl_info_in_ph_flag is equal to 1, slice_collocated_from_l0_flag is inferred to be equal to ph_collocated_from_l0_flag. - Otherwise (if rpl_info_in_ph_flag is equal to 0 and slice_type is equal to P), the value of slice_collocated_from_l0_flag is inferred to be equal to 1.

[0051] slice_collocated_ref_idx specifies the reference index of the collocated picture used for temporal motion vector prediction.

[0052] If slice_type is equal to P, or if slice_type is equal to B and slice_collocated_from_l0_flag is equal to 1, slice_collocated_ref_idx refers to an entry in reference picture list 0, and the value of slice_collocated_ref_idx shall be in the range from 0 to NumRefIdxActive[0]-1 (inclusive).

[0053] If slice_type is equal to B and slice_collocated_from_l0_flag is equal to 0, slice_collocated_ref_idx refers to an entry in reference picture list 1, and the value of slice_collocated_ref_idx shall be in the range from 0 to NumRefIdxActive[1]-1 inclusive.

[0054] If slice_collocated_ref_idx is not present, the following applies: - If rpl_info_in_ph_flag is equal to 1, the value of slice_collocated_ref_idx is inferred to be equal to ph_collocated_ref_idx. - Otherwise (rpl_info_in_ph_flag is equal to 0), the value of slice_collocated_ref_idx is inferred to be equal to 0.

[0055] It is a bitstream compliance requirement that the picture referenced by slice_collocated_ref_idx must be the same for all slices of a coded picture.

[0056] It is a bitstream compliance requirement that the values ​​of pic_width_in_luma_samples and pic_height_in_luma_samples of the reference picture referenced by slice_collocated_ref_idx must be equal to the values ​​of pic_width_in_luma_samples and pic_height_in_luma_samples of the current picture, respectively, and that RprConstraintsActive[slice_collocated_from_l0_flag?0:1][slice_collocated_ref_idx] must be equal to 0.

[0057] The values ​​of RprConstraintsActive[i][j] are derived in section 8.3.2 of the VVC specification. The derivation of the values ​​of RprConstraintsActive[i][j] is explained below.

[0058] Decoding process for constructing a reference picture list The decoding process for constructing a reference picture list is invoked at the start of the decoding process for each slice of a non-IDR picture.

[0059] A reference picture is addressed by a reference index, which is an index into a reference picture list. When decoding an I slice, the reference picture list is not used when decoding the slice data. When decoding a P slice, only reference picture list 0 (i.e., RefPicList[0]) is used when decoding the slice data. When decoding a B slice, both reference picture list 0 and reference picture list 1 (i.e., RefPicList[1]) are used when decoding the slice data.

[0060] At the beginning of the decoding process for each slice of a non-IDR picture, reference picture lists RefPicList[0] and RefPicList[1] are derived. The reference picture lists are used when marking reference pictures as specified in the video coding standard or when decoding slice data.

[0061] For an I-slice of a non-IDR picture that is not the first slice of the picture, RefPicList[0] and RefPicList[1] may be derived for the purpose of bitstream compliance checking, but their derivation is not required for decoding the current picture or pictures after the current picture in decoding order. For a P-slice that is not the first slice of the picture, RefPicList[1] may be derived for the purpose of bitstream compliance checking, but its derivation is not required for decoding the current picture or pictures after the current picture in decoding order.

[0062] The reference picture lists RefPicList[0] and RefPicList[1], the reference picture scaling ratios RefPicScale[i][j][0] and RefPicScale[i][j][1], and the reference picture scaling flags RprConstraintsActive[0][j] and RprConstraintsActive[1][j] are derived as follows:

number

[0063] scaling_win_left_offset, scaling_win_right_offset, scaling_win_top_offset, and scaling_win_bottom_offset specify offsets to be applied to the picture size for scaling ratio calculation. If not present, the values ​​of scaling_win_left_offset, scaling_win_right_offset, scaling_win_top_offset, and scaling_win_bottom_offset are inferred to be equal to pps_conf_win_left_offset, pps_conf_win_right_offset, pps_conf_win_top_offset, and pps_conf_win_bottom_offset, respectively.

[0064] The value of SubWidthC*(scaling_win_left_offset+scaling_win_right_offset) shall be less than pic_width_in_luma_samples, and the value of SubHeightC*(scaling_win_top_offset+scaling_win_bottom_offset) shall be less than pic_height_in_luma_samples.

[0065] The variables PicOutputWidthL and PicOutputHeightL are derived as follows: PicOutputWidthL=pic_width_in_luma_samples-SubWidthC*(scaling_win_right_offset+scaling_win_left_offset) PicOutputHeightL=pic_height_in_luma_samples-SubWidthC*(scaling_win_bottom_offset+scaling_win_top_offset)

[0066] Let refPicOutputWidthL and refPicOutputHeightL be the PicOutputWidthL and PicOutputHeightL, respectively, of the reference picture of the current picture that references this PPS. It is a bitstream compliance requirement that all of the following conditions be met: - PicOutputWidthL*2 shall be greater than or equal to refPicWidthInLumaSamples. - PicOutputHeightL*2 shall be greater than or equal to refPicHeightInLumaSamples. - PicOutputWidthL shall be less than or equal to refPicWidthInLumaSamples*8. - PicOutputHeightL shall be less than or equal to refPicHeightInLumaSamples*8. - PicOutputWidthL*pic_width_max_in_luma_samples shall be greater than or equal to refPicOutputWidthL*(pic_width_in_luma_samples-Max(8,MinCbSizeY)). - PicOutputHeightL*pic_height_max_in_luma_samples shall be greater than or equal to refPicOutputHeightL*(pic_height_in_luma_samples-Max(8,MinCbSizeY)).

[0067] In the current VVC, the mvd_l1_zero_flag is signaled in the PH without any conditional constraint. However, the function controlled by the flag mvd_l1_zero_flag is applicable only when the slice is a bi-predictive slice (B slice). Therefore, if the slice associated with the picture header is not a B slice, the signaling of the flag is redundant.

[0068] In another example, ph_disable_bdof_flag and ph_disable_dmvr_flag are signaled in PH only if the corresponding enable flags (sps_bdof_pic_present_flag, sps_dmvr_pic_present_flag) signaled in the sequence parameter set (SPS) are true. However, as shown in Table 2 below, the functionality controlled by the flags ph_disable_bdof_flag and ph_disable_dmvr_flag is applicable only if the slice is a bi-predictive slice (B slice). Therefore, if the slice associated with the picture header is not a B slice, the signaling of these two flags is redundant or useless. [Table 2]

[0069] The third issue is related to the syntax ph_temporal_mvp_enabled_flag. Currently, in VVC, the resolution of the collocated picture selected for temporal motion vector prediction (TMVP) derivation must be the same as the resolution of the current picture, so there is a bitstream compliance constraint that checks the value of ph_temporal_mvp_enabled_flag, as described below. If there is no reference picture in the DPB that has the same spatial resolution as the current picture, the value of ph_temporal_mvp_enabled_flag shall be equal to 0.

[0070] However, in the current VVC, not only does the resolution of the co-located picture affect TMVP enablement, but the offset applied to the picture size for scaling ratio calculation also affects TMVP enablement. However, in the current VVC, the offset is not taken into account in the bitstream compliance of ph_temporal_mvp_enabled_flag.

[0071] Furthermore, there is a bitstream compliance requirement that the picture referenced by slice_collocated_ref_idx must be the same for all slices of a coded picture. However, if a coded picture has multiple slices and there is no common reference picture for all these slices, this bitstream compliance has no chance to be met. Also, in such a case, ph_temporal_mvp_enabled_flag needs to be constrained to 0.

[0072] To address the above challenges, several methods are proposed. It should be noted that the proposed methods can be applied independently or in combination.

[0073] Since the functions controlled by the flags mvd_l1_zero_flag, ph_disable_bdof_flag, and ph_disable_dmvr_flag are applicable only when a slice is a bi-predictive slice (B slice), according to the method of this disclosure, it is proposed to signal these flags only when the associated slice is a B slice. Note that if a reference picture list is signaled in PH (e.g., rpl_info_in_ph_flag=1), this means that all slices of the coded picture use the same reference picture signaled in PH. Therefore, if a reference picture list is signaled in PH and the signaled reference picture list indicates that the current picture is not bi-predictive, the flags mvd_l1_zero_flag, ph_disable_bdof_flag, and ph_disable_dmvr_flag do not need to be signaled.

[0074] In some examples, some conditions are added to the syntax set in PH to prevent redundant signaling or undefined decoding behavior due to improper values ​​sent for some of the syntax in the picture header. Some examples are shown below, where the variable num_ref_entries[i][RplsIdx[i]] represents the number of reference pictures in list i. If(rpl_info_in_ph_flag&&num_ref_entries[0][RplsIdx[0]]>1&&num_ref_entries[1][RplsIdx[1]]>1) mvd_l1_zero_flag; If(sps_bdof_pic_present_flag&&rpl_info_in_ph_flag&&num_ref_entries[0][RplsIdx[0]]>1&&num_ref_entries[1][RplsIdx[1]]>1) ph_disable_bdof_flag

[0075] In the current VVC, not only can the resolution of a co-located picture affect the enablement of TMVP, but also the offset applied to the picture size for scaling ratio calculation can affect the enablement of TMVP. However, in the current VVC, the offset is not taken into account in the bitstream compliance of ph_temporal_mvp_enabled_flag. In some examples, it is proposed to add a bitstream compliance constraint to the current VVC that requires that the value of ph_temporal_mvp_enabled_flag must depend on the offset applied to the picture size for scaling ratio calculation, as described below. If there is no reference picture in the DPB that has the same spatial resolution and offset applied to the picture size for scaling ratio calculation as the current picture, the value of ph_temporal_mvp_enabled_flag shall be equal to 0.

[0076] The above bitstream compliance constraint can also be written in another way as follows: If there is no reference picture in the DPB whose associated variable value RprConstraintsActive[i][j] is equal to 0, the value of ph_temporal_mvp_enabled_flag shall be equal to 0.

[0077] In current VVC, there is a bitstream compliance requirement that the picture referenced by slice_collocated_ref_idx must be the same for all slices of a coded picture. However, if a coded picture has multiple slices and there is no common reference picture for all these slices, this bitstream compliance has no chance to be met.

[0078] In some examples, the bitstream compliance requirements for the ph_temporal_mvp_enabled_flag are modified to consider whether there is a reference picture common to all slices of the current picture.

[0079] ph_temporal_mvp_enabled_flag specifies whether a temporal motion vector predictor can be used for inter prediction of a slice associated with the PH. If ph_temporal_mvp_enabled_flag is equal to 0, the syntax elements of the slice associated with the PH shall constrain the temporal motion vector predictor not to be used when decoding the slice. Otherwise (if ph_temporal_mvp_enabled_flag is equal to 1), a temporal motion vector predictor may be used when decoding the slice associated with the PH. The value of ph_temporal_mvp_enabled_flag is inferred to be equal to 0 if not present. If there is no reference picture in the DPB that has the same spatial resolution as the current picture, the value of ph_temporal_mvp_enabled_flag shall be equal to 0. If there is no reference picture common to all slices associated with the PH, the value of ph_temporal_mvp_enabled_flag shall be equal to 0.

[0080] In some examples, bitstream compliance with respect to slice_collocated_ref_idx is simplified such that the bitstream compliance requirement is that RprConstraintsActive[slice_collocated_from_l0_flag?0:1][slice_collocated_ref_idx] must be equal to 0.

[0081] 5 is a block diagram illustrating an exemplary device for video encoding according to some implementations of the present disclosure. The device 500 may be, for example, a mobile phone, a tablet computer, a digital broadcast terminal, a tablet device, or a personal digital assistant.

[0082] As shown in FIG. 5, the device 500 may include one or more of the following components: a processing component 502, a memory 504, a power component 506, a multimedia component 508, an audio component 510, an input / output (I / O) interface 512, a sensor component 514, and a communication component 516.

[0083] The processing component 502 typically controls the overall operation of the device 500, such as operations related to display, telephony, data communication, camera operation, and recording operation. The processing component 502 may include one or more processors 520 for executing instructions to complete all or some of the steps of the methods described above. Additionally, the processing component 502 may include one or more modules for facilitating interaction between the processing component 502 and other components. For example, the processing component 502 may include a multimedia module for facilitating interaction between the multimedia component 508 and the processing component 502.

[0084] Memory 504 is configured to store various types of data to support the operation of device 500. Examples of such data include instructions for any applications or methods operating on device 500, contact data, phone book data, messages, photos, videos, etc. Memory 504 may be implemented by any type of volatile or non-volatile storage device or combination thereof, and memory 504 may be static random access memory (SRAM), electrically erasable programmable read-only memory (EEPROM), erasable programmable read-only memory (EPROM), programmable read-only memory (PROM), read-only memory (ROM), magnetic memory, flash memory, magnetic disk, or compact disk.

[0085] The power supply component 506 provides power to the various components of the device 500. The power supply component 506 may include a power management system, one or more power supplies, and other components associated with the generation, management, and distribution of power for the device 500.

[0086] The multimedia component 508 includes a screen that provides an output interface between the device 500 and a user. In some examples, the screen may include a liquid crystal display (LCD) and a touch panel (TP). If the screen includes a touch panel, the screen may be implemented as a touch screen that receives input signals from a user. The touch panel may include one or more touch sensors for sensing touches, slides, and gestures on the touch panel. The touch sensors may not only sense the boundaries of a touch or slide operation but also detect the duration and pressure associated with the touch or slide operation. In some examples, the multimedia component 508 may include a front camera and / or a rear camera. When the device 500 is in an operating mode, such as a photo mode or a video mode, the front camera and / or the rear camera may receive external multimedia data.

[0087] The audio component 510 is configured to output and / or input audio signals. For example, the audio component 510 includes a microphone (MIC). The microphone is configured to receive external audio signals when the device 500 is in an operation mode such as a call mode, a recording mode, and a voice recognition mode. The received audio signals may be further stored in the memory 504 or transmitted via the communication component 516. In some examples, the audio component 510 further includes a speaker for outputting audio signals.

[0088] The I / O interface 512 provides an interface between the processing component 502 and a peripheral interface module, which may be a keyboard, a click wheel, buttons, etc. These buttons may include, but are not limited to, a home button, volume buttons, a start button, and a lock button.

[0089] The sensor component 514 includes one or more sensors for providing status assessment of different aspects of the device 500. For example, the sensor component 514 may detect the on / off state of the device 500 and the relative position of components. For example, the components may be the display and keypad of the device 500. The sensor component 514 may also detect changes in the position of the device 500 or components of the device 500, the presence or absence of a user's contact with the device 500, the orientation or acceleration / deceleration of the device 500, and temperature changes of the device 500. The sensor component 514 may include a proximity sensor configured to detect the presence of a nearby object without physical contact. The sensor component 514 may further include an optical sensor, such as a CMOS or CCD image sensor used in imaging applications. In some examples, the sensor component 514 may further include an acceleration sensor, a gyroscope sensor, a magnetic sensor, a pressure sensor, or a temperature sensor.

[0090] The communication component 516 is configured to facilitate wired or wireless communication between the device 500 and other devices. The device 500 may access a wireless network based on a communication standard, such as WiFi, 4G, or a combination thereof. In one example, the communication component 516 receives a broadcast signal or broadcast-related information from an external broadcast management system via a broadcast channel. In one example, the communication component 516 may further include a near field communication (NFC) module to facilitate short-range communication. For example, the NFC module may be implemented based on radio frequency identification (RFID) technology, infrared data association (IrDA) technology, ultra-wideband (UWB) technology, Bluetooth (BT) technology, and other technologies.

[0091] In one example, the apparatus 500 may be implemented by one or more of an application specific integrated circuit (ASIC), a digital signal processor (DSP), a digital signal processing device (DSPD), a programmable logic device (PLD), a field programmable gate array (FPGA), a controller, a microcontroller, a microprocessor, or other electronic elements for performing the above-described methods.

[0092] The non-transitory computer-readable storage medium may be, for example, a hard disk drive (HDD), a solid-state drive (SSD), a flash memory, a hybrid drive or a solid-state hybrid drive (SSHD), a read-only memory (ROM), a compact disc read-only memory (CD-ROM), a magnetic tape, a floppy disk, etc.

[0093] FIG. 6 is a flowchart illustrating an example process for video encoding according to some implementations of this disclosure.

[0094] In step 602, processor 520 determines whether one or more reference picture lists are signaled in the PH associated with the picture and whether the one or more reference picture lists indicate that one or more slices associated with the picture are bi-predictive.

[0095] In step 604, the processor 620 adds one or more constraints to one or more syntax elements of the PH in response to determining that one or more reference picture lists are signaled in the PH and that the one or more reference picture lists indicate that one or more slices are not bi-predictive.

[0096] In some examples, the one or more constraints include skipping the parsing of one or more syntax elements.

[0097] In some examples, the one or more syntax elements include one or more flags applicable to one or more slices.

[0098] Processor 520 may further use an enable flag, such as the mvd_l1_zero_flag described above, to specify whether the corresponding motion vector differential (MVD) coding syntax structure is not parsed and whether two variables are set to zero for one or more slices associated with the PH, where the two variables respectively specify the difference between a list vector component and a prediction corresponding to the list vector component.

[0099] In some examples, mvd_l1_zero_flag equal to 1 indicates that the mvd_coding(x0,y0,1) syntax structure is not parsed, and MvdL1[x0][y0][compIdx] and MvdCpL1[x0][y0][cpIdx][compIdx] are set equal to 0 for compIdx=0 or 1 and cpIdx=0, 1, or 2. Furthermore, mvd_l1_zero_flag equal to 0 indicates that the mvd_coding(x0,y0,1) syntax structure is parsed. The mvd_coding(x0,y0,1) syntax structure is the corresponding MVD coding syntax structure. The array indexes x0, y0 identify the position (x0,y0) of the top-left luma sample of the coding block under consideration relative to the top-left luma sample of the picture.

[0100] Furthermore, the variable MvdLX[x0][y0][compIdx], where X is 0 or 1, specifies the list X vector component used and its difference from its prediction. The array indices x0, y0 specify the position (x0, y0) of the top-left luma sample of the coding block under consideration relative to the top-left luma sample of the picture. Horizontal motion vector component differences are assigned compIdx=0, and vertical motion vector components are assigned compIdx=1.

[0101] Furthermore, the variables MvdCpLX[x0][y0][cpIdx][compIdx], where X is either 0 or 1, identify the list X vector component to be used and its difference from its prediction. The array indices x0, y0 identify the position (x0, y0) of the top-left luma sample of the coding block under consideration relative to the top-left luma sample of the picture. The array index cpIdx identifies the index of the control point. Horizontal motion vector component differences are assigned compIdx=0, and vertical motion vector components are assigned compIdx=1.

[0102] Processor 520 may further constrain one or more syntax elements to MVD coding syntax structures to be parsed for one or more slices in response to determining that the enable flag is equal to 0.

[0103] Processor 520 may further determine, in response to determining that the enable flag is equal to one, to skip parsing the MVD syntax structure when decoding one or more slices.

[0104] Processor 520 may further use a disable flag such as the above-mentioned ph_disable_bdof_flag to specify whether bi-directional optical flow (BDOF) inter-prediction-based inter bi-prediction is disabled for one or more slices associated with the PH, and in response to determining that the disable flag is equal to 0, constrain one or more syntax elements to enable BDOF inter-prediction-based inter bi-prediction when decoding one or more slices, and in response to determining that the disable flag is equal to 1, disable BDOF inter-prediction-based inter bi-prediction when decoding one or more slices.

[0105] Processor 520 may further use a disable flag, such as the above-described ph_disable_dmvr_flag, to specify whether decoder motion vector refinement (DMVR)-based inter bi-prediction is disabled for one or more slices associated with the PH, and in response to determining that the disable flag is equal to 0, constrain one or more syntax elements to enable DMVR-based inter bi-prediction when decoding one or more slices, and in response to determining that the disable flag is equal to 1, disable DMVR-based inter bi-prediction when decoding one or more slices.

[0106] FIG. 7 is a flowchart illustrating an example process for video encoding according to some implementations of this disclosure.

[0107] In step 702, the processor 520 uses the enable flag to specify whether one or more temporal motion vector predictors are used for inter prediction of one or more slices associated with the PH of the picture.

[0108] In step 704, the processor 520 constrains the value of the enable flag according to a number of offsets applied to the size of the picture for scaling ratio calculation.

[0109] In response to determining that there is no reference picture in the DPB that has the same spatial resolution and the same offset as the picture, processor 520 may set the enable flag to 0. Additionally, the offset may be applied to the size of the picture for scaling ratio calculations.

[0110] Processor 520 may set the validation flag to 0 in response to determining that one or more slices do not have a common reference picture.

[0111] Processor 520 may set the enable flag to 0 in response to determining that there is no reference picture in the DPB whose reference picture scaling flag is equal to 0.

[0112] The processor 520 may derive the reference picture scaling flag based on multiple offsets applied to the size of the picture for scaling ratio calculation.

[0113] In some examples, an apparatus for video encoding is provided that includes one or more processors 520 and a memory 504 configured to store instructions executable by the one or more processors, the processors configured, upon execution of the instructions, to perform the method illustrated in FIG.

[0114] In some examples, an apparatus for video encoding is provided that includes one or more processors 520 and a memory 504 configured to store instructions executable by the one or more processors, the processors configured, upon execution of the instructions, to perform the method illustrated in FIG.

[0115] In some other examples, a non-transitory computer-readable storage medium 504 having instructions stored thereon is provided that, when executed by one or more processors 520, cause the processors to perform the method illustrated in FIG.

[0116] In some other examples, a non-transitory computer-readable storage medium 504 having instructions stored thereon is provided that, when executed by one or more processors 520, cause the processors to perform the method illustrated in FIG.

[0117] The description of the present disclosure has been presented for purposes of illustration and is not intended to be exhaustive or limiting of the present disclosure. Many modifications, variations and alternative implementations will be apparent to one skilled in the art having the benefit of the teachings presented in the foregoing descriptions and the associated drawings.

[0118] The examples have been chosen and described to explain the principles of the disclosure and to enable others skilled in the art to understand the disclosure in its various implementations and to best utilize the underlying principles and various modifications suitable for the particular applications contemplated. It is therefore to be understood that the scope of the disclosure should not be limited to the particular examples of implementations disclosed, and that modifications and other implementations are intended to be included within the scope of the disclosure.

Claims

1. 1. A method for video encoding, comprising: determining, by a decoder, whether one or more reference picture lists are signaled in a picture header (PH) associated with a picture and whether the one or more reference picture lists indicate that one or more slices associated with the picture are bi-predictive; adding, by the decoder, one or more constraints to one or more syntax elements of the PH in response to determining that the one or more reference picture lists are signaled in the PH and that the one or more reference picture lists indicate that the one or more slices are not bi-predictive; A method comprising:

2. The method of claim 1 , wherein the one or more constraints include skipping parsing of the one or more syntax elements.

3. The method of claim 1 , wherein the one or more syntax elements include one or more flags applicable to the one or more slices.

4. using an enable flag to specify whether a corresponding motion vector differential (MVD) coding syntax structure is not parsed and whether two variables are set to zero for the one or more slices associated with the PH, the two variables specifying a difference between a list vector component and a prediction corresponding to the list vector component, respectively; In response to determining that the enable flag is equal to 0, constraining the one or more syntax elements to parse the MVD coding syntax structure for the one or more slices; in response to determining that the enable flag is equal to one, skipping parsing the MVD coding syntax structure when decoding the one or more slices; The method of claim 1 further comprising:

5. using a disable flag to identify whether bidirectional optical flow (BDOF) inter prediction based inter bi-prediction is disabled for the one or more slices associated with the PH; in response to determining that the disable flag is equal to 0, constraining the one or more syntax elements such that the BDOF inter prediction-based inter bi-prediction is enabled when decoding the one or more slices; in response to determining that the disable flag is equal to one, disabling the BDOF inter prediction-based inter bi-prediction when decoding the one or more slices; The method of claim 1 further comprising:

6. using a disable flag to identify whether decoder motion vector refinement (DMVR)-based inter bi-prediction is disabled for the one or more slices associated with the PH; in response to determining that the disable flag is equal to 0, constraining the one or more syntax elements such that the DMVR-based inter bi-prediction is enabled when decoding the one or more slices; in response to determining that the disable flag is equal to one, disabling the DMVR-based inter bi-prediction when decoding the one or more slices; The method of claim 1 further comprising:

7. 1. A method for video encoding, comprising: using an enable flag to identify whether the decoder uses one or more temporal motion vector predictors for inter prediction of one or more slices associated with a picture header (PH) of the picture; constraining, by the decoder, the value of the enable flag according to a plurality of offsets applied to the size of the picture for scaling ratio calculation; A method comprising:

8. 8. The method of claim 7, further comprising: setting the enable flag to 0 in response to determining that there is no reference picture in a decoded picture buffer (DPB) having the same spatial resolution and the same offset as the picture, wherein the offset is applied to the size of the picture for scaling ratio calculation.

9. The method of claim 7 , further comprising: setting the validation flag to 0 in response to determining that the one or more slices do not have a common reference picture.

10. 8. The method of claim 7, further comprising: setting the enable flag to 0 in response to determining that there is no reference picture in a decoded picture buffer (DPB) whose reference picture scaling flag is equal to 0.

11. The method of claim 10 , further comprising: deriving the reference picture scaling flag based on the plurality of offsets applied to the size of the picture for scaling ratio calculation.

12. 1. An apparatus for video encoding, comprising: one or more processors; a memory configured to store instructions executable by the one or more processors; The one or more processors, upon execution of the instructions, determining whether one or more reference picture lists are signaled in a picture header (PH) associated with a picture and whether the one or more reference picture lists indicate that one or more slices associated with the picture are bi-predictive; adding one or more constraints to one or more syntax elements of the PH in response to determining that the one or more reference picture lists are signaled in the PH and that the one or more reference picture lists indicate that the one or more slices are not bi-predictive; and 20. An apparatus configured to:

13. The apparatus of claim 12 , wherein the one or more constraints include skipping parsing of the one or more syntax elements.

14. The apparatus of claim 12 , wherein the one or more syntax elements include one or more flags applicable to the one or more slices.

15. the one or more processors: using an enable flag to specify whether a corresponding motion vector differential (MVD) coding syntax structure is not parsed and whether two variables are set to zero for the one or more slices associated with the PH, the two variables specifying a difference between a list vector component and a prediction corresponding to the list vector component, respectively; In response to determining that the enable flag is equal to 0, constraining the one or more syntax elements to parse the MVD coding syntax structure for the one or more slices; in response to determining that the enable flag is equal to one, skipping parsing the MVD coding syntax structure when decoding the one or more slices; The apparatus of claim 12 , further configured to perform:

16. the one or more processors: using a disable flag to identify whether bidirectional optical flow (BDOF) inter prediction based inter bi-prediction is disabled for the one or more slices associated with the PH; in response to determining that the disable flag is equal to 0, constraining the one or more syntax elements such that the BDOF inter prediction-based inter bi-prediction is enabled when decoding the one or more slices; in response to determining that the disable flag is equal to one, disabling the BDOF inter prediction-based inter bi-prediction when decoding the one or more slices; The apparatus of claim 12 , further configured to perform:

17. the one or more processors: using a disable flag to identify whether decoder motion vector refinement (DMVR)-based inter bi-prediction is disabled for the one or more slices associated with the PH; in response to determining that the disable flag is equal to 0, constraining the one or more syntax elements such that the DMVR-based inter bi-prediction is enabled when decoding the one or more slices; in response to determining that the disable flag is equal to one, disabling the DMVR-based inter bi-prediction when decoding the one or more slices; The apparatus of claim 12 , further configured to perform:

18. 1. An apparatus for video encoding, comprising: one or more processors; a memory configured to store instructions executable by the one or more processors; The one or more processors, upon execution of the instructions, using an enable flag to identify whether one or more temporal motion vector predictors can be used for inter prediction of one or more slices associated with a picture header (PH) of the picture; constraining the value of the enable flag according to a plurality of offsets applied to the size of the picture for scaling ratio calculation; 20. An apparatus configured to:

19. the one or more processors:

20. The apparatus of claim 18, further configured to: in response to determining that there is no reference picture in a decoded picture buffer (DPB) having the same spatial resolution and the same offset as the picture, set the enable flag to 0, wherein the offset is applied to the size of the picture for scaling ratio calculation.

20. the one or more processors:

20. The apparatus of claim 18, further configured to: set the validation flag to 0 in response to determining that the one or more slices do not have a common reference picture.

21. the one or more processors:

20. The apparatus of claim 18, further configured to: set the enable flag to 0 in response to determining that no reference picture in a decoded picture buffer (DPB) has a reference picture scaling flag equal to 0.

22. the one or more processors:

22. The apparatus of claim 21, further configured to: derive the reference picture scaling flag based on the plurality of offsets applied to the size of the picture for scaling ratio calculation.

23. A non-transitory computer-readable storage medium for video encoding storing computer-executable instructions that, when executed by one or more computer processors, cause the one or more computer processors to perform the method of any of claims 1 to 6.

24. 12. A non-transitory computer-readable storage medium for video encoding storing computer-executable instructions that, when executed by one or more computer processors, cause the one or more computer processors to perform the method of any of claims 7 to 11.

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