Ad converter

Abstract

The AD converter has room for further study in terms of the input voltage range.SOLUTION: The AD converter (1X) includes a first capacitive DAC, a second capacitive DAC, a changeover switch, a comparator, and a control circuit. The second capacitive DAC is configured to have a larger capacitance than the first capacitive DAC. The changeover switch is configured to be capable of switching the first capacitive DAC and the second capacitive DAC between a conductive state and a non-conductive state. The comparator is configured such that only the output of the first capacitive DAC of the first capacitive DAC and the second capacitive DAC is input when the comparator is in a non-conductive state, and the outputs of the first capacitive DAC and the second capacitive DAC are input when the comparator is in a conductive state.SELECTED DRAWING: Figure 4

Description

[Technical Field]

[0001] The invention disclosed herein relates to an AD converter. [Background technology]

[0002] Conventionally, there is a successive approximation type AD (Analog Digital) converter.

[0003] As an example of the related prior art, Patent Document 1 can be mentioned. [Prior art documents] [Patent documents]

[0004] [Patent Document 1] Japanese Patent Application Laid-Open No. 2024-000179

[0005] [overview] The AD converter disclosed in Patent Document 1 leaves room for further consideration regarding the input voltage range.

[0006] The AD converter disclosed in this specification includes a first capacitive DAC, a second capacitive DAC, a changeover switch, a comparator, and a control circuit. The first capacitive DAC is configured to receive an analog input signal. The second capacitive DAC receives the analog input signal and is configured to have a larger capacitance than the first capacitive DAC. The changeover switch is configured to switch the first capacitive DAC and the second capacitive DAC between a conductive state and a non-conductive state. The comparator is configured such that, when in a non-conductive state, only the output of the first capacitive DAC is input to the comparator, and when in a conductive state, the outputs of the first capacitive DAC and the second capacitive DAC are input to the comparator. The control circuit is configured to control the first capacitive DAC and the second capacitive DAC based on the output of the comparator. [Brief explanation of the drawings]

[0007] [Figure 1] FIG. 1 is a block diagram showing the configuration of an AD converter 1Y of the comparative example. [Figure 2] FIG. 2 is a block diagram showing the configuration of an AD converter 1Y of the comparative example. [Figure 3] FIG. 3 is a diagram showing an example of the configuration of the low-bit ADC 8 according to the comparative example. [Figure 4] FIG. 4 is a block diagram showing the configuration of an AD converter 1X according to the present disclosure. [Figure 5] FIG. 5 is a graph showing the change in the DAC output voltage V1 during the successive approximation period. [Figure 6] FIG. 6 is a diagram showing the setting state of the bit values ​​of the digital output signal Dout during the successive approximation period. [Figure 7] FIG. 7 is a diagram showing a detailed configuration of the capacitive DACs 2xa and 2xb. [Figure 8] FIG. 8 is a diagram showing the connection relationship between the capacitor C[i], the switch S[i], and the wirings WR_IN, WR_VD, and WR_G. [Figure 9] FIG. 9 is a diagram showing the capacitance values ​​of the capacitors C[1] to C[N+A], the adjustment capacitor Ca, and the attenuation capacitor C[0]. [Figure 10] FIG. 10 is a flowchart of the AD conversion operation. [Figure 11] FIG. 11 is a flowchart showing an example of the flow of a state transition operation. [Figure 12] FIG. 12 is a diagram showing the structure of the register 31. [Figure 13] FIG. 13 is a flowchart showing the configuration of the successive approximation operation. [Figure 14] FIG. 14 is a flowchart showing an example of the flow of the low-gain DAC output operation. [Figure 15] FIG. 15 is a flowchart showing an example of the flow of the high-gain DAC output operation. [Figure 16] FIG. 16 is a diagram showing the configuration of an AD converter 1X according to the second embodiment. [Figure 17] FIG. 17 is a diagram showing the configuration of an AD converter 1X according to the third embodiment. [Figure 18] FIG. 18 is a diagram showing the configuration of an AD converter 1X according to the fourth embodiment.

[0008] [Detailed explanation] <Configuration of AD Converter 1Y According to Comparative Example> First, the configuration of an AD converter 1Y that is a comparative example of the AD converter 1X of the present disclosure will be described. Next, problems with the comparative AD converter 1Y will be described, and then the configuration of the AD converter 1X of the present disclosure will be described.

[0009] Fig. 1 is a block diagram showing the configuration of an AD converter 1Y of a comparative example. As shown in Fig. 1, the AD converter 1Y performs AD conversion on an analog input signal IN to generate a digital output signal Dout. The digital output signal Dout is a digital signal with a predetermined number of bits (for example, 16 bits).

[0010] The AD converter 1Y includes a capacitive DAC (Digital-to-Analog Converter) 2y, a comparator 3, and a control circuit 4.

[0011] The capacitive DAC 2y receives an analog input signal IN and a digital signal DG. The capacitive DAC 2y generates a DAC output voltage VA based on the analog input signal IN and the digital signal DG. Specifically, this is as follows.

[0012] The digital signal DG is a digital signal with a predetermined number of bits (for example, 16 bits). The digital signal DG is set by the control circuit 4. The capacitive DAC 2y has a function of sampling and holding the analog input signal IN. The capacitive DAC 2y varies the sampled and held analog input signal IN in accordance with the digital signal DG to generate a DAC output voltage VA.

[0013] The comparator 3 receives the DAC output voltage VA and the comparison voltage V2 as inputs. The comparator 3 compares the DAC output voltage VA with the comparison voltage V2 and generates a comparison result signal SCMP according to the comparison result. The comparator 3 inputs the comparison result signal SCMP to the control circuit 4.

[0014] The control circuit 4 controls the capacitive DAC 2y. The control circuit 4 sets the digital signal DG in accordance with the comparison result signal SCMP. The control circuit 4 outputs the digital output signal Dout.

[0015] The AD conversion operation of the AD converter 1Y will be specifically described as follows. First, the capacitive DAC 2y samples the analog input signal IN. Then, the control circuit 4 sets an initial value for the digital signal DG. Here, the most significant bit (MSB) is set to "1," and the other bits are set to "0."

[0016] The comparator 3 then outputs a comparison result signal SCMP according to the comparison result between the DAC output voltage VA and the comparison voltage V2. The control circuit 4 determines the value of the most significant bit according to the comparison result signal SCMP. Specifically, if the DAC output voltage VA is higher than the comparison voltage V2, the most significant bit is determined to be "1." If the DAC output voltage VA is lower than the comparison voltage V2, the most significant bit is determined to be "0."

[0017] Then, the control circuit 4 sets the bit next to the most significant bit (hereinafter referred to as the second most significant bit) to "1", and sets the bits lower than this second most significant bit to "0".

[0018] The comparator 3 then changes the value of the DAC output voltage VA in response to the digital signal DG. The control circuit 4 determines the value of the second most significant bit in response to the comparison result signal SCMP. Specifically, if the DAC output voltage VA is higher than the comparison voltage V2, the second most significant bit is determined to be "1." If the DAC output voltage VA is lower than the comparison voltage V2, the second most significant bit is determined to be "0."

[0019] Then, the control circuit 4 sets the bit higher than the second bit (hereinafter, the third bit) to "1" and sets the bits lower than the third bit to "0".

[0020] Subsequent similar operations are repeated. In this way, in the AD converter 1Y, the values (= values according to the result of successive comparison between the DAC output voltage VA and the comparison voltage V2) are sequentially determined from the most significant bit of the digital output signal Dout, and the digital output signal Dout is generated.

[0021] <Consideration on the input range of the AD converter> By the way, the input range of the AD converter as described above is determined by the power supply of the comparator (corresponding to the comparator 3 described above) provided in the AD converter. For example, when the driving power supply voltage of the comparator is 3V, the upper limit value of the input voltage to the AD converter is limited to 3V. Thus, the AD converter as described above has a limited input range. To solve such a problem, some adopt a configuration that separately provides a low-bit ADC (when described in accordance with FIG. 2, the low-bit ADC 8) as shown in FIG. 2. Specifically, it is as follows.

[0022] As shown in FIG. 2, in addition to the above-described configuration, the AD converter 1Y includes a low-bit ADC 8. The low-bit ADC 8 is a so-called flash ADC. The low-bit ADC 8 outputs an output with a number of bits lower (here, 3 bits as an example) than the number of bits of the digital output Dout of the ADC 10.

[0023] The low-bit ADC 8 compares the analog input signal IN with voltages obtained by dividing a reference voltage into a plurality of parts, and converts the comparison result into digital output signals FLADO and FLADOD.

[0024] When performing 16-bit AD conversion, first, initialization is performed, and then, in parallel with the low-bit ADC 8 and the capacitive DAC 2y, the above-described sampling operation is executed.

[0025] The digital output signals FLADO and FLADOD output from the low-bit ADC 8 are both 3-bit data. These 3 bits correspond to the upper 3 bits (15th, 14th, and 13th bits) of the digital output signal Dout after AD conversion. FLADOD is 1 less than FLADO in decimal notation.

[0026] The control circuit 4 sets the digital signal DG based on the digital output signal FLADO. The comparator 3 compares the DA conversion output, which is obtained by DA converting the digital signal DG using the capacitive DAC 2y, with the analog input signal IN. Based on the comparison result signal SSCMP from the comparator 3, the control circuit 4 selects one of FLADOD and FLADO and determines the value of the upper three bits (the 15th, 14th, and 13th bits).

[0027] Thereafter, in the same manner as in the above-described embodiment, setting of the digital signal DG and determination of the bit value based on the comparison result signal SCMP are repeated from the 12th bit to the least significant bit (0th bit).

[0028] 3 is a diagram showing an example of the configuration of a low-bit ADC 8 according to a comparative example. As shown in FIG. 3, the low-bit ADC 8 is a so-called flash ADC. The low-bit ADC 8 has six comparators 81 and a decoder 82. An analog input signal IN is input to a first input terminal of each of the comparators 81. Six voltages obtained by dividing the reference voltage REF ((13 / 16)×REF, (11 / 16)×REF, (9 / 16)×REF, (7 / 16)×REF, (5 / 16)×REF, and (3 / 16)×REF) are input to a second input terminal of each of the comparators 81.

[0029] Comparison outputs FLADI[5] to FLADI[0] are output from the comparators 81. The decoder 82 converts FLADI[5:0] into digital output signals FLADO[2:0] and FLADOD[2:0].

[0030] The low-bit ADC 8 detects which of the seven voltage ranges defined by the voltages obtained by dividing the reference voltage REF into six ranges the analog input signal IN belongs to. It is detected that the analog input signal IN belongs to the voltage range of (11 / 16)×REF to (13 / 16)×REF, and the digital signal DG is set based on FLADO (=110). Then, as shown in FIG. 27, the analog input signal IN is lower (16 to 14 bits) than the DA conversion output by the capacitive DAC 2y. Therefore, FLADOD is selected from FLADO and FLADOD, and the 16th to 14th bits are determined. Then, successive conversion is performed on the 13th bit and onward.

[0031] When the reference voltage REF is 2.4V and no flash ADC is provided, the comparator input range is ±1.2V. On the other hand, in this embodiment where a flash ADC is provided, the comparator input range is ±(1 / 16) × REF ±0.05 = ±0.15 ±0.05 = ±0.2V. Note that 0.05V is the accuracy of the flash ADC. This narrows the comparator input range.

[0032] As described above, the low-bit ADC 8 is a flash ADC. If a configuration including such a low-bit ADC 8 is adopted, the AD converter 1Y may have an increased circuit area, increased current consumption, or deteriorated linearity characteristics due to interference with the low-bit ADC.

[0033] In contrast, the AD converter 1X of the present disclosure is capable of suppressing the above-mentioned problems. The AD converter 1X according to each embodiment of the present disclosure will be described in detail below. Note that the AD converter 1X according to each embodiment of the present disclosure includes configurations in common with the AD converter 1Y described above. For this reason, the common configurations are denoted by the same reference numerals and descriptions thereof will be omitted.

[0034] <Basic Configuration of AD Converter 1X According to First Embodiment> Fig. 4 is a block diagram showing the configuration of an AD converter 1X according to the present disclosure. As shown in Fig. 4, the AD converter 1X performs AD conversion on an analog input signal IN to generate a digital output signal Dout.

[0035] The AD converter 1X includes the same comparator 3 as described above, and a control circuit 4. In addition, the AD converter 1X includes a capacitive DAC 2xa, a capacitive DAC 2xb, a changeover switch SW1, an attenuation capacitor C0, a comparison voltage generating circuit 40, a connection switch 50, and short-circuit switches 70 and 71.

[0036] The capacitive DACs 2xa and 2xb are capacitor-type DACs (capacitor-type digital-to-analog converters). The capacitive DACs 2xa and DAC2xb receive an analog input signal IN and a digital signal DG, respectively. The capacitive DAC 2xa has a plurality of capacitors (capacitors C[N+1] to C[N+A] in accordance with FIG. 5, which will be described later). The capacitive DAC 2xb has a plurality of capacitors (capacitors C[1] to C[N] in accordance with FIG. 5, which will be described later). The capacitive DACs 2xa and DAC2xb have a predetermined capacitance (hereinafter also referred to as "total capacitance") corresponding to the capacitance of each of their capacitors. The total capacitance of the capacitive DAC 2xa is smaller than the total capacitance of the capacitive DAC 2xb. The capacitive DACs 2xa and DAC2xb have a function of sampling and holding the analog input signal IN.

[0037] The capacitive DAC 2xa is connected to the non-inverting input terminal (+) of the comparator 3 via a first wiring WR1.

[0038] The changeover switch SW1 is controlled to be turned on / off by the control circuit 4. When the changeover switch SW1 is in the on state, it puts the capacitive DAC 2xa and the capacitive DAC 2xb into a conductive state. When the changeover switch SW1 is in the off state, it puts the capacitive DAC 2xa and the capacitive DAC 2xb into a non-conductive state. Specifically, this is as follows.

[0039] A first terminal of the changeover switch SW1 is connected to the first wiring WR1. A second terminal of the changeover switch SW1 is connected to the second wiring WR2. The second wiring WR2 is connected to the capacitive DAC 2xb. The changeover switch SW1 is configured to be switchable between an ON state (= a state in which its first terminal and its second terminal are electrically connected) and an OFF state (= a state in which its first terminal and its second terminal are electrically disconnected). Turning the changeover switch SW1 ON / OFF switches between a conductive state and a non-conductive state between the capacitive DAC 2xa and the capacitive DAC 2xb.

[0040] When the capacitive DAC 2xa and the capacitive DAC 2xb are in a conductive state (hereinafter simply referred to as a "conductive state"), the DAC output voltage V1 is generated by both the capacitive DAC 2xa and the capacitive DAC 2xb. On the other hand, when the capacitive DAC 2xa and the capacitive DAC 2xb are in a non-conductive state (hereinafter simply referred to as a "non-conductive state"), the DAC output voltage V1 is generated only by the capacitive DAC 2xa.

[0041] The attenuation capacitor C0 attenuates the DAC output voltage V1 according to its own capacitance. In the non-conducting state, the relationship of attenuation rate = "total capacitance of capacitive DAC2xa" / ("total capacitance of capacitive DAC2xa" + "capacitance of attenuation capacitor C0") holds. In the conducting state, the relationship of attenuation rate = ("total capacitance of capacitive DAC2xa" + "total capacitance of capacitive DAC2xb") / ("total capacitance of capacitive DAC2xa" + "total capacitance of capacitive DAC2xb" + "capacitance of attenuation capacitor C0") holds.

[0042] For example, if the total capacity of the capacitive DAC2xa is 2 12 C, and the total capacitance of the capacitive DAC2xb is 2 16 C-2 12 C, and the capacitance of the damping capacitor C0 is 2 14 In this case, in the non-conducting state, the DAC output voltage V1 is attenuated to 20% of the value when the attenuation capacitor C0 is not provided. 12 / (2 12 +2 14)=0.2. In the conductive state, the attenuation capacitor C0 attenuates the DAC output voltage V1 by 80%. Specifically, 2 16 / (2 16 +2 14 )=0.8.

[0043] In this way, the DAC output voltage V1 in the non-conductive state is attenuated relatively greatly, and can also be said to have a low gain. The period during which the bits of the digital output signal Dout are determined in the non-conductive state is called a low-gain period. On the other hand, the DAC output voltage V1 in the conductive state is attenuated relatively little, and can also be said to have a high gain. The period during which the values ​​of the bits of the digital output signal Dout are determined in the conductive state is called a high-gain period.

[0044] The comparison voltage generation circuit 40 generates a comparison voltage V2 and supplies it to the inverting input terminal (-) of the comparator via the comparison wiring WRc. The comparison voltage V2 is a predetermined constant voltage. The DAC output voltage V1 and the comparison voltage V2 are input to the comparator 3. The comparator 3 compares the DAC output voltage V1 with the second comparison voltage V2 and generates a comparison result signal SCMP according to the comparison result.

[0045] The control circuit 4 controls the capacitive DACs 2xa and 2xb. The control circuit 4 sets the digital signal DG in accordance with the comparison result signal SCMP. The control circuit 4 outputs the digital output signal Dout.

[0046] The control circuit 4 determines the values ​​of predetermined upper bits of the digital output signal Dout in a conductive state, and also determines the values ​​of all lower bits below these upper bits in a non-conductive state.

[0047] FIG. 5 is a graph showing changes in the DAC output voltage V1 during a successive approximation period. FIG. 6 is a diagram showing the setting state of the bit values ​​of the digital output signal Dout during the successive approximation period. In FIG. 5, the vertical axis represents the voltage value, and the horizontal axis represents the bit that is the target of successive approximation. Also in FIG. 5, the DAC output voltage VA of the capacitive DAC 2y that receives the analog input signal IN is shown by a dashed line for reference. Also, in FIGS. 5 and 6, the digital output signal Dout is described as a 16-bit digital signal.

[0048] The AD conversion operation of the AD converter 1X will be specifically described below with reference to FIGS. 4 to 6. The control circuit 4 first turns the change-over switch SW1 off. Then, the capacitive DAC 2xa samples the analog input signal IN. At this time, the capacitive DAC 2xb does not sample the analog input signal IN. After that, the control circuit 4 sets an initial value for the digital signal DG. Here, the 15th bit, which is the most significant bit (MSB [Most Significant Bit]), is set to "1," and the other bits are set to "0" (see FIG. 6).

[0049] The control circuit 4 then changes the voltage value of the DAC output voltage V1 in accordance with the digital signal DG (the voltage value of the 14th bit in accordance with FIG. 5). Specifically, it changes the amount of charge on multiple capacitors inside the capacitive DAC 2xa (details will be described later). The comparator 3 then outputs a comparison result signal SCMP in accordance with the comparison result between the DAC output voltage V1 and the comparison voltage V2. The control circuit 4 determines the value of the most significant bit in accordance with the comparison result signal SCMP. Specifically, if the DAC output voltage V1 is higher than the comparison voltage V2, it determines the 15th bit to be "1." If the DAC output voltage V1 is lower than the comparison voltage V2, it determines the 15th bit to be "0."

[0050] Then, the control circuit 4 sets the 14th bit, which is the next most significant bit after the most significant bit, to "1" and sets the 13th bit and below to "0" (see FIG. 6).

[0051] As shown in Figure 5, the DAC output voltage V1 is smaller during the 14th bit period than during the 15th bit period. The control circuit 4 then determines the value of the 14th bit in accordance with the comparison result signal SCMP. Specifically, if the DAC output voltage V1 is higher than the comparison voltage V2, the 14th bit is determined to be "1." If the DAC output voltage V1 is lower than the comparison voltage V2, the 14th bit is determined to be "0."

[0052] Then, the control circuit 4 sets the 13th bit to "1" and sets the 12th and subsequent bits to "0" (see FIG. 6).

[0053] The control circuit 4 then changes the voltage value of the DAC output voltage V1 in accordance with the digital signal DG (the voltage value of the 13th bit in accordance with FIG. 5). Specifically, it changes the amount of charge on multiple capacitors inside the capacitive DAC 2xa (details will be described later). As shown in FIG. 5, during the 13th bit period, the DAC output voltage V1 is smaller than during the 14th bit period. The comparator 3 and the control circuit 4 then determine the value of the 13th bit in accordance with the comparison result signal SCMP. Specifically, if the DAC output voltage V1 is higher than the comparison voltage V2, the control circuit 4 determines the value of the 13th bit as "1." If the DAC output voltage V1 is lower than the comparison voltage V2, the control circuit 4 determines the value of the 13th bit as "0."

[0054] At this point, the values ​​of the most significant three bits (=13th bit to 15th bit) of the digital output signal Dout have been determined. In accordance with FIG. 6, the determined values ​​are the values ​​shown in the low-gain conversion result column. Once the values ​​of the most significant three bits have been determined, the control circuit 4 switches from low-gain DAC output operation to high-gain DAC output operation, and the high-gain output period begins. Specifically, the control circuit 4 turns on the change-over switch SW1 to make it conductive (see FIG. 4).

[0055] As described above, the DAC output voltage V1 during the low gain period has a voltage value that corresponds to the total capacitance of the capacitive DAC 2xa and the attenuation capacitor C0. On the other hand, during the high gain period, the DAC output voltage V1 has a voltage value that corresponds to the total capacitance of the capacitive DAC 2xa, the total capacitance of the capacitive DAC 2xb, and the capacitance of the attenuation capacitor C0. Therefore, the attenuation effect of the attenuation capacitor C0 on the DAC output voltage V1 is relatively smaller during the high gain period than during the low gain period.

[0056] In this state, the control circuit 4 resets the value of the 13th bit. Specifically, this is as follows: The control circuit 4 resets the 13th bit, whose value has already been determined, to "1." The comparator 3 then changes the value of the DAC output voltage V1 in accordance with the digital signal DG. The control circuit 4 determines the value of the 13th bit in accordance with the comparison result signal SCMP. More specifically, if the DAC output voltage V1 is higher than the comparison voltage V2, the control circuit 4 determines the value of the 13th bit to "1." If the DAC output voltage V1 is lower than the comparison voltage V2, the control circuit 4 determines the value of the 13th bit to "0." This determines the values ​​of the upper three bits of the digital output signal Dout during the high gain period. Note that at this timing (= the start of the high gain period), the control circuit 4 may start searching for the value of the 12th bit, as described below, without resetting the value of the 13th bit.

[0057] Next, the comparator 3 changes the value of the DAC output voltage V1 in accordance with the digital signal DG. The control circuit 4 determines the value of the 12th bit in accordance with the comparison result signal SCMP. Specifically, if the DAC output voltage V1 is higher than the comparison voltage V2, the 12th bit is determined to be "1." If the DAC output voltage V1 is lower than the comparison voltage V2, the 12th bit is determined to be "0."

[0058] Similar operations are repeated thereafter to determine the values ​​of all bits up to the least significant bit (=bit 0). In this way, the AD converter 1X determines the values ​​of a predetermined number of bits from the most significant bit of the digital output signal Dout during the low gain period, and then determines the values ​​of the remaining lower bits during the high gain period to generate the digital output signal Dout.

[0059] As described above, the attenuation effect of the attenuation capacitor C0 is relatively large during the low-gain period. Therefore, as shown in FIG. 5, during the successive approximation period of the upper three bits, which is the low-gain period, the DAC output voltage V1 is lower than the DAC output voltage VA. Furthermore, during the high-gain period, the attenuation effect of the attenuation capacitor C0 is relatively small. Therefore, even when a relatively large analog input signal IN is input, the DAC output voltage V1 is less likely to exceed the allowable range of the input voltage of the comparator 3. This makes it possible to widen the input range of the analog input signal IN.

[0060] Furthermore, the value of the DAC output voltage V1 is larger during high-gain DAC output operation than during low-gain DAC output operation. Therefore, the value of the DAC output voltage V1 can be output with higher accuracy during high-gain periods than during low-gain periods.

[0061] Furthermore, the capacitive DAC 2xa has a relatively simple configuration, without including multiple comparators or a voltage divider circuit, as in the above-described low-bit ADC 8. Therefore, the AD converter 1X of the present disclosure can suppress an increase in the circuit area.

[0062] <Details about the capacitive DAC2xa and 2xb> Next, the detailed configuration of each of the capacitive DACs 2xa and 2xb will be described. Fig. 7 is a diagram showing the detailed configuration of the capacitive DACs 2xa and 2xb. As shown in Fig. 7, each of the capacitive DACs 2xa and 2xb is connected to a wiring WR_IN, a wiring WR_VD, and a wiring WR_G. The wiring WR_IN is an analog input wiring to which an analog input signal IN is applied. Each of the capacitive DACs 2xa and DAC2xb receives the analog input signal IN via the wiring WR_IN.

[0063] A predetermined power supply voltage VD is applied to the wiring WR_VD. The power supply voltage VD is input to each of the capacitive DACs 2xa and 2xb via the wiring WR_VD.

[0064] The wiring WR_G is a ground wiring to which the ground voltage GND is applied. The wiring WR_G itself can be considered as the ground. The ground voltage GND is input to each of the capacitive DACs 2xa and 2xb via the wiring WR_G. The ground voltage GND is 0V here.

[0065] The power supply voltage VD has a positive DC voltage value (for example, 4 V). The analog input signal IN has a voltage value greater than or equal to 0 V and less than or equal to the power supply voltage VD (here, 4 V).

[0066] 7, the capacitive DAC 2xa includes a capacitor array 11 and a switch array 12. The capacitor array 11 includes an adjustment capacitor Ca and capacitors C[N+1] to C[N+A].

[0067] The switch array 12 includes an adjustment switch Sa and switches S[N+1] to S[N+A], where N is a natural number equal to or greater than 1 and can be interpreted as a number corresponding to the number of bits of the digital output signal Dout.

[0068] Furthermore, A is a natural number greater than or equal to 1 and determines the number of capacitors C[N+1] to C[N+A] included in the capacitive DAC 2xa. For example, if the number of capacitors included in the capacitive DAC 2xa is three, excluding the adjustment capacitor Ca, then A=3. In other words, in this case, the capacitor array 11 has capacitors C[N+1], C[N+2], and C[N+3]. Furthermore, A can be interpreted as a numerical value corresponding to the number of bits, of all bits of the digital output signal Dout, whose value is determined by a low-gain DAC output operation, which will be described later.

[0069] More specifically, if the digital output signal Dout is a 16-bit digital signal and the bit value of the most significant 3 bits is determined by a low-gain DAC output operation described later, then N=16 and A=3. In this case, the capacitor array 11 includes an adjustment capacitor Ca and capacitors C17 to C20. Also, in this case, the switch array 12 includes an adjustment switch Sa and switches S17 to S20.

[0070] The capacitive DAC 2xb includes a capacitor array 13 and a switch array 14. The capacitor array 13 includes a plurality of capacitors (capacitors C[1] to C[N] in accordance with FIG. 7). The switch array 14 includes a plurality of switches (switches S[1] to S[N] in accordance with FIG. 7).

[0071] For example, as described above, if the digital output signal Dout is a 16-bit digital signal, the capacitor array 13 preferably includes 16 capacitors (capacitors C1 to C16 in accordance with FIG. 7). Furthermore, in this case, the switch array 12 preferably includes 16 switches (switches S1 to S16 in accordance with FIG. 7).

[0072] Each of the capacitors C[1] to C[N+A], the adjustment capacitor Ca, and the attenuation capacitor C0 stores or releases electric charge according to the potential difference between its first end and second end.

[0073] A first terminal of each of the capacitors C[N+1] to C[N+A], the adjustment capacitor Ca, and the attenuation capacitor C0 is connected to the first wiring WR1. A second terminal of each of the capacitors C[N+1] to C[N+A] and the adjustment capacitor Ca is connected to a first terminal of each of the switches S[N+1] to S[N+A]. A second terminal of the attenuation capacitor C0 is connected to the ground voltage GND.

[0074] The first terminals of the capacitors C[1] to C[N] are connected to the second wiring WR1, and the second terminals of the capacitors C[1] to C[N] are connected to the first terminals of the switches S[1] to S[N], respectively.

[0075] As described above, the first terminal of the changeover switch SW1 is connected to the first wiring WR1. Also, as described above, the second terminal of the changeover switch SW1 is connected to the second wiring WR2. When the changeover switch SW1 is in the on state (the conductive state described above), the first terminals of the capacitors C[1] to C[N] are connected to the first wiring WR1. When the changeover switch SW1 is in the off state (the non-conductive state described above), the capacitors C1[1] to C[N] are disconnected from the first wiring WR1.

[0076] The connection switch 50 is provided in series between the application terminal of the power supply voltage VD and the first wiring WR1. The connection switch 50 is controlled to be turned on and off by the control circuit 4. When the connection switch 50 is on, the first terminal and the second terminal of the connection switch 50 are conductive. Conversely, when the connection switch 50 is off, the first terminal and the second terminal of the connection switch 50 are non-conductive.

[0077] 8 is a diagram showing the connection relationship between the capacitor C[i], the switch S[i], and the wiring WR_IN, WR_VD, and WR_G. Note that the symbol [i] here can be interpreted as being replaced with the numbers 1 to N+A. As shown in FIG. 8, the switch S[i] is connected to the common terminal T COM and switching terminals Ta, Tb, and Tc. Common terminal TCOM is connected to the second end of the capacitor C[i]. For example, the common terminal T of the switch S[1] COM is connected to the second end of the capacitor C[1] and the common terminal T of the switch S[2] COM is connected to the second end of capacitor C[2]. The same applies to switch S[3], etc. The switching terminal Ta is connected to wiring WR_IN and receives the analog input signal IN. The switching terminal Tb is connected to wiring WR_VD and receives the power supply voltage VD. The switching terminal Tc is connected to wiring WR_G and receives the ground voltage GND.

[0078] Under the control of the control circuit 4, the common terminal T of the switch S[i] COM is selectively connected to one of the switching terminals Ta, Tb, and Tc. COM may be connected to none of the switching terminals Ta, Tb, and Tc.

[0079] Referring to FIG. 8, in the following, in any switch S[i], the common terminal T COM The states in which the terminals Ta, Tb, and Tc are connected are called the signal input state, the power supply connection state, and the ground connection state, respectively. TCOM is not connected to any of the switching terminals Ta, Tb, and Tc is called the open state. In the signal input state, power supply voltage connection state, and ground voltage connection state of the switch S[i], the analog input signal IN, power supply voltage VD, and ground voltage GND are applied to the second terminal of the capacitor C[i], respectively. The adjustment switch Sa has the same configuration as the above-mentioned switch S[i] and operates in the same manner as the switch S[i].

[0080] 7, the shorting switch 70 is provided in series between the first wiring WR1 and the ground voltage GND. The shorting switch 71 is provided in series between the second wiring WR2 and the ground voltage GND. The shorting switches 70 and 71 are on / off controlled by the control circuit 4.

[0081] When the shorting switch 70 is on, the ground voltage GND is supplied to the first wiring WR1. That is, when the shorting switch 70 is on, the ground voltage GND is supplied to the first ends of the capacitors C[N+1] to C[N+A]. When the shorting switch 70 is off, the wiring between the first wiring WR1 and the ground voltage GND is cut off.

[0082] When the shorting switch 71 is on, the ground voltage GND is supplied to the second wiring WR2. That is, the ground voltage GND is supplied to the first terminals of the capacitors C[1] to C[N]. When the shorting switch 71 is off, the wiring between the first terminals of the capacitors C[1] to C[N] and the ground voltage GND is cut off.

[0083] Each of the switches S[1] to S[N+A], the adjustment switch Sa, the connection switch 50, and the shorting switches 70 and 71 can be configured with any switching element such as a MOSFET. The switches S[1] to S[N+A] and the adjustment switch Sa may be a multiplexer.

[0084] The non-inverting input terminal (+) of the comparator 3 is connected to the first wiring WR1. The inverting input terminal (-) of the comparator 3 is connected to the comparison wiring WR3. As described above, the DAC output voltage V1 is applied to the first wiring WR1. On the other hand, the comparison voltage V2 is applied to the comparison wiring WR3. The comparator 3 receives the DAC output voltage V1 and the comparison voltage V2 as inputs, and generates and outputs a comparison result signal SCMP that indicates the comparison result (high / low relationship) of the DAC output voltage V1 and the comparison voltage V2. The comparison result signal SCMP is a binary signal having a value of "0" or "1."

[0085] The control circuit 4 receives the comparison result signal SCMP as input. The control circuit 4 controls the overall AD conversion operation and outputs the digital output signal Dout obtained by the AD conversion operation. The control circuit 4 is provided with a register 31, and the value of the digital output signal Dout can be stored in the register 31. The control circuit 4 supplies a digital signal DG to the capacitive DACs 2xa and DAC2xb, thereby individually controlling the states of the switches S[1] to S[N+A] and the adjustment switch Sa.

[0086] FIG. 9 is a diagram showing the capacitance values ​​of capacitors C[1] to C[N+A], adjustment capacitor Ca, and attenuation capacitor C[0]. Note that in FIG. 9, N=16 and A=3 are shown. As shown in FIG. 9, the capacitances of capacitors C[1] to C

[13] increase in ascending order of capacitors C[1] to C

[13] . For example, for any integer i among capacitors C[1] to C

[13] , the capacitance value of capacitor C[i+1] is greater than the capacitance value of capacitor C[i].

[0087] The capacitance of capacitor C[i], which is any integer i-th capacitor of capacitors C[1] to C

[19] (or, in accordance with Figure 9, capacitors C[1] to C[N+A]), is defined as follows for capacitors C[1] to C

[13] , capacitors C

[14] to C

[16] , and capacitors C

[17] to C

[19] , respectively.

[0088] In the capacitors C[1] to C

[13] (or, in accordance with FIG. 9, the capacitors C[1] to C[N-3]), the capacitance value of the capacitor C[i] is “2 i-1 C UNT "

[0089] In the capacitors C

[14] to C

[16] (or, in accordance with FIG. 9, the capacitors C[N-2] to C[N]), the capacitance value of the capacitor C[i] is “2 i-1 C UNT -2 i-5 C UNT "

[0090] In capacitors C

[17] to C

[19] (when described in accordance with FIG. 9, capacitors C[N + 1] to C[N + A]), the capacitance value of capacitor C[i] is "2 i-5 ·C UNT ". Also, the capacitance value of the adjustment capacitor Ca is equal to the capacitance value of capacitor C

[17] (when described in accordance with FIG. 5, capacitor C[N + 1]).

[0091] In other words, the capacitance value of capacitor C[i] in capacitors C

[14] to C

[16] (when described in accordance with FIG. 9, capacitors C[N - 2] to C[N]) is obtained by subtracting the value calculated according to the same definition as the capacitance value of capacitor C[i] in capacitors C

[17] to C

[19] from the value calculated according to the same definition as the capacitance value of capacitor C[i] in capacitors C[1] to C

[13] . Therefore, when the switching switch SW1 is in the ON state, the combined capacitance value Ct1 of capacitors C[1] to C

[19] can be calculated by the following formula (1).

[0092]

Equation

[0093] Therefore, when the switching switch SW1 is in the ON state, the combined capacitance value Ct2 of capacitors C[1] to C[N + A] shown in FIG. 9 can be calculated by the following formula (2).

[0094]

Equation

[0095] <Regarding the AD conversion operation> Next, the AD conversion operation will be described with reference to the drawings. In the following AD conversion operation, similar to the embodiment shown in FIG. 8, the number of arrays of the capacitor array 11 and the switch array 12 is set to 4, and the number of arrays of the capacitor array 13 and the switch array 14 is set to 16 for explanation.

[0096] Fig. 10 is a flowchart of the AD conversion operation. As shown in Fig. 10, in the AD conversion operation, first, a sampling operation is performed (step S1). Next, a state transition operation is performed (step S2). Next, a successive approximation operation is performed (step S3). Finally, a result output operation is performed (step S4).

[0097] Each of steps S1 to S4 will be described in detail below. The period during which the sampling operation is performed (the period of step S1) will be referred to as the sampling period. The period during which the successive approximation operation is performed (the period of step S3) will be referred to as the successive approximation period. The operation from the sampling operation to the successive approximation operation will be referred to as the state transition operation. The period during which the state transition operation is performed will be referred to as the state transition period (the period of step S2).

[0098] <About the sampling period> The sampling period has a predetermined time length. During the sampling period, the control circuit 4 controls all switches S[1] to S[N+A] in the capacitive DACs 2xa and 2xb to a signal input state. At the same time, the control circuit 4 supplies the power supply voltage VD to the first wiring WR1 and the second wiring WR2. Specifically, the control circuit 4 turns off the connection switch 50, turns on the changeover switch SW1, and turns on at least one of the shorting switches 70 and 71. Alternatively, the control circuit 4 turns off the connection switch 50 and the changeover switch SW1, and turns on both of the shorting switches 70 and 71.

[0099] As a result, the first terminals of the capacitors C[1] to C[N+A] are connected to the ground voltage GND (=0V), and the second terminals are connected to the analog input signal IN. Therefore, electric charge is accumulated in the capacitors C[1] to C[N+A] and the adjustment capacitor Ca by the analog input signal IN, with the ground voltage GND (0V) as the reference.

[0100] During the sampling period, the attenuation capacitor C0 accumulates a charge according to the potential difference between the first wiring WR1 and the ground terminal GND. Therefore, it can be said that the attenuation capacitor C0 attenuates the rate of increase of the DAC output voltage V1. Note that the operation of the comparator 3 and the comparison voltage generation circuit 40 may be stopped during the sampling period. Charges according to the analog input signal IN are accumulated in each of the capacitors C[1] to C[N+A], the adjustment capacitor Ca, and the attenuation capacitor C0, and the DAC output voltage V1 is generated.

[0101] The DAC output voltage V1 is determined by the combined capacitance value of the total capacitance of the capacitive DAC 2xa (the combined capacitance value of capacitors C[N+1] to C[N+A] and the adjustment capacitor Ca) and the total capacitance of the capacitive DAC 2xb (the combined capacitance value of capacitors C[N1] to C[N]), the electrostatic capacitance value of the attenuation capacitor C0, the power supply voltage VD, and the voltage value of the analog input signal IN.

[0102] <About the state transition period> Fig. 11 is a flowchart showing an example of the flow of the state transition operation. As shown in Fig. 11, in the state transition operation (step S2), first, all of the switches S[1] to S[N+A] are switched to the open state (step S21).

[0103] Then, the first wiring WR1 is disconnected from the ground terminal GND (step S22). Specifically, the shorting switches 70 and 71 are turned off. After step S22, the shorting switches 70 and 71 are maintained in the off state until the successive approximation operation of step S3 is completed.

[0104] After step S22, the power supply voltage VD is supplied to the first wiring WR1 (step S23). Specifically, the connection switch 50 is turned on. If the changeover switch SW1 is on at this time, the changeover switch SW1 is turned off. Then, the process proceeds to the successive approximation operation (step S3). After step S23, the connection switch 50 is maintained in the on state, and the changeover switch SW1 is maintained in the off state (=non-conducting state) until the successive approximation operation of step S3 is completed.

[0105] <Regarding the successive comparison period> Fig. 12 is a flowchart showing the configuration of the successive approximation operation. As shown in Fig. 12, in the successive approximation operation, first, a low-gain DAC output operation is executed (step S31). Specifically, the control circuit 4 determines the value of the upper bits (here, the bits up to the third bit counting from the most significant bit) of the digital output signal Dout by the low-gain DAC output operation.

[0106] After step S31, a high-gain DAC output operation is executed (step S32). Specifically, the high-gain DAC output operation determines the values ​​of the lower bits of the digital output signal Dout (here, the bits from the fourth bit counting from the most significant bit to the least significant bit).

[0107] The low-gain DAC output operation is an operation that generates a DAC output voltage V1 with a relatively high attenuation rate in response to an analog input signal IN. The low-gain DAC output operation is performed during a period from the start of a successive approximation period to a predetermined timing (hereinafter referred to as a "low-gain period"). On the other hand, the high-gain DAC output operation is performed during a period after the low-gain period to the end of the successive approximation period (hereinafter referred to as a "high-gain period"). The low-gain DAC output operation and the high-gain DAC output operation will be described in more detail below.

[0108] <Low gain DAC output operation> During the low gain period, each switch included in the switch array 12 (switches S[N+1] to S[N+A] in accordance with FIG. 7) is individually set to a power supply connection state or a ground connection state.

[0109] The charge accumulated in the capacitor array 11 during the sampling period is distributed to the capacitors included in the capacitor array 11 (capacitors C[N+1] to C[N+A] in accordance with FIG. 7) and the attenuation capacitor C0 during the low gain period. The state of distribution depends on the state of each switch in the switch array 12 during the low gain period. Consequently, the voltage value of the DAC output voltage V1 changes depending on the state of the switches S[N+1] to S[N+A] during the low gain period.

[0110] Fig. 13 is a diagram showing the structure of the register 31. As shown in Fig. 13, the register 31 has a storage capacity of N bits and stores values ​​Rg[1] to Rg[N].

[0111] Each of the values ​​Rg[1] to Rg[N] is either "0" or "1." For any integer i, the value Rg[i+1] is the value of the most significant bit of the value Rg[i]. In a successive approximation operation, the values ​​Rg[1] to Rg[N] are determined bit by bit from the most significant bit. The determined value Rg[i] becomes the value of the i-th bit in the digital output signal Dout.

[0112] During the low gain period, the control circuit 4 determines the value of the A (a natural number equal to or greater than 1) bits, bit by bit, starting from the most significant bit (=value Rg[N]) toward the least significant bit. At this time, the control circuit 4 determines the value of each bit while sequentially switching the state of the switch array 12 by binary search based on the comparison result signal SCMP.

[0113] Fig. 14 is a flowchart showing an example of the flow of the low-gain DAC output operation. As shown in Fig. 14, in the low-gain period, first, the value of N+A (= the number of bits of the digital output signal Dout plus the number of bits that determine the bit value in the low-gain period) is substituted for the variable j managed by the control circuit 4 (step S311).

[0114] Next, the control circuit 4 controls the switch S[j] to a power supply connection state, and controls the switches S[j-A+1] to S[j-1] to all to a ground connection state (step S312).

[0115] Next, the control circuit 4 acquires the value of the current comparison result signal SCMP and checks whether the comparison result signal SCMP is "1" (step S313). That is, the control circuit 4 acquires the value of the comparison result signal SCMP output from the comparator 3 and determines whether the value of the comparison result signal SCMP is "1".

[0116] If the value of the comparison result signal SCMP is "1" (Yes in step S313), the control circuit 4 sets the value Rg[j] to "1" (step S314). After that, the control circuit 4 maintains the switch S[j] in a power-on state (step S315). Thereafter, the switch S[j] is maintained in a power-on state until the successive approximation operation of FIG. 7 is completed.

[0117] If the value of the comparison result signal SCMP is "0" (No in step S313), the control circuit 4 sets the value Rg[j] to "0" (step S316). Then, the control circuit 4 switches the state of the switch S[j] from the power supply connection state to the ground connection state (step S317). Thereafter, the switch S[j] is maintained in the ground connection state until the successive approximation operation is completed.

[0118] After maintaining switch S[j] in the power supply connected state in step S315, or after switching switch S[j] to the ground connected state in step S317, control circuit 4 checks whether variable j is N+1 (step S318). If variable j is not N+1 (No in step S318), 1 is subtracted from variable j (step S319), and the process returns to step S312 to repeat the processing of step S312 and subsequent steps. For example, in the second processing of step S312, switch S[N+A-1] is set to the power supply connected state, and switches S[N+1] to S[N+A-2] (not shown) are set to the ground connected state.

[0119] If the variable j is N+1 in step S318 (Yes in step S318), the low-gain DAC output operation is terminated and the process proceeds to the high-gain DAC output operation (step S32). At this stage, the values ​​Rg[N+1] to Rg[N+A] have been determined. That is, the value Rg for the most significant A bits of the digital output signal Dout has been determined.

[0120] <High-gain DAC output operation> During the high gain period, the changeover switch SW1 is in the on state (= the capacitive DAC 2xa and the capacitive DAC 2xb are in the conductive state). Therefore, the capacitance value that the AD converter 1X can sample and hold (= can hold) is larger during the high gain period than during the low gain period. During the high gain period, the switches S[1] to S[N+A] are individually set to a power supply connection state or a ground connection state.

[0121] The charge accumulated in capacitors C[1] to C[N+A], adjustment capacitor Ca, and attenuation capacitor C0 before the high gain period is distributed to capacitors C[1] to C[N+A], adjustment capacitor Ca, and attenuation capacitor C0 during the high gain period. The state of distribution depends on the state of switches S[1] to S[N+A] during the high gain period. Consequently, the voltage value of the DAC output voltage V1 during the high gain period changes depending on the state of switches S[1] to S[N+A].

[0122] As described above, the values ​​of the most significant A bits of the digital output signal Dout (=value Rg[N+1] to value Rg[N+A]) are determined at the end of the low gain period. During the high gain period, the control circuit 4 determines the bits of the digital output signal Dout after the most significant A bits one by one based on the comparison result signal SCMP.

[0123] First, the lowest value of the A-bit values ​​that have already been determined is re-determined by performing a successive comparison. The total capacitance of the capacitive DAC 2xb is greater than the total capacitance of the capacitive DAC 2xa. Therefore, the bits whose values ​​are determined by the capacitive DAC 2xb have higher accuracy than the higher bits whose values ​​are determined by the capacitive DAC 2xa. Therefore, by re-determining the lowest bit of the A-bit values ​​whose values ​​have already been determined using the capacitive DAC 2xb, the bits of the digital output signal Dout can be made more accurate.

[0124] At this time, the control circuit 4 determines the value of each bit (=values ​​Rg[1] to Rg[N+1]) by sequentially switching the states of the switches S[1] to S[N+A] by binary search.

[0125] 15 is a flowchart showing an example of the flow of the high-gain DAC output operation. As shown in FIG. 15, in the high-gain period, first, the changeover switch SW1 is turned on (step S321). Note that the changeover switch SW1 is maintained in the on state at least until the end of the high-gain period.

[0126] Next, the value of N is assigned to the variable j (step S322). As described above, in the high-gain DAC output operation, the value of the least significant bit among the already determined bits is detected again and redefined, and then the values ​​are determined bit by bit toward the less significant bits. For this reason, the control circuit 4 controls the switch S[j+1] to be in a power supply connected state and the switches S[1] to S[j] to be all in a ground connected state (step S323).

[0127] The control circuit 4 acquires the current value of the comparison result signal SCMP and checks whether the comparison result signal SCMP is "1" (step S324). That is, it acquires the value of the comparison result signal SCMP output from the comparator 3 and determines whether the value of the comparison result signal SCMP is "1". If the value of the comparison result signal SCMP is "1" (Yes in step S324), the control circuit 4 sets the value Rg[j] to "1" (step S325). Thereafter, the control circuit 4 maintains the switch S[j] in a power supply connected state (step S326). Thereafter, the switch S[j] is maintained in a power supply connected state until the successive approximation operation of FIG. 7 is completed.

[0128] If the value of the comparison result signal SCMP is "0" (No in step S324), the control circuit 4 sets the value Rg[j] to "0" (step S327). Then, the control circuit 4 switches the state of the switch S[j] from the power supply connection state to the ground connection state (step S328). Thereafter, the switch S[j] is maintained in the ground connection state until the successive approximation operation is completed.

[0129] After maintaining the switch S[j] in the power supply connected state in step S326, or after switching the switch S[j] to the ground connected state in step S326, the control circuit 4 checks whether the variable j is 1 (step S329). If the variable j is not 1 (No in step S329), the control circuit 4 subtracts 1 from the variable j (step S330), and returns to step S323 to repeat the processing of step S323 and subsequent steps.

[0130] If "j=1" in step S329 (Yes in step S329), the high-gain DAC output operation ends. At this stage, the values ​​Rg[1] to Rg[N] have been determined.

[0131] Then, in the result output operation (step S4), the control circuit 4 outputs a digital signal having the values ​​Rg[1] to Rg[N] determined in the successive approximation operation of step S3 as a digital output signal Dout (see FIG. 10). The digital output signal Dout is output to an arbitrary circuit (not shown) that uses the digital output signal Dout.

[0132] <Regarding the AD converter 1X according to the second embodiment> Next, a second embodiment of the AD converter 1X will be described. Note that, hereinafter, differences from the first embodiment will be described, and the same components as those in the first embodiment will be assigned the same reference numerals and descriptions thereof will be omitted.

[0133] Fig. 16 is a diagram showing the configuration of an AD converter 1X according to the second embodiment. As shown in Fig. 16, the AD converter 1X of this embodiment includes an offset circuit 30. The offset circuit 30 applies an offset to each capacitor of the capacitive DACs 2Xa and 2Xb (capacitors C[1] to C[N+A] in accordance with Fig. 7). Specifically, this is as follows.

[0134] The offset circuit 30 includes a capacitor C30 and switches SW31 and SW32. A first terminal of the capacitor C30 is connected to the first wiring WR1. A second terminal of the capacitor C30 is connected in parallel to a first terminal of the switch SW31 and a first terminal of the switch SW32. A second terminal of the switch SW31 is connected to the ground voltage GND. A second terminal of the switch SW32 is connected to the power supply voltage VD.

[0135] When the switch SW31 is in an on state, it connects the second end of the capacitor C30 to the ground voltage GND, and when the switch SW31 is in an off state, it disconnects the second end of the capacitor C30 from the ground voltage GND.

[0136] When the switch SW32 is in the ON state, it connects the second terminal of the capacitor C30 to the power supply voltage VD, and when the switch SW32 is in the OFF state, it disconnects the second terminal of the capacitor C30 from the power supply voltage VD.

[0137] The capacitance of capacitor C30 is 1 / 10 or more of the combined capacitance of capacitor array 11. Capacitor C30 is charged as follows. In this case, connection switch 50 and switch SW31 are turned on, and switch SW32 is turned off. At this time, power supply voltage VD is applied to the first end of capacitor C30, and ground voltage GND is applied to the second end of capacitor C30. As a result, an amount of charge corresponding to power supply voltage VD is accumulated in capacitor C30, with ground voltage GND as the reference.

[0138] The charge of capacitor C30 is distributed as follows. As described above, the voltage value of the analog input signal IN is sampled and held in capacitors C[1] to C[N+A] by the sampling operation. Then, with capacitor C30 charged as described above, the connection switch 50 and switch SW31 are turned off, and switch SW32 is turned on. Then, each of switches S[1] to S[N+A] is connected to ground.

[0139] Here, the power supply voltage VD is higher than the analog input signal IN. Therefore, the potential of the capacitor C30 is dominant (higher) than the potential of the first wiring WR1 (= the potential based on the capacitors C[1] to C[N+A]). When the changeover switch SW1 is turned on, the charge stored in the capacitor C30 moves to the capacitors of the capacitive DACs 2Xa and 2Xb (capacitors C[1] to C[N+A] in accordance with FIG. 7) and the attenuation capacitor C0.

[0140] It is also possible to transfer the charge of the capacitors of the capacitive DACs 2Xa and 2Xb (capacitors C[1] to C[N+A] in accordance with FIG. 7) to capacitor C30. In this case, when the capacitors C[1] to C[N+A] have accumulated a charge amount exceeding that of capacitor C30, the switches S[1] to S[N+A] and the adjustment switch Sa are each connected to the power supply. This causes the potential of the first wiring WR1 (= the potential based on capacitors C[1] to C[N+A]) to be dominant (higher potential) than the potential of capacitor C30. When the changeover switch SW1 is turned on, the charge stored in the capacitors of the capacitive DACs 2Xa and 2Xb (capacitors C[1] to C[N+A] in accordance with FIG. 7) is transferred to capacitor C30.

[0141] When the changeover switch SW1 is in the off state, the charge held in the capacitor C30 at this time moves to the capacitors of the capacitive DAC2Xa (in accordance with FIG. 7, capacitors C[N+1] to C[N+A] and the adjustment capacitor C[N+1]) and the attenuation capacitor C0.

[0142] <AD Converter 1X According to the Third Embodiment> Next, a third embodiment of the AD converter 1X will be described. Note that, hereinafter, differences from the first embodiment will be described, and the same components as those in the first embodiment will be assigned the same reference numerals and descriptions thereof will be omitted.

[0143] 17 is a diagram showing the configuration of an AD converter 1X according to a third embodiment. As shown in FIG. 17, the AD converter 1X of this embodiment differs from the above embodiments in the configuration of a capacitive DAC 2xa. The capacitive DAC 2xa of this embodiment will be described below.

[0144] The capacitive DAC 2xa includes a first capacitive section 15, a second capacitive section 16, and switches SW2 and SW3.

[0145] Each of the first capacitance unit 15 and the second capacitance unit 16 includes a plurality of capacitors (capacitors C17a to C19a, C17b to C19b, and adjustment capacitors Ca and Cb, which will be described later with reference to FIG. 17). The total capacitance of the capacitive DAC 2xa is the sum of the combined capacitances of the first capacitance unit 15 and the second capacitance unit 16.

[0146] The first capacitance section 15 includes a capacitor array 20 and a switch array 21. The capacitor array 20 is connected to the first wiring WR1.

[0147] The capacitor array 20 includes a plurality of capacitors (capacitors C17a to C19a and an adjustment capacitor Ca, referring to FIG. 17). The switch array 21 includes a plurality of switches (switches S17a to S19a and an adjustment switch Sb, referring to FIG. 17). The switches S17a to S19a and the adjustment switch Sa correspond to the switch S[i] described above.

[0148] The adjustment capacitors Cb and Ca are 2 8 C UNT The capacitors C17a and C17b have a capacitance of 2 9 C UNT The capacitors C18a and C18b have a capacitance of 2 10 C UNT The capacitors C19a and C19b have a capacitance of 2 11 C UNT It has a capacitance of

[0149] A first terminal of each of the capacitors C17a to C19a and the adjustment capacitor Ca is connected to the first wiring WR. A second terminal of each of the capacitors C17a to C19a is connected to a first terminal of each of the switches S17a to S19a. A second terminal of the adjustment capacitor Ca is connected to a first terminal of the adjustment switch Sa.

[0150] The second capacitance section 16 includes a third wiring WR3, a capacitor array 22, and a switch array 23. The third wiring WR3 is connected to a first terminal of a switch SW2. A second terminal of the switch SW2 is connected to the first wiring WR1. The switch SW2 is configured to be able to switch the first wiring WR1 and the third wiring WR3 between a conductive state and a non-conductive state.

[0151] The capacitor array 22 includes capacitors C17b to C19b and an adjustment capacitor Cb. The switch array 23 includes a plurality of switches (switches S17b to S19b and an adjustment switch Sb, according to FIG. 17). The switches S17b to S19b and the adjustment switch Sb correspond to the switch S[i] described above.

[0152] A first terminal of each of the capacitors C17b to C19b and the adjustment capacitor Cb is connected to the third wiring WR3. A second terminal of each of the capacitors C17b to C19b is connected to a first terminal of each of the switches S17b to S19b. A second terminal of the adjustment capacitor Cb is connected to a first terminal of the adjustment switch Sb.

[0153] A first terminal of the switch SW3 is connected to the third wiring WR3. A second terminal of the switch SW3 is connected to the application terminal of the power supply voltage VD. The switch SW3 is configured to be able to switch the application terminal of the power supply voltage VD to the third wiring WR3 between a conductive state and a non-conductive state.

[0154] The sampling operation of the AD converter 1X of this embodiment is as follows: In each capacitor of the capacitor array 20 (=capacitors C17a to C19a and adjustment capacitor Ca), a charge is accumulated (=sampled) due to the potential difference between the analog input signal IN and the ground voltage GND. On the other hand, in each capacitor of the capacitor array 22 (=capacitors C17b to C19b and adjustment capacitor Cb), a charge is accumulated (=sampled) due to the potential difference between the analog input signal IN and the power supply voltage VD. Specifically, it is as follows.

[0155] During the sampling period, the switches S17a to S19a, S17b to S19b and the adjustment switches S17a and S17b are in a signal input state. The switch SW2 is off. That is, the first wiring WR1 and the third wiring WR3 are disconnected. The switch SW3 is on. The connection switch 50 is off, and the short-circuiting switch 70 is on.

[0156] Therefore, the first wiring WR1 is at the ground potential GND, and the third wiring WR3 is at a potential equivalent to the power supply voltage VD.

[0157] Then, the ground voltage GND is supplied to the first terminal of the capacitors C17a to C19a and the adjustment capacitor Ca, and the analog input signal IN is supplied to the second terminal of the capacitors C17b to C19b and the adjustment capacitor Cb. On the other hand, the power supply voltage VD is supplied to the first terminal of the capacitors C17b to C19b and the adjustment capacitor Cb, and the analog input signal IN is supplied to the second terminal of the capacitors C17b to C19b.

[0158] During successive approximation operation, capacitors C17a and C17b form one set, capacitors C18a and C18b form one set, and capacitors C19a and C19b form one set, and a value is determined bit by bit based on the amount of charge in each set.

[0159] In this way, the voltage characteristics generated in each capacitor of the capacitor array 20 (=capacitors C17a to C19a and adjustment capacitor Ca) and the voltage characteristics generated in each capacitor of the capacitor array 22 (=capacitors C17b to C19b and adjustment capacitor Cb) have opposite polarities.

[0160] Specifically, the capacitors C17a to C19a, which are charged by the potential difference between the analog input signal IN and the ground voltage GND, and the adjustment capacitor Ca have negative voltage characteristics. Conversely, the capacitors C17b to C19b, which are charged by the potential difference between the analog input signal IN and the power supply voltage VD, and the adjustment capacitor Cb have positive voltage characteristics.

[0161] As a result, these voltage characteristics cancel each other out, reducing the likelihood of a discrepancy between the amount of charge sampled and held by the sampling operation and the analog input signal IN, ultimately enabling the DAC output voltage V1 to be generated with high precision.

[0162] <AD Converter 1X According to the Fourth Embodiment> Next, a fourth embodiment of the AD converter 1X will be described. Note that, hereinafter, differences from the first embodiment will be described, and the same components as those in the first embodiment will be assigned the same reference numerals and descriptions thereof will be omitted.

[0163] 18 is a diagram showing the configuration of an AD converter 1X according to the fourth embodiment. As shown in FIG. 18, the AD converter 1X of this embodiment differs from the above embodiments in the configuration of the capacitive DAC 2xb. The capacitive DAC 2xb of this embodiment will be described below.

[0164] The capacitive DAC 2xb includes a first capacitive section 17, a second capacitive section 18, and switches SW4 and SW5.

[0165] Each of the first capacitance section 17 and the second capacitance section 18 includes a plurality of capacitors (capacitors C1 to C16a and C13b to C16b, which will be described later with reference to FIG. 18). The total capacitance of the capacitive DAC 2xb is the sum of the combined capacitances of the first capacitance section 17 and the second capacitance section 18.

[0166] The first capacitance section 17 includes a capacitor array 24 and a switch array 25. The capacitor array 24 is connected to the second wiring WR2.

[0167] The capacitor array 24 includes a plurality of capacitors (capacitors C17a to C19a and an adjustment capacitor Ca in accordance with FIG. 18). The switch array 25 includes a plurality of switches (switches S1 to S16a in accordance with FIG. 18). The switches S13a to S16a correspond to the above-mentioned switch S[i].

[0168] The first terminals of the capacitors C1 to C16a are connected to the second wiring WR, and the second terminals of the capacitors C1 to C16a are connected to the first terminals of the switches S1 to S16a, respectively.

[0169] The second capacitance section 18 includes a fourth wiring WR3, a capacitor array 26, and a switch array 27. The fourth wiring WR4 is connected to a first terminal of a switch SW4. A second terminal of the switch SW4 is connected to the second wiring WR2. The switch SW4 is configured to be able to switch the second wiring WR2 and the fourth wiring WR4 between a conductive state and a non-conductive state.

[0170] The capacitor array 26 includes a plurality of capacitors (capacitors C13b to C16b in accordance with FIG. 18). The switch array 27 includes a plurality of switches (switches S13b to S16b in accordance with FIG. 18). The switches S13b to S16b correspond to the above-mentioned switch S[i].

[0171] The capacitors C13a and C13b are (2 12 C UNT -2 11 C UNT The capacitors C14a and C14b have a capacitance of (2 13 C UNT -2 11 C UNT ) / 2. The capacitors C15a and C15b have a capacitance of (2 14 C UNT -2 11 C UNT ) / 2. The capacitors C16 and C16b have a capacitance of (2 12 C UNT -2 11 C UNT ) / 2.

[0172] The first terminals of the capacitors C13b to C16b are connected to the fourth wiring WR4, and the second terminals of the capacitors C13b to C16b are connected to the first terminals of the switches S13b to S16b, respectively.

[0173] A first terminal of the switch SW5 is connected to the fourth wiring WR4. A second terminal of the switch SW5 is connected to the application terminal of the power supply voltage VD. The switch SW5 is configured to be able to switch the application terminal of the power supply voltage VD to the fourth wiring WR4 between a conductive state and a non-conductive state.

[0174] The sampling operation of the AD converter 1X of this embodiment is as follows: In each capacitor (=capacitors C1 to C16a) of the capacitor array 24, a charge is accumulated (=sampled) due to the potential difference between the analog input signal IN and the ground voltage GND. On the other hand, in each capacitor (=capacitors C13b to C16b) of the capacitor array 26, a charge is accumulated (=sampled) due to the potential difference between the analog input signal IN and the power supply voltage VD. Specifically, this is as follows.

[0175] During the sampling period, the switches S1 to S16a and S13b to S16b are in a signal input state. The switch SW4 is turned off. That is, the second wiring WR2 and the fourth wiring WR4 are disconnected. The switch SW5 is turned on. The changeover switch SW1 is turned off. The short-circuiting switch 71 is turned on.

[0176] Therefore, the second wiring WR2 is at the ground potential GND, and the fourth wiring WR4 is at a potential equivalent to the power supply voltage VD.

[0177] Then, the ground voltage GND is supplied to the first terminal of the capacitors C1 to C16a, and the analog input signal IN is supplied to the second terminal of the capacitors C13b to C16b. On the other hand, the power supply voltage VD is supplied to the first terminal of the capacitors C13b to C16b, and the analog input signal IN is supplied to the second terminal of the capacitors C13b to C16b.

[0178] During successive approximation operation, capacitors C13a and C13b form one pair, capacitors C14a and C14b form one pair, capacitors C15a and C15b form one pair, and capacitors C16a and C16b form one pair, and a value is determined for each bit based on the charge amount of each pair. Capacitors C1 to C12 are the same as in the first embodiment.

[0179] In this way, the voltage characteristics generated in each capacitor of the capacitor array 24 (=capacitors C13a to C16a) and the voltage characteristics generated in each capacitor of the capacitor array 26 (=capacitors C13b to C16b) have opposite polarities.

[0180] Specifically, the capacitors C1 to C16a charged by the potential difference between the analog input signal IN and the ground voltage GND have negative voltage characteristics, while the capacitors C13b to C16b charged by the potential difference between the analog input signal IN and the power supply voltage VD have positive voltage characteristics.

[0181] As a result, these voltage characteristics cancel each other out, reducing the likelihood of a discrepancy between the amount of charge sampled and held by the sampling operation and the analog input signal IN, ultimately enabling the DAC output voltage V1 to be generated with high precision.

[0182] The capacitive DAC 2xa of this embodiment may be equivalent to the capacitive DAC 2xa according to the third embodiment.

[0183] <Modification> The present disclosure is not limited to the above-described embodiments, and various modifications are possible without departing from the spirit of the present disclosure. For example, in the above-described embodiments, the wiring WR_G is the ground wiring, but this is not limited to this. Alternatively, for example, the wiring can be a wiring to which a voltage lower than the power supply voltage VD is applied. However, by using the wiring WR_G as the ground wiring, it is not necessary to separately prepare a power supply circuit for generating the voltage applied to the wiring WR_G. Therefore, using the wiring WR_G as the ground wiring can simplify the circuit.

[0184] Furthermore, although it has been described that the connecting switch 50 is maintained in the ON state and the shorting switches 70 and 71 are maintained in the OFF state during the successive approximation period, this is not limitative. For example, during the successive approximation period, the shorting switches 70 and 71 can be maintained in the ON state, and the switches [1] to [N+A] that correspond to the bits to be compared can be connected to ground. In this case, the switches [1] to [N+A] that correspond to bits other than those to be compared can be connected to the power supply. Specifically, this is as follows.

[0185] As described above, during the successive approximation period, the shorting switches 70 and 71 are maintained in the off state. When, for example, capacitor C19 (see FIG. 9) is used as the comparison target, switch S19 is set to the ground connection state, and switches S1 to S18 are set to the power supply connection state. Similarly, when, for example, capacitor C5 is used as the comparison target, switch S5 is set to the ground connection state, and switches S1 to S4 and S6 to S19 are set to the power supply connection state.

[0186] As described above, in the third embodiment, the number of capacitors included in the capacitor array 22 is four. Specifically, these are capacitors C17b to C19b and the adjustment capacitor Cb. However, the number of capacitors included in the capacitor array 22 is not limited to this and may be, for example, three or less, or five or more. The same applies to the capacitors included in the capacitor array 20. In this case, it is preferable to configure the number of capacitors in the capacitor array 20 to be the same as the number of capacitors in the capacitor array 22.

[0187] As described above, the third embodiment is configured to include two divided capacitance sections, the first capacitance section 15 and the second capacitance section 16, but is not limited to this. For example, it may be configured to include three or more divided capacitance sections, such as one first capacitance section 15 and multiple second capacitance sections 16. In this case, a switch (corresponding to switch SW2) that can be switched between a conductive state and a non-conductive state is disposed between each second capacitance section 16 and the first wiring WR1.

[0188] As described above, in the fourth embodiment, the number of capacitors included in the capacitor array 26 is four. Specifically, these are capacitors C13b to C16b. However, the number of capacitors included in the capacitor array 26 is not limited to this, and may be, for example, four or less, or five or more.

[0189] As described above, the fourth embodiment is configured to include two divided capacitance sections, the first capacitance section 17 and the second capacitance section 18, but is not limited to this. For example, it is possible to configure to include three or more divided capacitance sections, such as one first capacitance section 17 and multiple second capacitance sections 18. In this case, a switch (corresponding to switch SW4) that can be switched between a conductive state and a non-conductive state is arranged between each second capacitance section 17 and the second wiring WR2.

[0190] <Additional Notes> The AD converter (1X) described in the specification includes a first capacitive DAC (2Xa) configured to receive an analog input signal (IN), a second capacitive DAC (2Xb) that receives the analog input signal (IN) and is configured to have a larger capacitance than the first capacitive DAC (2Xa), a changeover switch (SW1) configured to be able to switch the first capacitive DAC (2Xa) and the second capacitive DAC (2Xb) between a conductive and non-conductive state, a comparator (3) configured to receive only the output of the first capacitive DAC (2Xa) of the first capacitive DAC (2Xa) and the second capacitive DAC (2Xb) when in the non-conductive state and to receive the outputs of the first capacitive DAC (2Xa) and the second capacitive DAC (2Xb) when in the conductive state, and a control circuit (4) configured to control the first capacitive DAC (2Xa) and the second capacitive DAC (2Xb) based on the output of the comparator (3) (first configuration).

[0191] The AD converter (1X) according to the first configuration includes a first wiring (WR1) configured to connect a first capacitive DAC (2Xa) and a first end of a changeover switch (SW1), and a second wiring (WR2) to connect a second capacitive DAC (2Xb) and a second end of the changeover switch (SW1), and the changeover switch (SW1) is configured to switch between a conductive state and a non-conductive state by switching between an electrically connected state and an electrically disconnected state between its own first end and its own second end, and the first capacitive DAC (2Xa) is configured to connect a first capacitor (CN+1 to CN+2) and a second capacitor (CN+3) to a second capacitor (CN+4) and a second capacitor (CN+5) connected to the first capacitor (CN+6). a first switch array (12) configured to switch and connect at least some of the first capacitors (CN+1 to CN+A, C17a to C19a) to any one of a first reference voltage (GND), an analog input signal (IN), and a second reference voltage (VD) higher than the first reference voltage (GND); a second capacitive DAC (2Xb) includes a second capacitor array (14, 24) configured to include a plurality of second capacitors (1 to N, C13a to C16a); and a second switch array (14, 25) configured to switch and connect at least some of the second capacitors (1 to N, C13a to C16a) to any one of a first reference voltage (GND), an analog input signal (IN), and a second reference voltage (VD), wherein each of the first capacitors (CN+1 to CN+A, C17a to C19a) has a first end connected to a first wiring (WR1) and a second end connected to the first switch array (12), and each of the second capacitors (1 to N, C13a to C16a) has a first end connected to a second wiring (WR2) and a second end connected to the second wiring (WR3). The control circuit (4) is connected to the switch array (14, 25), and controls the first switch array (12) to connect at least a part of each of the first capacitors (CN+1 to CN+A, C17a to C19a) to an analog input signal (IN), thereby charging at least a part of each of the first capacitors (CN+1 to CN+A, C17a to C19a) in accordance with the analog input signal (IN), and controls the second switch array (14, 25) to connect at least a part of each of the second capacitors (1 to N, C13a to C16a) to the analog input signal (IN), thereby charging at least a part of each of the second capacitors (1 to N, C13a to C16a) in accordance with the analog input signal (IN).At least some of the capacitors C13a to C16a are charged in response to an analog input signal (IN) (second configuration).

[0192] In the AD converter (1X) according to the second configuration, the control circuit (4) supplies an analog input signal (IN) to a first capacitor array (11, 20) via a first switch array (12) in a non-conductive state, and supplies the analog input signal (IN) to a second capacitor array (14, 24) via a second switch array (14, 25), thereby accumulating charges corresponding to the analog input signal (IN) in at least a portion of each of the first capacitors (CN+1 to CN+A, C17a to C19a) and at least a portion of each of the second capacitors (1 to N, C13a to C16a), and accumulates charges corresponding to the analog input signal (IN) in at least a portion of each of the first capacitors (CN+1 to CN+A, C17a to C19a) and in at least a portion of each of the second capacitors (1 to N, C13a to C16a), and accumulates charges corresponding to the analog input signal (IN) in at least a portion of each of the first capacitors (CN+1 to CN+A, C13a to C16a) in a state in which a first reference voltage (GND) or a second reference voltage (VD) is supplied to each of the first capacitors (CN+1 to CN+A, C17a to C19a) via the switch array. The control circuit (4), in a conductive state, supplies a first reference voltage (GND) or a second reference voltage (VD) to each of the first capacitors (CN+1 to CN+A, C17a to C19a) via the first switch array (12) and supplies the first reference voltage (GND) or the second reference voltage (VD) to each of the second capacitors (1 to N, C13a to C16a) via the second switch array (14, 25), and generates a DAC output voltage (V1) on the first wiring (WR1) and the second wiring (WR2) that corresponds to the charge accumulated in each of the first capacitors (CN+1 to CN+A, C17a to C19a) and each of the second capacitors (1 to N, C13a to C16a) (third configuration).

[0193] The AD converter (1X) according to the third configuration includes an offset capacitor (C30) having a first end connected to a first wiring (WR1) or a second wiring (WR2) and having a capacitance value smaller than the combined capacitance value of the first capacitor array (11, 20); a first connection switch (SW31) having a first end connected to a second end of the offset capacitor (C30) and a second end connected to an application terminal of a first reference voltage (GND) and configured to switch between an electrically connected state and an electrically disconnected state between its first end and its second end; a second connection switch (SW32) connected to a second terminal of the offset capacitor (C30), having its second terminal connected to an application terminal of a second reference voltage (VD), and configured to switch its first terminal and its second terminal to either an electrically connected state or an electrically disconnected state, and a control circuit (4) controls on and off of the first connection switch (SW31) and the second connection switch (SW32) to charge the offset capacitor (C30) or to connect the offset capacitor (C30) to each of the first capacitors (CN+1 to CN+A, C17a to C19a). When charging the offset capacitor (C30), the control circuit (4) turns on the first connection switch (SW31) and turns off the second connection switch (SW32) while supplying a second reference voltage (VD) to a first end of the offset capacitor (C30) via the first wiring (WR1) or the second wiring (WR2), or turns off the first connection switch (SW31) and turns off the second connection switch (SW32) while supplying a first reference voltage (GND) to the first end of the offset capacitor (C30) via the first wiring (WR1) or the second wiring (WR2). When the first connection switch (SW31) is turned off and the second connection switch (SW32) is turned on to distribute the charge of the offset capacitor (C30) to each of the first capacitors (CN+1 to CN+A, C17a to C19a), the offset capacitor (C30) is charged, and when the first connection switch (SW31) is turned off and the second connection switch (SW32) is turned on, the charge of each of the first capacitors (CN+1 to CN+A, C17a to C19a) is moved to the offset capacitor (C30), the first connection switch (SW31) is turned on and the second connection switch (SW32) is turned off (fourth configuration).

[0194] In the AD converter (1X) according to the second configuration, the first capacitive DAC (2Xa) includes a first capacitance section (15), a second capacitance section (16), a third connection switch (70), and a fourth connection switch (SW2), the first capacitance section (15) includes a first capacitor array (11, 20) and a first switch array (12), and the second capacitance section (16) includes a third capacitor array (22) configured to include a plurality of third capacitors (C17b to C19b), and a first reference voltage (GND), an analog input signal (A1), and a second reference voltage (GND). a third switch array (23) configured to switch between and connect either a first reference voltage (IN) or a second reference voltage (VD); third wiring (WR3) connected to first ends of the third capacitors (C17b to C19b); and a fifth connection switch (SW3) having a first end connected to the third wiring (WR3) and a second end connected to an application end of one of the first reference voltage (GND) and the second reference voltage (VD), and configured to electrically connect or disconnect its first end and its second end to supply or cut off the second reference voltage (VD) to the third wiring (WR3), The connection switch (70) has a first end connected to the first wiring (WR1) and a second end connected to the other application end of the first reference voltage (GND) and the second reference voltage (VD), and is configured to electrically connect or disconnect its first end and its second end to supply or cut off the first reference voltage (GND) to the first wiring (WR1), and the fourth connection switch (SW2) has a first end connected to the third wiring (WR3) and a second end connected to the first wiring (WR1), and is configured to electrically connect or disconnect its first end and its second end to supply or cut off the first reference voltage (GND) to the first wiring (WR1). The control circuit (4) is configured to be switchable between an electrically connected state and an electrically disconnected state, and when the first wiring (WR1) and the third wiring (WR3) are disconnected, the control circuit (4) supplies the other of the first reference voltage (GND) and the second reference voltage (VD) to the first wiring (WR1), charges each of the first capacitors (CN+1 to CN+A, C17a to C19a) using a potential difference between the other of the first reference voltage (GND) and the second reference voltage (VD) and the analog input signal (IN), and supplies one of the first reference voltage and the second reference voltage (VD) to the third wiring (WR3);The third capacitors (C17b to C19b) are charged by the potential difference between one of the first reference voltage and the second reference voltage (VD) and the analog input signal (IN) (fifth configuration).

[0195] In the AD converter (1X) according to any one of the second to fifth configurations, the second capacitive DAC (2Xb) includes a third capacitance section (17), a fourth capacitance section (18), a sixth connection switch (71), and a seventh connection switch (SW4), the third capacitance section (17) includes a second capacitor array (14, 24) and a second switch array (14, 25), and the fourth capacitance section (18) includes a fourth capacitor array 26 configured to include a plurality of fourth capacitors (C14b to C16b), and a fourth wiring (W) connected to a first end of each of the fourth capacitors (C14b to C16b). an eighth connection switch (SW5) having a first end connected to the fourth wiring (WR4) and a second end connected to an application terminal of one of the first reference voltage (GND) and the second reference voltage (VD), and configured to electrically connect or disconnect its first end and its second end to supply or cut off the second reference voltage (VD) to the fourth wiring (WR4); and an eighth connection switch (SW5) configured to switch and connect each of the fourth capacitors (C14b to C16b) to either the other of the first reference voltage (GND) and the second reference voltage (VD), the analog input signal (IN), or the second reference voltage (VD). the sixth connection switch (71) has a first end connected to the second wiring (WR2) and a second end connected to an application terminal of a first reference voltage (GND), and is configured to supply or cut off the first reference voltage (GND) to the second wiring (WR2) by electrically connecting or disconnecting its first end and its second end; the seventh connection switch (SW4) has a first end connected to the fourth wiring (WR4) and a second end connected to the second wiring (WR2), and is configured to supply or cut off the first reference voltage (GND) to the second wiring (WR2). The control circuit (4) is configured to be able to switch between an electrically connected state and a disconnected state with the wiring (WR4), and when the second wiring (WR2) and the fourth wiring (WR4) are disconnected, the control circuit (4) supplies the other of the first reference voltage (GND) and the second reference voltage (VD) to the second wiring (WR2), charges each of the second capacitors (1 to N, C13a to C16a) using a potential difference between the other of the first reference voltage (GND) and the second reference voltage (VD) and the analog input signal (IN), and supplies one of the first reference voltage (GND) and the second reference voltage (VD) to the fourth wiring (WR4);The fourth capacitors (C14b to C16b) are charged by the potential difference between one of the first reference voltage (GND) and the second reference voltage (VD) and the analog input signal (IN) (sixth configuration). [Explanation of symbols]

[0196] 1x AD converter 1Y AD converter 3. Comparator 4 Control Circuit 11 Capacitor array (first capacitor array) 12 Switch array (first switch array) 13 Capacitor array (second capacitor array) 14 Switch array (second switch array) 15 1st capacity section 16 2nd capacity section 20 Capacitor array (first capacitor array) 21 Switch array (first switch array) 22 Capacitor Array (Third Capacitor Array) 23 Switch Array (Third Switch Array) 24 Capacitor array (second capacitor array) 25 Switch array (second switch array) 26 Capacitor Array (4th Capacitor Array) 27 Switch Array (4th Switch Array) 30 Offset circuit 31 registers 40 Comparison voltage generation circuit 50 Connection switch 70 Short-circuit switch (third connection switch) 71 Short-circuit switch (6th connection switch) 81 Comparator 82 decoder C0 damping capacitor Ca~Cc adjustment capacitor CN+1 to CN+A capacitors (first capacitor) C17a to C19a capacitors (first capacitors) C1~CN capacitors (second capacitors) C13a to C16a Capacitors (second capacitors) C30 capacitor (offset capacitor) 2Xa capacitive DAC (first capacitive DAC) 2Xb capacitive DAC (second capacitive DAC) DG Digital signal Dout Digital output signal GND Ground voltage (first reference voltage) IN Analog input signal S1~N+A Switch SW1 changeover switch SW2 switch (fourth connection switch) SW3 switch (5th connection switch) SW4 switch (7th connection switch) SW5 switch (8th connection switch) SW31 Switch (first connection switch) SW32 switch (second connection switch) SCMP comparison result signal Sa~Sc adjustment switch T COM Common Terminal Ta, Tb, Tc switching terminal V1 DAC output voltage V2 Comparison voltage VD Power supply voltage (second reference voltage) WR1 First wiring WR2 Second wiring WR3 3rd wiring WR4 4th wiring WRc comparison wiring

Claims

1. a first capacitive DAC configured to receive an analog input signal; a second capacitive DAC that receives the analog input signal and has a capacitance greater than that of the first capacitive DAC; a changeover switch configured to be able to switch the first capacitive DAC and the second capacitive DAC between a conductive state and a non-conductive state; a comparator configured to receive, in the non-conductive state, an output of only the first capacitive DAC out of the first capacitive DAC and the second capacitive DAC, and to receive, in the conductive state, the outputs of the first capacitive DAC and the second capacitive DAC; a control circuit configured to control the first capacitive DAC and the second capacitive DAC based on an output of the comparator; An AD converter comprising:

2. a first wiring configured to connect the first capacitive DAC and a first end of the changeover switch; a second wiring connecting the second capacitive DAC and a second terminal of the changeover switch; Equipped with the changeover switch is configured to switch between a conductive state and a non-conductive state by switching between an electrically connected state and an electrically disconnected state between a first end of the changeover switch and a second end of the changeover switch; The first capacitive DAC comprises: a first capacitor array configured to include a plurality of first capacitors; a first switch array configured to switchably connect at least some of the first capacitors to one of a first reference voltage, the analog input signal, and a second reference voltage higher than the first reference voltage; Equipped with The second capacitive DAC comprises: a second capacitor array configured to include a plurality of second capacitors; a second switch array configured to switchably connect at least a portion of each of the second capacitors to one of the first reference voltage, the analog input signal, and the second reference voltage; Equipped with Each of the first capacitors has a first end connected to the first wiring and a second end connected to the first switch array; Each of the second capacitors has a first end connected to the second wiring and a second end connected to the second switch array, The control circuit controlling the first switch array to connect at least a portion of each of the first capacitors to the analog input signal, thereby charging at least a portion of each of the first capacitors in response to the analog input signal; 2. The AD converter according to claim 1, wherein the second switch array is controlled to connect at least a portion of each of the second capacitors to the analog input signal, and at least a portion of each of the second capacitors is charged in response to the analog input signal.

3. In the non-conducting state, the control circuit supplying the analog input signal to the first capacitor array via the first switch array and supplying the analog input signal to the second capacitor array via the second switch array, thereby storing charges corresponding to the analog input signal in at least a portion of each of the first capacitors and at least a portion of each of the second capacitors; generating a DAC output voltage on a first wiring according to an amount of charge stored in each of the first capacitors while supplying the first reference voltage or the second reference voltage to each of the first capacitors via the one switch array; In the conductive state, the control circuit 3. The AD converter according to claim 2, wherein the DAC output voltage corresponding to the charge stored in each of the first capacitors and each of the second capacitors is generated on the first wiring and the second wiring while the first reference voltage or the second reference voltage is supplied to each of the first capacitors via the first switch array and while the first reference voltage or the second reference voltage is supplied to each of the second capacitors via the second switch array.

4. an offset capacitor having a first end connected to the first wiring or the second wiring and having a capacitance value smaller than a combined capacitance value of the first capacitor array; a first connection switch having a first end connected to the second end of the offset capacitor and a second end connected to the application terminal of the first reference voltage, and configured to switch between an electrically connected state and an electrically disconnected state between its first end and its second end; a second connection switch having a first end connected to the second end of the offset capacitor and a second end connected to the application terminal of the second reference voltage, and configured to switch between an electrically connected state and an electrically disconnected state between its first end and its second end; Equipped with the control circuit is capable of charging the offset capacitor or transferring charge between the offset capacitor and each of the first capacitors by controlling on and off of the first connection switch and the second connection switch, The control circuit When charging the offset capacitor, turning on the first connection switch and turning off the second connection switch while the second reference voltage is being supplied to a first end of the offset capacitor via the first wiring or the second wiring; or turning off the first connection switch and the second connection switch in a state where the first reference voltage is supplied to the first end of the offset capacitor via the first wiring or the second wiring; When distributing the charge of the offset capacitor to each of the first capacitors, turning off the first connection switch and turning on the second connection switch in a charged state of the offset capacitor; When transferring charge from each of the first capacitors to the offset capacitor, 4. The AD converter according to claim 3, wherein the first connection switch is turned on and the second connection switch is turned off.

5. the first capacitive DAC includes a first capacitance unit, a second capacitance unit, a third connection switch, and a fourth connection switch; The first capacitance section is the first capacitor array; the first switch array; Equipped with The second capacitance section is a third capacitor array configured to include a plurality of third capacitors; a third switch array configured to switchably connect each of the third capacitors to one of the first reference voltage, the analog input signal, and the second reference voltage; a third wiring connected to a first end of each of the third capacitors; a fifth connection switch having a first end connected to the third wiring and a second end connected to an application terminal for one of the first reference voltage and the second reference voltage, and configured to electrically connect or disconnect its first end and its second end to supply or cut off the second reference voltage to the third wiring; Equipped with the third connection switch has a first end connected to the first wiring and a second end connected to the other application end of the first reference voltage and the second reference voltage, and is configured to electrically connect or disconnect its first end and its second end to supply or cut off the first reference voltage to the first wiring; the fourth connection switch has a first end connected to the third wiring and a second end connected to the first wiring, and is configured to be able to electrically connect or disconnect its first end and its second end to switch between an electrically connected state and an electrically disconnected state between the first wiring and the third wiring, The control circuit, in a state where the first wiring and the third wiring are disconnected, supplying the other of the first reference voltage and the second reference voltage to the first wiring, and charging each of the first capacitors with a potential difference between the other of the first reference voltage and the second reference voltage and the analog input signal; 3. The AD converter according to claim 2, wherein one of the first reference voltage and the second reference voltage is supplied to the third wiring, and each of the third capacitors is charged by a potential difference between the analog input signal and one of the first reference voltage and the second reference voltage.

6. the second capacitive DAC includes a third capacitive unit, a fourth capacitive unit, a sixth connection switch, and a seventh connection switch; The third capacitance section is the second capacitor array; the second switch array; Equipped with The fourth capacitance section is a fourth capacitor array configured to include a plurality of fourth capacitors; a fourth wiring connected to a first end of each of the fourth capacitors; an eighth connection switch having a first end connected to the fourth wiring and a second end connected to an application terminal for one of the first reference voltage and the second reference voltage, and configured to electrically connect or disconnect its first end and its second end to supply or cut off the second reference voltage to the fourth wiring; a fourth switch array configured to switchably connect each of the fourth capacitors to the other of the first reference voltage and the second reference voltage, the analog input signal, or the second reference voltage; Equipped with the sixth connection switch has a first end connected to the second wiring and a second end connected to an application terminal of the first reference voltage, and is configured to electrically connect or disconnect its first end and its second end to supply or cut off the first reference voltage to the second wiring; the seventh connection switch has a first end connected to the fourth wiring and a second end connected to the second wiring, and is configured to electrically connect or disconnect its first end and its second end, thereby switching the second wiring and the fourth wiring to an electrically connected or disconnected state; The control circuit, in a state where the second wiring and the fourth wiring are disconnected, supplying the other of the first reference voltage and the second reference voltage to the second wiring, and charging each of the second capacitors with a potential difference between the other of the first reference voltage and the second reference voltage and the analog input signal; 6. An AD converter according to claim 2, wherein one of the first reference voltage and the second reference voltage is supplied to the fourth wiring, and each of the fourth capacitors is charged by a potential difference between one of the first reference voltage and the second reference voltage and the analog input signal.

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