Logic output circuit, semiconductor device

Abstract

A drive current independent of the power supply voltage is generated in a logic output circuit. [Solution] A logic output circuit (1) includes a first output circuit (10) configured to switch the direction of a first drive current (I10) output to an output node (50) based on a digital input signal (DI) so that the first drive current (I10) decreases in response to a decrease in the applied power supply voltage (Vcc), a second output circuit (20) configured to switch the direction of a second drive current (I20) output to the output node (50) based on the digital input signal (DI) and adjust the second drive current (I20) using constant current sources (23, 24), and a correction circuit (40) configured to adjust the current value of the constant current generated by the constant current sources (23, 24) in response to the power supply voltage (Vcc).

Description

[Technical Field]

[0001] The present disclosure relates to a logic output circuit and a semiconductor device. [Background technology]

[0002] 2. Description of the Related Art Conventionally, semiconductor devices including logic output circuits that generate digital output signals have been installed in a variety of applications.

[0003] Prior art related to the above includes Patent Documents 1 and 2. [Prior art documents] [Patent documents]

[0004] [Patent Document 1] Japanese Patent Application Publication No. 6-132807 [Patent Document 2] Japanese Patent Application Laid-Open No. 2002-314394

[0005] [overview] However, the drive current of the logic output circuit has power supply voltage characteristics, and there is room for improvement in adjusting this.

[0006] The logic output circuit according to the present disclosure comprises a first output circuit configured to switch the direction of a first drive current output to an output node based on a digital input signal, so that the first drive current decreases in response to a decrease in an applied power supply voltage; a second output circuit configured to switch the direction of a second drive current output to the output node based on the digital input signal, so that the second drive current is adjusted by a constant current source; and a correction circuit configured to adjust the current value of the constant current generated by the constant current source in response to the power supply voltage. [Brief explanation of the drawings]

[0007] [Figure 1] FIG. 1 is a diagram illustrating a first comparative example of a logic output circuit. [Figure 2] FIG. 2 is a diagram showing the power supply voltage characteristics of the drive current in the first comparative example. [Figure 3] FIG. 3 is a diagram illustrating a second comparative example of a logic output circuit. [Figure 4] FIG. 4 is a diagram showing the power supply voltage characteristics of the drive current in the second comparative example. [Figure 5] FIG. 5 is a diagram illustrating a third comparative example of a logic output circuit. [Figure 6] FIG. 6 is a diagram showing the power supply voltage characteristics of the drive current in the third comparative example. [Figure 7] FIG. 7 is a diagram showing an embodiment of a logic output circuit. [Figure 8] FIG. 8 is a diagram showing the power supply voltage characteristics of the drive current in the example. [Figure 9] FIG. 9 is a diagram showing a list of MOS sizes in the first to third comparative examples and the example. [Figure 10] FIG. 10 shows in detail the correction circuit according to FIG. [Figure 11] FIG. 11 is a diagram showing a semiconductor device equipped with a logic output circuit.

[0008] [Detailed explanation] Hereinafter, exemplary embodiments of the present disclosure will be described with reference to the drawings. Before describing the embodiments of the present disclosure, a comparative example will be described for comparison. By describing the comparative example, the problems will become more apparent.

[0009] <First Comparative Example> 1 is a diagram showing a first comparative example of a logic output circuit. A logic output circuit 100a of the first comparative example includes a transistor 101, a transistor 102, and an output node 103. The transistor 101 may be, for example, a PMOS (positive-channel metal oxide semiconductor). The transistor 102 may be, for example, an NMOS (negative-channel MOS).

[0010] The transistor 101 is configured to source a drive current I from the application terminal of the power supply voltage Vcc toward an output node 103. The transistor 102 is configured to sink the drive current I from the output node 103 toward the ground terminal GND. The transistors 101 and 102 are configured as a general inverter that switches the logic level (high level or low level, the same applies below) of the digital output signal DO by switching between sourcing and sinking the drive current I in accordance with the digital input signal DI.

[0011] The output node 103 is a terminal that outputs the drive current I. Note that the output node 103 may be, for example, a digital output node to which an external load capacitance is connected.

[0012] FIG. 2 is a diagram showing the power supply voltage characteristics of drive current I in the first comparative example. As shown in this figure, logic output circuit 100a has a power supply voltage characteristic of drive current I such that drive current I increases as power supply voltage Vcc increases, and conversely, drive current I decreases as power supply voltage Vcc decreases. IL represents the required drive current required for logic output circuit 100a. As shown in FIG. 2, in logic output circuit 100a of the first comparative example, when power supply voltage Vcc is lower than threshold voltage Vth, i.e., in a so-called reduced power state, drive current I falls below required drive current IL.

[0013] In an integrated circuit with an analog circuit that shares a common power supply and ground with the logic output circuit, the current used to drive the external load capacitance connected to the digital output node (the aforementioned drive current I) can fluctuate the power supply or ground of the integrated circuit, degrading the characteristics of the analog circuit. For example, if the integrated circuit is an ADC (analog-to-digital converter), the characteristics of the AD conversion circuit located upstream of the logic output circuit can be degraded. Furthermore, if the integrated circuit is a digital isolator, the characteristics of the analog receiving circuit located in the same power and ground system (e.g., the receiving side) as the logic output circuit can be degraded.

[0014] The degree of characteristic degradation can be reduced by reducing the drive current I of the logic output circuit 100a. However, simply reducing the drive current I of the logic output circuit 100a has the disadvantage of reducing the maximum operating frequency of the digital output signal DO. Therefore, the drive current I of the logic output circuit 100a can only be reduced to the required drive current IL corresponding to the maximum operating frequency required for the digital output signal DO.

[0015] In the configuration of the first comparative example, the drive current I varies depending on the power supply voltage Vcc, decreasing as the power supply voltage Vcc decreases. Therefore, if the drive is enabled to operate at the highest operating frequency when the power supply voltage is at its lowest (undervoltage), the performance will be too high when the power supply voltage is at its highest (overvoltage), resulting in a problem of significant impact on the analog input circuit.

[0016] <Second Comparative Example> 3 is a diagram showing a second comparative example of a logic output circuit. A logic output circuit 100b of the second comparative example includes, in addition to the components of the first comparative example (FIG. 1), a transistor 104, a transistor 105, an inverter 106, an inverter 107, a NAND gate 108, and a NOR gate 109.

[0017] The transistor 104 may be, for example, a PMOS, and the transistor 105 may be, for example, an NMOS.

[0018] The transistors 101 and 102 switch between the source and sink of the drive current I1 in response to the signal S1.

[0019] The gate of the transistor 104 is connected to the output terminal of the NAND gate 108. The transistor 104 switches whether or not to source the drive current I2 to the output node 103 in response to the output signal S3 of the NAND gate 108.

[0020] The gate of the transistor 105 is connected to the output terminal of the NOR gate 109. The transistor 105 switches whether or not to sink the drive current I2 from the output node 103 in accordance with the output signal S4 of the NOR gate 109.

[0021] The inverter 106 generates the signal S1 by inverting the logic level of the digital input signal DI.

[0022] The inverter 107 generates the signal S2 by inverting the logic level of the signal OE. The signal OE is at a high level when the power supply voltage Vcc is lower than the threshold voltage Vth. The signal OE is at a low level when the power supply voltage Vcc is higher than the threshold voltage Vth.

[0023] The NAND gate 108 outputs a NAND signal of the signal OE and the digital input signal DI as a signal S3.

[0024] The OR gate 109 outputs the logical sum signal of the signal S2 and the digital input signal DI as a signal S4.

[0025] The driving current I flowing through the output node 103 is a composite current (combined current) of the driving current I1 and the driving current I2.

[0026] According to the configuration of the second comparative example, when the digital input signal DI is at a high level, the transistor 101 is turned on and the transistor 102 is turned off. Therefore, the drive current I1 is sourced from the application terminal of the power supply voltage Vcc to the output node 103 via the transistor 101. On the other hand, when the digital input signal DI is at a low level, the transistor 101 is turned off and the transistor 102 is turned on. Therefore, the drive current I1 is sunk from the output node 103 to the ground terminal GND via the transistor 102.

[0027] Here, when the signal OE is at a high level (Vcc≦Vth), S3=S4=S1 holds. That is, the transistors 104 and 105 are turned on / off in response to the digital input signal DI, just like the transistors 101 and 102. Therefore, I=I1+I2 holds whether the transistors are sourcing or sinking.

[0028] On the other hand, when the signal OE is at a low level (Vcc>Vth), S3 is fixed at H and S4 is fixed at L regardless of the digital input signal DI. That is, the transistors 104 and 105 are turned off regardless of the digital input signal DI. Therefore, I=I1 both when sourcing and when sinking.

[0029] 4 is a diagram showing the power supply voltage characteristics of the drive current I in the second comparative example. Note that the dashed line in this figure shows the power supply voltage characteristics of the drive current I in the first comparative example for comparison. As can be seen from this figure, in the second comparative example, the introduction of the drive current I2 prevents the drive current I from falling below the required drive current IL even during reduced power.

[0030] Therefore, in the second comparative example, even during reduced power, the logic output circuit 100b can be driven with a drive current equal to or greater than the required drive current IL corresponding to the maximum operating frequency of the digital output signal DO. Therefore, there is no need to unnecessarily increase the drive current I1 in consideration of reduced power. Furthermore, during overvoltage, the drive current I2 does not flow. Therefore, it is possible to suppress the impact on the analog input circuit caused by unnecessarily increasing the drive current I.

[0031] However, in the configuration of the second comparative example, when the power supply voltage Vcc fluctuates near the threshold voltage Vth, the drive current I changes significantly, causing a problem in that the output delay time of the logic output circuit 100b changes suddenly. This poses a problem in that it becomes necessary to limit the power supply voltage range in which operation is guaranteed.

[0032] <Third Comparative Example> 5 is a diagram showing a third comparative example of a logic output circuit. A logic output circuit 100c of the third comparative example includes transistors 110 and 111 in addition to the components of the first comparative example (FIG. 1). The transistor 110 may be, for example, a PMOS. The transistor 111 may be, for example, an NMOS.

[0033] The transistors 101 and 102 and the output node 103 have the same configuration as in the first comparative example (FIG. 1). The transistors 101 and 102 switch between the source and sink of the drive current I in response to the digital input signal DI.

[0034] The transistor 110 is connected between the application terminal of the power supply voltage Vcc and the transistor 101. As shown in the balloon box, the transistor 110 functions as a constant current source that keeps the drive current I sourced to the output node 103 via the transistor 101 at a constant value.

[0035] The transistor 111 is connected between the transistor 102 and the ground terminal GND. As shown in the balloon box, the transistor 111 functions as a constant current source that keeps the drive current I sunk from the output node 103 via the transistor 102 at a constant value.

[0036] 6 is a diagram showing the power supply voltage characteristics of the drive current I in the third comparative example. In the third comparative example, by introducing transistors 110 and 111 that function as constant current sources, it becomes possible to output a flat drive current I that is independent of the power supply voltage Vcc.

[0037] Therefore, the third comparative example solves the problem discussed in the second comparative example (Figures 3 and 4) mentioned above, namely, the problem of the output delay time of the logic output circuit 100b changing suddenly due to a sudden change in the drive current I near the threshold voltage Vth.

[0038] However, in the configuration of the third comparative example, in order to pass the drive current I with the same capacity during reduced voltage as during overvoltage, the transistors 101 and 102 must be large enough to pass the drive current I during reduced voltage as during overvoltage. This poses a problem in that the MOS size used for the transistors 101 and 102 must be large.

[0039] <Example> 7 is a diagram showing an embodiment of a logic output circuit 1. The logic output circuit 1 of the embodiment includes a first output circuit 10, a second output circuit 20, an inverter 30, a correction circuit 40, and an output node 50.

[0040] The first output circuit 10 switches the direction of the first drive current I10 output to the output node 50 based on the digital input signal DI. The first output circuit 10 has a power supply voltage characteristic such that the first drive current I10 decreases as the applied power supply voltage Vcc decreases. For example, the first output circuit 10 includes transistors 11 and 12. The transistor 11 may be, for example, a PMOS. The transistor 12 may be, for example, an NMOS.

[0041] The transistor 11 is controlled to be turned on and off in response to a signal S11. When the transistor 11 is turned on, it sources a drive current I10 from the application terminal of the power supply voltage Vcc to the output node 50.

[0042] The transistor 12 is controlled to be turned on and off in response to a signal S11. When the transistor 12 is turned on, it sinks a drive current I10 from the output node 50 to the ground terminal GND.

[0043] The second output circuit 20 switches the direction of the second drive current I20 output to the output node 50 based on the digital input signal DI. For example, the second output circuit 20 includes transistors 21 and 22 and constant current sources 23 and 24. The transistor 21 and the constant current source 110 may be, for example, PMOS. The transistor 22 and the constant current source 111 may be, for example, NMOS.

[0044] The transistor 21 is connected between the constant current source 23 and the output node 50. A signal S11 is input to the gate of the transistor 21. The transistor 21 is controlled to be turned on and off in response to the signal S11. When the transistor 21 is turned on, it sources a drive current I20 in a direction from the application terminal of the power supply voltage Vcc toward the output node 50 via the constant current source 23. In other words, the transistor 21 functions as a first switch that switches between conducting and blocking the current sourced to the output node 50.

[0045] The transistor 22 is connected between the constant current source 24 and the output node 50. A signal S11 is input to the gate of the transistor 22. The transistor 22 is controlled to be turned on and off in response to the signal S11. When the transistor 22 is turned on, it sinks a drive current I20 in a direction from the output node 50 through the constant current source 24 toward the ground terminal GND. In other words, the transistor 22 functions as a second switch that switches between conducting and blocking the current sunk to the output node 50.

[0046] The constant current source 23 is connected between the application terminal of the power supply voltage Vcc and the transistor 21. The constant current source 23 generates a constant current that is sourced to the output node 50 via the transistor 21 in response to the control signal S12 output from the correction circuit 40. From another perspective, the constant current source 23 adjusts the drive current I20 flowing through the transistor 21 so that it has a constant current value in response to the control signal S12.

[0047] The constant current source 24 is connected between the ground terminal GND and the transistor 22. The constant current source 24 generates a constant current that is sunk from the output node 50 via the transistor 22 in response to a control signal S12 output from the correction circuit 40. From another perspective, the constant current source 24 adjusts the drive current I20 flowing through the transistor 22 to a constant current value in response to the control signal S12.

[0048] The first output circuit 10 and the second output circuit 20 switch between sourcing and sinking the drive currents I10 and I20 in response to the signal S11. Referring to the figure, when the signal S11 is at a low level, the transistors 11 and 21 are on, and the transistors 12 and 22 are off. This state can be understood as a state in which the drive currents I10 and I20 are sourced from the power supply voltage Vcc application terminal toward the output node 50. On the other hand, when the signal S11 is at a high level, the transistors 11 and 21 are off, and the transistors 12 and 22 are on. This state can be understood as a state in which the drive currents I10 and I20 are sunk from the output node 50 toward the ground terminal GND.

[0049] The inverter 30 generates the signal S11 by inverting the logic level of the digital input signal DI. Therefore, the signal S11 is at a low level when the digital input signal DI is at a high level. On the other hand, the signal S11 is at a high level when the digital input signal DI is at a low level.

[0050] The drive current I flowing to the output node 50 is a composite current (combined current) of the drive currents I10 and I20. When the drive current I is sourced from the application terminal of the power supply voltage Vcc toward the output node 50, the digital output signal DO goes high. On the other hand, when the drive current I is sunk from the output node 50 toward the ground terminal GND, the digital output signal DO goes low.

[0051] The correction circuit 40 is connected to the constant current sources 23 and 24. The correction circuit 40 outputs a signal S12 that controls the current value of the drive current I20. The correction circuit 40 is configured to adjust the current values ​​of the constant currents generated by the constant current sources 23 and 24 in accordance with the magnitude of the power supply voltage Vcc. More specifically, the correction circuit 40 increases the current values ​​of the constant currents generated by the constant current sources 23 and 24 as the power supply voltage Vcc decreases.

[0052] 8 is a diagram showing the power supply voltage characteristics of the drive current I in the example. In this diagram, the solid line represents the drive current I. The small dashed line and large dashed line represent the drive currents I10 and I20, respectively.

[0053] Note that Idrv_min in the figure indicates the minimum drive current of the logic output circuit 1, that is, the current value at which the load connected to the logic output circuit 1 will no longer be driven. Also, IL in the figure indicates the required drive current required for the logic output circuit 1. Taking into account current value fluctuations due to manufacturing variations, the required drive current IL may be set to a current value obtained by adding a margin current Imargin to the minimum drive current Idrv_min.

[0054] In the embodiment, the drive current I is generated by adding together a drive current I10 having a power supply voltage characteristic that decreases as the power supply voltage Vcc decreases and a drive current I20 having a power supply voltage characteristic that increases as the power supply voltage Vcc decreases.

[0055] By doing so, the drive current I does not fall below the required drive current IL even during power reduction, which means that it is possible to output a drive current I that is less dependent on the power supply voltage Vcc.

[0056] In addition, the embodiment also solves the problem discussed in the second comparative example (Figures 3 and 4) above, namely, the problem of the output delay time of the logic output circuit 100b changing suddenly due to a sudden change in the drive current I near the threshold voltage Vth.

[0057] Furthermore, according to the embodiment, the second output circuit 20 compensates for only the insufficient drive current of the drive current I10. Therefore, the MOS size used for the transistors 21 and 22 is smaller than that of the configuration of the third comparative example.

[0058] Fig. 9 is a diagram showing a list of MOS sizes for the first to third comparative examples and the working example. In Fig. 9, "MOS Size Ratio" shows the MOS size ratio for each of the first to third comparative examples and the working example, with the MOS size for a typical inverter configuration in the first comparative example, i.e., two transistors, being set to 1.

[0059] According to this figure, the MOS size of the third comparative example, which achieves flat power supply voltage characteristics using only a constant current source, can be 10 times larger than that of the first comparative example. On the other hand, the MOS size of this embodiment is only 5 times larger than that of the first comparative example, i.e., 1 / 2 of that of the third comparative example.

[0060] As can be seen from the list in FIG. 9 and the explanations of the first to third comparative examples and the working example, the working example is optimal in that it can make the power supply voltage characteristics of the drive current I nearly flat while suppressing an increase in MOS size.

[0061] 10 is a detailed diagram of the correction circuit 40 shown in FIG. 7. The correction circuit 40 includes transistors P1 to P3, transistors N1 to N3, resistors R1 and R2, diodes D1 to D4, and constant current sources CS1 and CS2. Transistors P4 and N4 are also provided outside the correction circuit 40. The transistors P4 and N4 can be understood as components of the constant current sources 23 and 24, respectively. The transistors P1 to P4 may be, for example, PMOS transistors. The transistors N1 to N4 may be, for example, NMOS transistors.

[0062] The transistors P1 to P3, the resistor R1, the diodes D1 and D2, and the constant current source CS1 are all used to adjust the current of the constant current source 23. The sources of the transistors P1 to P3 are connected to the application terminal of the power supply voltage Vcc. The gates of the transistors P1 and P2 are connected to the drain of the transistor P1. The drain of the transistor P1 is connected to the first terminal of the resistor R1. The second terminal of the resistor R1 is connected to the positive terminal (anode) of the diode D1. The negative terminal (cathode) of the diode D1 is connected to the positive terminal (anode) of the diode D2. The negative terminal (cathode) of the diode D2 is connected to the ground terminal GND. The drains of the transistors P2 and P3 are connected to the first terminal of the constant current source CS1. The second terminal of the constant current source CS1 is connected to the ground terminal GND. The gates of the transistors P3 and P4 are connected to the drain of the transistor P3.

[0063] The transistors P1 and P2 are configured as a typical PMOS current mirror. That is, a current I41 flowing through the drain of the transistor P1 is mirrored as a current I42 flowing through the drain of the transistor P2. Similarly, the transistors P3 and P4 are configured as a typical PMOS current mirror. That is, a current I43 flowing through the drain of the transistor P3 is mirrored as a current I44 flowing through the drain of the transistor P4.

[0064] The transistors P1 and P2, the resistor R1, and the diodes D1 and D2 constitute a variable current generator. The variable current generator generates a current I43 (=variable current) that varies depending on the power supply voltage Vcc. On the other hand, the constant current source CS1 functions as a fixed current generator. The fixed current generator generates a predetermined current I40 (=fixed current).

[0065] With the above configuration, the constant current generated by the constant current source 23 can be adjusted by the following operation. First, a current I41 that varies depending on the power supply voltage Vcc flows through the drain of the transistor P1. The higher the power supply voltage Vcc, the larger the current I41 becomes, and the lower the power supply voltage Vcc, the smaller the current I41 becomes.

[0066] A current I42 that is a mirror of the current I41 flows through the drain of the transistor P2. Therefore, the current I42 has the same power supply voltage characteristics as the current I41. In other words, the current I42 increases as the power supply voltage Vcc increases, and decreases as the power supply voltage Vcc decreases.

[0067] A current I43 (=I40-I42), which is the current I40 minus the current I42, flows through the drain of transistor P3. Therefore, current I43 has the opposite power supply voltage characteristics to current I42. In other words, current I43 decreases as the power supply voltage Vcc increases and increases as the power supply voltage Vcc decreases.

[0068] A current I44 that is a mirror of the current I43 flows through the drain of the transistor P4. Therefore, the current I44 has the same power supply voltage characteristics as the current I43. In other words, the current I44 decreases as the power supply voltage Vcc increases, and increases as the power supply voltage Vcc decreases.

[0069] In this way, current I44 corresponding to the difference between current I42, which is a variable current, and current I40, which is a fixed current, is passed through transistor P4, thereby adjusting the current of constant current source 23. In other words, current I44 generated by constant current source 23 is adjusted according to power supply voltage Vcc. Note that if power supply voltage Vcc is a fixed value, current I44 also becomes a fixed value (=constant current).

[0070] The transistors N1 to N3, the resistor R2, the diodes D3 and D4, and the constant current source CS2 are all used to adjust the current of the constant current source 24. The sources of the transistors N1 to N3 are connected to the ground terminal GND. The gates of the transistors N1 and N2 are connected to the drain of the transistor N1. The drain of the transistor N1 is connected to the negative terminal (cathode) of the diode D4. The positive terminal (anode) of the diode D4 is connected to the negative terminal (cathode) of the diode D3. The positive terminal (anode) of the diode D3 is connected to a first terminal of the resistor R2. The second terminal of the resistor R2 is connected to an application terminal of the power supply voltage Vcc. The drains of the transistors N2 and N3 are connected to a first terminal of the constant current source CS2. The second terminal of the constant current source CS2 is connected to an application terminal of the power supply voltage Vcc. The gates of the transistors N3 and N4 are connected to the drain of the transistor N3.

[0071] Transistors N1 and N2 are configured as a typical NMOS current mirror. That is, a current I46 flowing through the drain of transistor N1 is mirrored as a current I47 flowing through the drain of transistor N2. Similarly, transistors N3 and N4 are configured as a typical NMOS current mirror. That is, a current I48 flowing through the drain of transistor N3 is mirrored as a current I49 flowing through the drain of transistor N4.

[0072] The transistors N1 and N42, the resistor R2, and the diodes D3 and D4 constitute a variable current generator. The variable current generator generates a current I46 (=variable current) that varies depending on the power supply voltage Vcc. Meanwhile, the constant current source CS2 functions as a fixed current generator. The fixed current generator generates a predetermined current I45 (=fixed current).

[0073] With the above configuration, the constant current generated by constant current source 24 can be adjusted by the following operation. First, a current I46 that varies depending on the power supply voltage Vcc flows through the drain of transistor N1. The higher the power supply voltage Vcc, the larger the current I46 becomes, and the lower the power supply voltage Vcc, the smaller the current I46 becomes.

[0074] A current I47, which is a mirror of the current I46, flows through the drain of the transistor N2. Therefore, the current I47 has the same power supply voltage characteristics as the current I46. In other words, the current I47 increases as the power supply voltage Vcc increases, and decreases as the power supply voltage Vcc decreases.

[0075] A current I48 (=I45-I47), which is the current I45 minus the current I47, flows through the drain of transistor N3. Therefore, current I48 has the opposite power supply voltage characteristics to current I47. In other words, current I48 decreases as the power supply voltage Vcc increases and increases as the power supply voltage Vcc decreases.

[0076] A current I49 that is a mirror of the current I48 flows through the drain of transistor N4. Therefore, the current I49 has the same power supply voltage characteristics as the current I48. In other words, the current I49 decreases as the power supply voltage Vcc increases, and increases as the power supply voltage Vcc decreases.

[0077] In this way, current I49 corresponding to the difference between current I47, which is a variable current, and current I45, which is a fixed current, is passed through transistor N4, thereby adjusting the current of constant current source 24. In other words, current I49 generated by constant current source 24 is adjusted according to power supply voltage Vcc. Note that if power supply voltage Vcc is a fixed value, current I49 also becomes a fixed value (=constant current).

[0078] 11 is a diagram showing a semiconductor device equipped with a logic output circuit. The semiconductor device 200 includes an analog input circuit 210, a connection block 220, a logic output circuit 230, and a power supply monitor 240.

[0079] The semiconductor device 200 also includes external terminals T1 to T3. The external terminal T1 is a power supply terminal that receives an input of a power supply voltage Vcc. The external terminal T2 is an output terminal that outputs a logic output signal DO. The external terminal T3 is a ground terminal that is connected to a ground terminal GND. A capacitive load Co is connected between the external terminals T2 and T3.

[0080] The analog input circuit 210 operates upon receiving a power supply voltage Vcc. Referring to the figure, the analog input circuit 210 receives an analog signal from the outside and outputs a signal S21 based on the analog signal. For example, if the semiconductor device 200 is an ADC, the analog input circuit 210 may have a function of converting the analog signal into a digital signal. In other words, the analog input circuit 210 may be an AD conversion circuit provided in the preceding stage of the logic output circuit 230.

[0081] The connection block 220 operates by receiving the supply of the power supply voltage Vcc. Referring to this figure, the connection block 220 receives a signal S21 and outputs a signal S22 based on the signal S21.

[0082] The logic output circuit 230 operates by receiving a power supply voltage Vcc. Referring to the figure, the logic output circuit 230 outputs a digital output signal DO for controlling an external load. The logic output circuit 1 described in the embodiments above can be used as the logic output circuit 230.

[0083] The analog input circuit 210, the connection block 220, and the logic output circuit 230 are all connected to the external terminals T1 and T3, respectively. That is, the analog input circuit 210, the connection block 220, and the logic output circuit 230 share a common power supply and ground.

[0084] The power supply monitor 240 monitors the power supply voltage Vcc supplied to the external terminal T1. The power supply monitor 240 may output a signal S23 corresponding to the power supply voltage Vcc to the logic output circuit 230. In accordance with the above-mentioned embodiment, the power supply monitor 240 may be understood as a functional block equivalent to the correction circuit 40. In this case, the signal S23 may be understood as a signal applied to the gates of the transistors P4 and N4, respectively. Alternatively, the signal S23 may be understood as currents I43 and I48.

[0085] In this way, with a configuration that monitors the power supply voltage Vcc and adjusts the drive current of the logic output circuit 230, even when the power supply voltage Vcc decreases, the drive current of the logic output circuit 230 will not fall below the required drive current. As a result, it becomes possible to always drive the digital output signal DO at the highest operating frequency, regardless of the power supply voltage Vcc.

[0086] <Additional Notes> A supplementary note will be provided for the present disclosure, the specific configuration examples of which have been shown in the above-described embodiments.

[0087] (Appendix 1) a first output circuit (10) configured to switch the direction of a first drive current (I10) output to an output node (50) based on a digital input signal (DI) so that the first drive current (I10) decreases in response to a decrease in an applied power supply voltage (Vcc); a second output circuit (20) configured to switch the direction of a second drive current (I20) output to the output node (50) based on the digital input signal (DI) and adjust the second drive current (I20) using constant current sources (23, 24); a correction circuit (40) configured to adjust the current value of the constant current generated by the constant current sources (23, 24) in accordance with the power supply voltage (Vcc); A logic output circuit (1) comprising:

[0088] (Appendix 2) 2. The logic output circuit according to claim 1, wherein the correction circuit increases the current value of the constant current as the power supply voltage Vcc decreases.

[0089] (Appendix 3) 3. The logic output circuit (1) of claim 1 or 2, wherein the constant current sources (23, 24) include a first constant current source (23) and a second constant current source (24), the first constant current source (23) generating a current that is sourced to the output node (50), and the second constant current source (24) generating a current that is sunk from the output node (50).

[0090] (Appendix 4) 4. The logic output circuit (1) of claim 3, wherein the second output circuit (20) includes a first switch (21) configured to switch between conducting and blocking a current sourced to the output node (50) and a second switch (22) configured to switch between conducting and blocking a current sunk from the output node (50).

[0091] (Appendix 5) 5. The logic output circuit according to any one of appendices 1 to 4, wherein the first output circuit (10) is smaller in size than the second output circuit (20).

[0092] (Appendix 6) The logic output circuit (1) according to any one of appendices 1 to 5, wherein the correction circuit (40) includes a variable current generating unit configured to generate variable currents (I42, I47) that depend on the power supply voltage (Vcc), and a fixed current generating unit configured to generate fixed currents (I40, I45), and causes currents (I44, I49) that correspond to a difference between the variable currents (I42, I47) and the fixed currents (I40, I45) to flow through the constant current sources (23, 24).

[0093] (Appendix 7) A semiconductor device (200) comprising the logic output circuit (1) according to any one of appendices 1 to 6. [Explanation of symbols]

[0094] 1 Logic Output Circuit 10 First output circuit 11 Transistor (P-channel type) 12 Transistor (N-channel type) 20 Second output circuit 21 Transistor (P-channel type) 22 Transistor (N-channel type) 23, 24 constant current source 30 inverters 40 Correction circuit 50 output nodes 100a, 100b, 100c Logic output circuit 101, 104, 110 Transistor (P-channel type) 102, 105, 111 Transistor (N-channel type) 103 Output Node 106, 107 Inverter 108 NAND gates 109 NOR Gate 200 Semiconductor device 210 Analog Input Circuit 220 Connection Circuit 230 Logic Output Circuit 240 Power supply monitoring circuit Co capacitive load CS1, CS2 constant current source D1~D4 Diodes N1~N4 transistors (N-channel type) P1~P4 Transistors (P-channel type) R1, R2 resistance T1~T3 external terminals

Claims

1. a first output circuit configured to switch a direction of a first drive current output to an output node based on a digital input signal, and to decrease the first drive current in response to a decrease in an applied power supply voltage; a second output circuit configured to switch a direction of a second drive current output to the output node based on the digital input signal and adjust the second drive current using a constant current source; a correction circuit configured to adjust the current value of the constant current generated by the constant current source in accordance with the power supply voltage; A logic output circuit comprising:

2. 2. The logic output circuit according to claim 1, wherein said correction circuit increases the current value of said constant current as said power supply voltage decreases.

3. 2. The logic output circuit of claim 1, wherein the constant current source comprises a first constant current source and a second constant current source, the first constant current source generating a current sourced to the output node and the second constant current source generating a current sunk from the output node.

4. 4. The logic output circuit of claim 3, wherein the second output circuit further includes: a first switch configured to switch between conducting and blocking a current sourced to the output node; and a second switch configured to switch between conducting and blocking a current sunk from the output node.

5. 2. The logic output circuit of claim 1, wherein the first output circuit is smaller in size than the second output circuit.

6. 2. The logic output circuit according to claim 1, wherein the correction circuit comprises a variable current generating unit configured to generate a variable current that depends on the power supply voltage, and a fixed current generating unit configured to generate a fixed current, and causes a current corresponding to a difference between the variable current and the fixed current to flow through the constant current source.

7. A semiconductor device comprising the logic output circuit according to any one of claims 1 to 6.

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