Charge / discharge control circuit, protection circuit, and battery pack

Abstract

Even if high frequency noise is applied to a terminal or circuit for detecting a discharge overcurrent, false detection or malfunction can be avoided. [Solution] A charge / discharge control circuit of the present invention controls a charge control switch element and a discharge control switch element that control charging and discharging of a secondary battery. The charge / discharge control circuit includes a shunt resistor that detects a voltage corresponding to a discharge current or a charge current, a comparator that compares a first potential with a potential of an added voltage obtained by adding a predetermined threshold voltage to a second potential and outputs a comparison result signal indicative of an overcurrent, a logic circuit that controls the charge control switch element or the discharge control switch element based on the comparison result signal, a first low-pass filter inserted between a first terminal of the shunt resistor and the comparator, and a second low-pass filter inserted between a second terminal of the shunt resistor and the comparator.

Description

[Technical Field]

[0001] The present invention relates to a charge / discharge control circuit, a protection circuit including the charge / discharge control circuit, and a battery pack including the protection circuit. [Background technology]

[0002] Lithium-ion batteries are often used in mobile devices such as smartphones and tablets. Lithium-ion batteries can explode or catch fire if overcharged, and can become unable to be charged even with a charger if overdischarged. Therefore, battery packs are configured with a protection circuit connected to the secondary battery (see, for example, Patent Document 1). Hereinafter, field-effect transistors are referred to as FETs.

[0003] First, a conventional method for detecting a discharge overcurrent in a battery pack will be described below.

[0004] Fig. 1 is a circuit diagram showing the configuration of a battery pack according to Conventional Example 1. The battery pack in Fig. 1 comprises a secondary battery B1, a charge / discharge control circuit 1, a charge control FET (CFET) 2 and its body diode 3, a discharge control FET (DFET) 4 and its body diode 5, a shunt resistor 6, a positive terminal (P+) 7, and a negative terminal (P-) 8. Here, the charge control FET 2 is an example of a charge control switch element, and the discharge control FET 4 is an example of a discharge control switch element.

[0005] In Figure 1, the positive electrode of secondary battery B1 is connected to the source of charge control FET2 and the anode of body diode 3, and the drain of charge control FET2 and the cathode of body diode 3 are connected to the drain of discharge control FET4 and the cathode of body diode 5. The source of discharge control FET4 and the anode of body diode 5 are connected to the positive terminal (P+) 7 of the battery pack via shunt resistor 6. Meanwhile, the negative electrode of secondary battery B1 is connected to the VSS terminal T2 of charge / discharge control circuit 1 and the negative terminal (P-) 8 of the battery pack. Here, the VDD terminal T1 of charge / discharge control circuit 1 is connected to the positive electrode of secondary battery B1, the COUT terminal T11 of charge / discharge control circuit 1 is connected to the gate of charge control FET2, and the DOUT terminal T12 of charge / discharge control circuit 1 is connected to the gate of discharge control FET4. Furthermore, the RSENS terminal T13 of the charge / discharge control circuit 1 is connected to the source of the discharge control FET 4 and one end of the shunt resistor 6, and the VP terminal T3 of the charge / discharge control circuit 1 is connected to the other end of the shunt resistor 6 and the positive terminal (P+) 7 of the battery pack. Between the positive terminal (P+) 7 and the negative terminal (P-) 8, a load resistor Rload such as a CPU or microcomputer, a charger, or both are connected.

[0006] The charge / discharge control circuit 1 is configured with a boost circuit 9, a logic circuit 10, a comparator 11, a constant current source 13, a resistor 12, and six terminals T1 to T3, T11 to T13. A power supply voltage VDD input to a VDD terminal T1 is input to the boost circuit 9, which boosts the power supply voltage VDD and outputs the boosted voltage VCP to the logic circuit 10. A detection potential v2 detected at a VP terminal T3 is applied to the inverting input terminal of the comparator 11. A voltage detected at an RSENS terminal T13 is applied as a potential v1 to the non-inverting input terminal of the comparator 11 via one end and the other end of a resistor 12. The other end of the resistor 12 is grounded via a constant current source 13.

[0007] The comparator 11 compares the input potential v2 with the input potential v1 and outputs a comparison result signal Sout to the logic circuit 10. Based on the boosted voltage VCP and the comparison result signal Sout, the logic circuit 10 generates a charge control gate control signal Sc and a discharge control gate control signal Sd, as will be described in detail below, and outputs them to the gates of the charge control FET2 and the discharge control FET4 via the COUT terminal T11 and the DOUT terminal T12, respectively.

[0008] Fig. 2 is an example of a circuit diagram showing the configuration of the boost circuit 9 in Fig. 1, and Fig. 3 is an example of a circuit diagram showing the configuration of the comparator 11 in Fig. 1. In Fig. 2, the boost circuit 9 is configured to include a control circuit 9a, transistor switches 8a, 8b, 8c, and 8d, and a capacitor C1. The comparator 11 is configured to include N-channel MOSFETs (NMOSFETs) 11a and 11b, P-channel MOSFETs (PMOSFETs) 17a and 17b, and a constant current source 16.

[0009] First, the circuit operation of the charge / discharge control circuit 1 in FIG. 1 during discharging will be described below.

[0010] During discharge, a load resistor Rload such as a CPU or a microcontroller is connected between the positive terminal (P+) 7 and the negative terminal (P-) 8. The discharge current from the positive electrode of the secondary battery B1 flows through the charge control FET2, the discharge control FET4, the shunt resistor 6, and the positive terminal (P+) 7 to the load resistor Rload, and further flows through the negative terminal (P-) 8 to the negative electrode of the secondary battery B1. When the discharge current flows, the charge / discharge control circuit 1 monitors the potential difference (I×R6 = Vrsens - Vvp) between the potential Vrsens of the RSENS terminal T13 and the potential Vvp of the VP terminal T3 generated by the discharge current I and the shunt resistor 6 (resistance value R6). Here, when the potential Vvp of the VP terminal T3 becomes lower than a predetermined threshold voltage Vth than the potential Vrsens of the RSENS terminal T13, that is, when v2 < Vrsens - Vth = v1, an over-discharge current is detected. When the over-discharge current is detected, the comparator 11 outputs a comparison result signal Sout of H level to the logic circuit 10. In response to this, the logic circuit 10 outputs a gate control signal Sd of L level to the gate of the discharge control FET4, turning off the discharge control FET4 and stopping the discharge current of the secondary battery B1. Specifically, based on the potential Vrsens of the RSENS terminal T13, a detection potential v1 (v1 = Vrsens - Vth, Vth = R12×I13) is generated using the resistor 12 (resistance value R12) and the constant current source 13 (current value I13). The comparator 11 compares the detection potential v1 with the detection potential v2 (v2 = Vvp) of the VP terminal T3. The predetermined threshold voltage Vth may be generated by a constant voltage source since it is created by the resistor 12 and the constant current source 13.

[0011] During normal discharge current, v1 < v2, and the comparator 11 outputs a comparison result signal Sout of L level (VSS) to the logic circuit 10. In response to this, the logic circuit 10 generates the H-level VCP (for example, VDD×2) generated by the boost circuit 9 shown in FIG. 2 as the gate control signal Sd, and applies the gate control signal Sd to the gate of the discharge control FET4 to turn on the discharge control FET4 and allow the discharge current to flow.

[0012] Also, the control circuit 9a of the boost circuit 9 follows a predetermined clock, (1) An operation of charging the capacitor C1 with an electric charge corresponding to the voltage difference between the output voltage VDD and the ground voltage VSS by turning on the switch 8a, turning off the switch 8b, turning off the switch 8c, and turning on the switch 8d in FIG. 2; (2) An operation of generating a boost voltage VCP (for example, VDD×2) and outputting it to the logic circuit 10 by turning off the switch 8a, turning on the switch 8b, turning on the switch 8c, and turning off the switch 8d in FIG. 2; The operation of the booster circuit 9 is controlled so as to repeat the above.

[0013] In the case of an abnormal discharge current (discharge overcurrent), v1>v2, and as described above, the comparator 11 outputs the comparison result signal Sout of H level (VDD) to the logic circuit 10. In response to this, the logic circuit 10 applies the gate control signal Sd of L level (VSS) to the gate of the discharge control FET4, turning off the discharge control FET4 and thereby stopping the abnormal discharge current (discharge overcurrent). [Prior art documents] [Patent documents]

[0014] [Patent Document 1] Patent No. 5338047 Summary of the Invention [Problem to be solved by the invention]

[0015] In the configuration of a battery pack having a protection circuit according to the above-described conventional example 1, there was a problem in that when high-frequency noise of, for example, approximately 1 GHz or more is applied to the terminals (VSS terminal T2, VP terminal T3, RSENS terminal T13) or circuits for detecting a discharge overcurrent, the protection circuit makes a false detection and malfunctions.

[0016] The object of the present invention is to solve the above problems and to provide a charge / discharge control circuit, a protection circuit including a charge / discharge control circuit, and a battery pack including a protection circuit, which can detect a discharge overcurrent and avoid false detection or malfunction even when high-frequency noise of, for example, approximately 1 GHz or more is applied to a terminal or circuit for detecting a discharge overcurrent. [Means for solving the problem]

[0017] A charge / discharge control circuit according to one aspect of the present invention includes: a charge control switch element that controls charging of the secondary battery; a discharge control switch element connected in series with the charge control switch element to control discharge of the secondary battery; A charge / discharge control circuit for controlling The charge / discharge control circuit a shunt resistor connected in series with the charge control switch element or the charge control switch element and connected between the secondary battery and a load, the shunt resistor detecting a voltage corresponding to a discharge current or a charge current and outputting first and second potentials at a first terminal and a second terminal of the shunt resistor; a comparator that compares the first potential with a potential of an added voltage obtained by adding a predetermined threshold voltage to the second potential, and outputs a comparison result signal that indicates an overcurrent; a logic circuit that controls the charge control switch element or the discharge control switch element based on the comparison result signal; a first low-pass filter inserted between a first terminal of the shunt resistor and the comparator; a second low-pass filter inserted between a second terminal of the shunt resistor and the comparator; Equipped with. [Effects of the Invention]

[0018] Therefore, according to the charge / discharge control circuit of the present invention, a low-pass filter is inserted into the detection voltage circuit of the charge / discharge control circuit, so even if high-frequency noise is applied to the terminal or circuit that detects the discharge overcurrent, the noise can be attenuated, making it possible to detect erroneous detection or malfunction of the protection circuit of the battery pack and detect and stop the discharge overcurrent. [Brief explanation of the drawings]

[0019] [Figure 1] FIG. 1 is a circuit diagram showing the configuration of a battery pack according to Conventional Example 1. [Figure 2] 2 is a circuit diagram showing a configuration of a booster circuit 9 in FIG. 1. [Figure 3] 2 is a circuit diagram showing a configuration of a comparator 11 in FIG. 1. [Figure 4A] 1 is a circuit diagram showing an example of the configuration of a battery pack according to a first embodiment. [Figure 4B] FIG. 10 is a circuit diagram showing an example of the configuration of a battery pack according to a modified example of the first embodiment. [Figure 5] FIG. 10 is a circuit diagram showing an example of the configuration of a battery pack according to a second embodiment. [Figure 6] FIG. 10 is a circuit diagram showing an example of the configuration of a battery pack according to a third embodiment. [Figure 7] FIG. 10 is a circuit diagram showing an example of the configuration of a battery pack according to a fourth embodiment. [Figure 8] FIG. 10 is a circuit diagram showing the configuration of a battery pack according to Conventional Example 2. [Figure 9] FIG. 10 is a circuit diagram showing an example of the configuration of a battery pack according to a fifth embodiment. [Figure 10] FIG. 10 is a circuit diagram showing an example of the configuration of a battery pack according to a sixth embodiment. [Figure 11] FIG. 11 is a circuit diagram showing an example of the configuration of a battery pack according to a seventh embodiment. DETAILED DESCRIPTION OF THE INVENTION

[0020] Hereinafter, embodiments and modifications of the present invention will be described with reference to the drawings, in which the same or similar components are designated by the same reference numerals.

[0021] (Inventor's Knowledge) First, the mechanism of erroneous detection in the protection circuit will be described below with reference to the above-mentioned FIGS.

[0022] For example, assume that high-frequency noise of 1 GHz or higher is generated by irradiation with high-frequency radio waves of 1 GHz or higher, or by the operation of a system (load resistor Rload in FIG. 1) connected between positive terminal 7 and negative terminal 8 for some other reason, and propagates to RSENS terminal T13 and VP terminal T3. At this time, the noise amplitude of potential v1 input to the non-inverting input terminal of comparator 11 is attenuated to some extent by a low-pass filter consisting of resistor 12 and the input capacitor (not shown) of comparator 11. On the other hand, the noise amplitude of potential v2 input to the inverting input terminal of comparator 11 is not attenuated because it is connected directly from VP terminal T3 to the inverting input terminal of comparator 11.

[0023] 3 includes a current mirror circuit composed of two PMOSFETs 17a and 17b, two NMOSFETs 11a and 11b, and a constant current source 16. A power supply voltage VDD, which is an input voltage, is applied to the sources of the two PMOSFETs 17a and 17b. The gates of the PMOSFETs 17a and 17b are connected to each other, and the gate and drain of the PMOSFET 17a are also connected to each other. The drains of the two PMOSFETs 17a and 17b are connected to the drains of the two NMOSFETs 11a and 11b, respectively, and the sources of the two NMOSFETs 11a and 11b are grounded via the constant current source 16.

[0024] In the comparator 11 configured as described above, the gates of the two NMOSFETs 11a and 11b are at the potential v1 at the non-inverting input terminal and the potential v2 at the inverting input terminal, respectively. Here, as shown in FIG. 3, let the current flowing through the channel of the NMOSFET 11a be the current i1, and the current flowing through the channel of the NMOSFET 11b be the current i2. Here, when the amplitude of the noise propagating to the latter potential v2 is larger than the noise propagating to the former potential v1, due to the non-linearity of a general transistor, i1 < i2, so the comparison result signal Sout of the comparator 11 is forcibly fixed at the L level (the level when overcurrent is not detected). When the comparison result signal Sout is fixed at the L level, the gate control signal Sd of the logic circuit 10 is fixed at the H level, so the discharge control FET 4 continues to be on.

[0025] As a result, for example, when irradiated with a high-frequency radio wave of 1 GHz or higher, or when a high-frequency noise of 1 GHz or higher propagates to the RSENS terminal T13 and the VP terminal T3, even if an abnormal discharge current flows, the current abnormality cannot be detected (that is, the discharge overcurrent cannot be detected). This problem occurs. This embodiment is provided to solve this problem.

[0026] (Embodiment 1) FIG. 4A is a circuit diagram showing a configuration example of a battery pack according to Embodiment 1. The battery pack in FIG. 4A is different from the battery pack in FIG. 1 in the following points. (1) A low-pass filter 54 including a resistor 14a and a capacitor 14b is inserted between one end of the shunt resistor 6 and the RSENS terminal T13. (2) A low-pass filter 55 including a resistor 15a and a capacitor 15b is inserted between the other end of the shunt resistor 6 and the VP terminal T3. (3) Here, although the low-pass filters 54 and 55 are inserted outside the charge and discharge control circuit 1, they may be inserted inside the charge and discharge control circuit 1, or the charge and discharge control circuit 1 may include the low-pass filters 54 and 55.

[0027] In FIG. 4A, the entire circuit of FIG. 4A including the secondary battery B1 and excluding the resistive load Rload is a battery pack, and the circuit excluding the charge control FET2 and the discharge control FET4 from the battery pack may be the charge / discharge control circuit, or the circuit excluding the charge control FET2, the discharge control FET4, and the low-pass filters 54 and 55 from the battery pack may be the charge / discharge control circuit.

[0028] 4A configured as described above, the provision of low-pass filters 54 and 55 makes it possible to attenuate the amplitude of noise propagating from RSENS terminal T13 to potential v1 of the non-inverting input terminal of comparator 11 and from VP terminal T3 to potential v2 of the inverting input terminal of comparator 11. This makes it possible to prevent noise from propagating to each gate of the differential pair NMOSFET 11a and NMOSFET 11b (FIG. 3) of comparator 11. As a result, it is possible to solve the problem of output signal Sout of comparator 11 being fixed at L level due to the influence of noise generated in the conventional configuration.

[0029] Fig. 4B is a circuit diagram showing an example of the configuration of a battery pack according to a modification of Embodiment 1. The battery pack in Fig. 4B differs from the battery pack in Fig. 4A in the following respects. (1) The circuit of the resistor 12 and the constant current source 13 in the charge / discharge control circuit 1 is moved and inserted into the circuit between the VP terminal T3 and the inverting input terminal of the comparator 11. (2) Instead of the resistive load, a charger CV1 is provided.

[0030] The battery pack of FIG. 4B configured as above has the same effects as the battery pack of FIG. 4A.

[0031] (Embodiment 2) Fig. 5 is a circuit diagram showing an example of the configuration of a battery pack according to embodiment 2. The battery pack in Fig. 5 differs from the battery pack in Fig. 4A in the following respects. (1) The charge / discharge control circuit 1 is replaced with a charge / discharge control circuit 1A, and configured as follows. (2) The low-pass filter 54 is moved and inserted between the resistor 12 and the non-inverting input terminal of the comparator 11 . (3) The low-pass filter 55 is moved and inserted between the VP terminal T3 and the inverting input terminal of the comparator 11.

[0032] The battery pack of FIG. 5 configured as above has the same effects as the battery packs of FIGS. 4A and 4B.

[0033] (Embodiment 3) Fig. 6 is a circuit diagram showing an example of the configuration of a battery pack according to embodiment 3. The battery pack in Fig. 6 differs from the battery pack in Fig. 4A in the following respects. (1) The charge / discharge control circuit 1 is replaced with a charge / discharge control circuit 1B, and configured as follows. (2) PMOSFETs 31 and 32, which are transistor switches, and a detection circuit 33 are inserted in the circuit between the RSENS terminal T13 and the resistor 12, and in the circuit between the VP terminal T3 and the inverting input terminal of the comparator 11. The differences will be explained below.

[0034] When charging the secondary battery B1, a resistive load Rload, such as a charger, is connected between the positive terminal 7 and the negative terminal 8. It is possible that the charger connected to the positive terminal 7 may output a high voltage due to some kind of malfunction. Therefore, the elements connected to the RSENS terminal T13 and the VP terminal T3 must be constructed with high-voltage-resistant elements to withstand high voltages. However, this increases the circuit area of ​​the LSI, the number of masks used in the semiconductor manufacturing process, and lead time, resulting in cost and manufacturing time disadvantages. Therefore, when the voltage at the positive terminal 7 exceeds a predetermined threshold voltage (e.g., VDD + 1 V), the detection circuit 33 outputs H-level gate control signals S31 and S32 to the gates of the PMOSFETs 31 and 32, respectively, thereby turning off the PMOSFETs 31 and 32. This prevents the high voltage from the charger connected to the positive terminal 7 from being applied to the resistor 12, constant current source 13, and comparator 11, allowing the resistor 12, constant current source 13, and comparator 11 to be constructed with low-voltage-resistant elements. Therefore, it is possible to obtain the advantages of reducing the area of ​​the LSI circuit, reducing the number of masks used in the semiconductor manufacturing process, and shortening the lead time.

[0035] Also, assume that high-frequency noise of 1 GHz or higher, generated by irradiation with high-frequency radio waves of, for example, 1 GHz or higher, or by the operation of a system (load resistor such as a CPU) connected between positive terminal 7 and negative terminal 8, propagates to RSENS terminal T13 and VP terminal T3. When noise propagates to RSENS terminal T13 and VP terminal T3, PMOSFETs 31 and 32 turn off due to transistor nonlinearity. Here, transistor nonlinearity means that the transistor Vgs opens and closes in response to noise, but when the amplitude is large, the off period becomes longer than the on period, and the time-averaged current value is closer to that of the off period.

[0036] Here, when PMOSFETs 31 and 32 are turned off, the DC voltage at the non-inverting input terminal of comparator 11 is pulled down to the ground voltage VSS by constant current source 13. On the other hand, there is no circuit connected to pull down the inverting input terminal of comparator 11. Therefore, the magnitude relationship of the DC voltages at each input terminal of comparator 11 becomes v1 < v2, and the output signal Sout of comparator 11 is fixed at the L level. As a result, there is a problem that even if an abnormal discharge current flows when noise is irradiated, the abnormality (discharge overcurrent) of the discharge current cannot be detected.

[0037] To solve this problem, by providing low-pass filters 54 and 55 at the RSENS terminal T13 and the VP terminal T3 respectively, the amplitude of the noise propagated to the PMOSFETs 31 and 32 can be attenuated.

[0038] Furthermore, when a charger connected between the positive terminal 7 and the negative terminal 8 outputs a steep high voltage due to some failure, there is a risk that a high voltage will be instantaneously applied to resistor 12, constant current source 13, and comparator 11 until detection circuit 33 detects the high voltage of the charger voltage and turns off PMOSFETs 31 and 32. However, the low-pass filters 54 and 55 can slow down the voltage rise change at the RSENS terminal T13 and the VP terminal T3, and prevent a high voltage from being instantaneously applied to resistor 12, constant current source 13, and comparator 11.

[0039] Note that PMOSFETs 31 and 32, which are transistor switches, may be NMOSFETs, and detection circuit 33 may be configured to output gate control signals S31 and S32 at the H level when the charger voltage exceeds a predetermined threshold. Also, resistor 12 and constant current source 13 may be voltage sources respectively. Further, the circuit including detection circuit 33 can also be applied to a charging overcurrent detection circuit.

[0040] As described above, according to this embodiment, the low-pass filters 54 and 55 attenuate the amplitude of noise propagating to the PMOSFETs 31 and 32, thereby preventing the PMOSFETs 31 and 32 from being turned off due to their nonlinearity and preventing the comparison result signal Sout of the comparator 11 from being fixed at the H level or the L level. This makes it possible to detect a discharge overcurrent even when noise is propagating. Furthermore, the resistor 12, the constant current source 13, and the comparator 11 can be configured using low-voltage elements. This provides the advantages of reduced LSI circuit area, a reduced number of masks used in the semiconductor manufacturing process, and a shorter lead time.

[0041] (Embodiment 4) Fig. 7 is a circuit diagram showing an example of the configuration of a battery pack according to embodiment 4. The battery pack in Fig. 7 differs from the battery pack in Fig. 6 in the following respects. (1) The charge / discharge control circuit 1B is replaced with a charge / discharge control circuit 1C, and the following configuration is performed. (2) A low-pass filter 59 consisting of a resistor 19 a and a capacitor 19 b is inserted between the other end of the resistor 12 and the non-inverting input terminal of the comparator 11 . (3) A low-pass filter 60 consisting of a resistor 20 a and a capacitor 20 b is inserted between the drain of the PMOSFET 32 and the inverting input terminal of the comparator 11 . The differences will be explained below.

[0042] 6 propagates to RSENS terminal T13 and VP terminal T3, the noise may propagate to each input terminal of comparator 11 via PMOSFETs 31 and 32, which are transistor switches. Alternatively, noise applied on the secondary battery B1 side of low-pass filter 54 may propagate to each input terminal of comparator 11. As with the battery pack of FIG. 4, the nonlinearity of the differential pair transistors in comparator 11 causes the comparison result signal Sout of comparator 11 to be fixed at the L level, resulting in the inability to detect a discharge overcurrent. In this embodiment, low-pass filters 59 and 60 are provided immediately before each input terminal of comparator 11, respectively, to attenuate the amplitude of the noise propagating to each input terminal of comparator 11.

[0043] As described above, according to this embodiment, by providing the low-pass filters 59 and 60 immediately before each input terminal of the comparator 11, it is possible to cut noise of frequencies that are not attenuated by the low-pass filters 54 and 55, and to prevent noise from propagating to the comparator 11. Therefore, even if high-frequency noise of, for example, 1 GHz or higher propagates to the RSENS terminal T13 and the VP terminal T3, it is possible to normally detect a discharge overcurrent. Furthermore, by connecting the external low-pass filters 54 and 55 to the low-pass filters 59 and 60 in the charge / discharge control circuit 1C, it is possible to remove noise of different frequency bands, further attenuate noise in specific frequency bands, and remove radio wave noise received immediately before the terminals of the charge / discharge control circuit or within the charge / discharge control circuit, thereby making it possible to deal with various types of noise propagation.

[0044] The threshold value created by the resistor 12 and the constant current source 13 may be replaced with a predetermined constant voltage source. This embodiment can also be applied to a charging overcurrent detection circuit.

[0045] (Conventional example 2) Conventional example 2 will be described below to explain embodiments 5 to 8.

[0046] Fig. 8 is a circuit diagram showing the configuration of a battery pack according to Conventional Example 2. The battery pack in Fig. 8 differs from the battery pack in Fig. 1 in the following respects. (1) The charge / discharge control circuit 1 is replaced with a charge / discharge control circuit 1D, and configured as follows. (2) RSENS terminal T13 has been moved to RSENS terminal T13A. (3) A shunt resistor 6 is inserted between the anode terminal of the secondary battery B1 and the charge control FET2, one end of the shunt resistor 6 is connected to the anode terminal of the secondary battery B1, and the other end of the shunt resistor 6 is connected to the RSENS terminal T13A. (4) The circuit of the resistor 12 and the constant current source 13 in the charge / discharge control circuit 1 is moved and inserted into the circuit between the VDD terminal T1 and the input terminal of the boost circuit 9. The differences will be explained below.

[0047] In Figure 8, RSENS terminal T13A is connected to the inverting input terminal (potential v2) of comparator 11, with v2 = Vrsens. VDD terminal T1 is connected to a voltage generation circuit, which is made up of resistor 12 and constant current source 13, that generates a predetermined threshold voltage Vth, and the potential v1 of this voltage generation circuit is applied to the non-inverting input terminal of comparator 11 (potential v1 = VDD - Vth). Shunt resistor 6 detects an overcurrent abnormality (discharge overcurrent detection) from the potential difference (Vvdd - Vrsens) between the voltage VDD of VDD terminal T1 and the potential Vrsens of RSENS terminal T13A. Here, the current I flowing through shunt resistor 6 is expressed by the following equation:

[0048] I=(Vvdd-Vrsens) / R6)

[0049] When RSENS terminal T13A is located on the positive terminal 7 side as in Figure 1, a charger that malfunctions for some reason may output a high voltage, so the circuit connected to RSENS terminal T13 must be made of high-voltage elements. On the other hand, if RSENS terminal T13A is located on the secondary battery B1 side as in Figure 8, the voltage of secondary battery B1 is applied to RSENS terminal T13A, so a voltage as high as that of the charger is not applied. As a result, low-voltage elements can be used in the circuit connected to RSENS terminal T13A, which offers the benefits of saving the area of ​​the LSI circuit, reducing the number of masks used in the semiconductor manufacturing process, and shortening lead time.

[0050] 8 configured as described above, if secondary battery B1 is irradiated with high-frequency radio waves during discharge, or if noise is generated by a system (such as a CPU or microcomputer corresponding to load resistance Rload in FIG. 8) connected between positive terminal 7 and negative terminal 8, the noise propagates to RSENS terminal T13A and VDD terminal T1 via discharge control FET 4 and charge control FET 2. Note that it is assumed here that noise (e.g., a sine wave) propagating to positive terminal 7 via charge control FET 2 and discharge control FET 4 propagates directly to VDD terminal T1.

[0051] In this conventional example, the comparison result signal Sout of the comparator 11 is fixed to the L level (non-detection) as in the conventional example 1 in Fig. 1, and the same problem occurs that a discharge overcurrent cannot be detected even when an abnormal discharge current occurs. In order to solve this problem, embodiments 5 to 7 are proposed.

[0052] (Embodiment 5) Fig. 9 is a circuit diagram showing an example of the configuration of a battery pack according to embodiment 5. The battery pack in Fig. 9 differs from the battery pack in Fig. 8 in the following respects. (1) A low-pass filter 54 made up of a resistor 14a and a capacitor 14b is inserted between the other end of the shunt resistor 6 and the RSENS terminal T13A. (2) A low-pass filter 55 consisting of a resistor 15a and a capacitor 15b is inserted between one end of the shunt resistor 6 and the VDD terminal T1.

[0053] According to the fifth embodiment configured as described above, the problem of the second conventional example in FIG. 8 can be solved by providing low-pass filters 54 and 55. In FIG. 9, the threshold voltage generated by resistor 12 and constant current source 13 may be generated by a constant voltage source. Furthermore, the fifth embodiment can also be applied to a charging overcurrent detection circuit.

[0054] (Embodiment 6) Fig. 10 is a circuit diagram showing an example of the configuration of a battery pack according to embodiment 6. The battery pack in Fig. 10 differs from the battery pack in Fig. 9 in the following respects. (1) The charge / discharge control circuit 1D is replaced with a charge / discharge control circuit 1E, and the following configuration is performed. (2) The low-pass filter 54 is moved and inserted between the other end of the resistor 12 and the non-inverting input terminal of the comparator 11 . (3) The low-pass filter 55 is moved and inserted between the RSENS terminal T13A and the inverting input terminal of the comparator 11.

[0055] Here, a problem specific to the battery pack of FIG. 9 will be described below. In the configuration of FIG. 9, the voltage drop due to constant current source 13 and resistor 15a affects the potential v1 of the non-inverting input terminal of comparator 11, causing the potential v1 to drop. Furthermore, because the currents due to resistor 15a and constant current source 13 vary depending on the manufacturing process, the voltage drops due to constant current source 13 and resistor 15a vary, affecting the potential v1 of the non-inverting input terminal of comparator 11 and causing the potential v1 to vary. This results in a problem of degraded overcurrent detection accuracy compared to the configuration of FIG. 8 according to Conventional Example 2. To solve this problem, the configuration of Embodiment 6 has been proposed.

[0056] According to the sixth embodiment configured as described above, by providing the low-pass filters 54 and 55 immediately before each input terminal of the comparator 11, it is possible to avoid erroneous detection due to noise as in FIG. 4A and solve the problem of deterioration in detection accuracy in FIG. 9. That is, by connecting the low-pass filters 54 and 55 within the charge / discharge control circuit 1E, radio wave noise received by the charge / discharge control circuit 1E can be removed, thereby preventing noise from propagating to each gate (FIG. 3) of the differential pair NMOSFET 11a and NMOSFET 11b of the comparator 11. The threshold voltage generated by the resistor 12 and constant current source 13 may be generated by a constant voltage source. The sixth embodiment can also be applied to a charging overcurrent detection circuit.

[0057] (Embodiment 7) Fig. 11 is a circuit diagram showing an example of the configuration of a battery pack according to embodiment 7. The battery pack in Fig. 11 differs from the battery pack in Fig. 9 in the following respects. (1) The low-pass filter 55 is inserted between the secondary battery B1 and the VSS terminal T2. (2) The shunt resistor 6 and the capacitor 14b constitute a low-pass filter 54A. The differences will be explained below.

[0058] In FIG. 11, the resistor 15a of the low-pass filter 55 is connected between the negative terminal of the secondary battery B1 and the VSS terminal T2, and the capacitor 15b is connected between the VSS terminal T2 and the VDD terminal T1.

[0059] According to the seventh embodiment configured as described above, it is possible to attenuate noise propagating to the VDD terminal T1 and the RSENS terminal T13A, thereby preventing erroneous detection by the comparator 11. It is also possible to solve the specific problem of FIG. 9, namely, the degradation of accuracy in detecting a discharging overcurrent due to variations in potential v1 caused by a voltage drop due to manufacturing variations in the constant current source 13 and the resistor 15a of the VDD terminal T1. The threshold voltage generated by the resistor 12 and the constant current source 13 may be generated by a constant voltage source. Furthermore, the seventh embodiment can also be applied to a charging overcurrent detection circuit. [Industrial Applicability]

[0060] As described above in detail, according to the charge / discharge control circuit of the present invention, a low-pass filter is inserted into the detection voltage circuit of the charge / discharge control circuit, so even if high-frequency noise is applied to the terminal or circuit that detects the discharge overcurrent, the noise can be attenuated, making it possible to detect erroneous detection or malfunction of the protection circuit of the battery pack and detect and stop the discharge overcurrent. [Explanation of symbols]

[0061] 1,1A~1E Charge / discharge control circuit 2 Charge control FET 3 Body diode 4 Discharge control FET 5 Body diode 6 shunt resistors 7 Positive terminal 8 Negative terminal 8a, 8b, 8c, 8d Transistor switches 9. Boost circuit 9a Control circuit 10 Logic Circuits 11 Comparator 11a, 11b NMOSFET 12,12A resistance 13,13A constant current source 14a Resistance 14b Capacitor 15a resistance 15b capacitor 16 constant current source 17a, 17b PMOSFET 19a Resistance 19b Capacitor 20a resistor 20b capacitor 31,32 PMOSFET 33 Detection circuit 54, 54A, 55 Low-pass filters B1 secondary battery CV1 charger Rload Load resistance T1 to T13, T13A terminals

Claims

1. a charge control switch element that controls charging of the secondary battery; a discharge control switch element connected in series with the charge control switch element to control discharge of the secondary battery; A charge / discharge control circuit for controlling The charge / discharge control circuit a shunt resistor connected in series with the charge control switch element or the charge control switch element and connected between the secondary battery and a load, the shunt resistor detecting a voltage corresponding to a discharge current or a charge current and outputting first and second potentials at a first terminal and a second terminal of the shunt resistor; a comparator that compares the first potential with a potential of an added voltage obtained by adding a predetermined threshold voltage to the second potential, and outputs a comparison result signal that indicates an overcurrent; a logic circuit that controls the charge control switch element or the discharge control switch element based on the comparison result signal; a first low-pass filter inserted between a first terminal of the shunt resistor and the comparator; a second low-pass filter inserted between a second terminal of the shunt resistor and the comparator; A charge and discharge control circuit comprising:

2. 2. The charge / discharge control circuit according to claim 1, wherein the first and second low-pass filters are provided as an inner circuit or an outer circuit of the charge / discharge control circuit.

3. 2. The charge / discharge control circuit according to claim 1, wherein the first and second low-pass filters are provided as internal circuits of the charge / discharge control circuit and are directly connected to the input terminals of the comparator, respectively.

4. a detection circuit connected to the first terminal or the second terminal of the shunt resistor, the detection circuit detecting that a predetermined high voltage is applied to the shunt resistor; a switch element that disconnects a circuit between the shunt resistor and the comparator when the detection circuit detects that the predetermined high voltage is applied; The charge / discharge control circuit according to claim 1 , further comprising:

5. a detection circuit connected to the first terminal or the second terminal of the shunt resistor, the detection circuit detecting that a predetermined high voltage is applied to the shunt resistor; first and second switch elements that disconnect a circuit between the shunt resistor and the comparator when the detection circuit detects that the predetermined high voltage is applied; a third low-pass filter inserted between the first switch element and the comparator; a fourth low-pass filter inserted between the second switch element and the comparator; The charge / discharge control circuit according to claim 1 , further comprising:

6. the shunt resistor is inserted between the secondary battery and the charge control switch element; the first potential is applied to a power supply voltage terminal of the charge / discharge control circuit via the second low-pass filter; 2. The charge / discharge control circuit according to claim 1.

7. the first and second low-pass filters are provided as inner circuits of the charge / discharge control circuit; 7. The charge / discharge control circuit according to claim 6.

8. the second low-pass filter is inserted between a negative terminal of the secondary battery and a ground terminal of the charge / discharge control circuit, instead of being inserted between the second terminal of the shunt resistor and the comparator; 7. The charge / discharge control circuit according to claim 6.

9. the charge / discharge control circuit; the charge control switch element; the discharge control switch element; 9. The protection circuit according to claim 1, comprising:

10. the secondary battery; the charge / discharge control circuit; the charge control switch element; the discharge control switch element; The battery pack according to any one of claims 1 to 8, comprising:

Images